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ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R)

FULL SUBTRACTOR VHDL CODE USING DATA FLOW MODELING


Library declaration

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-------------------------------------------entity full_subtractor is
Port ( a, b, c: in STD_LOGIC;
diff ,borrow: out STD_LOGIC);
end full_subtractor;
---------------------------------------------

Std_logic_1164; package for std_logic (predefined data type).

Entity declaration.
a, b, c :- input port bits (bits to be
added)
diff, borrow: - output port bits.

architecture Behavioral_FS of full_subtractor is


begin
--------------------------------------------------------------------------diff<= a xor b xor c;
borrow<= (((not a)and b) or ( b and c) or (c and (not a)));
----------------------------------------------------------------------------end Behavioral_FS;

RTL VIEW:-

INFOOP2R.WIX.COM/OP2R

OUT PUT WAVEFORMS:

Concurrent statements.
These are the circuit
expressions which are formed
by k-map or Boolean function.