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FPGA
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A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
F 0 0 0 1 0 1 0 1
A B C
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LUT (B+C) A
A 3LUT has 3 inputs and 1 output A 4LUT has 4 inputs and 1 output 4LUTs are the most common
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3LUT #3
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4LUT #1
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An FPGA is a Programmable Logic Device (PLD) It can be programmed to perform any function desired.
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out
4LUT
D Q
16
clk
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out
4LUT
D Q
16
clk
out
4LUT
D Q
16
clk
out
4LUT
D Q
16
clk
On power up, configuration bits are loaded into FPGA This customizes its operation (LUT function, MUX selection)
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out
4LUT
D Q
16
clk
Typically, configuration bits are not changed during circuit operation (but, some FPGAs are dynamically reconfigurable)
ECEn 224
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Another LE Structure
Provides two outputs
One combinational, one registered
inA inB inC inD inE
0
D Q 4LUT
1
outReg
16
0
clk outComb
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One Configuration
inA inB inC inD inE
0
D Q 4LUT
1
outR = reg(inB(inC+inD))
=1
16
0
clk
fn=inB(inC+inD)
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Another Configuration
inA inB inC inD inE
0
D Q 4LUT
1
outR = reg(inA)
=0
16
fn=inC
=1
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D Q 4LUT
1
outR = reg(inC)
=1
16
fn=inC
=1
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out
D Q
clk Cin
Can do two functions at once (Sum and Cout) Carry/cascade logic optimized for add/subtract and wide AND,OR, Cin and Cout have dedicated connections to neighboring LEs fast carry chains fast arithmetic
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Row wires
Each LE is configured to do a function Wire intersections are programmed to either connect or not
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=1 Row wire
ON
Connected
=0
OFF
Unconnected
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Example Problem
Generate the N, Z, P status flags for a 6-bit microprocessor
D0-D5
D5
Z N
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Example Problem
Generate the N, Z, P status flags for a 6-bit microprocessor
D0-D5
D5
Z N
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1
D0 D1
10
P
D2
11
D3 D4 D5
12
13
14
15
1
D0 D1
10
P
D2
11
D3 D4 D5
12
13
14
15
1
D0 D1
10
P
D2
11
D3 D4 D5
12
13
14
15
1
D0 D1
10
P
D2
11
D3 D4 D5
12
13
14
15
1
D0 D1
10
P
D2
11
D3 D4 D5
12
13
14
15
Configuring an FPGA
Most FPGAs have a configuration input pin
Configuration bits are shifted into FPGA using this pin, one bit per cycle Configuration bits in FPGA linked into a long shift register (SIPO)
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Structure of a 3LUT
b0 b1 b2 b3 b4 b5 b6 b7
3
LUT Output Its just an 8:1 MUX LUT inputs select which config bit is sent to LUT output Programming LUT function setting configuration bits
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LUT Inputs
ECEn 224
D Q
1
B6
CONFIG
0
CCLK
These are the configuration bits which the LUT selects from
B7
D Q
1
CONFIG
CCLK
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Column wire
Configuration bit
Row wire
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At this point, can use following sections slides on advanced FPGA features or simply show data sheets for commercial FPGAs
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Configurable Input/Output
I/O blocks allow internal FPGA signals to connect to external pins Configurable I/O block features: Can be configured as inputs or outputs Electrostatic discharge (ESD) protection Input signal conditioning (voltage levels, ) Output drive
Fast, slow Strong, weak Tri-state
I/O blocks are configured when the rest of the chip is configured
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Configuration Storage
Actual configuration storage is not flip flops
Many use SRAM memory cells
Different technologies
Program once
Fuse, anti-fuse configuration
Some chips can be partially reconfigured, even while rest of chip is running
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Programmable Interconnections
Expensive to put programmable connections at every wire junction
Commercial parts use partially populated junctions Little or no loss of routing flexibility
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Hierarchical Routing
Collection of short, medium, and long wires
Both rows and columns
Signals use wires that go distance needed CAD tools make determinations Like alleys, streets, expressways in a city
Longer distance more limited access points
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Clustered LEs
Cluster: >= 1 LE
Example: Cluster of 4 Dedicated wires within groups of 4 LEs
Closely related to hierarchical routing Higher performance Different vendors different clustering
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FPGAs
ASICs
Performance
Both CPUs and FPGAs can be reprogrammed (reconfigured) in the field The winner: CPUs
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Result:
FPGAs are slower, physically larger, and more power hungry than a custom ASIC chip For some/many applications FPGAs may
be too slow ...not hold enough logic be too power hungry
ASIC
NRE costs = $5M Per-part cost = $1
Cost to produce 100 = $5M + $100 $5M Cost to produce 106 = $5M + $1M = $6M
Fixing Bugs
FPGA = modify design + reconfigure FPGA
Reconfigurability can make debugging easier
Complex Decision
Only partially based on technical issues Significant business issues
Cost Risk Time-to-market Market characteristics (elasticity, price sensitivity, )
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