COMPREHENSIVE EXAM FOR Ph.D CONFIRMATION Name Of The Candidate : V.JEAN SHILPA Time : #.1$a.m % 1&.1$ '.m ANS.

ER ALL /0ESTIONS PART A 1- X & 1 &- MAR2S Date : 1 !"!1

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1. Which hazard is more critical in pipelines and how can it be avoided? 2. What are the merits and demerits of static branch prediction? 3. Define multithreading and mention the importance of it. 4. What is the need for cache coherency? . What are the features of heterogeneous multicore architecture!"#$%? &ive few e'amples where "#$ are implemented. (. Differentiate deadloc) and live loc). *. What are the overheads involved in a thread? +. ,ompare the sources of power dissipation between static and dynamic ,#-. circuits. /. What is glitching power dissipation? "ow can it be minimized? 10. When do re1uire distributed buffers in a digital system? PART 3 $ X 14 1 5- MAR2S

11. $% .uppose you have two e'ecution pipelines2 each capable of beginning e'ecution of one

instruction per cycle2 and enough fetch3decode bandwidth in the front end so that it will not stall your e'ecution. $ssume results can be immediately forwarded from one e'ecution unit to another2 or to itself. 4urther assume that the only reason an e'ecution pipeline would stall is to observe a true data dependence. 5ow how many cycles does the loop re1uire in the following code? LATENC6
6oop7 6D 4220!8'% :-7 #;6<D 42240242 :17 D:=D 4+242240 :27 6D 4420!8y% :37 $DDD 44240244 :47 $DDD 41024+242 : 7 .D 4420!8y% :(7 $DD: 8'28'2?+ :*7 $DD: 8y28y2?+ :+7 .;> 82028428' :/7 >5@ 82026oop #emory 6D #emory .D :nteger $DD2 .;> >ranches $DDD #;6<D D:=D 93 91 90 91 92 94 910

!-8% b% Describe how a thread level parallelism can be converted into :6A using .imultaneous #ultithreading with an e'ample. 12a% B'plain the basics of DirectoryC>ased ,ache ,oherence Arotocol !-8% b% $ssume that words '1 and '2 are in the same cache bloc)2 which is in the shared state in the caches of both A1 and A2. $ssuming the following se1uence of events2 identif7 ea8h mi,, as a true sharing miss2 a false sharing miss2 or a hit. $ny miss that would occur if the bloc) size were one word is designated a true sharing miss. Time 1 2 3 4 P1 Write '1 Write '1 P& 8ead '2

Write '2 8ead '2 13 a% i% ,alculate the speedup of pipelining that can be obtained with * tas)s if the mean overhead of a pipeline is considered as and an e'ecution time per stage of 1 cycle? !+% ii% What will be the mean overhead of a pipeline with stages and an e'ecution time per stage of 1 cycle? !+% !-8%

b% ,lassify and e'plain the parallel programming models used on hybrid platforms 14 a%

!-8% b% !i% Derive an e'pression for short circuit power dissipation of a ,#-. inverter. !ii% Write a short note on drain induced barrier lowering. 1 a% !i% "ow can power be reduced in write driver circuits and sense B'plain. !ii% Differentiate #<,#-. from D<,#-.. !-8% b% !i% B'plain the wor)ing of D,=. voltage level converter.

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amplifier circuits? !10% !(%

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!ii% Design a full adder using $diabatic logic.

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