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Experiment 7 Lab Manual

Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 1



American International University- Bangladesh
Department of Electrical and Electronic Engineering
EEE 4215: VLSI Circuit Design Laboratory

Title: Top-Down Design of VLSI Circuits using Schematic Entry and Electronic
Design Automation Part-IComparators, Adders and Adder-Subtractors.

Abstract:

This experiment introduces students with a schematic entry tool DSCH 3.5 from
Microwind that allows digital VLSI designers design digital circuits at Gate and Switch-
Level. The students will also learn hierarchical design of VLSI Circuits utilizing DSCH
symbols. At the end students will use Microwind 3.5 as a silicon compiler to generate
physical layout from Register Transfer Level (RTL) code (aka Verilog Hardware
Description Language) generated by DSCH 3.5.

Introduction:

DSCH schematic entry tool allows designers to design digital circuits using schematic
entry at switch and gate level. The technology libraries of DSCH, as displayed below, are
generic or silicon-technology-independent that allows designers freedom to target their
designs to both Application Specific Integrated Circuits (ASIC) and Field Programmable
Gate Arrays (FPGA). DSCH v.3.5 has technology libraries and design rule files for
technology nodes as small as 65 nm.





















Experiment 7 Lab Manual

Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 2

At switch level, DSCH allows the designers can define transistor sizes, as illustrated
below. DSCH also allows designers to generate circuit level SPICE descriptions as well
as low level RTL such as dataflow, gate or switch level Verilog HDL (in IEEE standard
1364-1995 or Verilog-95 style).




















Theory And Methodology:

In hierarchical design a bigger design is designed as an interconnection of smaller
designs. For example, a 2-bit comparator can be designer from two 1-bit comparators and
some basic logic gates. Similarly, a 4-bit adder is designed using the cell of a fulladder
(and using it 4 times). DSCH is well-suited for hierarchical digital design.

Comparator:

The operation of a 1-bit comparator is illustrated with the following truth-table.












A B GT LT EQ
0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1
Experiment 7 Lab Manual

Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 3

Note that a 2-bit adders outputs are same as a 1-bit adder, but the inputs are 2-bit wide.













Adder:

Note that a full adders Sum and Carryout equations are as follows.

SUM = A B CIN

CARRYOUT = A B + (A B) CIN

























+ +
+
Experiment 7 Lab Manual

Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 4

A 2-bit adders top-level diagram is shown below.















Adder-Subtracter:

An n-bit adder-subtractor can be designed using the cells of an n-bit adder and an n-bit,
2-input XOR gate. Note that subtraction can be implemented as 2s complement addition,
rather than using original subtraction algorithm. This will allow adders to be reused for
both addition and subtraction, save hardware and simplify the design process.

1s complement is essentially NOT operation. We need to add a 1 to it to make it 2s
complement. We need to generate 1s complement of B and then add a 1 to it only when
we are subtracting. Consider a 2-bit adder-subtracter that subtracts B from A. In this
case, we need to conditionally generate 1s complement of B. The output of the XOR
gate, say named B_to_Add, has to be added to A (not the actual input B) to implement
the adder-subtractor. This can be easily generated by XOR gates, as illustrated by the
truthtable of XOR gate shown below.










The Add_Sub input can be used to add the extra 1 we need to generate 2s compliment
(we are subtracting when Add_Sub = 1). To do that we need to connect Add_Sub to the
CarryIn bit of the full adder that adds least significant bits of A and B. When we add,
Add_Sub remains 0; so it sends B unchanged through XOR gates and does not add any
extra 1 to the calculation, which is exactly what we want for addition. On the other hand,
when we subtract, Add_Sub is set to 1, which allows the XOR gate to send 1s
A B Y
(B_to_Add)
Remarks
0 0 0 Y = A when A = 0
0 1 1
1 0 1 Y = not A when A = 1
1 1 0
Experiment 7 Lab Manual

Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 5

complement of B to the adder. Since we are also adding the Add_Sub signal, an extra 1 is
added to the adder that makes it possible to get 2s complement of B added to A, which is
essentially the implementation of A - B. Therefore, the adder-subtrators operation can be
described by a single arithmetic equation as shown below.

SUM = A + B_TO_ADD + ADD_SUB, where

B_TO_ADD = ADD_SUB B






































+
Experiment 7 Lab Manual

Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 6

Creating Symbols and Verilog HDL Descriptions in DSCH:

After one can designs a circuit in DSCH, he can define it as a symbol to re-use it in a
larger design. To create a symbol, one has to select File-Schema to New Symbol.





















To insert a symbol one has to select Insert-User Symbol.




















Experiment 7 Lab Manual

Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 7

To create a Verilog HDL description from a DSCH schematic file, one has to select File-
Make Verilog File. To generate a SPICE file, the File-Generate SPICE File can be used.




















Apparatus:

1. A Windows-based (XP or 7) PC with standard word processors (i.e. Microsoft
Office) and PDF readers (i.e. Adobe Acrobat Reader/Writer, Foxit
Reader/Phantom) installed.
2. A PSPICE simulator, preferably ORCAD PSpice Student 9.1 Student from
Cadence

Precautions:

1. A PC with a standard Anti-Virus program installed should be used.


Experimental Procedure:

Design the following circuits in DSCH, simulate them using the built-in simulator, and
generate Verilog HDL descriptions from your top-level DSCH files and physical layout
from Microwind from these Verilog HDL descriptions.

1. Design a 2-input NAND gate and a 2-input NOR gate at switch-level in DSCH and
verify their operation through simulation.

2. Design a 2-bit Comparator using the cell of a 1-bit comparator. The inputs are A (2-bit)
and B (2-bit) and the outputs are GT, LT and EQ. Design a 1-bit comparator in DSCH
Experiment 7 Lab Manual

Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 8

first. After verifying its operation, create a symbol for it and use this symbol to design a
2-bit comparator. Verify the operation of the 2-bit comparator, generate Verilog HDL
descriptions from your top-level DSCH files and physical layout from Microwind from
these Verilog HDL descriptions.

Use the Hex Keyboard for providing A and B and Lights to display comparator outputs
GT, LT and EQ.

3. Design a 2-bit adder using the cell of a 1-bit full adder. The inputs are CARRYIN (1-
bit), A (2-bit) and B (2-bit) and the outputs are SUM (2-bit) and CARRYOUT (1-bit).
Design the full adder in DSCH, verify it and then create a symbol for it. Design the 2-bit
adder using the symbol of the full adder and verify its operation. Generate Verilog HDL
description from your top-level DSCH files (file for 2bit adder) and then its physical
layout from Microwind from the Verilog HDL description.

Use a Button for providing CARRYIN and the Hex Keyboard for providing A and B. Use
a Light to display CARRYOUT and the Hex Display to display SUM.

4. Design a 4-bit adder-subtractor using the cells of a 4-bit adder and a 4-bit, 2-input
XOR gate. The inputs are ADD_SUB (1-bit), A (4-bit) and B (4-bit) and the outputs are
SUM (4-bit) and CARRYOUT (1-bit). This adder-subtractor has a control input
ADD_SUB. If ADD_SUB is 0, it performs addition and if it is 1, it performs subtraction.
This adder-subtractor subtracts B from A.





The 4-bit adder has to be built using the cell of full adders and the 4bit, 2-input XOR gate
has to be built using the cell of 1-bit, 2-input XOR gates. Verify their operation. Generate
Verilog HDL description from your top-level DSCH file (file for 4bit adder-subtractor)
and then its physical layout from Microwind from the Verilog HDL description.

Use a Button for providing ADD_SUB and the Hex Keyboard for providing A and B.
Use a Light to display CARRYOUT and the Hex Display to display SUM.

Simulation And Measurement:

Add the DSCH schematic, generated Verilog HDL code and simulation for top-level of
all the circuits discussed above.

Result:

Add the logic simulation from DSCH and generated layout from MICROWIND.


Add_Sub Operation
0 A + B
1 A - B
Experiment 7 Lab Manual

Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 9

Discussion And Conclusion:

Summarize what you have done in this experiment

Answer the questions posed in the procedure section and those added by your teacher, if
any.

If you have any recommendations to improve the experiment, mention them as well.

Acknowledgement:

This laboratory instruction sheet has been updated by Shahriyar M. Rizvi, Assistant
Professor, Faculty of Engineering, AIUB, 2011, 2013

Reference:

1. DSCH Users Manual