It may be noted that this fault is not testable, because there is no alternative to backtrack, as there were no choices at any

step.

Module - X Sequential Circuit Testing and Scan Chains

1.Introduction Till now we have been looking into VLSI testing, only from the context of combinational circuits. In this module we will study ATPG for sequential circuits. In the first lecture we will see the variations required in fault model, algebra and ATPG procedure in sequential circuits compared to combinational ones. Also we will compare the ATPG complexity in both the cases and show that testing sequential circuits is many folds more involved than testing combinational circuits. Following that in the next lecture we will introduce a special scheme called scan chain which ``modifies a sequential circuit into a virtual combinational one. So, test patterns for a sequential circuit with scan chain can be generated with slight variation in ATPG algorithms for combinational circuits (Dalgorithm, for example). In this lecture we will first discuss the difference between sequential and combinational circuits from the context of ATPG and single stuck-at fault model. In this course we will concentrate only on sequential synchronous circuits with a single clock. 2. ATPG and testing: Sequential versus combinational circuits Let us first see the basic architecture of a sequential circuit in Figure 1. In the figure it may be noted that there are three blocks, namely NSF, OFB and state flip-flop. The first two blocks are combinational circuits and the state flip-flop has sequential elements. So ATPG procedure for the NSF and OFB blocks should be similar to the ones already introduced in the previous lectures. However, it may be noted that compared to a standard combinational circuit, in case of NSF some inputs (state feedback) are not controllable and its outputs are not observable. Similarly, in case of the OFB, some of its inputs are non-controllable. When a circuit powers up, the flip-flops can have any value (0 or 1). So for ATPG of the combinational blocks in sequential circuits, we need to control

(indirectly) the values in the nets which are outputs of flip-flops and observe (indirectly) the nets which are inputs to the flip-flops. Once indirect controllability and observability are achieved, ATPG for these combinational blocks (in sequential circuits) can be done using D-algorithm (or any other combinational APTG algorithm).

Figure 1. Basic architecture of a sequential circuit [1] Before we illustrate how indirect controllability and observability can be achieved in these combinational blocks, we will discuss some assumptions in ATPG for single clock sequential circuits. In single clock sequential circuits, each flip-flop is treated as 1-bit memory element with ONE common clock. For each primary input pattern and secondary input pattern (present state), the resulting primary output and secondary output (next state) patterns are produced. After a clock edge, the secondary output pattern (next state) is transferred to the output of the flip-flops (present state), which become new secondary inputs. Also, the primary outputs are updated. This activity occurs at each clock edge, and so it is called synchronous operation. Single stuck at faults are assumed in the two combinational blocks namely, NSF and OFB. Internal faults of flip-flops are not modeled; their output and input faults are modeled as faults on input and output signals of the combinational blocks. In other words, flip-flops are treated as ideal memory elements and no faults are considered in the clock signal. Most of the time, D-flip-flops are used in VLSI designs. So in this course whenever we refer to a flip-flop we essentially mean a D-flip-flop.

Figure 2. A simple sequential circuit with a stuck-at-0 fault Let us consider a simple sequential circuit in Figure 2, with a s-a-0 fault at net a . If we compare this circuit with the block diagram shown in Figure 1, it may be noted that gate-1 corresponds to the OFB, gate-2 is for the NSF and D-flip flop is the memory element.

Figure 3. Problems in ATPG for the stuck-at-0 fault To test the s-a-0 fault, simply, a=1 and f =0, which results in D being propagated to the primary output. It may be noted that net f (secondary input) is driven by the output of the state flip-flop. As netf is not directly controllable, we cannot make it 0 and test the fault. As discussed, after power up, the flip-flop can have any signal value (marked as X). So testing the s-a-0 fault is not as simple as in case of combinational circuits. This problem is shown in Figure 3. For ATPG of the fault, we need to indirectly control the net f to 0. Following that, we can apply the test pattern as a =1 and b =X, which propagates D to the primary output. From the circuit it may be noted that to make f to 0, we first need to make net d=0, which is the input to the flip-flop; following that a clock edge can transfer the value of d to f (in the next state). The process of making f =0 in a indirect manner (by state change) is shown in Figure 4.

Figure 4. Indirect controlling of f to 0 After net f is made 0, then a =1 and b =X would propagate the fault effect (D) to the primary output; this is shown in Figure 5.

Figure 5. Test pattern for the s-a-0 fault So, it may be noted that ATPG for combinational blocks in sequential circuits require more than one pattern. In this example, the first pattern is a =X, b =0 and clock edge followed by a =1 and b =X. In such cases, final pattern is according to combinational ATPG (that sensitize the fault and propagates the effect to a primary output) and all other initial patterns are to bring the secondary inputs to their required value. ATPG for a fault in the NSF block is more complex than the ones in the OFB. In case of a fault in the NSF we need to indirectly control the secondary inputs and in addition, propagate the fault effect to the primary output via OFB. This is illustrated using a s-a-1 fault at net c in the circuit (Figure 6). First, primary input b =0 ( a =X) and a clock edge is applied; this makes e =0 (and also c =0) after the edge. It may be noted that even in presence of the s-a-1 fault, b =0 and a clock edge makes c =0; this sensitizes the fault ( D at c ). In the next step, b =1 ( a =X) and a clock edge would propagate the fault effect ( D ) to the output of the flip-flop (i.e, secondary input of the OFB). Finally, a =0 ( b=X) would propagate fault effect to the primary output. Above mentioned three steps are shown in Figure 6.

Figure 6. ATPG for s-a-1 fault in the NSF block 2.1Algebra for ATPG of sequential circuits In the last module we saw that Boolean algebra is not suitable for ATPG of combinational circuits; Routh's (5 value) algebra was found appropriate for ATPG algorithms. Now we will find whether this 5 value algebra suffices for ATPG of sequential circuits or we need to move to even higher orders. Let us try ATPG for a s-a-1 fault in the sequential circuit shown in Figure 7 using 5 value algebra.

Figure 7. A simple sequential circuit with a stuck-at-1 fault Fault effect can be propagated by two paths e-d-g or f-g . Let us take the shorter path ( f-g ). For this case we need net d =0. Also, to sensitize the fault we need to apply 0 at b. As net d is not directly controllable, we need to make a =0 ( b =X) and apply a clock pulse. Next, if we apply b =0 (a=X), the fault effect D would appear in the primary output. This process is shown in Figure 8.

Figure 8. ATPG for s-a-1 fault (using Routh's algebra) Now, we will see an interesting thing. If we use higher order algebra, then only one pattern can test the fault. Let us see the case if b =0 ( a =X). Fault is sensitized as D and e=f = D. Now as the secondary input ( c ) is not controlled, c =X. By 5 value algebra, d =X and so fault effect cannot be propagated to the output. However, if we observe carefully at net d, we will note that if the fault is there then d =X (as value is determined by the flip-flop at start up of circuit). However, if fault is not there then d =0 (as e =0). So we can mark d as 0/X. Now, f = D, which in turn makes g= D; D(=0/1) OR 0/X = 0/1 (= D). So fault can be detected using a single pattern b =0 ( a =X). All these steps are shown in Figure 9.

Figure 9. ATPG for s-a-1 fault using higher order algebra The following points are to be noted In the example, higher order algebra is used, as a net is marked as 0/X, which is not available in 5 value algebra. Higher order algebra improves efficiency of ATPG of sequential circuits. As higher order algebra reduces the number of input (primary and secondary) lines to be controlled, there is reduction in the number of steps (in terms of clock edges and test patters) to control the secondary inputs (or make the NSF block outputs observable via OFB). However, it does not guarantee that ATPG will not require controlling the secondary inputs and propagating the fault effect to the primary output via OFB. This example was a special case where controlling the secondary inputs were not required. Higher order algebra will also reduce the number of lines to be controlled in ATPG of a combinational circuit. However, it is not applied as computational complexity rises with increase in order of the algebra and inputs are easily controllable in combinational circuits. Table 1 illustrates a 9 value algebra which is used for ATPG of combinational blocks in sequential circuits. Table 1. Nine value algebra Symbol 0 1 X D D G0 G1 F0 F1 Implication (0/0) (1/1) (X/X) (1/0) (0/1) (0/X) (1/X) (X/0) (X/1) Normal Circuit 0 1 X 1 0 0 1 X X Faulty Circuit 0 1 X 0 1 X X 0 1

3. ATPG of sequential circuits: Time frame expansion method ATPG for (combinational blocks in) sequential circuits involves the following two broad steps: 1. Replace all the flip-flops by nets. Perform D-algorithm on the virtual combinational circuit and find the values of primary and secondary inputs. 2. Using multiple steps (primary inputs, secondary inputs and clock pulses) to apply the required signals to the secondary inputs (determined in Step 1).

The circuit shown in Figure 10 will be used to illustrate ATPG for sequential circuits using the time frame expansion approach.

Figure 10. Sequential circuits with a s-a-0 fault In the circuit we may note that nets a,b,c are primary inputs and nets d,i are secondary inputs. So if we replace the flip-flops with nets we get the circuit shown in Figure 11; such replaced nets are marked by doubled sided arrows. Also in the same figure we determine the test pattern to detect the s-a-0 fault as: a =1, b =1, c =1, d =1, i =1 and output is D. a =1, b =1, c =1 can be obtained by directly controlling the primary inputs. However, d =1, i =1 corresponds to secondary inputs which need to be achieved by setting primary inputs appropriately and clock edges, in steps previous to applying the final primary input as a =1, b =1, c =1.

Figure 11. Sequential circuit of Figure 10 with flip-flops replaced by nets Before we study in detail the ATPG for the circuit given in Figure 10, we disuses the following definitions and conditions. Definition 1: Sequential depth of a flip-flop: If the output of a flip-flop can be controlled by only primary inputs (and a clock pulse) it has sequential depth of 1. In the circuit of Figure 10, flip-flop F1 has sequential depth of 1 as it is controllable by primary input(s) c . A flip-flop has a sequential dept of dseq if its output is dependent on primary inputs and at least one flip-flop of depth dseq-1. In the example, flip-flop F2 is dependent on primary input b and output of flip-flop F1 (via nete ); so sequential depth of F2 is 2.

Definiation2: Non-cyclic Circuit A sequential circuit is non-cyclic if there is no flip-flop whose input is dependent on its output. For example, in the circuit of Figure 10, input of F1 is dependent on only primary inputs. On the other hand, input of F2 is dependent on primary inputs (net b ) as well as the output of F1 (net d ). So the circuit non-cyclic. An example of a cyclic sequential circuit is given in Figure 12. In this case input of F1 is dependent on its own output (and primary input). It may be noted that in cyclic circuits we may not be able to control the secondary inputs; this concept will be elaborated in an exercise problem. A flip-flop whose input is dependent on its own output is called a cyclic flip-flop.

Figure 12. Cyclic sequential circuit Property 1. The secondary inputs of a cycle free sequential circuit of depth dseqcan be brought to controllable value is at most dseq primary input patterns and clock pulses. Proof Idea: The proof is obvious. All flip-flops with dseq=1 can be controlled by setting primary inputs and a clock pulse. Now, as all flip-flops with dseq=1 have been set, we can control flip-flops withdseq=2 by setting primary inputs and a clock pulse. In this order, if there are flip-flops with dseq= n , we require at most n primary input patterns and n clock pulses. The proof idea for a circuit with dseq=2 is shown in Figure 13.

Figure 13. Illustration of the proof idea of Property 1 Now we will illustrate ATPG for the s-a-0 fault in the circuit of Figure 10, using time fame expansion approach and nine value algebra. For the circuit, dseq=2; so we require 2 primary input patterns and clock pulses to set the secondary inputs ( d,i ). As determined from the virtual combinational circuit (Figure 11), test pattern for the fault is a =1, b =1, c =1, d =1, i =1. So we need set d =1, i =1 and finally apply a =1, b =1, c =1. This can be achieved in three time steps: Time Step-1: Set primary inputs such that F1 is set appropriately which (along with primary inputs) can enable F2 to be 1 in Time Step-2. As i is to be 1 in Time Step-2, so d is to be made 1 by making primary input c =1 (in Time Step-1). Other primary inputs are don't cares in this step. Finally a clock pulse is given.

 Time Step-2: Net d =1 from settings in Step-1. Now we need to appropriately set primary inputs such that F2 is 1 and along with it F1 is also 1, in Time Step-3. To make F2=1 (having set d =1) we need to have b =1. Also, to have F1=1 we need to have c =1. The other primary input a is don't care. Finally a clock pulse is given. Time Step-3: So we have d =1 and i =1, from the setting in Time Step-2; equivalently F1=1 and F2=1. Now as per the test pattern given in Figure 11, primary input a =1 and b =1 would result in Dat the output . So the test pattern for the fault is (i) a =X, b =X, c =1 (clock pulse), (ii) a =X, b =1, c =1 (clock pulse) and (iii) a =1, b =1, c =X. Now we will discuss in brief the procedure of drawing the circuit structure for sequential ATPG using time frame expansion approach for the running example. The ATPG space is divided into dseq + 1 sub spaces. The subspaces are numbered from - dseq to 0. 0 th sub-space represents Time Step= dseq + 1, where all secondary inputs are set. - dseqsub-space represents the first time step when the circuit has just powered up and all secondary inputs are initialized to X. Following that, each sub-space represents change of signal values in the circuit with progress in time steps (i.e., primary input pattern and clock pulses). The basic block diagram of this procedure is shown in Figure 14. Figure 15 shows time steps for ATPG of the s-a-0 fault in the circuit of Figure 10.

Figure 14. Time Steps for sequential ATPG using time frame expansion method

Figure 14. ATPG for the s-a-0 fault in the circuit of Figure 10: time frame expansion approach 3. Conclusions In this lecture we have seen that for ATPG and testing sequential circuits (combinational blocks) we need multiple patterns and clock pulses. So applying the patterns for testing a sequential circuit involves much more test time than a combinational circuit. Also the complexity of ATPG algorithms for sequential circuits is higher than of combinational ones. The problem was the controllability of secondary inputs and observability of secondary outputs. In the next two lectures we will study a

DFT technique called scan-chain which eases sequential circuits testing and ATPG by making controllability and observability much simpler. References 1. Mano, M. Morris,. Digital Design, 2/e. Prentice-Hall of India . 1995. Questions and Answers Can ATGP and testing be performed for any fault in the XOR gate of circuit given below

Answer: The circuit is cyclic as input of F1 depends on its own output. When the circuit starts, output of F1 is X. Now, input of F1 is inversion of the primary input value, if F1 at startup was 1. Similarly, input of F1 is the primary input value if output of F1 at startup was 0. So it is obvious that as X is unknown we cannot set F1 according to need for ATPG. So ATGP and testing cannot be performed for any fault in the XOR gate of the circuit.

Lecture 2
1. Introduction In the last lecture we have seen that the major problem in testing (and ATPG) of sequential circuits is difficulty in controlling secondary inputs (i.e., outputs of flip-flops) and difficulty in observing secondary outputs (i.e., inputs of flip-flops). In this lecture we will discuss various techniques to make the flip-flops controllable and observable, which convert a sequential circuit into virtual combinational one. Following that ATPG for combinational circuits would suffice for sequential circuits. However, for achieving this, additional circuitry, called design for test (DFT), will be put onchip, which would add to extra area overhead. In the next section we will explore different schemes to control and observe the flip-flops. 2. Controllability and observability of flip-flops 2.1 Set and reset lines One of the simplest way to directly control flip-flops is through set-reset lines. Set-reset lines can directly make the output of a flip-flop to be 1/0 without any input and clock pulse. A D flip-flop with set-reset lines is shown in Figure 1 and its functionality is shown in Table 1.

Figure 1. D-Flip-flop with set and reset Table 1. Truth table for D flip-flop with set-reset lines Input (D) Don't care Don't care Don't care 1 0 Output (Q) 1 0 Illegal 1 0

set
1 0 1 0 0

reset
0 1 1 0 0

clock
Don't care Don't care Don't care Clock edge Clock edge

From the truth table it may be observed that set (reset) lines makes the output 1(0) irrespective of input D and clock pulse. However, both the set and reset lines cannot be made high simultaneously. Also, when the D-flip-flop functions normally, both set and reset lines are kept low. Now we will see how use of this type of flip-flop helps in testing the circuit given in exercise of last lecture (Lecture 1, module 12). The circuit with a s-a-1 fault in the primary input line is shown in Figure 2 (a). Also, the flip-flop has set/reset lines. By D-algorithm, a test pattern would be: primary input =0,secondary input (other input of XOR gate)=0 and fault effect at primary output = D. So in Step-1 (Figure 2 (b)), set =1 and reset =0 (and and primary input =X); this makes output of flipflop (i.e., secondary input) to be 1. In Step-2 (Figure 2 (c)), set =0, reset =0 and primary input =0; this sensitizes fault location as D and its effect propagates to the input of the flip-flop as D . Also a positive clock pulse is applied which transfers D to output of the flip-flop (primary output). These two steps complete ATPG (and testing) of the fault. So it may be observed that the fault which was un-testable by time frame expansion method becomes testable using set/reset flip-flop. Further, one pattern is required to set/reset the flip-flops and another pattern (at primary inputs) is required to sensitize and propagate the fault effect to a primary output. So, unlike time frame expansion method where dseq+1 test patterns are required (dseqpatterns to initialize the flip-flops and one pattern to sensitize/propagate fault effects), in case of set/reset flip-flops only two patters are required (one to set or reset the flops and one to sensitize/propagate fault effects). This saving in number of test patterns (i.e., test time) is illustrated in the circuit example of Figure 10 of the last lecture. The circuit (Figure 10 of Lecture 1, module 12) with set/reset flip flops is shown in Figure 3(a).

Figure 2. Testing using set/reset flip-flops for a cyclic circuit

Figure 3. Testing using set/reset flip-flops: illustration of saving in test patterns

As discussed in the last lecture, three patterns were required to test the s-a-0 fault at net j: (i) a =X, b =X, c =1 and clock pulse (ii) a =X, b =1, c =1 and clock pulse and (iii) a =1, b =1, c =X. Also it is to be noted that dseq=2, for the circuit.

Now, by using the set/reset flip-flops, we will see only two patterns are required to test the fault. By ATPG using D-algorithm, nets d and i are to be 1 for testing the fault. So both the flip-flops are set by the pattern: a =X, b =X, c =X, set (F1)=1, reset (F1)=0, set (F2)=1 and reset (F2)=0; this is shown in Figure 3(b). Finally, pattern a =1, b =1, c =X, set (F1)=0, reset (F1)=0, set (F2)=0 and reset(F2)=0 is applied to sensitize and propagate the effect of the fault to primary output; this is shown in Figure 3(c). So, only two patterns can test the fault. However the most important point is Irrespective of the value of dseq, only two patterns are required to test a sequential circuit with set/reset flip-flops. The gain can be easily understood because any practical circuit has more than thousands of flip-flops. On the other hand, there is a big problem with the scheme that makes it impractical to be applied in a practical system. An input output block diagram of the circuit of Figure 3 is shown in Figure 4. It may be noted that it has 9 I/O pins (3 primary inputs + 1 primary output +2 x nffs set-reset lines, where nffs is the number of flip-flops and a clock). The largest number of I/O pins supported in most complicated packages is about 1024. So, for a circuit with thousands of flip-flops, this approach requires a package of thousands of I/O pins (for the 2 x nffs factor) with makes it impractical.

Figure 4. Input output block diagram of the circuit shown in Figure 3.

2.2.Set and reset by shift register In the last sub-section we saw that flip-flops with set/reset capability can ease the testing and ATPG problem for sequential circuits. However, the main problem is the huge number of I/O lines that gets added to the chip. To avoid this issue of high I/Os, another technique called set and reset by shift register is used which uses a shift register and loads itself with the pattern required for setting the flip-flops. Now the set and reset lines of the flip-flops of the circuit (under test) are connected with the outputs of the flip-flops of the shift resister. The shift register has an input line and a separate clock (for shifting data) and an output line. So in this case only three extra I/O lines are

required. ATPG and testing for the circuit shown in Figure 3, using shift register is illustrated in Figure 5. As there are two flip-flops in the circuit under test, there are four flip-flops in the shift register. Now, set and reset lines of F1 (flip-flop) of the circuit under test are connected to output of SR1 and SR2 (flip-flops of register), respectively. Similarly, set and reset lines of F2 are connected to output of SR3 and SR4, respectively. As already discussed, testing the fault (s-a-0 at j ) requires the two flipflops of the circuit to be set to 1. So the pattern is set (F1)=1, reset (F1)=0, set (F2)=1 and reset (F2)=0, which when mapped to the flip-flops of the shit register is SR1=1,SR2=0,SR3=1 and SR4=0. The pattern 1010 can be inserted in the shift register using four clock edges of S_clock . Once the shift register is loaded, the flip-flops F1 and F2 are set; this is shown in Figure 5(a). Now, another pattern 0000 is inserted in the shift register using four clock edges of S_clock; this makes the circuit under test ready to be operational. Following that input pattern a =1, b =1, c =X is applied to sensitize and propagate effect of the fault to primary output; this is shown in Figure 5(b). The block diagram of the circuit (under test) with shift register is shown in Figure 6. So in addition to original I/Os, three new I/Os get added namely, (i) S_clock , (ii) test in and (iii) test out .

Figure 5. Testing using set/reset flip-flops and shift register

Figure 6. Input output block diagram of the circuit under test (Figure 5) with shift register The following are the pros and cons of shift register based testing and ATPG. Pros: ATPG algorithm does not require time frame expansion approach and flip-flops can be directly controlled from the register. So ATPG complexity is lower than time frame expansion approach. I/O requirements for testing is minimal (only 3) Cons: Area overhead of the shift register is high (twice the number of flip-flops in the circuit) Test pattern application time is almost same as in the time frame expansion approach. Applying bit sequence in the shift register (required for setting/resetting the flip-flops) takes 2 X nffs pulses of the clock of the register. In the next section we will discuss another scheme similar to shift resister based testing called scan chain. In scan chain based technique the flip-flops are directly controllable and I/O requirements are minimal. However, on the other side there is no requirement of the additional shift register and separate set/reset lines in flip-flops; due to these two points scan chain based scheme is widely accepted in VLSI testing. 3. Scan Chain based Testing and ATPG for sequential circuits In the last section we saw that shift register based testing of sequential circuits solved the problem of a large number of I/Os. However, the major drawback of the scheme is due to the huge area

overhead; twice the number of flip-flops in the circuit under test is required in the shift register. The concept of Scan chin is motivated from the idea of shift register based testing, however, alleviates the problem of area overhead [1]. The basic idea in scan chain is to convert the flip-flops in the circuit under test itself to a shift register, rather than using a separate one. To elaborate, the circuit under test has two modes: (i) test (or scan chain) and (ii) working (or normal). In test mode the flip-flops are decoupled from the circuit and they are connected in form of a shift register (called scan chain). The input of the first flip-flop in the scan chain is taken out as a special input test pin called Scan in and the output of the last flip-flop in the scan chain is taken out as a special output test pin called Scan out. Now all the flip-flops are set as required by shifting bit values in the scan chain. Once the flip-flops are set they are removed from the scan chain and connected back to the circuit. So another advantage of scan chain based testing over shift register based testing is due to non requirement of set/reset lines. The basic concept of scan chain is shown in Figure 7.

Figure 7. Scan chain in state flip-flop block Figure 7 shows the state flip-flops with scan chain in a sequential circuit; other blocks are not shown for clarity. As discussed, flip-flops with scan-chain take inputs from two parts of the circuit (i) next state function block (when operating normally) and (ii) from the previous flip-flop in the chain (when in test mode); the first flip-flop in the scan chain takes input from a primary input Scan in. So in state flip-flop block with scan chain, all the flip-flops must have a 2X1 multiplexer. One input is from the next state function block and the other is from the previous flip-flop in the chain. The control input called mode basically decides the mode of operation; 1 for scan-chain and 0 for normal operation. Figure 7 shows this concept for a circuit with three flip-flops. Figure 8 shows a flip-flop used in scan chain calledscan flip-flop and Figure 9 shows the block diagram representation of scan flip-flop. Figure 10 shows the flip-flops of Figure 7 in scan chain mode and Figure 11 shows the flip-flops of Figure 7 in normal mode. Figure 12 shows the basic block diagram of a sequential circuit with scan chain in both normal and test mode.

Figure 10. Flip-flops of Figure 7 in scan chain mode

Figure 11. Flip-flops of Figure 7 in normal mode

Figure 12.Sequentail circuit with scan chain: normal and test mode 4. ATPG and testing using scan chain in a sequential circuit: An Example In this section we will discuss ATPG and testing of the sequential circuit discussed in last lecture (Module 12, Lecture 1, Figure 10), now with scan chain. The circuit with the flip-flops having scan chain compatibility is shown in Figure 13(a). As discussed about the circuit (in Module 12, Lecture 1,

Figure 10), to test the s-a-0 fault at net j, the signal values at nets d and i are to be 1. So both the flip-flops are to be set to 1; this was achieved by making the set input as 1 and reset input as 0 in case of testing using set/reset flip-flops. In case of scan chain, to set the flip-flops, in the first step mode (M) is made 1. Making M=1, removes the next state function block from the circuit and the flip-flops are connected in a chain; this is shown by dotted lines in Figure 13(b). Two 1s are applied in the Scan in input at two clock pulses which makes d =1 and i =1. Now, the circuit is brought in normal mode by making M=0. In this stage testing is performed by making a =1, b =1, c =X which propagates the fault effect to the output; this is shown in Figure 13(c).

Figure 13. ATPG and testing of a sequential circuit (Figure 10, Module 12, Lecture 1) with scan chain In the last example we saw how scan chain can be used to set the flip-flops to desired value for testing. However, D-algorithm is required on the entire circuit (after removing flip-flops) to find the test pattern. Now we will see another advantage of scan chain, which eliminates the need for performing ATPG on the whole circuit. One needs to consider input of the nearest flip-flop from the fault site as an output line and perform ATPG on the sub-circuit lying in the cone of influence of the

output line (i.e., input of the nearest flip-flop). This concept will be illustrated on a circuit example given in Figure 14.

Figure 14. A sequential circuit with scan chain and s-a-0 fault at d We will first illustrate the scheme of testing using scan chain where D-algorithm is applied on entire circuit and scan chain is used only to control the flip-flops; the procedure is shown in Figure 15. Figure 15 (a) illustrates D-algorithm applied on the full circuit of Figure 14 (after removing the flipflops) where fault propagation path is taken as d-i-o-p-m-n. D-algorithm determines that h is to be 1 and gis to be 1; this implies that flip-flop F1 and F3 are to be set while F2 can be set or reset. Further, a =X,b =X, c =0 ,d =1, e =X would apply the pattern to sensitize and propagate the fault effect. So to make flip-flops F1 and F3 to be 1 and F2 to be X, pattern 1X1 is applied at Scan in input with three clock pulses keeping M=1; this is shown in Figure 15 (b). Finally, M is made 0 and test pattern a =X, b=X, c =0 ,d =1, e =X is applied, which propagates fault effect through primary output n; this is illustrated in Figure 15(c).

Figure 15. Testing using scan chain and fault propagation through circuit output

Figure 16. Fault sensitization and effect propagation to input of nearest flip-flop (of the circuit of Figure 14)

As already discussed, even in ATPG for sequential circuits, D-algorithm is performed on the full circuit with flip-flops removed. In the last example we saw the use of scan chain only to set/reset the flip-flops. Now we will see another use of scan chain in propagating the fault effect. So we need to just bring the fault effect to the input of the nearest flip-flop. This in turn requires ATPG on a subcircuit whose output drives the input of the nearest flip-flop. In other words, ATPG is to be performed on the sub-circuit that lies in the cone of influence of the nearest flip-flop's input. Figure 16 illustrates that the nearest flip-flop from the fault site (s-a-0 at net d, of the circuit of Figure 14) is F2. So fault effect needs to be propagated to net j (which is input of F2). So, APTG is to be performed on the sub-circuit which lies in the cone of influence of net j, which includes inputs d,e and AND gate marked gray in Figure 16; test pattern is d =1, e =1 and fault effect D is propagated to net j . Obviously ATPG complexity is simplified. Now we will see how scan chain can propagate this fault effect out of the circuit. The whole testing procedure, when fault is propagated through scan chain (for the circuit of Figure 16) is illustrated in Figure 17 I and Figure 17 II.