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This document discusses system-level physical design considerations for VLSI circuits. It covers topics such as clocked flip-flops, clocking styles, pipelined systems, and clock generation and distribution. Specifically, it describes how pipelining can be used to increase throughput by dividing logic into stages separated by registers. It also discusses challenges of clock distribution at high frequencies, such as skew and signal degradation, and techniques for clock stabilization, generation, and routing tree structures.
This document discusses system-level physical design considerations for VLSI circuits. It covers topics such as clocked flip-flops, clocking styles, pipelined systems, and clock generation and distribution. Specifically, it describes how pipelining can be used to increase throughput by dividing logic into stages separated by registers. It also discusses challenges of clock distribution at high frequencies, such as skew and signal degradation, and techniques for clock stabilization, generation, and routing tree structures.
This document discusses system-level physical design considerations for VLSI circuits. It covers topics such as clocked flip-flops, clocking styles, pipelined systems, and clock generation and distribution. Specifically, it describes how pipelining can be used to increase throughput by dividing logic into stages separated by registers. It also discusses challenges of clock distribution at high frequencies, such as skew and signal degradation, and techniques for clock stabilization, generation, and routing tree structures.