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QPACE Collaboration: H. Baier1, H. Boettiger1, M. Drochner2, N. Eicker2,3, U. Fischer1, Z. Fodor3, A. Frommer3, C. Gomez10,
G. Goldrian1, S. Heybrock4, M. Hüsken3, D. Hierl4, T. Huth1, B. Krill1, J. Lauritsen1, T. Lippert2,3, J. McFadden1,
T. Maurer4, N. Meyer4, A. Nobile4, I. Ouda6, M. Pivanti4,5, D. Pleiter7, A. Schäfer4, H. Schick1, F. Schifano8,
H. Simma7,9, S. Solbrig4, T. Streuer4, K.-H. Sulanke7, R. Tripiccione8, J. S. Vogt1, T. Wettig4, F. Winter7
1IBM Böblingen, 2FZ Jülich, 3Univ. Wuppertal, 4Univ. Regensburg, 5INFN Trento, 6IBM Rochester,
7DESY Zeuthen, 8Univ. Ferrara, 9Univ. Milano Bicocca, 10IBM La Gaude
We present an overview of the design and implementation of the QPACE Network Processor. The Network Processor implements a standard Ethernet network and a high-speed communica-
tion network that allows for a tight coupling of the processing nodes. By using an FPGA we have the flexibility to further optimize our design and to adapt it to different application requirements.
Ethernet
• Construct desired logic by setting up a number of these elements Flash Inbound-Write Outbound-Write
Reader Controller Controller • Serial interfaces: 2x UART, SPI, Global
Outbound
• Trade-off between performance and resource usage UART Read Signals
128 bit 208MHz 128 bit, 208MHz
They also provide other primitives like Block RAMs, Ethernet MACs, Configuration • Most logic controlled through Device Con-
processor cores, high-speed transceivers, etc. Status trol Register (DCR) Bus
Version
We chose a Xilinx Virtex-5 LX110T-FF1738-3:
to Cell BE
UART DCR
SPI Master 6 Torus Links DCR • just enough High Speed Serial Transceivers
Ethernet
• just enough pins to connect all 6 Torus links
Global • highest speed grade and sufficient capacity
Signals
RGMII
MDIO
to hold our logic
6 XGMII 4bit 250MHz
MDIO
32bit 250MHz
by SFB by IBM
to Global Signal Tree to Flash to Torus Transceivers to Ethernet Transceiver