04 HJ Ch04 p2

4-1
Chapter 4Processor Design
Chapter 4: Processor Design

Topics 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 The Design Process A 1-Bus Microarchitecture for the SRC Data Path Implementation Logic Design for the 1-Bus SRC The Control Unit The 2- and 3-Bus Processor Designs The Machine Reset Machine Exceptions
Computer Systems Design and Architecture by V. Heuring and H. Jordan
1997 V. Heuring and H. Jordan
4-2
Block Diagram of 1-Bus SRC
Page 1
4-3
High-Level View of the 1-Bus SRC Design
ADD SUB AND OR SHR SHRA SHL SHC NOT NEG C=B INC4
12
4-4
Constraints Imposed by the Microarchitecture

One bus connecting most registers allows many different RTs, but only one at a time 31 R0 Memory address must be copied into MA by CPU Memory data written from or read into MD R31 First ALU operand always in A, result A goes to C Second ALU operand always comes A from bus Information only goes into IR and MA from bus
A decoder (not shown) interprets contents of IR MA supplies address to memory, not to CPU bus
Computer Systems Design and Architecture by V. Heuring and H. Jordan 1997 V. Heuring and H. Jordan
0 32 32-bit general purpose registers 31..0 32 31 PC 0
IR
MA B ALU C C To memory subsystem MD
Page 2
4-5
Abstract and Concrete RTN for SRC add Instruction

Abstract RTN: (IR M[PC]: PC PC + 4; instruction_execution); instruction_execution := ( add (:= op= 12) R[ra] R[rb] + R[rc]:
31 R0 0 32 32-bit general purpose registers 31..0 32 31 PC 0
Concrete RTN for the add instruction Step T0 T1 T2 T3 T4 T5 RTN MA PC: C PC + 4; MD M[MA]: PC C; IR MD; IF A R[rb]; IEx. C A + R[rc]; R[ra] C;
R31 IR A
MA A ALU C C B To memory subsystem MD
Parts of 2 RTs (IR M[PC]: PC PC + 4;) done in T0 Single add RT takes 3 concrete RTs (T3, T4, T5)
4-6
Concrete RTN Gives Information About Sub-units

The ALU must be able to add two 32-bit values ALU must also be able to increment B input by 4 Memory read must use address from MA and return data to MD Two RTs separated by : in the concrete RTN, as in T0 and T1, are operations at the same clock Steps T0, T1, and T2 constitute instruction fetch, and will be the same for all instructions With this implementation, fetch and execute of the add instruction takes 6 clock cycles
Page 3
4-7
Concrete RTN for Arithmetic Instructions: addi

Abstract RTN: addi (:= op= 13) R[ra] R[rb] + c216..0 {2's complement sign extend} :
31 0 32 32-bit general purpose registers 31..0 32 31 PC 0
Concrete RTN for addi: Step T0. T1. T2. T3. T4. T5. RTN MA PC: C PC + 4; MD M[MA]; PC C; Instr Fetch IR MD; Instr Execn. A R[rb]; C A + c216..0 {sign ext.}; R[ra] C;
R0
R31 IR A
MA A ALU C C B To memory subsystem MD
Differs from add only in step T4 Establishes requirement for sign extend hardware
4-8
More Complete View of Registers and Buses in the 1-Bus SRC Design, Including Some Control Signals
Concrete RTN lets us add detail to the data path
Instruction register logic and new paths Condition bit flip-flop Shift count register
Page 4
4-9
Abstract and Concrete RTN for Load and Store

ld (:= op= 1) R[ra] M[disp] : st (:= op= 3) M[disp] R[ra] : where disp31..0 := ((rb=0) c216..0 {sign ext.} : (rb0) R[rb] + c216..0 {sign extend, 2's comp.} ) :
The ld and St Instructions
Step RTN for ld RTN for st T0T2 Instruction fetch T3 A (rb = 0 0: rb 0 R[rb]); T4 C A + (16@IR16#IR15..0); T5 MA C; T6 MD M[MA]; MD R[ra]; T7 R[ra] MD; M[MA] MD;
4-10
Notes for Load and Store RTN

Steps T0 through T2 are the same as for add and addi, and for all instructions In addition, steps T3 through T5 are the same for ld and st, because they calculate disp A way is needed to use 0 for R[rb] when rb = 0 15-bit sign extension is needed for IR16..0 Memory read into MD occurs at T6 of ld Write of MD into memory occurs at T7 of st
Page 5
4-11
Concrete RTN for Conditional Branch

br (:= op= 8) (cond PC R[rb]): cond := ( c32..0=0 0: c32..0=1 1: c32..0=2 R[rc]=0: c32..0=3 R[rc]0: c32..0=4 R[rc]31=0: c32..0=5 R[rc]31=1 ): never always if register is zero if register is nonzero if positive or zero if negative
The Branch Instruction, br
Step T0T2 T3 T4
RTN Instruction fetch CON cond(R[rc]); CON PC R[rb];

4-12
Notes on Conditional Branch RTN

c32..0 are just the low-order 3 bits of IR cond() is evaluated by a combinational logic circuit having inputs from R[rc] and c32..0 The one bit register CON is not accessible to the programmer and only holds the output of the combinational logic for the condition If the branch succeeds, the program counter is replaced by the contents of a general register
Page 6
4-13
Abstract and Concrete RTN for SRC Shift Right

shr (:= op = 26) R[ra]31..0 (n @ 0) # R[rb]31..n : n := ( (c34..0 = 0) R[rc]4..0 : Shift count in register or constant field of (c34..0 0) c34..0 ): instruction
The shr Instruction
Step T0T2 T3 T4 T5 T6
T7
Concrete RTN Instruction fetch n IR4..0; (n = 0) (n R[rc]4..0 ); C R[rb]; Shr (:= (n 0) (C31..0 0#C31..1 : n n - 1; Shr) ); R[ra] C; step T6 is repeated n times
4-14
Notes on SRC Shift RTN

In the abstract RTN, n is defined with := In the concrete RTN, it is a physical register n not only holds the shift count but is used as a counter in step T6 Step T6 is repeated n times as shown by the recursion in the RTN The control for such repeated steps will be treated later
Page 7
4-15
4-16
The Register File and Its Control Signals

31 27 26 22 21 17 16 12 11 2
IR Op
Gra 3
ra 5
Grb
rb 5
Grc
Rout gates selected register onto bus Rin strobed selected register from bus
From Figure 4.3
31 R0 32 32-bit general purpose registers 0 32 5 Select logic IR
rc 5
5
... ...
1
Bus b<31...0> 32 32
6
D Q R31 Q
8
32 32
5 to 32 decoder
31
32 R31
...
1
1 R1 0 R0 32
D Q R1 Q
8 1
32
6
...
32
R31
BAout differs from Rout by gating 0 when R[0] is selected

BA = Base Address
Rin Rout BAout
D Q R0 Q
32
32
6
32
7
Page 8
4-17
4-18
Extracting c1, c2, and OP from the Instruction Register, IR<31...0>

32 D Q 5 Q
IR31..27
I21 is the sign bit of C1 that must be extended

From Figure 4.3 5 Op 32 32 IR
Select logic c131..0
To control unit
D Q 10 Q
IR26..22
31..22
1
c231..0
D Q 1 Q
IR21
21
c1out
I16 is the sign bit of C2 that must be extended Sign bits are fanned out from one to several bits and gated to bus
D Q Q
4 15
20..17 31..17 1
c2out 1
IR20..17
D Q 1 Q
IR16
16
D Q 16 IRin Q
IR15..0
16
15..0 Bus
Page 9
4-19
4-20
The CPUMemory Interface: Memory Address and Memory Data Registers, MA<31...0> and MD<31...0>
MD is loaded from memory or from CPU bus
From Figure 4.3 MA
To memory subsystem
32 32
MDbus MDrd
1 32 2 3
32
D Q MD Q
MD31..0
32
32
32
Read Write Done
Strobe
32
32
data31..0
MD MDwr MDout Memory bus

32 32 addr31..0
MD can drive CPU bus or memory bus
D Q MA Q
MA31..0
MAin
CPU bus
Page 10
4-21
4-22
The ALU and Its Associated Registers

32 D A From Figure 4.3
A A ALU C C B
Q 32 Q
A in
ADD SUB AND
A 11 ALU C
B 32
...
NOT C=B INC4
32 D C Cin Q Q
32
C out
Page 11
4-23
From Concrete RTN to Control Signals: The Control Sequence

The Instruction Fetch
Step T0 T1 T2 T3
Concrete RTN MA PC: C PC + 4; MD M[MA]: PC C; IR MD; Instruction_execution
Control Sequence PCout, MAin, INC4, Cin Read, Cout, PCin, Wait MDout, IRin
The register transfers are the concrete RTN The control signals that cause the register transfers make up the control sequence Wait prevents the control from advancing to step T3 until the memory asserts Done
4-24
Page 12
4-25
Control Steps, Control Signals, and Timing

Within a given time step, the order in which control signals are written is irrelevant
In step T0, Cin, Inc4, MAin, PCout == PCout, MAin, INC4, Cin
The only timing distinction within a step is between gates and strobes The memory read should be started as early as possible to reduce the wait MA must have the right value before being used for the read Depending on memory timing, Read could be in T0
4-26
Control Sequence for the SRC add Instruction

add (:= op = 12) R[ra] R[rb] + R[rc]:
The add Instruction
Step T0 T1 T2 T3 T4 T5
Concrete RTN MA PC: C PC + 4; MD M[MA]: PC C; IR MD; A R[rb]; C A + R[rc]; R[ra] C;
Control Sequence PCout, MAin, INC4, Cin, Read Cout, PCin, Wait MDout, IRin Grb, Rout, Ain Grc, Rout, ADD, Cin Cout, Gra, Rin, End
Note the use of Gra, Grb, and Grc to gate the correct 5-bit register select code to the registers End signals the control to start over at step T0
Page 13
4-27
Control Sequence for the SRC addi Instruction

addi (:= op= 13) R[ra] R[rb] + c216..0 {2s comp., sign ext.} :
The addi Instruction
Step T0. T1. T2. T3. T4. T5.
Concrete RTN MA PC: C PC + 4; MD M[MA]; PC C; IR MD; A R[rb]; C A + c216..0 {sign ext.}; R[ra] C;
Control Sequence PCout, MAin, Inc4, Cin, Read Cout, PCin, Wait MDout, IRin Grb, Rout, Ain c2out, ADD, Cin Cout, Gra, Rin, End
The c2out signal sign extends IR16..0 and gates it to the bus
4-28
Control Sequence for the SRC st Instruction

st (:= op = 3) M[disp] R[ra] : disp31..0 := ((rb=0) c216..0 {sign extend} : (rb0) R[rb] + c216..0 {sign extend, 2s complement} ) :
The st Instruction
Step T0T2 T3 T4 T5 T6 T7
Concrete RTN Instruction fetch A (rb=0) 0: rb 0 R[rb]; C A + c216..0 {sign-extend}; MA C; MD R[ra]; M[MA] MD;
Control Sequence Instruction fetch Grb, BAout, Ain c2out, ADD, Cin Cout, MAin Gra, Rout, MDin, Write Wait, End
Note BAout in T3 compared to Rout in T3 of addi

Page 14
4-29
The Register File and Its Control Signals

31 27 26 22 21 17 16 12 11 2
IR Op
Gra 3
ra 5
Grb
rb 5
Grc
rc 5
5
... ...
1
Bus b<31...0> 32 32
6
Rout gates selected register onto bus Rin strobed selected register from bus
From Figure 4.3
31 R0 32 32-bit general purpose registers 0 32 5 Select logic IR
D Q R31 Q
8
32 32
5 to 32 decoder
31
32 R31
...
1
1 R1 0 R0 32
D Q R1 Q
8 1
32
6
...
32
R31
BAout differs from Rout by gating 0 when R[0] is selected

BA = Base Address
Rin Rout BAout
D Q R0 Q
32
32
6
32
7
4-30
Page 15
4-31
The Shift Counter

The concrete RTN for shr relies upon a 5-bit register to hold the shift count It must load, decrement, and have an = 0 test
Bus From Figure 4.3
4..0 32 4 0
4..0 n=0 Decr Ld
5 n: shift count 5-bit down counter n = Q4..Q0
Decrement
Shift count, n
31..0 n=0
4-32
Control Sequence for the SRC shr InstructionLooping

Step T0T2 T3 T4 T5 T6 Concrete RTN Instruction fetch n IR4..0; (n=0) (n R[rc]4..0); C R[rb]; Shr (:= (n0) (C31..0 0#C31..1: n n-1; Shr) ); R[ra] C; Control Sequence Instruction fetch c1out, Ld n=0 (Grc, Rout, Ld) Grb, Rout, C=B, Cin n0 (Cout, SHR, Cin, Decr, Goto6) Cout, Gra, Rin, End
T7
Conditional control signals and repeating a control step are new concepts
Page 16
4-33
The ALU and Its Associated Registers

32 D A From Figure 4.3
A A ALU C C B
Q 32 Q
A in
ADD SUB AND
A 12 ALU C
B 32
...
NOT C=B INC4 SHR
32 D C Cin Q Q
32
C out
4-34
A Logic-Level Design for One Bit of the 1Bus SRC ALU
Page 17
4-35
4-36
Branching
cond := ( c32..0=0 0: c32..0 = 1 1: c32..0 = 2 R[rc] = 0: c32..0 = 3 R[rc] 0: c32..0 = 4 R[rc]31 = 0: c32..0 = 5 R[rc]31 = 1 ):
This is equivalent to the logic expression
cond = (c32..0 = 1) (c32..0 = 2)(R[rc] = 0) (c32..0 = 3)(R[rc] = 0) (c32..0 = 4)R[rc]31 (c32..0 = 5)R[rc]31
Page 18
4-37
Computation of the Conditional Value CON

IR2..0 3 Bus From Figure 4.3
D Q 32 CON in CON
Decoder 5 4 3 2 1
0 1 =0 0
32
Cond logic
c32..0
31 31..0
0 <0 CONin
D Q CON Q
NOR gate does = 0 test of R[rc] on bus

4-38
Control Sequence for SRC Branch Instruction, br

br (:= op = 8) (cond PC R[rb]): Step T0T2 T3 T4 Concrete RTN Instruction fetch CON cond(R[rc]); CON PC R[rb]; Control Sequence Instruction fetch Grc, Rout, CONin Grb, Rout, CON PCin, End
Condition logic is always connected to CON, so R[rc] only needs to be put on bus in T3 Only PCin is conditional in T4 since gating R[rb] to bus makes no difference if it is not used
Page 19
4-39
Summary of the Design Process

Starting with informal description formal RTN description block diagram architecture concrete RTN steps hardware design of blocks control sequences control unit and timing At each level, more decisions must be made
These decisions refine the design Also place requirements on hardware still to be designed
The nice one-way process above has circularity

Decisions at later stages cause changes in earlier ones Happens less in a text than in reality because Can be fixed on re-reading Confusing to first-time student
4-40
Clocking the Data Path: Register Transfer Timing

Source register D Q R1 CK Q Rin n Rout Combinational logic Bus gate n-bit bus Logic block Destination register D Q R2 CK Q
Circuit propagation delay
Gate prop. time, tg
Bus prop. delay, tbp
ALU, etc. delay, tcomb
Latch prop. delay, tl
Gate signal: Rout
Latch hold time, th Latch setup time, tsu
tR2valid is the period from begin of gate signal till inputs to R2 are valid tcomb is delay through combinational logic, such as ALU or cond logic
Strobe signal: Rin tR2valid Minimum pulse width, tw
Minimum clock period, tmin

Page 20
4-41
The Control Unit

The control units job is to generate the control signals in the proper sequence Things the control signals depend on
The time step Ti The instruction opcode (for steps other than T0, T1, T2) Some few data path signals like CON, n = 0, etc. Some external signals: reset, interrupt, etc. (to be covered)
The components of the control unit are: a time state generator, instruction decoder, and combinational logic to generate control signals
4-42
Control Unit Detail with Inputs and Outputs
Page 21
4-43
Synthesizing Control Signal Encoder Logic

Step
T0. T1. T2.
Control Sequence
PC out , MA , Inc4, C , Read in in Cout, PC in, Wait MD , IR out in
add
Step T3. T4. T5. Control Sequence Step Grb, R ,A T3. out in Grc, R , ADD, C T4. out in R , End C , T5. out Gra, in
addi
Control Sequence Step Grb, R ,A T3. out in c2 , ADD, C T4. out in T5. C , R , End out Gra, in T6. T7.
st
Control Sequence Step Grb, BA ,A T3. out in c2 , ADD, C T4. out in Cout, MA in T5. T6. R , MD , Write Gra, out in
Wait, End c1 out
shr
Control Sequence
, Ld , Ld) out n=0 (Grc, R
Grb, Rout, C=B n0 (C out, SHR, C in, Decr, Goto7) C , out
T7.
Gra, Rin, End
Design process: Comb through the entire set of control sequences. Find all occurrences of each control signal. Write an equation describing that signal. Example: Gra = T5(add + addi) + T6st + T7shr + ...
4-44
Use of Data Path Conditions in Control Signal Logic

Step
T0. T1. T2.
Control Sequence
PCout, MAin, Inc4, Cin, Read Cout, PCin, Wait MDout, IRin
add
Step T3. T4. T5. Control Sequence Step Grb, Rout, Ain T3. T4. Grc, Rout, ADD, Cin T5. Cout, Gra, Rin, End
addi
Control Sequence Step Grb, Rout, A in T3. c2 , ADD, C T4. out in Cout, Gra, Rin, End T5. T6. T7.
c2
st
Control Sequence Step Grb, BA out, Ain T3.
, ADD, C out in Cout, MAin Gra, R out, MDin, Write Wait, End
shr
Control Sequence
c1out, Ld
T4. T5. T6. T7.
n=0 (Grc, Rout, Ld)

Grb, Rout, C=B n0 (C , SHR, C , out in Decr, Goto7) Cout, Gra, Rin, End
Example: Grc = T4add + T4(n=0)shr + ...
Page 22
4-45
Generation of the logic for Cout and Gra
...
T1 T5 add
Cout
...
add addi
T5 T7 ld
...
Gra
...
4-46
Page 23
4-47
Branching in the Control Unit

3-state gates allow 6 to be applied to counter input Reset will synchronously reset counter to step T0
4-48
Page 24
4-49
The Clocking Logic: Start, Stop, and Memory Synchronization
Mck is master clock oscillator

4-50
The Complete 1-Bus Design of SRC

High-level architecture block diagram Concrete RTN steps Hardware design of registers and data path logic Revision of concrete RTN steps where needed Control sequences Register clocking decisions Logic equations for control signals Time step generator design Clock run, stop, and synchronization logic
Page 25
4-51
Other Architectural Designs Will Require a Different RTN

More data paths allow more things to be done in one step Consider a two bus design By separating input and output of ALU on different buses, the C register is eliminated Steps can be saved by strobing ALU results directly into their destinations
4-52
The 2-Bus SRC Microarchitecture

A bus ( In bus ) 32 32 general purpose registers 31 0 R0 B bus (Out bus ) 32
R31 IR PC MA Memory bus MD A
Bus A carries data going into registers Bus B carries data being gated out of registers ALU function C = B is used for all simple register transfers
A ALU C
Page 26
4-53
The 2-Bus add Instruction
Step T0 T1 T2 T3 T4
Concrete RTN Control Sequence MA PC; PCout, C = B, MAin, Read PC PC + 4: MD M[MA];PCout, INC4, PCin, Wait IR MD; MDout, C = B, IRin A R[rb]; Grb, Rout, C = B, Ain R[ra] A + R[rc]; Grc, Rout, ADD, Sra, Rin, End
A bus ( In bus ) 32 31 32 general purpose registers 0 R0 B bus (Out bus ) 32
Note the appearance of Grc to gate the output of the register rc onto the B bus and Sra to select ra to receive data strobed from the A bus Two register select decoders will be needed
R31 IR PC MA MD A A ALU B Memory bus
1997 V. Heuring and H. Jordan C
4-54
Performance and Design
%Speedup
T 1 bus T 2 bus 100 T 2 bus CPI
Where T = Exec' n.Time = IC
Page 27
4-55
Speedup By Going to 2 Buses

Assume for now that IC and dont change in going from 1 bus to 2 buses Naively assume that CPI goes from 8 to 7 clocks.
%Speedup =
T1 bus T 2 bus 100 T 2 bus
IC 8 IC 7 87 100 = 100 = 14% IC 7 7
Class Problem: How will this speedup change if clock period of 2-bus machine is increased by 10%?
4-56
3-Bus Architecture Shortens Sequences Even More

A 3-bus architecture allows both operand inputs and the output of the ALU to be connected to buses Both the C output register and the A input register are eliminated Careful connection of register inputs and outputs can allow multiple RTs in a step
Page 28
4-57
The 3-Bus SRC Design

C bus 32 31 32 general purpose registers 0 R0 A bus B bus 32 32
R31 IR PC MA Memory bus MD
A-bus is ALU operand 1, B-bus is ALU operand 2, and C-bus is ALU output Note MA input connected to the B-bus
A ALU C
4-58
The 3-Bus add Instruction
Step Concrete RTN T0 MA PC: MD M[MA]; PC PC + 4: T1 IR MD; T2 R[ra] R[rb] + R[rc];

Note the use of 3 register selection signals in step T2: GArc, GBrb, and Sra In step T0, PC moves to MA over bus B and goes through the ALU INC4 operation to reach PC again by way of bus C
PC must be edge-triggered or master-slave
Control Sequence PCout, MAin, INC4, PCin, Read, Wait MDout, C = B, IRin GArc, RAout, GBrb, RBout, ADD, Sra, Rin, End
C bus 32 31 32 general purpose registers 0 R0 32 32
A bus B bus
R31 IR PC MA Memory bus MD
A ALU C
Page 29
4-59
Performance and Design

How does going to three buses affect performance? Assume average CPI goes from 8 to 4, while increases by 10%:
% Speedup =
IC
IC 4 IC 4 1 . 1
1 . 1
100
8 4 .4 4 .4
100
82 %
4-60
Processor Reset Function

Reset sets program counter to a fixed value
May be a hardwired value, or contents of a memory cell whose address is hardwired
The control step counter is reset Pending exceptions are prevented, so initialization code is not interrupted It may set condition codes (if any) to known state It may clear some processor state registers A soft reset makes minimal changes: PC, T (trace) A hard reset initializes more processor state
Page 30
4-61
SRC Reset Capability

We specify both a hard and soft reset for SRC The Strt signal will do a hard reset
It is effective only when machine is stopped It resets the PC to zero It resets all 32 general registers to zero
The Soft Reset signal is effective when the machine is running

It sets PC to zero It restarts instruction fetch It clears the Reset signal
Actions are described in instruction_interpretation
4-62
Abstract RTN for SRC Reset and Start

Processor State Strt: Rst:
Start signal External reset signal
instruction_interpretation := ( RunStrt (Run 1: PC, R[0..31] 0); RunRst (IR M[PC]: PC PC + 4; instruction_execution): RunRst ( Rst 0: PC 0); instruction_interpretation):
Page 31
4-63
Resetting in the Middle of Instruction Execution

The abstract RTN implies that reset takes effect after the current instruction is done To describe reset during an instruction, we must go from abstract to concrete RTN Questions for discussion:
Why might we want to reset in the middle of an instruction? How would we reset in the middle of an instruction?
4-64
The add Instruction with Reset Processing

Step T0 T1 T2 T3 T4 T5 Concrete RTN Rst (MA PC: C PC + 4): Rst (Rst 0: PC 0: T 0): Rst (MD M[MA]: P C): Rst (Rst 0: PC 0: T 0): Rst (IR MD): Rst (Rst 0: PC 0: T 0): Rst (A R[rb]): Rst (Rst 0: PC 0: T 0): Rst (C A + R[rc]): Rst (Rst 0: PC 0: T 0): Rst (R[ra ] C): Rst (Rst 0: PC 0: T 0):
See text for the corresponding control signals

Page 32
4-65
Control Sequences Including the Reset Function

Step Control Sequence T0 Reset (PCout, MAin, Inc4, Cin, Read): Reset (ClrPC, ClrR, Goto0): T1 Reset (Cout, PCin, Wait): Reset (ClrPC, ClrR, Goto0):
ClrPC clears the program counter to all zeros, and ClrR clears the 1-bit Reset flip-flop Because the same reset actions are in every step of every instruction, their control signals are independent of time step or opcode
4-66
General Comments on Exceptions

An exception is an event that causes a change in the program specified flow of control Often called interrupts We will use exception for the general term and use interrupt for an exception caused by an external event, such as an I/O device condition The usage is not standard. Other books use these words with other distinctions, or none
Page 33
4-67
Combined Hardware/Software Response to an Exception

The system must control the type of exceptions it will process at any given time The state of the running program is saved when an allowed exception occurs Control is transferred to the correct software routine, or handler, for this exception This exception, and others of less or equal importance, are disallowed during the handler The state of the interrupted program is restored at the end of execution of the handler
4-68
Hardware Required to Support Exceptions

To determine relative importance, a priority number is associated with every exception Hardware must save and change the PC, since without it no program execution is possible Hardware must disable the current exception lest is interrupt the handler before it can start Address of the handler is called the exception vector and is a hardware function of the exception type Exceptions must access a save area for PC and other hardware saved items
Choices are special registers or a hardware stack
Page 34
4-69
New Instructions Needed to Support Exceptions

An instruction executed at the end of the handler must reverse the state changes done by hardware when the exception occurred There must be instructions to control what exceptions are allowed
The simplest of these enable or disable all exceptions
If processor state is stored in special registers on an exception, instructions are needed to save and restore these registers
4-70
An Interrupt Facility for SRC

The exception mechanism for SRC handles external interrupts There are no priorities, but only a simple enable and disable mechanism The PC and information about the source of the interrupt are stored in special registers
Any other state saving is done by software
The interrupt source supplies 8 bits that are used to generate the interrupt vector It also supplies a 16-bit code carrying information about the cause of the interrupt
Page 35
4-71
SRC Processor State Associated with Interrupts

Processor interrupt mechanism Interrupt request signal From Device ireq: iack: Interrupt acknowledge signal To Device IE: 1-bit interrupt enable flag Internal IPC 31..0 : Storage for PC saved upon interrupt to CPU II 31..0 : Information on source of last interrupt to CPU Isrc_info 15..0 : Information from interrupt source From Device Isrc_vect 7..0 : Type code from interrupt source From Device Internal Ivect31..0:= 20@0#Isrc_vect7..0#4@0:
000 . . . 0 31
Ivect31..0 Isrc_vect7..0 0000 12 11 4 3 0

4-72
SRC Instruction Interpretation Modified for Interrupts

instruction_interpretation := (RunStrt Run 1: Run(ireqIE) (IR M[PC]: PC PC + 4; instruction_execution): Run(ireqIE) (IPC PC 31..0: II15..0 Isrc_info15..0: iack 1: IE 0: PC Ivect31..0 ; iack 0); instruction_interpretation); If interrupts are enabled, PC and interrupt information are stored in IPC and II, respectively
With multiple requests, external priority circuit (discussed in later chapter) determines which vector and information are returned
Interrupts are disabled The acknowledge signal is pulsed

Page 36
4-73
SRC Instructions to Support Interrupts

Return from interrupt instruction
rfi (:= op = 29 ) (PC IPC: IE 1):
Save and restore interrupt state

svi (:= op = 16) (R[ra] 15..0 II15..0 : R[rb] IPC31..0): ri (:= op = 17) (II 15..0 R[ra]15..0 : IPC31..0 R[rb]):
Enable and disable interrupt system

een (:= op = 10 ) (IE 1): edi (:= op = 11 ) (IE 0): The 2 rfi actions are indivisible, cant een and branch
4-74
Concrete RTN for SRC Instruction Fetch with Interrupts

Step (ireqIE) Concrete RTN (ireqIE) T0 ((ireqIE) ( (ireqIE) (IPC PC: II Isrc_info: MA PC: C PC+4): IE 0: PC 20@0#Isrc_vect 7..0#0000: Iack1; Iack 0: End); T1 MD M[MA] : PC C; T2 IR MD; PC could be transferred to IPC over the bus II and IPC probably have separate inputs for the externally supplied values iack is pulsed, described as 1; 0, which is easier as a control signal than in RTN
Page 37
4-75
Recap of the Design Process: the Main Topic of Chapter 4

Informal description Formal RTN description Block diagram architecture Concrete RTN steps Chapter 4 Hardware design of blocks Control sequences Control unit and timing
SRC Chapter 2
4-76
Chapter 4 Summary
Chapter 4 has done a nonpipelined data path and a hardwired controller design for SRC The concepts of data path block diagrams, concrete RTN, control sequences, control logic equations, step counter control, and clocking have been introduced The effect of different data path architectures on the concrete RTN was briefly explored We have begun to make simple, quantitative estimates of the impact of hardware design on performance Hard and soft resets were designed A simple exception mechanism was supplied for SRC
Page 38

04 HJ Ch04 p2

Загружено:

Сведения о документе

Исходное описание:

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

04 HJ Ch04 p2

Загружено:

Авторское право:

Доступные форматы

4-1

Chapter 4Processor Design

Chapter 4: Processor Design

Computer Systems Design and Architecture by V. Heuring and H. Jordan

1997 V. Heuring and H. Jordan

Chapter 4Processor Design

Block Diagram of 1-Bus SRC

Computer Systems Design and Architecture by V. Heuring and H. Jordan

1997 V. Heuring and H. Jordan

Chapter 4Processor Design

High-Level View of the 1-Bus SRC Design

Computer Systems Design and Architecture by V. Heuring and H. Jordan

1997 V. Heuring and H. Jordan

Chapter 4Processor Design

Constraints Imposed by the Microarchitecture

MA B ALU C C To memory subsystem MD

Chapter 4Processor Design

Abstract and Concrete RTN for SRC add Instruction

MA A ALU C C B To memory subsystem MD

Chapter 4Processor Design

Concrete RTN Gives Information About Sub-units

Computer Systems Design and Architecture by V. Heuring and H. Jordan

1997 V. Heuring and H. Jordan

Chapter 4Processor Design

Concrete RTN for Arithmetic Instructions: addi

MA A ALU C C B To memory subsystem MD

Chapter 4Processor Design

Computer Systems Design and Architecture by V. Heuring and H. Jordan

1997 V. Heuring and H. Jordan

Chapter 4Processor Design

Abstract and Concrete RTN for Load and Store

Chapter 4Processor Design

Notes for Load and Store RTN

Computer Systems Design and Architecture by V. Heuring and H. Jordan

1997 V. Heuring and H. Jordan

Chapter 4Processor Design

Concrete RTN for Conditional Branch

The Branch Instruction, br

RTN Instruction fetch CON cond(R[rc]); CON PC R[rb];

Computer Systems Design and Architecture by V. Heuring and H. Jordan

Chapter 4Processor Design

Notes on Conditional Branch RTN

Computer Systems Design and Architecture by V. Heuring and H. Jordan

1997 V. Heuring and H. Jordan

Chapter 4Processor Design

Abstract and Concrete RTN for SRC Shift Right

Computer Systems Design and Architecture by V. Heuring and H. Jordan

Chapter 4Processor Design

Notes on SRC Shift RTN

Computer Systems Design and Architecture by V. Heuring and H. Jordan

1997 V. Heuring and H. Jordan

Chapter 4Processor Design

Computer Systems Design and Architecture by V. Heuring and H. Jordan

1997 V. Heuring and H. Jordan

Chapter 4Processor Design

The Register File and Its Control Signals

BAout differs from Rout by gating 0 when R[0] is selected

Rin Rout BAout

Computer Systems Design and Architecture by V. Heuring and H. Jordan

Chapter 4Processor Design

Computer Systems Design and Architecture by V. Heuring and H. Jordan

1997 V. Heuring and H. Jordan