EXPERIMENT D4: ADDER AND COUNTER Related course: KEEE2232 (Digital Design) OBJECTIVES: To design a 1-bit half adder

To understand the design of a synchronous counter and to observe the outputs from simulation EQUIPMENT: MAX+Plus II software PREPARATIONS: Students are required to first learn and understand about MAX+Plus n software, ALTERA University Program board and VHDL before starting the experiment. REFERENCE(S): Refer to the main references of KEEE2232 (Digital Design) TESTS: TEST 1: Adder TEST 2: Counter TEST 1: Adder A. Half Adder a) Designing half adder circuit 1. Using Graphic Editor, open a new file and save it with a name of halfadder.gdf. 2. From File menu, set "Project to current file". 3. Place components by double-clicking at the position that the component needs to be placed. 4. Draw the circuit shown in Figure 1 using not, and2, or2, input and output from prim library. 5. Save the file and check for any error in the circuit (File->Project). 6. Build symbol from the circuit by selecting File->Create Default Symbol. 7. From MAX +Plus II menu, open Compiler and check for errors. b) Adding waveform for simulation 1. If there is no error, then the circuit can be simulated. 2. Before doing the simulation, a waveform is needed. Open Waveform Editor. 3. Choose the node that is needed (Use Enter Nodes from SNF in Node submenu). 4. List down all nodes by clicking on List button. Choose all nodes that are needed and move those nodes into a box on the right-hand side by using arrow button. 5. Form the following waveform to test the circuit. 6. To change the grid size for time, use Grid Size from Options submenu. 7. Save the file.

Last updated on 19th January 2014

Figure 1: 1-bit half adder

c) Simulation 1. Open Simulation from MAX+Plus II menu. 2. Begin simulation by clicking on START button. 3. Simulation results can be observed by opening SCF file (Open SCF button). B. Full adder 1. Open a new project file and name it as fulladder.gdf. 2. Using Graphic Editor, draw the circuit shown in Figure 2. 3. Half Adder symbol can be inserted by using Enter Symbol from Symbol menu. 4. Save the file and compile it. Build FullAdder symbol to be used later (File>Create Default Symbol). 5. By using the same steps for the half adder, form the waveform for simulation.

Last updated on 19th January 2014

Figure 2: Full adder C. 4-bit adder 1. By using FullAdder symbol, design a 4-bit adder using 4 blocks of full adder. 2. Connect Cout pin for FullAdder to Cin pin for the next full adder. 3. Compile the file and form the waveform for simulation. 4. 4. RUIl simulation and make sure the outputs are correct. EXERCISE: 1. Build the truth table for a 1-bit full adder. 2. Draw the 4-bit adder circuit using logic gates. TEST 2: COUNTER 1. By using MAX+Plus II, draw the circuit in Figure 3 in Graphic Editor and save the file as syncounter.gdf. 2. Compile the file and correct the errors if any. 3. Set CLK by right-clicking the mouse and set Overwrite->clock. Press OK. This is done in Waveform Editor. 4. Simulate the waveform. 5. Obtain the waveform generated from the simulation. EXERCISE: Design a 3-bit synchronous counter using JK flip-flops that will count according to the following sequence: 000->001->011-> I 0 1->000. Show all the steps by using K-map. Assume that the values not staled in the sequence will go to 000.

Last updated on 19th January 2014

Figure 3

END OF EXPERIMENT

Last updated on 19th January 2014