Design and Experiment of a Back-To-Back (BTB) System Using Modular Multilevel Cascade Converters for Power Distribution Systems

Pracha Khamphakdi, Student Member, IEEE, Kei Sekiguchi, Makoto Hagiwara, Member, IEEE, and Hirofumi Akagi, Fellow, IEEE Department of Electrical and Electronic Engineering Tokyo Institute of Technology, Tokyo, Japan E-mail: akagi@ee.titech.ac.jp

Abstract This paper presents an application of the modular multilevel cascade converter based on double-star chopper-cells (MMCC-DSCC) to a back-to-back (BTB) system for installation on 6.6-kV power distribution systems. The DSCC is characterized by a cascade connection of multiple chopper-cells per leg, leading to exible circuit design, low voltage steps, low EMI emission, and low harmonic voltage and current. The DSCC-based BTB system is equipped with neither dc capacitor nor voltage sensor on the common dc link. The paper designs, constructs, and tests a three-phase, 200-V, and 10-kW downscaled system to verify and justify its operating principles and performance. Experimental and simulated results agree well with each other, showing a promising possibility of the DSCC-based BTB system. Index Terms Back-to-back systems, grid-connected converters, modular multilevel cascade converters (MMCC)

Feeder 1 66 kV / 6.6 kV Loads Primary Distribution Transformer Feeder 2 BTB System

Loads Distibuted Power Generators Fig. 1. A 6.6-kV power distribution system consisting of two radial feeders.

I. I NTRODUCTION The global warming, one of critical issues in environment, has resulted in calling for review in a new way of electric power generation. The goal of the way is to reduce CO2 emission by means of replacing a part of conventional fossilfuel power plants with renewable energy sources such as solar power and wind power. This type of generation is called often as distributed generators, because most of them are installed on power distribution systems. Fig. 1 shows a simplied utility power distribution system consisting of two 6.6-kV radial feeders in Japan, where feeder 1 has no distributed generator whereas feeder 2 has many distributed generators. As a result, the so-called back feed may occur throughout feeder 2, so that the grid voltage at the load end of feeder 2 increases while that of feeder 1 decreases. This may cause voltage imbalance between the two feeders, thus making it difcult for both feeders to comply with the utility voltage code [1]. A back-to-back (BTB) system intended for installation between the ends of the two 6.6-kV distribution feeders, was designed, constructed, and tested to mitigate the voltage imbalance. This type of BTB system is referred to as a loop balance controller in [2]. However, the BTB system with a common dc-link voltage of 13.2 kV suffered from supply (line) harmonic currents as well as EMI emissions because it is based on traditional two-level PWM converters with a string of eight series-connected 3.3-kV IGBTs per arm. Recently, attention has been paid to the so-called modular multilevel converter (MMC) for high-voltage and high-power applications such as long-distance high-voltage direct-current

(HVDC) transmission systems and BTB systems [3], [4]. However, the use of the MMC in either title or contents of technical papers or articles may cause confusion about terminology if the reader is not an expert of multilevel converters. To avoid this confusion, the author of [5] classied modular multilevel converters from circuit topology, combining the family name, modular multilevel cascade converter with different given names. For example, the modular multilevel cascade converter based on single-star bridge-cells (MMCCSSBC) is suitable for STATCOMs and battery energy storage systems, while the modular multilevel cascade converter based on double-star chopper-cells (MMCC-DSCC) can achieve bidirectional (ac-to-dc and dc-to-ac) power conversion. Note that the MMCC-DSCC (hereinafter, just called as the DSCC) is the same in circuit conguration as the MMC in a narrow sense. Many technical papers described the DSCC, as well as its applications to HVDC and BTB systems, with focus on control, modeling, analysis, and/or system design [6][12]. However, their authors have conrmed the validity of their papers by carrying out computer simulation without experimental verication. Siemens [13] has put the DSCC-based HVDC systems into practical use with a trade name of HVDCplus. All the papers published from Siemens have made neither description of achieving dc-capacitor-voltage balancing of all the chopper-cells and regulating the common dc-link voltage, nor disclosure of presenting experimental waveforms. Moreover, no comparison has been made in voltage and current waveforms between experiment and simulation for the purpose of enhancing their reliability. This paper has an intensive discussion on a DSCC-based BTB system intended for installation on the 6.6-kV distribution feeders. This BTB system is characterized by installing neither common dc-link capacitor nor voltage sensor on the

978-1-4799-0482-2/13/$31.00 2013 IEEE

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 1 8 cell cell 1 8

DSCC-A cell cell cell cell

(= )

respectively. The instantaneous active power at the dc link, , is given by = . (1)

DSCC-B

B. Circuit Equations In Fig 2(a), and are the positive and negative arm currents, and is the supply current. The following equations exist = + , (2)

9 16

cell cell

9 16

cell cell

cell cell

(a)

( : 1 16)

1 ( + ), (3) 2 where is the circulating current along the dc loop in the -phase leg, which is dened in [6]. Note that contains only a dc component under an ideal condition [6]. From (2) and (3), the arm currents and can be expressed by using and as follows: = 1 = , 2 (4)

(b)

(c)

Fig. 2. Circuit conguration for the DSCC-based BTB system with 16 cells/leg. (a) Main power circuit. (b) Chopper-cell. (c) Center-tapped inductor (or coupled inductor).

common dc link. Modeling and analysis are done for regulating the common dc-link voltage to a preset reference voltage. A three-phase, 200-V, and 10-kW downscaled system is designed, constructed, and tested to verify the validity of the whole control system in steady and transient conditions. In addition, computer simulation using a software package of PSCAD/EMTDC is executed under the same conditions as the experiment using the downscaled system. Experimental waveforms agree with simulated ones well enough to guarantee the reliability of both experiment and simulation. II. C IRCUIT C ONFIGURATION AND E QUATIONS A. Circuit Conguration Fig. 2(a) shows the circuit conguration for the DSCCbased BTB system. Each leg consists of a cascade connection of 16 chopper-cells depicted in Fig. 2(b), and a center-tapped inductor in Fig. 2(c). Each chopper-cell consisting of a dc capacitor and two IGBTs forms the so-called bidirectional chopper. Here, is the low-voltage-side voltage of each chopper-cell, and is the high-voltage-side voltage of each chopper-cell. Two terminals of the center-tapped inductor, a and b are connected to the positive and negative arms, and terminal c is connected to an ac-link inductor sitting at the front end of the DSCC-A. The dc terminal at the back end is directly connected to that of the DSCC-B without any dc-link capacitor. Let the common dc-link current and voltage be and ,

1 (5) = + . 2 Note that , , and are the branch currents, while is the loop current that cannot be measured directly. The dc-link current can be expressed from Kirchhoffs current law (KCL) as follows: = = =
=,,

1 ( ), 2 =,, .
=,,

(6)

where the relation of + + = 0 is utilized. Equation (6) means that the supply currents produce no effect on the dc-link current . Each arm of the DSCC in Fig. 2(a) is represented by a voltage source equal to the sum of the low-voltage-side voltages of the chopper-cells. For example, of the DSCC-A, the -phase collective positive-arm and negative-arm voltages, and , are expressed as follows:
/2 =1 =1+ 2

(7)

(8)

312

where is the number of the chopper-cells per leg. The -phase collective leg voltage of the DSCC-A, , is obtained from (7) and (8) as = + =
=1

This assumption is valid because the six legs are operated in the same way, especially in terms of the dc components. Substituting (13) into (11) yields = . (14)

(9)

The following equation exists in the -phase leg of the DSCCA as . (10) The center-tapped inductor presents inductance only to the circulating current , and no inductance to the supply current [6]. In other words, provides no effect on the voltage across the center-tapped inductor. Finally, making reference to the Appendix can express and as ) ( 1 = + , (11) 6 =,, =,, = + 1 = 2 (
=,,

Equation (9) indicates that contains no fundamentalfrequency component, because those included in and cancel out each other. Hence, contains only a dc component if the switching-ripple components are ignored. Let the dc component included in be () . Equation (14) is changed from (9) to = () . (15)

The chopper-cell can produce an arbitrary dc voltage, so long as it is lower than the dc-capacitor voltage [6]. This paper sets () as follows: 1 , (16) 2 where is the average value of all the dc-capacitor voltages used for the BTB system. Substituting (16) into (15) yields () = 1 . (17) 2 Equation (17) means that can be regulated by adjusting . For example, is regulated at 400 V when = 50 V and = 16. It is possible to force to follow the reference by applying an appropriate feedback control of the dc capacitor voltages, which has already proposed in [6] and [7]. This method is characterized by indirectly regulating , thus making it possible to eliminate a voltage sensor and a dc capacitor from the common dc-link of the BTB system. = B. Control of the DC-Link Current Equation (6) means that the dc-link current is expressed by the circulating currents. This implies that can be adjusted indirectly by controlling these circulating currents. The reference for the dc-link current, , is given by = , /2 (18)

=,,

) . (12)

Equation (11) means that is equal to the average value of all the low-voltage-side voltages of the chopper-cells used in the BTB system. Moreover, is independent of and . Equation (12) means that the dc-link current can be controlled by adjusting a voltage difference between the sum of the low-voltage-side voltages of the DSCC-A and that of the DSCC-B. III. C ONTROL M ETHOD The control method for the DSCC-based BTB system can be classied into the following four parts: control of instantaneous active and reactive power [16] at the ac mains, voltage control of the oating dc capacitors, control of the dc-link voltage, and control of the dc-link current. The power control is achieved by using the synchronous reference frames along with the decoupled current control. The voltage control of the dc capacitors can be achieved by applying the control method proposed in [6] and [7]. Note that the aim of the voltage control is not to regulate the instantaneous voltage of each dc capacitor, but to regulate the mean voltage with the help of a moving-average lter of 50 Hz [8]. A. Control of the DC-Link Voltage The following reasonable assumption is made in (11):
=,,

where is the active power reference and /2 corresponds to the dc-link voltage as predicted from (17). The references for the circulating currents of the DSCC-A and the DSCC-B, and , are expressed as . (19) 3 Note that each chopper-cell should produce an amount of voltage for adjusting the corresponding circulating current [6]. For example, each chopper-cell in the -phase leg of the DSCC-A produces the voltage that is given by
= =

=,,

= 6 .

(13)

313

Fig. 2(a) DSCC-A 200 V 50 Hz 200 V/200 V PT (= 0) 2 48 MUX 6

DSCC-B

200 V/200 V

6 96 6 96 48 MUX 6 2

PT

gate signals

MUX : Multiplexer

DSP (TMS320C6713)

FPGA-A (Altera Cyclone II) A/D Converters

FPGA-B (Altera Cyclone II) A/D Converters

Fig. 3.

Overview of the three-phase, 200-V, and 10-kW experimental system.

TABLE I

( ), (20) where is the feedback gain. Considering the above equation allows the -phase collective leg voltage of the DSCC-A, , to be changed from (14) to the following equation: = = + . (21)

C IRCUIT PARAMETERS USED IN THE EXPERIMENT AND SIMULATION

The similar equations exist in the other ve legs. Equations (6), (19), and (20) produce the following equation:
=,,

=,,

( ).

Rated power 10 kW Nominal line-to-line rms voltage 200 V Nominal line frequency 50 Hz AC-link inductor 2 mH (16%)* Coupled inductor 3 mH (24%)* Number of chopper-cells per leg 16 DC-link voltage 400 V DC-capacitor voltage 50 V (= 400 V/8) DC-capacitor 6.6 mF Unit capacitance constant [15] 40 ms at 50 V PWM carrier frequency 450 Hz Switching-ripple frequency 16 7.2 kHz *These values are on a 200-V, 10-kW, and 50-Hz base.

(22) ac-link inductors = 2.0 mH (16%) and a line-frequency transformer with unity voltage ratio for galvanic isolation. The center-tapped inductor shown in Fig. 2(c) has an inductance value of = 3.0 mH (24%). Although the inductance value of is larger than that of , the size of the center-tapped inductor is half of the ac-link inductor in volume because presents no inductance to the supply current. The capacitance value of the dc capacitor is = 6.6 mF, which corresponds to = 40 ms in the unit capacitance value [15]. Each chopper-cell uses four power MOSFETs connected in parallel as a power switch for reducing the conduction loss, thus making the experimental system more reliable and effective as a downscaled system of the 6.6-kV BTB system. The reference = 50 V. Note value for the dc-capacitor voltage is set as that neither electric capacitor nor lm capacitor is connected to the common dc-link terminals. The control systems consists of a digital signal processor (DSP) unit using the Texas Instruments TMS320C6713 and two eld-programmable gate array (FPGA) units using the Altera Cyclone II. Each FPGA unit including A/D converters detects the 48 dc-capacitor voltages, the positive and negative arm currents, and the ac-mains voltages. These signals are sent

The dc-link current can be expressed from (12), (21), and (22) as follows: 1 2 [
=,,

= =

=,,

] (23)

( ).

Hence, the actual dc-link current exhibits a rst-order response to its reference with a time constant of / . Moreover, can be controlled, independent of . IV. E XPERIMENT AND S IMULATION A. System Conguration Used for Experiment and Simulation Fig. 3 shows the overview of the three-phase, 200-V, and 10kW experimental system, that is used as a downscaled system of the 6.6-kV BTB system. Table I summarizes the circuit parameters used in experiment and simulation. Each DSCC has eight chopper-cells per arm. Hence, the total number of chopper-cells used for the BTB system is 96 (= 862). Each DSCC is connected to the three-phase 200-V ac mains via

314

[V] 400 0 -400 [V] 400 0 -400 50 [A] 0 -50 50 [A] [A] 0 -50 50 0

20 ms

THD of = 0.24%

0 -50 50 [A] [A] 0 -50 50 0

[V] 400 0 -400 [V] 400 0 -400 50 [A]

20 ms

THD of = 0.25%

-50 75 [V] 1 50 9 25 0 [V] 600 400 200 0 50 0 -50 Fig. 4. kVA).

-50 75 [V] 1 50 9 25 0 [V] 600 400 200 0 50 0 -50 Fig. 5. kVA).

() = 77.8 V

() = 84.3 V

24.7 A [A]

24.6 A

[A]

Experimental waveforms during rectication ( = 10 kW, = 0

Simulated waveforms during rectication ( = 10 kW, = 0

to the A/D converters. Note that the dc-link voltage is not detected. Here, the multiplexer (MUX) unit is used to reduce the number of A/D converters from 48 to six. The FPGA unit produces 96-bit (= 2 48) gate signals in total, because each chopper-cell includes two power switches. The experimental waveforms were taken by using a personal computer via the Yokogawa WE7000 PC-based data acquisition system. The sampling frequency is 100 kHz in Figs. 4 and 5, and 50 kHz in Figs. 6 and 7. The PSCAD/EMTDC software package is used for simulation. The following conditions are considered: one-sampling delay of 140 s (= 1/(16 )) resulting from digital control, and a dead time of 8 s, and each chopper-cell uses ideal power switches with no switching interval of time. B. Operating Performance Under Steady-State Conditions Fig. 4 shows the experimental waveforms when the DSCCA acts as a rectier ( = 10 kW and = 0 kVA). Here, and represent the power references for the instantaneous active and reactive powers at the ac mains. Note that has a positive value when active power is transferred from the DSCC-A to the DSCC-B, and vice versa. The ac-terminal (front-end) line-to-line voltages , , and get multilevel PWM waveforms with a voltage step of 25 V (= 400 V/16). As a consequence,

they contain much less harmonic voltages and much less common-mode voltage than a traditional two-level voltagesource PWM inverter. Since the carrier frequency of each chopper-cell is 450 Hz, the switching-ripple frequency is 7.2 kHz (= 450 Hz16). As a result, the waveforms of the supply currents , , and look purely sinusoidal with a 50-Hz fundamental-frequency component. The total harmonic distortion (THD) value of is less than 1%. The arm currents, and , contain dc components, 50-Hz fundamental-frequency components, 3.6-kHz (= 450 Hz8) switching-ripple components, and 100-Hz secondorder harmonic components resulting from the control system [6]. However, no 100-Hz component appears in because those included in and cancel out each other. The circulating current contains a dc component of 8.3 A (= 10kW /(3 400V )), the 3.6-kHz switching-ripple component, and the 100-Hz second-order harmonic component. However, the 100-Hz component is small enough compared to the dc component in terms of amplitude. The dc-capacitor voltages 1 and 9 contain both dc and ac components, as shown in Fig. 4, where the voltage control regulates the dc component at 50 V. The ac components consist of the most dominant 50-Hz component and the second dominant 100-Hz component. Both components are proportional to the amplitude of , and inversely proportional to [18]. The mean dc-link voltage is regulated at 400 V without any steady-state error because each dc-capacitor

315

100 ms [kW] 10 0 -10 [kW] 10 0 -10

100 ms

[V] 400 0 -400 [V] 400 0 -400 50 [A] 0 -50 50 [A] 0 -50 50 [A] 0 -50 75 [V] 50 1 9 25 0 [V] 600 400 200 0 50 0 -50

[V] 400 0 -400 [V] 400 0 -400 50 [A] 0 -50 50 [A] 0 -50 50 [A] 0 -50 75 [V] 50 1 9 25 0 [V] 600 400 200 0 50 0 -50

9 1

9 1

() = 101.7 V

() = 101.1 V

24.6 A 24.3 A [A]

24.3 A

[A]

24.5 A

Fig. 6. Experimental waveforms during transient state from the rated rectication to inversion mode

Fig. 7. Simulated waveforms during transient state from the rated rectication to inversion mode

voltage is regulated at 50 V. The dc-link current has a dc component of 25 A, which agrees well with the theoretical value obtained from (18). Fig. 5 shows the simulated waveforms when the DSCCA acts as a rectier ( = 10 kW and = 0 kVA). This simulation was carried out under the same conditions as the experiment. Comparing Fig. 4 with 5 shows that both waveforms agree well with each other, bringing high reliability to both experiment and simulation. C. Operating Performance under a Transient-State Condition Figs. 6 and 7 show the experimental and simulated waveforms of the DSCC-A, in which the active-power reference is changed from 10 kW to 10 kW under a ramp change in 100 ms. Here, is set to zero. This means that the DSCC-A changes its operation from rectication to inversion. Comparing Fig. 6 with 7 reveals that experiment and simulation agree well with each other even under such a transient-state condition. No overcurrent occurs in the supply currents, the arm currents, the circulating current, and the dclink current. Moreover, the dc-capacitor voltages and the dclink voltage are well regulated to their references even during the transient period. Carefully looking into reveals that the switching-ripple component () , increases slightly

during the transient state. However, it is about 25% in peak-topeak of the mean value of 400 V, which is within an acceptable value. V. C ONCLUSION This paper has described an application of a modular multilevel cascade converter based on double-star choppercells (MMCC) to a back-to-back (BTB) system, intended for installation on 6.6-kV power distribution systems. The derived circuit equations of the BTB system has shown that the dc-link voltage and current can be controlled independently without any mutual inference. Moreover, an indirect control of the dclink voltage developed in this paper has eliminated neither a voltage sensor nor dc-link capacitors from the dc link. The validity and effectiveness of the BTB system has been conrmed and justied by both experiment using a threephase, 200-V, and 10-kVA downscaled system and simulation using the PSCAD/EMTDC software package. VI. ACKNOWLEDGEMENT The authors would like to thank the Japanese ministry of economy, trade and industry for nancially supporting this research project.

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A PPENDIX A. Derivation of equations (11) and (12) When attention is paid to either DSCC-A or DSCC-B, making reference to (10) allows to be expressed as follows: 1 = 3 1 = 3 ( + =,, =,,
=,,

) , ) . (25) (24)

+ =,,

The dc-link current is expressed from Fig. 2(a) and Kirchhoffs current law (KCL) as = =
=,,

, (26)

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=,,

Substituting (26) into (24) and (25) yields = ) 1( , 3 =,, ) 1( + . 3 =,, (27)

(28)

Equations (27) and (28) give (11) for and (12) for . R EFERENCES
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