Mealy and Moore Type Finite State Machines

Introduction
There are two basic ways to design clocked sequential circuits. These are using: 1. Mealy Machine, which we have seen so far. 2. Moore Machine.

Mealy Machine
In a Mealy machine, the out uts are a function of the resent state and the value of the in uts as shown in !igure 1. "ccordingly, the out uts may change asynchronously in res onse to any change in the in uts.

Figure 1: Mealy Type Machine

Mealy Machine
In a Moore machine the out uts de end only on the resent state as shown in !igure 2. " combinational logic block ma s the in uts and the current state into the necessary fli #flo in uts to store the a ro riate ne$t state %ust like Mealy machine. &owever, the out uts are com uted by a combinational logic block whose in uts are only the fli #flo s state out uts.

The out uts change synchronously with the state transition triggered by the active clock edge.

Figure 2: Moore Type Machine

Comparison of the Two Machine Types

'onsider a finite state machine that checks for a attern of (1)* and asserts logic high when it is detected. The state diagram re resentations for the Mealy and Moore machines are shown in !igure +. The state diagram of the Mealy machine lists the in uts with their associated out uts on state transitions arcs. The value stated on the arrows for Mealy machine is of the form ,i-.i where ,i re resents in ut value and .i re resents out ut value. " Moore machine roduces a unique out ut for every state irres ective of in uts. "ccordingly the state diagram of the Moore machine associates the out ut with the state in the form state#notation-out ut#value. The state transition arrows of Moore machine are labeled with the in ut value that triggers such transition. /ince a Mealy machine associates out uts with transitions, an out ut sequence can be generated in fewer states using Mealy machine as com ared to Moore machine. This was illustrated in the revious e$am le.

Figure 3: Mealy and Moore State Diagrams for 1! Se"uence Detector

Timing Diagrams
To analy0e Mealy and Moore machine timings, consider the following roblem. " state#machine out uts (1* if the in ut is (1* for three consecutive clocks.

Figure #: Mealy State Machine for 111 Se"uence Detector

Mealy State Machine The Mealy machine state diagram is shown in !igure 1. 2ote that there is no reset condition in the state machine that em loys two fli # flo s. This means that the state machine can enter its unused state (11* on start u . To make sure that machine gets resetted to a valid state, we use a (3eset* signal. The logic diagram for this state machine is shown in !igure 4. 2ote that negative edge triggered fli #flo s are used.

Figure $: Mealy State Machine Circuit Implementation

Timing 5iagram for the circuit is shown in !igure 6. /ince the out ut in Mealy model is a combination of resent state and in ut values, an unsynchroni0ed in ut with triggering clock may result in invalid out ut, as in the resent case. 'onsider the resent case where in ut ($* remains high for sometime after state ("7 8 1)* is reached. This results in (!alse 9ut ut*, also known as (9ut ut :litch*.

Figure %: Timing Diagram for Mealy Model Se"uence Detector

Moore State Machine The Moore machine state diagram for (111* sequence detector is shown in !igure ;. The state diagram is converted into its equivalent state table </ee Table 1=. The states are ne$t encoded with binary values and we achieve a state transition table </ee Table 2=.

Figure &: Moore Machine State Diagram

Ta'le 1: State Ta'le

Present Next State Present Next State State x=0 x=1 Initial Initial Got-1 Got-1 Got-11 Initial Got-11 Initial Got-111

Output Output Z 0 0 0 1

Got-111 Initial Got-111

Ta'le 2: State Transition Ta'le and (utput Ta'le Present State Initial Got-1 Got-11 Got-111 Next State x=0 x=1 Initial Initial Initial Initial Got-1 Got-11 Got-111 Got-111 Output Z 0 0 0 1

>e will use ?@ and 5 fli #flo s for the Moore circuit im lementation. The e$citation tables for ?@ and 5 fli #flo s <Table + A 1= are referenced to tabulate e$citation table </ee Table 4=.
Ta'le 3: )*citation Ta'le for +, flip-flop Q(t) 0 0 1 1 Q(t+1) J 0 1 0 1 0 1 X X K X X 1 0

Ta'le #: )*citation Ta'le for D flip-flop Q(t) 0 0 1 1 Q(t+1) D 0 1 0 1 0 1 0 1

Ta'le $: )*citation Ta'le for the Moore Implementation Inputs of Comb.Circuits Present Input State A B X 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Next State A B 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 Outputs of Comb.Circuit Flip-flop Inputs JA KA DB 0 X 0 0 X 1 0 X 0 1 X 0 X 1 0 X 0 1 X 1 0 X 0 1

Output Z 0 0 0 0 0 0 1 1

/im lifying Table 4 using ma s, we get the following equations: o JA = X.B o KA = X o DB =X(A + B) o Z=A.B 2ote that the out ut is a function of resent state values only. The circuit diagram for Moore machine circuit im lementation is shown in !igure B. The timing diagram for Moore machine model is also shown in !igure C. There is no false out ut in a Moore model, since the out ut de ends only on the state of the flo flo s, which are synchroni0ed with clock. The out uts remain valid throughout the logic state in Moore model.

Figure .: Moore Machine Circuit Implementation for Se"uence Detector/

Figure 0: Timing Diagram for Moore Model Se"uence Detector/