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Course Overview!
This course covers the verication process used in validating the functional correctness in today's complex Application Specic Integrated Circuits (ASICs). Topics include fundamentals of simulation based functional verication, stimulus generation, results checking, coverage, debug, and assertions. Provides the students with real world verication problems to allow them to apply what they learn.

Instructor ! !Dr. Meeta Yadav!

!Email: myadav@ncsu.edu! Ofce hours: TBD! Prof. Paul Franzon! Email: paulf@ncsu.edu! Ofce hours: By e-mail!

TAs! !TBD! Prerequisite!

ECE 520 ASIC Design or equivalent. A good working knowledge of Verilog or VHDL is essential. This is not suitable as a rst course in a hardware description language. !

2010, Meeta Yadav

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Design Complexity!

Communication

Entertainment

Broadcasting

Computing

Telematics

Image Processing

Location-Based Services

Designs become complex as more functionality is added to them!

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Technology Scaling!

Increased functionality increases the number of transistors in the design thus increasing the possibility of error in the design!
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Bug Trends!

75% 50% of of them ASICs have require logical more or than functional one respin bugs!!
[Collet 2005]

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1. Making sure there are no bugs in the design!

2. All design functionality has been implemented!

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!!

Traditional Verication methods cannot keep up with the verication challenge !

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Functional Verication!

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Tool!

Mentors QuestaSim!

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Language!

SystemVerilog!

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Verication Plan!

Create a verication plan and list what you are going to verify and how!

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Testbench Development!

Generate and Apply Stimulus!

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Testbench Development!

Testbench functionality!
!! !!

Generate stimulus! Apply stimulus to the Design Under Test (DUT) !

Stimulus Generation

Stimulus Application

Design Under Test

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Testbench Development!

Generate and Apply Stimulus!

Capture Response and Check for correctness!

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Testbench Development!

Testbench functionality!
!! !! !! !!

Generate stimulus! Apply stimulus to the Design Under Test (DUT)! Capture the response! Check for correctness!

Stimulus Generation

Stimulus Application

Design Under Test

Response Capture

Correctness Check

Golden Model

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Testbench Development!

Generate and Apply Stimulus!

Capture Response and Check for correctness!

Measure Progress (Coverage)!

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Testbench Development!

Testbench functionality!
!! !! !! !! !!

Generate stimulus! Apply stimulus to the Design Under Test (DUT)! Capture the response! Check for correctness! Measure the progress against the overall verication goals!
Progress Check and Control of Verification Process

Stimulus Generation

Stimulus Application

Design Under Test

Response Capture

Correctness Check

Golden Model

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Testbench Development!

Generate and Apply Stimulus!

Capture Response and Check for correctness!

Measure Progress (Coverage)!

Write Assertions!

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Testbench Development!

Testbench functionality!
!! !! !! !! !!

Generate stimulus! Apply stimulus to the Design Under Test (DUT)! Capture the response! Check for correctness! Measure the progress against the overall verication goals!
Progress Check and Control of Verification Process

Stimulus Generation

Assertions Stimulus Application Design Under Test Response Capture

Correctness Check

Golden Model

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Projects!

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Project 1!

Project 1:!
Perform functional verication on the unpipelined LC3 microprocessor! !! Find bugs in the design! !! Analyze the bugs! !! Include all the tests to recreate the bugs!
!!

Stimulus Generation

Stimulus Application

Un-pipelined LC3 processor

Response Capture

Correctness Check

Golden Model

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Project 2a!

Project 2a:!
Perform functional verication on pipelined LC3 microprocessor! !! Find bugs in the design! !! Analyze the bugs! !! Include all the tests to recreate the bugs!
!!

Stimulus Generation

Stimulus Application

Pipelined LC3 processor

Response Capture

Correctness Check

Golden Model

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Project 2b!

Project 2b!
Perform coverage on pipelined LC3 microprocessor! !! Write assertions! !! Detect bugs! !! Analyze bugs!
!!
Progress Check and Control of Verification Process

Stimulus Generation

Assertions Stimulus Application Response Capture

Design Under Test

Correctness Check

Golden Model

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Course Overview!
Topics!
!Introduction to Verication! !2. !Test Bench Environments! !3. !Interfaces! !4. !Stimulus Generation! 5. Object Oriented Programming! !5. !Functional Coverage! !6. !Assertions! !7. !SystemVerilog Language Constructs!
!1.

Text!
C. Spear, System Verilog for Verication, Springer 2006.

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References!
! ! ! ! ! !
Comprehensive functional verication the complete industry cycle by Bruce Wile, John C. Goss, Wolfgang Roesner."""""Elsevier/Morgan Kaufmann, c2005! SystemVerilog for Verication: A Guide to Learning the Testbench Language Features by Chris Spear. Springer, 2006! SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling by Stuart Sutherland, Simon Davidman, Peter Flake and P. Moorby. Springer, 2006! Verication Methodology Manual for SystemVerilog by Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale. Springer, 2005! SystemVerilog Assertions Handbook by Ben Cohen, S Venkataramananm, A Kumari. VhdlCohen Publishing, 2005.! SystemVerilog 3.1a , Language Reference Manual Accelleras Extensions to Verilog!

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Course Overview!
Evaluation!
Labs! Midterm! Project 1! 15%! 15%! 15%! There will be 5 labs! The exams will be open book and open notes! Verication of an LC3 microprocessor by developing a test environment using SystemVerilog. Students will be required to nd embedded bugs in the design and analyze them.! Verication of an LC3 microprocessor by developing a complete test environment using SystemVerilog, writing SVA and gathering functional coverage metrics. Students will be required to nd embedded bugs, analyze them and report functional coverage numbers.! The exam will be comprehensive and open books and open notes.!

Project 2a and Project 2b!

35%!

Final!

20%!

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Designers are doing Verication!

Source: 2004/2002 IC/ASIC Functional Verification Study, Collett International Research, Used with Permission

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Thank You!

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