DESIGN OF SYNCHRONOUS FIFO

ABSTRACT FIFO is a First-In-First-Out memory queue with control logic that manages the read and write operations, generates status flags, and provides optional handshake signals for interfacing with the user logic. It is often used to control the flow of data between source and destination. FIFO can be classified as synchronous or asynchronous depending on whether same clock or different (asynchronous clocks control the read and write operations. In this pro!ect the ob!ective is to design, verify and synthesi"e a synchronous FIFO using binary coded read and write pointers to address the memory array. FFIO full and empty flags are generated and passed on to source and destination logics, respectively, to pre-empt any overflow or underflow of data. In this way data integrity between source and destination is maintained.

INTRODUCTION

#$%& I' % FIFO (first in first out ( In computer programming, FIFO (first-in, first-out is an approach to handling program work requests from queues or stacks so that the oldest request is handled first. In hardware it is either an array of flops or )ead*#rite memory that store data given from one clock domain and on request supplies with the same data to other clock domain following the first in first out logic. &he clock domain that supplies data to FIFO is often referred as #)I&+ O) I,-.& /O0I1 and the clock domain that reads data from the FIFO is often referred as )+%2 O) O.&-.& /O0I1. FIFOs are used in designs to safely pass multi-bit data words from one clock domain to another or to control the flow of data between source and destination side sitting in the same clock domain. If read and write clock domains are governed by same clock signal the FIFO is said to be '3,1$)O,O.' and if read and write clock domains are governed by different (asynchronous clock signals FIFO is said to be %'3,1$)O,O.'.

FIFO full and FIFO empty flags are of great concern as no data should be written in full condition and no data should be read in empty condition, as it can lead to loss of data or generation of non relevant data. &he full and empty conditions of FIFO are controlled using binary or gray pointers. In this report we deal with binary pointers only since we are designing '3,1$)O,O.' FIFO. &he gray pointers are used for generating full and empty conditions for %'3,1$)O,O.' FIFO. &he reason why they are used is beyond the scope of this document.

Figure 45 2ata Flow through FIFO

'3,1$)O,O.' FIFO % synchronous FIFO refers to a FIFO design where data values are written sequentially into a memory array using a clock signal, and the data values are sequentially read out from the memory array using the same clock signal.

In synchronous FIFO the generation of empty and full flags is straight forward as there is no clock domain crossing involved. 1onsidering this fact user can even generate programmable partial empty and partial full flags which are needed in many applications. %--/I1%&IO,' 6 FIFO7s are used to safely pass data between two asynchronous clock domains. In 'ystem-on1hip designs there are components which often run on different clocks. 'o, to pass data from one such component to another we need %'3,1$)O,O.' FIFO 6 'ome times even if the 'ource and )equestor sides are controlled by same clock signal a FIFO is needed. &his is to match the throughputs of the 'ource and the )equestor. For e8ample in one case source may be supplying data at rate which the requestor cannot handle or in other case requestor may be placing requests for data at a rate at which source cannot supply. 'o, to bridge this gap between source and requestor capacities to supply and consume data a '3,1$)O,O.' FIFO is used which acts as an elastic buffer.

BLACK BOX VIEW OF SYNCHRONOUS FIFO

Figure 1: Bla !"#$% &ie' $( a S)* +r$*$u, FIFO

-ORT LIST

CO..ON -ORTS

WRITE SIDE -ORTS

READ SIDE -ORTS

F.,1&IO,%/ 2+'1)I-&IO, Figure 9 depicts the basic building blocks of a synchronous FIFO which are5 memory array, write control logic and read control logic. &he memory array can be implemented either with array of flip-flops or with a dual-port read*write memory. :oth of these implementations allow simultaneous read and write accesses. &his simultaneous access gives the FIFO its inherent synchroni"ation property. &here are no restrictions regarding timing between accesses of the two ports. &his means simply, that while one port is writing to the memory at one rate, the other port can be reading at another rate totally independent of one another. &he only restriction placed is that the simultaneous read and write access should not be from*to the same memory location.

&he 'ynchronous FIFO has a single clock port clk for both data-read and data-write operations. 2ata presented at the module;s data-input port write<data is written into the ne8t available empty

memory location on a rising clock edge when the write-enable input write<enable is high. &he full status output fifo<full indicates that no more empty locations remain in the module;s internal memory. 2ata can be read out of the FIFO via the module;s data-output port read<data in the order in which it was written by asserting read-enable signal read<enable prior to a rising clock edge. &he memory-empty status output fifo<empty indicates that no more data resides in the module;s internal memory. &here are almost empty and almost full flags too vi". fifo<aempty and fifo<afull which can be used to control the read and write speeds of the requestor and the source.

Figure /: Bl$ ! Diagra0 $( a S)* +r$*$u, FIFO

WRITE CONTROL LOGIC #rite 1ontrol /ogic is used to control the write operation of the FIFO7s internal memory. It generates binary-coded write pointer which points to the memory location where the incoming data is to be written. #rite pointer is incremented by one after every successful write operation. %dditionally it generates FIFO full and almost full flags which in turn are used to prevent any data loss. For e8ample if a write request comes when FIFO is full then #rite 1ontrol /ogic stalls the write into the memory till the time fifo<full flag gets de-asserted. It intimates the stalling of

write to source by not sending any acknowledgement in response to the write request. Figure = below shows the black-bo8 view of #rite 1ontrol /ogic

Figure 1: Wri2e C$*2r$l L$gi Bla !"#$% Vie' -O)& /I'&

)+%2 1O,&)O/ /O0I1 )ead 1ontrol /ogic is used to control the read operation of the FIFO7s internal memory. It generates binary-coded read pointer which points to the memory location from where the data is to be read. )ead pointer is incremented by one after every successful read operation. %dditionally it generates FIFO empty and almost empty flags which in turn are used to prevent any spurious data read. For e8ample if a read request comes when FIFO is empty then )ead 1ontrol /ogic stalls the read from the memory till the time fifo<empty flag gets de-asserted. It intimates the stalling of read to the requestor by not asserting rdata<valid in response to the read request.

Figure > below shows the black-bo8 view of )ead 1ontrol /ogic

Figure >5 )ead 1ontrol /ogic :lack-bo8 ?iew

-O)& /I'&

.E.ORY ARRAY @emory %rray is an array of flip-flops which stores data. ,umber of data words that the memory array can store is often referred as 2+-&$ of the FIFO. /ength of the data word is referred as #I2&$ of the FIFO. :esides flop-array it comprises read and write address decoding logic. &he functionality of @emory %rray is relatively straight forward as described below5

4. If write<enable signal is high 2%&% present on write<data is written into the row pointed by write<addr on the ne8t rising edge of the clock signal clk. ,ote that write<enable is asserted only when wdata<valid is high and FIFO is not full to avoid any data corruption

9. If read<enable signal is high the 2%&% present in the row pointed by read<addr is sent onto the read<data bus on the ne8t rising edge of the clock signal clk. ,ote that read<enable is asserted only when read<req is high and FIFO is not empty to avoid any spurious data being sent to the requestor =. It can handle simultaneous read and write enables as long as their addresses do not match

Figure A below shows the black-bo8 view of @emory %rray.

Figure A5 @emory %rray :lack-bo8 ?iew

-O)& /I'&

FULL 3 E.-TY FLAG GENERATION FIFO full and almost full flags are generated by #rite 1ontrol /ogic whereas empty and almost empty flags are generated by )ead 1ontrol /ogic. FIFO almost full and almost empty flags are generated to intimate the source and the requestor about impending full or empty conditions. &he almost full and almost empty levels are parameteri"ed. It is important to note that read and write pointers point to the same memory location at both full and empty conditions. &herefore, in order to differentiate between the two one e8tra bit is added to read and write pointers. For e8ample if a FIFO has depth of 9>A then to span it completely Bbits will be needed. &herefore with one e8tra bit read and write pointers will be of C-bits. #hen their lower B-bits point to same memory location their @':s are used to ascertain whether it is a full condition or empty condition. In empty conditions the @':s are equal whereas in full condition @':s are different. &he verilog code shown below depicts the same5 assign fifo<full D ( (write<ptrEF 5 GH DD read<addrEF 5 GH II (write<ptrEBH J read<ptrEBH K

assign fifo<empty D (read<ptrEB 5 GH DD write<ptrEB 5 GH K

Following piece of verilog code shows logic almost full generation5 ** 0enerating fifo almost full status always LM begin if ( write<ptrEBH DD read<ptrEBH fifo<afull D ((write<ptrEF5GH - read<ptrEF5GH ND (2+-&$ - %F.// K else fifo<afull D ((read<ptrEB5GH - write<ptrEB5GH OD %F.// K end $ere %F.// signifies the almost full-level. .ser can set it to P, B or whatever value depending on how soon it wants to intimate the source about impending full condition. (%F.//DP means almost full flag will get asserted when at most P locations are left for new data. Following piece of verilog code shows logic almost empty generation5 **assigning fifo almost empty always LM begin if (read<ptrEBH DD write<ptrEBH fifo<aempty D ( (write<ptrEF5GH - read<ptrEF5GH OD %+@-&3 K

else fifo<aempty D ((read<ptrEB5GH - write<addrEB5GH ND (2+-&$ - %+@-&3 K end $ere %+@-&3 signifies the almost empty-level. .ser can set it to P, B or whatever value depending on how soon it wants to intimate the requestor about impending empty condition. (%+@-&3DP means almost empty flag will get asserted when at most P data locations are left to be read.

OVERALL SE4UENCE OF O-ERATIONS 6 %t reset, both read and write pointers are G. &his is the empty condition of the FIFO, and fifo<empty is pulled high and fifo<full is low 6 %t empty, reads are blocked and only operation possible is write6 'ince fifo<full is low, upon seeing a valid write data #rite 1ontrol /ogic will ensure the data be written into location G of memory array and write<ptr be incremented to 4. &his causes the empty signal to go /O# 6 #ith fifo<empty pulled down, read operation can now be performed. .pon seeing read request at this state )ead 1ontrol /ogic will fetch data from location G and will increment read<prt to 4 6 In this way read keeps following write until the FIFO gets empty again 6 If write operations are not matched by read soon FIFO will get full and any further write will get stalled until fifo<full is pulled down by a read 6 #ith the help of FIFO full and empty flags data integrity is maintained between the source and the requestor

)&/ )+-)+'+,&%&IO, OF '3,1$)O,O.' FIFO ?erilog $2/ has been used to represent the design at )egister &ransfer

/evel. &he top-level design sync<fifo has been partitioned into = logical blocks5 6 write<control<logic 6 read<control<logic 6 mem<array

Following parameters have been used in the )&/ representation of the FIFO to keep it scalable5 6 2+-&$ 5 FIFO depth which can take any positive integer value 6 %22)<#I2&$ 5 FIFO %ddress bus width 6 2%&%<#I2&$ 5 #idth of the data input to FIFO 6 %+@-&3 5 %lmost empty level 6 %F.// 5 %lmost full level

&he verilog codes for each of these modules along with the top-level module are presented in %ppendi8 %4.

?+)IFI1%&IO, OF &$+ @O2./+ % &3-I1%/ &+'&:+,1$ % test bench is a virtual environment used to verify the correctness or soundness of a design or model. It is a computer program written in a hardware description language ($2/ , such as the ?erilog language, for the purpose of verifying a module7s functional behavior.

% testbench typically includes the following components5

6 Input stimulus block 6 &ransactor*bus functional models 6 2esign under test (2.& 6 Output checker block

Figure F5 'implified ?iew of a &ypical &estbenc &: FO) '3,1$)O,O.' FIFO % verilog testbench has been developed to test the functional correctness of 'ynchronous FIFO. It comprises simplified source and destination models along with a checker which asserts match*mismatch depending on whether the data written into and read out of FIFO are indeed same.

2ifferent aspects of the test bench sync<fifo<tb are as follows5 6 -arameteri"ed clock generator block

6 )eset signal generator 6 4A-bit /F') counter to generate 4A-bit pseudo-random data 6 4A bit input data is generated using ma8imum length /F') 6 /F') bits are also used to generate source<ready and read<req signals 6 F'@ to generate wdata<valid signal which uses source<ready as input 6 'ource and destination buffers to store each data word sent to FIFO and read out of FIFO respectively. &he content of these buffers are compared continuously to assert*de-assert @%&1$ flag

% complete verilog description of the testbench is present in %ppendi8 %9.