Computing Practices

Computing Practices

Designing an Alpha Microprocessor

Dening and designing a high-performance processor is high adventure in computer engineering. Nevertheless, this journey into new technologies and the unknown has a well-dened path. An architect shares the process the Alpha design teams use to develop their processors.

Matt Reilly
Compaq Computer Corp.

o those who have experienced one, any large engineering project can feel like a journey on a rocket. At the start, all is excitement and anticipationand frequent frustrationas a team wonders if the whole project will ever get off the ground. Then there is a rapid acceleration and the realization that there is no turning back. Eventually, in midight, you feel the transition into cruising mode as the pace becomes more steady, the path a little clearer. Finally, as deadlines approach, the landing zone comes into sight. The project-rocket picks up speed, and the team comes face-toface with the fact that theyre about to land. Processor design teams at Compaq Computer Corp. have been designing and building microprocessors for about 20 years. For the past 10 years, they have been designing Alpha processors, with the goal of maintaining industry-leading performance with each generation. Over this time, the teams have developed a process, outlined here, that supports this goal. The process has changed as technology has improved. Teams have become larger and projects more complex. The design trajectory has changed over time to adapt to technical and market conditions, but the design goal remains the sameto produce a microprocessor that is functional with rst-pass silicon. Unlike a rockets trajectory, however, the development of a new Alpha microprocessor passes through more than a dozen phases, which overlap to a great degree. Several occur in parallel. Nevertheless, the trajectory analogy feels right. Sticklers may point out that as a chip design travels along its trajectory, unlike a rocket, it gains mass. So, mercifully, we will dispense with the rocket trajectory analogy here.

PRODUCT DEFINITION
At the projects outset, a small groupcomposed of senior technical and marketing professionalssurveys the market, current research, competitors plans, and technology road maps. This group determines a new processors performance goals and best feature set. The task is complex because the market is a moving target. Five years or more could pass between this ini0018-9162/99/$10.00 1999 IEEE

tial planning stage and the time a customer actually sees a new processor. Market surveys often appear to have more in common with crystal ball gazing than with science. In ve years, will processors for backroom servers be substantially different from those for personal systems? What workloads will be important? Will speech recognition be the major computational task for the desktop? Or will it be real-time animation? How important are multiprocessor platforms? What will customers want? Every year the organization sends engineers, researchers, and managers to dozens of conferences, seminars, and workshops. Much of the information gathered at these meetings is incorporated into requirements and features for the next generation of processors. The microprocessor marketplace is extremely competitive. Customers demand to know the road map for processors they are considering. This appetite for advanced information and the competition among teams for marketing presence and even personnel make most companies surprisingly eager to talk about products that are years away from completion. This situation has the rather happy effect of creating a positive feedback loop: Moores law works because semiconductor companies say it will. If the Froodly Computer Company announces that its SuperFroodly VX90 will deliver 4,000 bogoMips to the desktop in four years, project planners at Compaq had better have an answer when
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the board of directors asks how Alpha processors will stack up against such competition. Finally, the semiconductor industry makes projections of its own on a regular basis. These projectionswhich influence die size, wafer size, production costs, device performance, interconnect characteristics, and a host of other technical and nancial measuresare a guide for equipment manufacturers. They also guide Even before product product planners. The technology projections dene (or at least suggest) the raw materials that denition, teams will be on hand when the product ships. sometimes work At the end of this stage, the project has someto design new thing that looks like a charter. The product defcircuit packaging. inition group has outlined the design task, enumerated the target markets, suggested likely technology features and resources, and (of course) dened the performance goals. Most contributors to product denition have experience in the Alpha design group as circuit designers, architects, marketeers, or researchers. This broad experience is crucial to nding a balance between market desires, available technology, and time-to-market.

EXPLORING THE ARCHITECTURAL DESIGN SPACE

As this group develops requirements, the architecture team begins searching for an organizational

scheme for the design. They seek to answer several questions: How can the project best use a xed die area to meet product requirements? How many functional units does it need? How much on-chip memory? What policies, structures, and algorithms will take maximum advantage of the processors resources? At the start of this phase, the team is comparatively smallperhaps a half-dozen architects. They are, however, assisted by a much larger advanced development and research team as well as Compaqs research centers. They work in parallel with (and some are members of) the product denition group. The architecture team tests most of the trade-offs and new concepts they develop using a performance model. This model is a high-level simulator with components that represent each of the major structures and features under consideration. The design, construction, and maintenance of the model is a signicant software development project on its own.1 But not all questions are answered by a performance study. Much of the exploration at this stage takes place on whiteboards, at technical conferences, and in discussions with circuit designers. As the major questions are answeredfor example, how many integer units will this processor have? How many floating-point units and memory ports? What does the pipeline look like? the team begins to sketch out a oor plan, a

Life for a Processor Design Team

Perhaps we can describe the atmosphere around a microprocessor project by examining the parking lot.

The Alpha development group is winding down one project and starting another.

Product Denition 5:30 p.m.: John, an architect, has been meeting all day with the marketing group. After weeks of brainstorming and reading surveys from market research and industry consultants, he eagerly thinks about starting on the actual design, as he walks across the full parking lot. The current processor development project will tape out in a few months. Johns project is years away from tape out. Exploring the Architectural Design Space 7:30 p.m.: Most of the small architecture team has already gone home as Doug wanders across the parking lot deep in thought. Hes spent the day considering alternatives to the branch predictor that was used on the last project. His day is done, and his simulations will run all night. The parking lot is nearly empty now.

Technology Development, Foundry Specication, and Feasibility Studies 5:15 p.m.: George walks to the parking lot with the rest of the technology and process team. The day has gone well. The new technology models indicate that the likelihood is high that the project will hit its cycle time goalif all goes well. The parking lot is almost empty by 7:00 p.m. 10:30 p.m.: Sharon, a circuit designer, has been working on block diagrams all day. Hers is the last car to leave the lot. Tool Development and RTL Modeling 12:00 midnight: Tracey has a deadline. All the VBox RTL code must be ready for review by next Tuesday. This means long nights, long daysbut just for a few weeks. Traceys car stands alone in the parking lot. Schematic Design and Functional Verication 7:30 p.m.: Was there ever a time when she wasnt drawing schematics? Dianne

cant remember. For 7:30 p.m. on a winters evening, there are more cars than usual in the parking lot, yet the schedule says things are as they should be. While much of the team is working a standard work week (and will continue to do so through the end of the project), almost a quarter of the team eats dinner at work. Dinner is served each evening at 6:00 p.m.

Logic Verication, Layout, and Circuit Verication 4:00 p.m.: Harold, a layout designer, walks to his car. The days are warm and hes off to spend some time in the sun after spending the morning and afternoon reworking a circuit layout to fix a few cross talk problems. It is Saturday. There are a few dozen cars in the parking lot. Tape Out 9:00 p.m.: Ronnie has just checked the last box on the status board. The design database has been passed on to the mask preparation folks. The chip has taped out. Tomorrow the parking lot will be empty.

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geographic block diagram of the processor. The result of this stages studies is a complete performance model and an understanding of the processors block-level structure. This information is documented in various functional-unit specications, block diagrams, charts, tables, memos, and interface denitions. At this point in the project, the architecture team divides the processor into boxes. Each box has a particular function. A simple processor might comprise an IBox that fetches and parses instructions, an EBox that executes integer instructions, an FBox that executes oating-point operations, and an MBox to handle memory operations. As the team divides the chip into boxes, it does the same to itself. This division of task and team carries through to the circuit design, layout, and the verication teams: Each box has its own group of engineers responsible for its development, design, and testing. This division of the team into subgroups is crucial to managing complexity. Dividing the chip into boxes creates interface boundaries. If poorly chosen or ill-dened, the regions around the boundaries can become bug farms. The assignment of team members to individual boxes is an interesting management task in itself: an exercise in matching widely different skill sets and temperaments to the characteristics, complexity, and size of each box. The division of the chip into boxes also creates a framework for resolving global design issues. Naturally, it also forms the framework for what is generally good-natured competition between teams and the occasional dispute as competing needs and perspectives conict. For example, an operation downstream in the execution unit may need support from a feature in the instruction fetch unit. The fetch units team has a set of performance targets and project milestones that they intend to meet. If the new feature raises the risk of missing a fetch-unit performance goal, how is this to be balanced against the schedule risk taken by the execution unit? As in most ventures, the questions are resolved by reasoned discussion among peers, blizzards of e-mail, stacks of charts and graphs, hours and days of simulation, and an occasional heated debate. A typical member of the architecture team has a degree in computer engineering. The level of experience varies, but most members have either industrial experience in circuit design, verication, or systems architecture, or a PhD in computer engineering.

As the design group develops requirements, the architecture team develops an organizational scheme for the design.

TECHNOLOGY DEVELOPMENT AND FOUNDRY SPECIFICATION

Often, before product denition, the technology and process teams are at work designing new packages the housings around the actual microprocessor circuits. They also work with vendors to select a new fabrication process, usually one based on CMOS (complementary metal oxide semiconductor). The intent is to

dene a fabrication technology that will be ready but not yet mature when the rst prototypes are fabricated. Though Compaqs Alpha Design Group operates under a fabless model (that is, the company doesnt own its own production plants or fabs), vendors rarely present a completely specied process on a takeit-or-leave-it basis. The eventual target process for a new Alpha product comes from a collaboration among circuit designers, Compaqs technology team, and the chip foundry. The development of the process continues through the life of the project and well into the manufacturing run of a new processor. The technology team gathers requirements from the circuit designers, architects, and product managers. The team considers both external and internal research and development efforts. They release a series of notes describing the process in increasingly greater detail and eventually arrive at a set of technology specications and low-level design rules. For instance, the document will specify the dielectric constants of all insulating layers, the nominal thickness of each layer of metal, resistance and capacitance of on-chip interconnect, and transistor characteristics. Further, the technology specication will set out the limits of the process, indicating the minimum spacing and width for wires at each layer or the minimum space between transistors, for example. These details are documented in a technology le (actually a book) that describes feature dimensions, layout design rules, electrical limits, and transistor characteristics. Members of the technology team come from a variety of backgrounds in materials science, electrical engineering, physics, chemistry, or other physical sciences. The members working with the foundry vendors typically have extensive experience in process development. (The collaboration between vendor and customer is much easier when the customer has been there before.)

FEASIBILITY STUDIES
Early in the design process and in parallel with the architectural exploration, circuit designers test new design concepts. For example, what type of state storage elements will the new chip use: edge-triggered ipJuly 1999

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ops or level-sensitive latches? Are new circuit types made possible by innovations in the target CMOS process? Is it possible to build the structures proposed by the architecture team? Feasibility studies follow the development of the processors block diagram and pipeline charts. As the architecture begins to take form, it becomes possible to identify critical features and architectural loops that may be difcult to Early in the design implement. process and in For example, register-renaming structures must often implement algorithms that require the parallel with the output at cycle N to depend on the output at cycle architectural N1. The circuit that implements this algorithm exploration, circuit must complete its task within the target cycle designers test new time. At times, the feasibility analysis nds that a structure cant be implemented in the technoldesign concepts. ogy at hand and still meet the cycle time target. In other cases, a study may indicate that a circuit does meet cycle time requirements. Or the study may nd that a circuit can impose intolerable risks to the project, either in terms of schedule (it will take too much time to design, lay out, or verify) or reliability (its reliability would be in question until the company fabricated a few thousand parts). When studies indicate that an architectural feature is infeasible, architects and circuit designers return to the whiteboard to work out alternatives. At the end of the feasibility process, the circuit feasibility team has a fairly clear picture of the major structures on the chip. Additionally, members have developed a great deal of experience with the new technology and architecture. Much of this information inuences the authors of a project design guide a handbook (or set of handbooks) that circuit designers and layout designers will use to draw and lay out production schematic diagrams. The team working on feasibility studies will eventually form the core of the circuit design team. Typically, members have degrees in electrical or computer engineering. Some team members are fresh out of school but work under the supervision of more experienced engineers.

layout synthesis tools to design rule checkers for both circuits and layout. The design of custom, high-performance microprocessors requires a custom set of design tools, many of which the CAD team must build or modify especially for the current design effort. For the projects duration, the CAD team develops new tools based on designer suggestions, the CAD teams research, industry trends, and technology requirements. Typically, CAD team members have degrees in electrical or computer engineering or computer science.

RTL MODELING
Before manufacturing a processor, the team must be reasonably sure that the chip will actually work. For quite some time, chip design teams have used simulation to test designs before they are manufactured. Modern microprocessors, however, are far too complex to simulate at the circuit levelthe level of every transistor or gate. While a team will subject some components to circuit simulation, it simulates the whole chip at a much higher level of abstraction. Even switch-level simulation is too slow for processors with tens of millions of transistors. Therefore, most of the architectural design verication effort centers on a high-level description of the chip. This description also serves as a component of the chip specication. The high-level description takes the form of an executable register-transfer-level (RTL) model, a program written in a hardware description language. The RTL describes every bit of state in the processor and all of the operations that can take place on that state. It describes every register, RAM array, adder, and logic block. Written by the architecture team with substantial assistance from the circuit design team, the RTL model culminates the teams work on block diagrams, feasibility analysis, product requirements, and architecture research. As the RTL model begins to take shape, the team starts feeling that the project is nally coming together. Every engineer knows the feeling of turning on a newly designed widget for the rst time. Many architects get that feeling when the RTL model executes its rst program. But the team is still many months away from turning on an actual chip.

TOOL DEVELOPMENT
With each new generation of Alpha processors, the design style evolves; the team may add new circuit types or enumerate new design rules. In addition, as geometries have shrunk from feature sizes of 2 m to less than 0.18 m, second- or third-order physical effects (such as noise and cross talk) have become important to the chips performance or even its functional correctness. To cope with these effects and with constantly increasing design complexity, Compaq has devoted signicant effort to developing new computer-aided design tools. These CAD tools range from circuit and 30
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FUNCTIONAL VERIFICATION
As a program that describes an Alpha processor, the RTL model can execute Alpha programs. The verication team builds a set of tools and a structure that creates test programs, runs the programs on the RTL model, and compares the state of the RTL model to a reference model of an Alpha processor. The reference model is based on the chip specication and the Alpha System Reference Manual. Much of the reference model is borrowed from previous chip efforts, but

with each new chip the reference model must incorporate additions to the instruction set and correctly mimic the implementation-specic behaviors that are peculiar to the new chip. The architecturally dened states of the two models must correspond perfectly at each clock cycle. In this way, the team gains confidence that the RTL model describes a processor that correctly executes Alpha instructions. Architects also use many of these same tests to show that the circuit design corresponds to the RTL model. They run the same program on both the RTL model and a gate-level simulation of the circuit schematics. By comparing the major signals described in both, they demonstrate that the circuit schematics are a faithful translation of the RTL model. Unfortunately, no practical simulation effort can exhaustively test a processor design. For this reason, the verication team devotes signicant attention to developing test programs that stress the processor in as many ways as possible before the rst prototype chips. The goal of functional verication is to establish an acceptable level of condence in the assertion that the RTL model describes an Alpha microprocessor. The verication team is roughly the same size as the architecture team. It builds the infrastructure for creating tests, tracking their results, reporting bugs, and tracking their resolution. Most team members have backgrounds in computer science or computer engineering.

The verication team devotes signicant attention to developing test programs that stress the processor.

SCHEMATIC DESIGN
The RTL is sufficiently detailed to describe the processor to a simulation engine, but is far too abstract to use to generate a layout for the chip. A translation stepschematic designis necessary before the design can be handed over to the physicallayout team. Schematic diagrams drawn for Alpha processors typically describe both the connections between transistors and the relative position of signal wires the layout team should use as a guide. These geographically organized schematics reduce the probability that signal-integrity problems will later force a change in the physical-design layout. The circuit design team translates the RTL model into circuit schematics. At times, the schematic designer will use the RTL model as a guide. At other times, the designer will ignore the model altogether and design a structure that is functionally equivalent or better. In these cases, the architecture team modifies the RTL model to correctly reflect the revised structures behavior. The Alpha team makes no distinction between gate- and transistor-level design. A circuit designer is free to use the most appropriate level of abstraction for describing a logic function.

Experienced circuit designers are often able to come up with creative and elegant designs that would be difcult for an automated system to produce. Compaqs design teams have worked to nd a balance between the productivity advantages of synthesis and the creativity of clever circuit designers. For this reason, the Alpha team synthesizes some of the processors control logic but designs most data path circuits by hand. Efcient, fast data path logic proceeds from careful planning of the interconnect, tuning of component sizes, and considering a host of third-order effects that are beyond the ken of synthesis tools. Data path design is more art than science and so is better performed by the designer-artist than by a machine. As circuit designers draw the schematics, others review them. The schematics are also critiqued by a suite of CAD programs developed to identify departures from accepted design practice. These programs also identify circuits that may be vulnerable to realworld effects like cross talk, clock skew, and CMOS (fabrication) process variation. Because of the increasing level of detailmillions of transistors to draw and miles of wire to routethe circuit design team is two to three times larger than the architecture team. The schematic design effort consumes about a third of the time spent on the project between the start of RTL modeling and delivery of masks to the foundry. Most team members see this as the cruising phase, where the project assumes a steady pace. The schematic design phase typically exposes problems in the original architecture scheme. These are resolved by collaboration between the architecture and implementation teams. As in any collaboration there is give and take, heat and humor.

LOGIC VERIFICATION
The functional verication step attempts to show that the RTL model is correct. But the RTL model is translated (frequently by humans) into a more detailed description (the schematics). This translation step is difcult and error prone, so demonstrating the correctness of the RTL model is only part of the task. The architecture team is responsible for ensuring that the translation from RTL to schematics was faithJuly 1999

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A translation stepschematic designis necessary before the design can be handed over to the physicallayout team.

late schematic descriptions into optimally packed arrangements of polygons in two dimensions on as many as ten layers. Complex sets of rules (described in the technology le) establish the constraints on the placement of polygons relative to other polygons on the same layer and on other layers.

CIRCUIT VERIFICATION
ful. They test this correspondence schematic by schematic, building a gate-level logic simulation for each schematic and running it in parallel with the RTL simulation of the same circuit. Identical stimuli sequences of input data or programsare presented to both the RTL and logic models. The outputs of both models must match in the expected manner at every cycle. The team resolves discrepancies by either xing the schematic or adapting the RTL model. Since the RTL is only a guide for the circuit designer, the RTL is frequently changed to match the schematic. In addition to simulation at the RTL and logic levels, Compaq has recently made more use of tools that provide an analytic comparison of the schematics to the RTL. Such comparison tools can provide a denitive and automatic proof that the schematic is a faithful translation of the RTL model. Demonstrating a logical correspondence between the schematics and the RTL model does not mean that the actual circuit will work. Logic verication assumes a universe where all transistors are either on or off, and all signals are either true or false and travel at innite speed. In real life, transistors leak, noise and other circuit effects corrupt signal values, and signals incur delay in owing from driver to receiver. Circuit designers use a host of special-purpose CAD tools developed by our own CAD group to verify the correct timing behaviorthat signals leave and arrive when they are supposed tofor every circuit. These tools also help ensure that signals corrupted by cross talk are still discernible as high or low levels and that such signals do not cause temporary or permanent circuit failures. These CAD tools also ensure that every wire on the chip can carry the current that will ow through it, that clock signals arrive at each point on the chip within tolerances for skew and edge rate, and that every circuit adheres to accepted design practice. Most of the tests done at this point require full characterization of the wires that connect the chips transistorsthe analysis accounts for each wires resistance and its capacitance to ground and to neighboring wires. Again, the CAD suite is used to extract capacitance and resistance information from the layout database. This information is used in timing analysis (for slow paths as well as race analysis), cross talk checks, and electromigration checks. This phase of the design task will require a year or more of concentrated effort. The circuit verication steps occur in parallel with the nal layout tasks and all of the logic and functional verication. In the projects last few months, the pace becomes frenetic. Dozens of tasks in dozens of areas converge, and team members update project-wide status boards in ofces, hallways, and conference rooms. Imagine the frenzy of an undergraduate computing lab the night before term projects are due, and you can almost get a feel for the atmosphere in the two or three months before the chip is released for fabrication.

LAYOUT
Schematics, though geographically drawn, are still not sufciently detailed to describe the chips physical layout. As schematics are completed, a team of layout designers begins to translate them into descriptions of actual chip geometries. That is, they enter each transistor on every schematic into a database as a set of polygonsat least nine rectangles in the case of a transistorrepresenting its source, drain, and gate terminals. Every wire is also entered into the database. Along the way, they compare each piece of the layout database to the schematics it represents. The correspondence must be 100 percent faithful. Again, Compaq has found that automatic layout synthesis is useful for only some parts of the design. For much of the design, skilled layout designers produce faster, smaller layouts. At the end of the layout design effort, the chip has been described in minute detail. At this point, the layout can be translated into masks for production. But rst, the layout is used to generate capacitance and resistance estimates for every wire on the chip. These are used as inputs to the timing and circuit verication steps. At its peak, the layout team is similar in size to the circuit design team. The size of the team during any given week varies as the project needs change. Members of the layout team are specically trained in high-performance VLSI layout. Very few have a background in electrical engineering, and all are adept at solving spatial problems. Layout designers must trans32
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FABRICATION
The processor team releases the design to the fabrication facility only after we are condent that the design will produce a chip capable of executing Alpha programs. Tape out, as this nal release is called, is a major milestone for the entire team. It may take as little as three weeks from the release date (or tape out) to

the arrival of the rst chips for testing. During this waiting period, team members take a much-needed break.

DEBUG
Finally, waferseach comprising dozens of processor chipsemerge and then go on to a wafer test station where testers exercise the chip. As the team gains condence in the design, selected chips are packaged and tested with another set of tests, and they are eventually tested in an actual computer system. Once in a system, the processor undergoes thousands of test programs, perhaps none so complex as the operating systems that Alpha supports: OpenVMS, Tru64 Unix, Windows NT, and Linux. Booting the operating system(s) is another major milestone; an e-mail sent from the prototype system announces that the new processor is alive. Each generation of Alpha processor has been able to boot an operating system with rst-pass chips, an accomplishment that the Alpha teams are extremely proud of. This allows the team to conduct much of the debug phase with the aid of an operating system and using real software applications to test the design. As engineers nd bugs in the design, we incorporate xes into a second or even third pass. Each pass of the design entails a repeat of the design, layout, verication, fabrication, and debug steps.

Compaq system design groups. The system groups provide input to product planning, schedule management, and, of course, the feature set. From the very beginning, the Alpha team has invested in best-of-the-art CAD tools and processes. Upper management recognized that highperformance processor design was so specialized as to require capabilities and tools that just dont come from the commodity electronic design automation market. Alphas CAD development group has produced advanced tools for everything from high-level hardware modeling to special-purpose design-rule checkers. Sophisticated tools often require sophisticated users, but the low turnover in the hardware design group allows us to effectively deploy these special-purpose, sophisticated design automation tools.

As schematics are completed, a team of layout designers begins to translate them into descriptions of actual chip geometries.

Cultural factors
Certainly, the organization has encouraged and enabled close ties among architecture, circuit design, and base-technology development. The organization lacks stratication and maintains an ethic of cooperation that frowns upon throwing the problem over the wall. These factors provide an environment in which iteration and compromise allow the team to make the most of the available talent and technical resources. The Alpha design team has also always had a clear technical charter. Although business models may have changed in the 10 years since the rst Alpha processor effort began, the technical mandate has always been to build the worlds fastest microprocessor. Each major new processor design has taken that as its primary goal. This has the happy consequence of allowing the team to develop cost-reduced designs that often outperform all but our own newest designs. Most visitors to the Alpha design team are surprised by the number of engineers in the group with eight, 10, even 15 years and more with the same company. This comparatively low turnover allows the organization to invest in the career development of each team member. It is much easier to justify two or three years of intense mentoring of a new hire if management can expect the newly trained engineer to stay. As engineers gain more experience, there is less need for a rigid design guide: We can place more trust in an individual engineers judgment. This increased exibility allows engineers to make trade-offs at every level of the design process. Just as low turnover provides an opportunity for more intense training, it also provides an opportunity for each engineer to acquire a broader set of skills. Although Ive discussed the design process as divided into discrete steps, Compaq has found signicant advantage in avoiding strict correspondence between tasks along the development path and individual team members. At various times in the project, team members might
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WHY DOES THIS WORK?

With each announcement of a new Alpha processor, presenters, project leaders, and marketeers are asked the same question: Why is it that the industrys highest performing processors come from a design group centered in Shrewsbury, a small town in Massachusetts? It is likely that no one will ever know the complete reason, but Id like to suggest a few factors that clearly make a difference.

Technical factors
First, the Alpha instruction set architecture was among the last of the major RISC instruction sets introduced. In fact, it was preceded by at least two other proposals within Digital Equipment Corp. (The original home of the Alpha processor, Digital was purchased by Compaq Computer Corp. in 1998.) Alphas instruction set clearly beneted from the experiences of other design teams both within the company and in the rest of the industry. As a result, the instruction set presents relatively few quirks or impediments to high-performance implementations. But the instruction set design is by no means the greatest contributor to the teams success. Alpha processors have always had the benet of excellent compilers, and the corporations investment in compiler technology is substantial. Compaqs compiler development groups work closely with the processor architects to tune our products to make optimal use of each generations new features. The Alpha team also benets from close ties to our major rst-level customerthe

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It may take as little as three weeks from tape out to the arrival of the rst chips.

rom assembling a team to assembling the nal design package for fabrication, the whole effort seems sometimes like a dance. Like dancers, we all have a pretty good idea as to what will come next, though there are always little surprises along the way. While the dance is always fun, it is the surprises that make it exciting. O

work on tasks that would normally be outside their job function. A circuit designer, for example, might contribute to RTL modeling (often viewed as an architects job) or CAD tool development. An architect might draw a schematic or two or help in circuit verication. Not only does such a practice promote the development of each team member, it also provides an opportunity for closer cooperation among groups within the team. This practice results in a design that takes advantage of the best efforts and advances the team can make in circuits, logic, architecture, and tool design. Perhaps the most striking and dening characteristic of the Alpha design team is its sense of a shared culture. The design processes are encoded, more often than not, in a set of rituals rather than a set of documents. The process is passed on from the more experienced engineers to those at the start of their careers. This cultural memory is embodied in the group as a whole rather than in any one team member or even any small subgroup.

Reference 1. J. Edmondson and M. Reilly, Performance Simulation of an Alpha Microprocessor, Computer, May 1998, pp. 50-58.

Matt Reilly is a senior member of technical staff at Compaq Computer Corp., where he helps develop the microarchitecture for Compaqs next-generation Alpha microprocessors. Reilly received a BSEE from Virginia Polytechnic Institute and State University and an MSEE and a PhD in computer engineering from Carnegie Mellon University. He is a member of the IEEE.

Contact Reilly at Compaq Computer Corp., 334 South St., SHR3-1/S30, Shrewsbury, MA 01545; matthew.reilly@compaq.com.

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