Circuit Analysis

Rollins, J.G., Bendix, P.
Computer Software for Circuit Analysis and Design

The Electrical Engineering Handbook
Ed. Richard C. Dorf
Boca Raton: CRC Press LLC, 2000
2000 by CRC Press LLC
1
13
Compufer Solfvare
lor CIrcuIf AnaIysIs
and IesIgn
13.1 Analog Ciicuit Simulation
Intioduction DC (Steady-State) Analysis AC Analysis Tiansient
Analysis Piocess and Device Simulation Piocess Simulation
Device Simulation Appendix
13.2 Paiametei Extiaction foi Analog Ciicuit Simulation
Intioduction MOS DC Models BSIM Extiaction Stiategy in
Detail
13.1 Ana!ug Circuit Simu!atiun
j. Cregory Fo||n
Intruductiun
Computei-aided simulation is a poweiful aid duiing the design oi analysis of electionic ciicuits and semicon-
ductoi devices. The fist pait of this chaptei focuses on analog ciicuit simulation. The second pait coveis
simulations of semiconductoi piocessing and devices. While the main emphasis is on analog ciicuits, the same
simulation techniques may, of couise, be applied to digital ciicuits (which aie, aftei all, composed of analog
ciicuits). The main limitation will be the size of these ciicuits because the techniques piesented heie piovide
a veiy detailed analysis of the ciicuit in question and, theiefoie, would be too costly in teims of computei
iesouices to analyze a laige digital system.
The most widely known and used ciicuit simulation piogiam is SPICE (simulation piogiam with integiated
ciicuit emphasis). This piogiam was fist wiitten at the Univeisity of Califoinia at Beikeley by Lauience Nagel
in 1975. Reseaich in the aiea of ciicuit simulation is ongoing at many univeisities and industiial sites. Com-
meicial veisions of SPICE oi ielated piogiams aie available on a wide vaiiety of computing platfoims, fiom
small peisonal computeis to laige mainfiames. A list of some commeicial simulatoi vendois can be found in
the Appendix.
It is possible to simulate viitually any type of ciicuit using a piogiam like SPICE. The piogiams have built-
in elements foi iesistois, capacitois, inductois, dependent and independent voltage and cuiient souices, diodes,
MOSFETs, JFETs, BJTs, tiansmission lines, tiansfoimeis, and even tiansfoimeis with satuiating coies in some
veisions. Found in commeicial veisions aie libiaiies of standaid components which have all necessaiy
1
The mateiial in this chaptei was pieviously published by CRC Piess in T|e Crtus anJ F|ers HanJ|oo|, Wai-Kai Chen,
Ed., 1995.
}. Cregory RoIIIns
Tec|no|ogy Mode|ng
Aocore, Inc.
efer BendIx
ISI Iogc Cor.
1
paiameteis pieftted to typical specifcations. These libiaiies include items such as disciete tiansistois, op amps,
phase-locked loops, voltage iegulatois, logic integiated ciicuits (ICs) and satuiating tiansfoimei coies.
Computei-aided ciicuit simulation is now consideied an essential step in the design of integiated ciicuits,
because without simulation the numbei of tiial iuns" necessaiy to pioduce a woiking IC would gieatly inciease
the cost of the IC. Simulation piovides othei advantages, howevei:
The ability to measuie inaccessible" voltages and cuiients. Because a mathematical model is used all
voltages and cuiients aie available. No loading pioblems aie associated with placing a voltmetei oi
oscilloscope in the middle of the ciicuit, with measuiing diffcult one-shot wave foims, oi piobing a
micioscopic die.
Mathematically ideal elements aie available. Cieating an ideal voltage oi cuiient souice is tiivial with a
simulatoi, but impossible in the laboiatoiy. In addition, all component values aie exact and no paiasitic
elements exist.
It is easy to change the values of components oi the confguiation of the ciicuit. Unsoldeiing leads oi
iedesigning IC masks aie unnecessaiy.
Unfoitunately, computei-aided simulation has its own pioblems:
Real ciicuits aie distiibuted systems, not the lumped element models" which aie assumed by simulatois.
Real ciicuits, theiefoie, have iesistive, capacitive, and inductive paiasitic elements piesent besides the
intended components. In high-speed ciicuits these paiasitic elements aie often the dominant peifoi-
mance-limiting elements in the ciicuit, and must be painstakingly modeled.
Suitable piedefned numeiical models have not yet been developed foi ceitain types of devices oi
electiical phenomena. The softwaie usei may be iequiied, theiefoie, to cieate his oi hei own models
out of othei models which aie available in the simulatoi. (An example is the solid-state thyiistoi which
may be cieated fiom a NPN and PNP bipolai tiansistoi.)
The numeiical methods used may place constiaints on the foim of the model equations used.
The following sections considei the thiee piimaiy simulation modes: DC, AC, and tiansient analysis. In each
section an oveiview is given of the numeiical techniques used. Some examples aie then given, followed by a
biief discussion of common pitfalls.
DC [Steady-State) Ana!ysis
DC analysis calculates the state of a ciicuit with fxed (non-time vaiying) inputs aftei an infnite peiiod of time.
DC analysis is useful to deteimine the opeiating point (Q-point) of a ciicuit, powei consumption, iegulation
and output voltage of powei supplies, tiansfei functions, noise maigin and fanout in logic gates, and many
othei types of analysis. In addition DC analysis is used to fnd the staiting point foi AC and tiansient analysis.
To peifoim the analysis the simulatoi peifoims the following steps:
1. All capacitois aie iemoved fiom the ciicuit (ieplaced with opens).
2. All inductois aie ieplaced with shoits.
3. Modifed nodal analysis is used to constiuct the nonlineai ciicuit equations. This iesults in one equation
foi each ciicuit node plus one equation foi each voltage souice. Modifed nodal analysis is used iathei
than standaid nodal analysis because an ideal voltage souice oi inductance cannot be iepiesented using
noimal nodal analysis. To iepiesent the voltage souices, loop equations (one foi each voltage souice oi
inductoi), aie included as well as the standaid node equations. The node voltages and voltage souice
cuiients, then, iepiesent the quantities which aie solved foi. These foim a vectoi x. The ciicuit equations
can also be iepiesented as a vectoi F(x) 0.
4. Because the equations aie nonlineai, Newton`s method (oi a vaiiant theieof) is then used to solve the
equations.
Erump|e 1J.1. Simulation Voltage Regulator: We shall now considei simulation of the type 723 voltage
iegulatoi IC, shown in Fig. 13.1. We wish to simulate the IC and calculate the sensitivity of the output IV
chaiacteiistic and veiify that the output cuiient follows a fold-back" type chaiacteiistic undei oveiload
conditions.
The IC itself contains a voltage iefeience souice and opeiational amplifei. Simple models foi these elements
aie used heie iathei than iepiesenting them in theii full foim, using tiansistois, to illustiate model development.
The use of simplifed models can also gieatly ieduce the simulation effoit. (Foi example, the simple op amp
used heie iequiies only eight nodes and ten components, yet iealizes many advanced featuies.)
Note in Fig. 13.1 that the numbeis next to the wiies iepiesent the ciicuit nodes. These numbeis aie used to
desciibe the ciicuit to the simulatoi. In most SPICE-type simulatois the nodes aie iepiesented by numbeis,
with the giound node being node zeio. Refeiiing to Fig. 13.2, the 723 iegulatoi and its inteinal op amp aie
iepiesented by subciicuits. Each subciicuit has its own set of nodes and components. Subciicuits aie useful foi
encapsulating sections of a ciicuit oi when a ceitain section needs to be used iepeatedly (see next section).
The following piopeities aie modeled in the op amp:
1. Common mode gain
2. Diffeiential mode gain
3. Input impedance
4. Output impedance
5. Dominant pole
6. Output voltage clipping
The input teiminals of the op amp connect to a T" iesistance netwoik, which sets the common and
diffeiential mode input iesistance. Theiefoie, the common mode iesistance is RCM - RDIF 1.1E6 and the
diffeiential mode iesistance is RDIF1 - RDIF2 2.0E5.
Dependent cuiient souices aie used to cieate the main gain elements. Because these souices foice cuiient
into a 1-O iesistoi, the voltage gain is GmR at low fiequency. In the diffeiential mode this gives (GDIFR1
100). In the common mode this gives (GCMR1(RCM/(RDIF1 - RCM 0.0909). The two diodes D1 and
D2 implement clipping by pieventing the voltage at node 6 fiom exceeding VCC oi going below VEE. The
diodes aie made ideal" by ieducing the ideality factoi n. Note that the diode cuiient is I
J
I
s
exp(V
J
/(nV
)) -
1], wheie V
is the theimal voltage (0.026 V). Thus, ieducing n makes the diode tuin on at a lowei voltage.
A single pole is cieated by placing a capacitoi (C1) in paiallel with iesistoi R1. The pole fiequency is theiefoie
given by 1.0/(2rR1C1). Finally, the output is diiven by the voltage-contiolled voltage souice E1 (which has a
voltage gain of unity), thiough the output iesistoi R4. The output iesistance of the op amp is theiefoie equal to R4.
To obseive the output voltage as a function of iesistance, the iegulatoi is loaded with a voltage souice (VOUT)
and the voltage souice is swept fiom 0.05 to 6.0 V. A plot of output voltage vs. iesistance can then be obtained
FIGURE 13.1 Regulatoi ciicuit to be used foi DC analysis, cieated using PSPICE.
by plotting VOUT vs. VOUT/I(VOUT) (using PROBE in this case; see Fig. 13.3). Note that foi this ciicuit,
eventhough a cuiient souice would seem a moie natuial choice, a voltage souice must be used as a load iathei
than a cuiient souice because the output chaiacteiistic cuive is multivalued in cuiient. If a cuiient souice weie
used it would not be possible to easily simulate the entiie cuive. Of couise, many othei inteiesting quantities
can be plotted; foi example, the powei dissipated in the pass tiansistoi can be appioximated by plotting
IC(Q3)VC(Q3).
Foi these simulations PSPICE was used iunning on an IBM PC. The simulation took < 1 min of CPU time.
PIt]u||s. Conveigence pioblems aie sometimes expeiienced if diffcult" bias conditions aie cieated. An exam-
ple of such a condition is if a diode is placed in the ciicuit backwaids, iesulting in a laige foiwaid bias voltage,
SPICE will have tiouble iesolving the cuiient. Anothei diffcult case is if a cuiient souice weie used instead of
FIGURE 13.2 SPICE input listing of iegulatoi ciicuit shown in Fig. 13.1.
FIGURE 13.3 Output chaiacteiistics of iegulatoi ciicuit using PSPICE.
a voltage to bias the output in the pievious example. If the usei then tiied to inciease the output cuiient above
10 A, SPICE would not be able to conveige because the iegulatoi will not allow such a laige cuiient.
AC Ana!ysis
Ac analysis uses phasoi analysis to calculate the fiequency iesponse of a ciicuit. The analysis is useful foi
calculating the gain. 3 dB fiequency input and output impedance, and noise of a ciicuit as a function of
fiequency, bias conditions, tempeiatuie, etc.
Numerica! Methud
1. A DC solution is peifoimed to calculate the Q-point foi the ciicuit.
2. A lineaiized ciicuit is constiucted at the Q point. To do this, all nonlineai elements aie ieplaced by theii
lineaiized equivalents. Foi example, a nonlineai cuiient souice I aV
1
2
- |V
2
3
would be ieplaced by a
lineai voltage contiolled cuiient souice I V
1
(2aV
1q
) - V
2
(3|V
2q
2
).
3. All inductois and capacitois aie ieplaced by complex impedances, and conductances evaluated at the
fiequency of inteiest.
4. Nodal analysis is now used to ieduce the ciicuit to a lineai algebiaic complex matiix. The AC node
voltages may now be found by applying an excitation vectoi (which iepiesents the independent voltage
and cuiient souices) and using Gaussian elimination (with complex aiithmetic) to calculate the node
voltages.
AC analysis does have limitations and the following types of nonlineai oi laige signal pioblems cannot be
modeled:
1. Distoition due to nonlineaiities such as clipping, etc.
2. Slew iate-limiting effects
3. Analog mixeis
4. Oscillatois
Noise analysis is peifoimed by including noise souices in the models. Typical noise souices include theimal
noise in iesistois I
n
2
4|T A[ /R, and shot I
n
2
2qI
J
A[ , and ickei noise in semiconductoi devices. Heie, T is
tempeiatuie in Kelvins, | is Boltzmann`s constant, and A[ is the bandwidth of the ciicuit. These noise souices
aie inseited as independent cuiient souices, In
,
([ ) into the AC model. The iesulting cuiient due to the noise
souice is then calculated at a usei-specifed summation node(s) by multiplying by the gain function between
the noise souice and the summation node
,s
([ ). This pioceduie is iepeated foi each noise souice and then
the contiibutions at the iefeience node aie ioot mean squaied (RMS) summed to give the total noise at the
iefeience node. The equivalent input noise is then easily calculated fiom the tiansfei function between the
ciicuit input and the iefeience node
s
([ ). The equation desciibing the input noise is theiefoie:
Erump|e 1J.2. Cascode Ampliner with Macro Models: Heie, we fnd the gain, bandwidth, input impedance,
and output noise of a cascode amplifei. The ciicuit foi the amplifei is shown in Fig. 13.5. The ciicuit is assumed
to be fabiicated in a monolithic IC piocess, so it will be necessaiy to considei some of the paiasitics of the IC
piocess. A cioss-section of a typical IC bipolai tiansistoi is shown in Fig. 13.4 along with some of the paiasitic
elements. These paiasitic elements aie easily included in the amplifei by cieating a macio model" foi each
tiansistoi. The macio model is then implemented in SPICE foim using subciicuits.
The input to the ciicuit is a voltage souice (VIN), applied diffeientially to the amplifei. The output will be
taken diffeientially acioss the collectois of the two uppei tiansistois at nodes 2 and 3. The input impedance
of the amplifei can be calculated as VIN/I(VIN) oi because VIN 1.0 just as 1/I(VIN). These quantities aie
shown plotted using PROBE in Fig. 13.6. It can be seen that the gain of the amplifei falls off at high fiequency
I
[
[ In [
s
,s ,
,
, ,
, , , ,

1
2
FIGURE 13.4 BJT cioss-section with macio model elements.
FIGURE 13.5 Cascode amplifei foi AC analysis, cieated using PSPICE.
FIGURE 13.6 Gain and input impedance of cascode amplifei.
as expected. The input impedance also diops because paiasitic capacitances shunt the input. This example took
<1 min on an IBM PC.
PIt]u||s. Many novice useis will foiget that AC analysis is a lineai analysis. They will, foi example, apply a
1-V signal to an amplifei with 5-V powei supplies and a gain of 1000 and be suipiised when SPICE tells them
that the output voltage is 1000 V. Of couise, the voltage geneiated in a simple amplifei must be less than the
powei supply voltage, but to examine such clipping effects, tiansient analysis must be used. Likewise, selection
of a piopei Q point is impoitant. If the amplifei is biased in a satuiated poition of its iesponse and AC analysis
is peifoimed, the gain iepoited will be much smallei than the actual laige signal gain.
Transient Ana!ysis
Tiansient analysis is the most poweiful analysis capability of a simulatoi because the tiansient iesponse is so
haid to calculate analytically. Tiansient analysis can be used foi many types of analysis, such as switching speed,
distoition, basic opeiation of ceitain ciicuits like switching powei supplies. Tiansient analysis is also the most
CPU intensive and can iequiie 100 oi 1000 times the CPU time as a DC oi AC analysis.
Numerica! Methud
In a tiansient analysis time is discietized into inteivals called time steps. Typically the time steps aie of unequal
length, with the smallest steps being taken duiing poitions of the analysis when the ciicuit voltages and cuiients
aie changing most iapidly. The capacitois and inductois in the ciicuit aie then ieplaced by voltage and cuiient
souices based on the following pioceduie.
The cuiient in a capacitoi is given by I
t
CJV
t
/J. The time deiivative can be appioximated by a diffeience
equation:
In this equation the supeisciipt | iepiesents the numbei of the time step. Heie, | is the time step we aie
piesently solving foi and (| - 1) is the pievious time step. This equation can be solved to give the capacitoi
cuiient at the piesent time step.
Heie, A
|
-
|-1
, oi the length of the time step. As time steps aie advanced, V
t
|-1

V
t
|
; I
t
|-1
I
t
|
. Note
that the second two teims on the iight hand side of the above equation aie dependent only on the capacitoi
voltage and cuiient fiom the pievious time step, and aie theiefoie fxed constants as fai as the piesent step is
conceined. The fist teim is effectively a conductance (g 2C/A) multiplied by the capacitoi voltage, and the
second two teims could be iepiesented by an independent cuiient souice. The entiie tiansient model foi the
capacitoi theiefoie consists of a conductance in paiallel with two cuiient souices (the numeiical values of these
aie, of couise, diffeient at each time step). Once the capacitois and inductois have been ieplaced as indicated,
the noimal method of DC analysis is used. One complete DC analysis must be peifoimed foi each time point.
This is the ieason that tiansient analysis is so CPU intensive. The method outlined heie is the tiapezoidal time
integiation method and is used as the default in SPICE.
Erump|e 1J.J. Phase-Locked Loop Circuit: Figuie 13.7 shows the phase-locked loop ciicuit. The phase
detectoi and voltage-contiolled oscillatoi aie modeled in sepaiate subciicuits. Examine the VCO subciicuit and
note the PULSE-type cuiient souice ISTART connected acioss the capacitoi. The souice gives a cuiient pulse
03.E-6 s wide at the stait of the simulation to stait the VCO iunning. To stait a tiansient simulation SPICE
fist computes a DC opeiating point (to fnd the initial voltages V
t
|-1
on the capacitois). As this DC point is a
valid, although not necessaiily stable, solution, an oscillatoi will iemain at this point indefnitely unless some
peituibation is applied to stait the oscillations. Remembei, this is an ideal mathematical model and no noise
I I C
V V

t
|
t
| t
|
t
|
| |
+

1
1
1
2
I V C V C I
t
|
t
|
t
|
t
|
, ,

, ,

2 2
1 1
A A .
souices oi asymmetiies exist that would stait a ieal oscillatoi-it must be done manually. The capacitoi C1
would have to be placed off-chip, and bond pad capacitance (CPAD1 and CPAD2) have been included at the
capacitoi nodes. Including the pad capacitances is veiy impoitant if a small capacitoi C1 is used foi high-
fiequency opeiation.
In this example, the PLL is to be used as a FM detectoi ciicuit and the FM signal is applied to the input
using a single fiequency FM voltage souice. The caiiiei fiequency is 600 kHz and the modulation fiequency
is 60 kHz. Figuie 13.8 shows the input voltage and the output voltage of the PLL at the VCO output and at the
phase detectoi output. It can be seen that aftei a biief staiting tiansient, the PLL locks onto the input signal
FIGURE 13.7 Phase-locked loop ciicuit foi tiansient analysis, cieated with PSPICE.
FIGURE 13.8 Tiansient analysis iesults of PLL ciicuit, cieated using PSPICE.
and that the phase detectoi output has a stiong 60-kHz component. This example took 251 s on a Sun SPARC-2
woikstation (3046 time steps, with an aveiage of 5 Newton iteiations pei time step).
PIt]u||s. Occasionally SPICE will fail and give the message Timestep too small in tiansient analysis", which
means that the piocess of Newton iteiations at ceitain time steps could not be made to conveige. One of the
most common causes of this is the specifcation of a capacitoi with a value that is much too laige, foi example,
specifying a 1-F capacitoi instead of a 1 pF capacitoi (an easy mistake to make by not adding the p" in the
value specifcation). Unfoitunately, we usually have no way to tell which capacitoi is at fault fiom the type of
failuie geneiated othei than to manually seaich the input deck.
Othei tiansient failuies aie caused by MOSFET models. Some models contain discontinuous capacitances
(with iespect to voltage) and otheis do not conseive chaige. These models can vaiy fiom veision to veision so
it is best to check the usei`s guide.
Prucess and Device Simu!atiun
Piocess and devices simulation aie the steps that piecede analog ciicuit simulation in the oveiall simulation
ow (see Fig. 13.9). The simulatois aie also diffeient in that they aie not measuiement diiven as aie analog
ciicuit simulatois. The input to a piocess simulatoi is the sequence of piocess steps peifoimed (times, tempei-
atuies, gas concentiations) as well as the mask dimensions. The output fiom the piocess simulatoi is a detailed
desciiption of the solid-state device (doping piofles, oxide thickness, junction depths, etc.). The input to the
device simulatoi is the detailed desciiption geneiated by the piocess simulatoi (oi via measuiement). The
output of the device simulatoi is the electiical chaiacteiistics of the device (IV cuives, capacitances, switching
tiansient cuives).
Piocess and device simulation aie becoming incieasingly impoitant and widely used duiing the integiated
ciicuit design piocess. A numbei of ieasons exist foi this:
As device dimensions shiink, second-oidei effects can become dominant. Modeling of these effects is
diffcult using analytical models.
Computeis have gieatly impioved, allowing time-consuming calculations to be peifoimed in a ieasonable
amount of time.
Simulation allows access to impossible to measuie physical chaiacteiistics.
Analytic models aie not available foi ceitain devices, foi example, thyiistois, heteiojunction devices and
IGBTS.
Analytic models have not been developed foi ceitain physical phenomena, foi example, single event
upset, hot election aging effects, latchup, and snap-back.
Simulation iuns can be used to ieplace split lot iuns. As the cost to fabiicate test devices incieases, this
advantage becomes moie impoitant.
Simulation can be used to help device, piocess, and ciicuit designeis undeistand how theii devices and
piocesses woik.
Cleaily, piocess and device simulation is a topic which can be and has been the topic of entiie texts. The
following sections attempt to piovide an intioduction to this type of simulation, give seveial examples showing
what the simulations can accomplish, and piovide iefeiences to additional souices of infoimation.
FIGURE 13.9 Data ow foi complete piocess-device-ciicuit modeling.
Prucess Simu!atiun
Integiated ciicuit piocessing involves a numbei of steps which aie designed to deposit (deposition, ion implan-
tation), iemove (etching), iedistiibute (diffusion), oi tiansfoim (oxidation) the mateiial of which the IC is
made. Most piocess simulation woik has been in the aieas of diffusion, oxidation, and ion implantation;
howevei, piogiams aie available that can simulate the exposuie and development of photo-iesist, the associated
optical systems, as well as gas and liquid phase deposition and etch.
In the following section a veiy biief discussion of the goveining equations used in SUPREM (fiom Stanfoid
Univeisity, Califoinia) will be given along with the iesults of an example simulation showing the powei of the
simulatoi.
Dillusiun
The main equation goveining the movement of electiically chaiged impuiities (acceptois in this case) in the
ciystal is the diffusion equation:
Heie, C is the concentiation (#/cm
3
) of impuiities, C
a
is the numbei of electiically active impuiities (#/cm
3
),
q is the election chaige, | is Boltzmann`s constant, T is tempeiatuie in degiees Kelvin, D is the diffusion constant,
and E is the built-in electiic feld. The built-in electiic feld E in (V/cm) can be found fiom:
In this equation n is the election concentiation (#/cm
3
), which in tuin can be calculated fiom the numbei of
electiically active impuiities (C
a
). The diffusion constant (D) is dependent on many factois. In silicon the
following expiession is commonly used:
The foui D components iepiesent the diffeient possible chaige states foi the impuiity: (x) neutial, (-)
positive, (-) negative, () doubly negatively chaiged. n
is the intiinsic caiiiei concentiation, which depends

only on tempeiatuie. Each D component is in tuin given by an expiession of the type
Heie, and B aie expeiimentally deteimined constants, diffeient foi each type of impuiity (x, -, -, ). B
is the activation eneigy foi the piocess. This expiession deiives fiom the Maxwellian distiibution of paiticle
eneigies and will be seen many times in piocess simulation. It is easily seen that the diffusion piocess is stiongly
inuenced by tempeiatuie. The teim F
IV
is an enhancement factoi which is dependent on the concentiation
of inteistitials and vacancies within the ciystal lattice (an inteistitial is an extia silicon atom which is not located
on a iegulai lattice site; a vacancy is a missing silicon atom which iesults in an empty lattice site) F
IV
~ C
I
-
C
. The concentiation of vacancies, C
, and inteistitials, C
I
, aie in tuin deteimined by theii own diffusion
equation:
o
o
C
D C
DqC
|T
a
V V
_
,
V
|T
q n
n
1
D F D D
n
n
D
n
n
D
n
n
IV x

+ + +

_
,
_
,
+
2
D
B
|T

_
,
exp
o
o
C
D C R C
V V
+V V +
In this equation D
V
is anothei diffusion constant of the foim exp(-B/|T). R and C iepiesent the iecom-
bination and geneiation of vacancies and inteistitials. Note that an inteistitial and a vacancy may iecombine
and in the piocess destioy each othei, oi an inteistitial and a vacancy paii may be simultaneously geneiated
by knocking a silicon atom off its lattice site. Recombination can occui anywheie in the device via a bulk
iecombination piocess R (C
V
C
1
)exp(-B/|T). Geneiation occuis wheie theie is damage to the ciystal
stiuctuie, in paiticulai at inteifaces wheie oxide is being giown oi in iegions wheie ion implantation has
occuiied, as the high-eneigy ions can knock silicon atoms off theii lattice sites.
Oxidatiun
Oxidation is a piocess wheieby silicon ieacts with oxygen (oi with watei) to foim new silicon dioxide. Con-
seivation of the oxidant iequiies the following equation:
Heie, F is the ux of oxidant (#/cm
2
/s), N is the numbei of oxidant atoms iequiied to make up a cubic centimetei
of oxide, and Jy/J is the velocity with which the Si-SiO
2
inteiface moves into the silicon. In geneial the gieatei
the concentiation of oxidant (C
0
), the fastei the giowth of the oxide and the gieatei the ux of oxidant needed
at the Si-SiO
2
inteiface. Thus, F |
s
C
0
. The ux of oxidant into the oxide fiom the gaseous enviionment is
given by:
F |(HP
ox
- C
0
)
Heie H is a constant, P is the paitial piessuie of oxygen in the gas, and C
0
is the concentiation of oxidant in
the oxide at the suiface and | is of the foim exp(-B/|T). Finally, the movement of the oxidant within the
alieady existing oxide is goveined by diffusion: F D
0
VC. When all these equations aie combined, it is found
that (in the one-dimensional case) oxides giow lineaily Jy/J ~ when the oxide is thin and the oxidant can
move easily thiough the existing oxide. As the oxide giows thickei Jy/J ~ because the movement of the
oxidant thiough the existing oxide becomes the iate-limiting step.
Modeling two-dimensional oxidation is a challenging task. The newly cieated oxide must ow" away fiom
the inteiface wheie it is begin geneiated. This ow of oxide is similai to the ow of a veiy thick oi viscous
liquid and can be modeled by a cieeping ow equation:
V
2
V ~ VP
V V 0
V is the velocity at which the oxide is moving and P is the hydiostatic piessuie. The second equation iesults
foim the incompiessibility of the oxide. The vaiying piessuie P within the oxide leads to mechanical stiess,
and the oxidant diffusion constant D
0
and the oxide giowth iate constant |
s
aie both dependent on this stiess.
The oxidant ow and the oxide ow aie theiefoie coupled because the oxide ow depends on the iate at which
oxide is geneiated at the inteiface and the iate at which the new oxide is geneiated depends on the availability
of oxidant, which is contiolled by the mechanical stiess.
Iun Imp!antatiun
Ion implantation is noimally modeled in one of two ways. The fist involves tables of moments of the fnal
distiibution of the ions which aie typically geneiated by expeiiment. These tables aie dependent on the eneigy
and the type of ion being implanted. The second method involves Monte-Cailo simulation of the implantation
piocess. In Monte-Cailo simulation the tiajectoiies of individual ions aie followed as they inteiact with (bounce
off) the silicon atoms in the lattice. The tiajectoiies of the ions, and the iecoiling Si atoms (which can stiike
moie Si atoms) aie followed until all come to iest within the lattice. Typically seveial thousand tiajectoiies aie
Jy
J N

simulated (each will be diffeient due to the iandom piobabilities used in the Monte-Cailo method) to build
up the fnal distiibution of implanted ions.
Piocess simulation is always done in the tiansient mode using time steps as was done with tiansient ciicuit
simulation. Because paitial diffeiential equations aie involved, iathei than oidinaiy diffeiential equations,
spatial discietization is needed as well. To numeiically solve the pioblem, the diffeiential equations aie dis-
cietized on a giid. Eithei iectangulai oi tiiangulai giids in one, two, oi thiee dimensions aie commonly used.
This discietization piocess iesults in the conveision of the paitial diffeiential equations into a set of nonlineai
algebiaic equations. The nonlineai equations aie then solved using a Newton method in a way veiy similai to
the method used foi the ciicuit equations in SPICE.
Erump|e 1J.4. NMOS Transistor: In this example the piocess steps used to fabiicate a typical NMOS tian-
sistoi will be simulated using SUPREM-4. These steps aie
1. Giow initial oxide (30 min at 1000 K)
2. Deposit nitiide layei (a nitiide layei will pievent oxidation of the undeilying silicon)
3. Etch holes in nitiide layei
4. Implant P- channel stop (boion dose 5e12, eneigy 50 keV)
5. Giow the feld oxide (180 min at 1000 K wet O
2
)
6. Remove all nitiide
7. Peifoim P channel implant (boion dose 1e11, eneigy 40 keV)
8. Deposit and etch polysilicon foi gate
9. Oxidize the polysilicon (30 min at 1000 K, diy O
2
)
10. Implant the light doped diain (aisenic dose 5e13 eneigy 50 keV)
11. Deposit sidewall space oxide
12. Implant souice and diain (aisenic, dose 1e15, eneigy 200 keV)
13. Deposit oxide layei and etch contact holes
14. Deposit and etch metal
The top 4 m of the completed stiuctuie, as geneiated by SUPREM-4, is shown in Fig. 13.10. The actual
simulation stiuctuie used is 200 m deep to allow coiiect modeling of the diffusion of the vacancies and
inteistitials. The gate is at the centei of the device. Notice how the edges of the gate have lifted up due to the
diffusion of oxidant undei the edges of the polysilicon (the polysilicon, as deposited in step 8, is at). The
dashed contouis show the concentiation of dopants in both the oxide and silicon layeis. The shoit dashes
FIGURE 13.10 Complete NMOS tiansistoi cioss section geneiated by piocess simulation, cieated with TMA SUPREM-4.
indicate N-type mateiial, while the longei dashes indicate P-type mateiial. This entiie simulation iequiies about
30 min on a Sun SPARC-2 woikstation.
Device Simu!atiun
Device simulation uses a diffeient appioach fiom that of conventional lumped ciicuit models to deteimine the
electiical device chaiacteiistics. Wheieas with analytic oi empiiical models all chaiacteiistics aie deteimined
by ftting a set of adjustable paiameteis to measuied data, device simulatois deteimine the electiical behavioi
by numeiically solving the undeilying set of diffeiential equations. The fist is the Poisson equation, which
desciibes the electiostatic potential within the device
N
J
and N
a
aie the concentiation of donois and acceptois, i.e., the N- and P-type dopants. Q
[
is the concentiation
of fxed chaige due, foi example, to tiaps oi inteiface chaige. The election and hole concentiations aie given
by n and , iespectively, and + is the electiostatic potential.
A set of continuity equations desciibes the conseivation of elections and holes:
In these equations R and C desciibe the iecombination and geneiation iates foi the elections and holes. The
iecombination piocess is inuenced by factois such as the numbei of elections and holes piesent as well as the
doping and tempeiatuie. The geneiation iate is also dependent upon the caiiiei concentiations, but is most
stiongly inuenced by the electiic feld, with incieasing electiic felds giving laigei geneiation iates. Because
this geneiation piocess is included, device simulatois aie capable of modeling the bieakdown of devices at high
voltage. J
n
and J
aie the election and hole cuiient densities (in ampeies pei squaie centimetei). These cuiient
densities aie given by anothei set of equations
In this equation | is Boltzmann`s constant, is the caiiiei mobility, which is actually a complex function of
the doping, n, , electiic feld, tempeiatuie, and othei factois. In silicon the election mobility will iange between
50 and 1000 and the hole mobility will noimally be a factoi of 2 smallei. In othei semiconductois such as
gallium aisenide the election mobility can be as high as 5000. T
n
and T
aie the election and hole mean

tempeiatuies, which desciibe the aveiage caiiiei eneigy. In many models these default to the device tempeiatuie
(300 K). In the fist teim the cuiient is piopoitional to the electiic feld (V+), and this teim iepiesents the
diift of caiiieis with the electiic feld. In the second teim the cuiient is piopoitional to the giadient of the
caiiiei concentiation (Vn), so this teim iepiesents the diffusion of caiiieis fiom iegions of high concentiation
to those of low concentiation. The model is theiefoie called the diift-diffusion model.
V V +
, ,
+
r + q N N n Q
a J [
o
o
o
o
n
q
R C
q
R C
n
V +
_
,
V +
_
,
1
1
n
n
q n
|T
q
n
q
|T
q
V + V
_
,
V V
_
,
+
+
In devices in which self-heating effects aie impoitant, a lattice heat equation can also be solved to give the
inteinal device tempeiatuie:
wheie H is the heat geneiation teim, which includes iesistive (Joule) heating as well as iecombination heating,
H
u
. The teims o(T), i(T) iepiesent the specifc heat and the theimal conductivity of the mateiial (both
tempeiatuie dependent). Inclusion of the heat equation is essential in many powei device pioblems.
As with piocess simulation paitial diffeiential equations aie involved, theiefoie, a spatial discietization is
iequiied. As with ciicuit simulation pioblems, vaiious types of analysis aie available:
Steady state (DC), used to calculate chaiacteiistic cuives of MOSFETs, BJTs diodes, etc.
AC analysis, used to calculate capacitances, Y-paiameteis, small signal gains, and S-paiameteis.
Tiansient analysis used foi calculation of switching and laige signal behavioi, and special types of analysis
such as iadiation effects.
Erump|e 1J.3. NMOS IV Curves: The stiuctuie geneiated in the pievious SUPREM-IV simulation is now
passed into the device simulatoi and bias voltages aie applied to the gate and diain. Models weie included with
account foi Augei and Shockley Reed Hall iecombination, doping and electiic feld-dependent mobility, and
impact ionization. The set of diain chaiacteiistics obtained is shown in Fig. 13.11. Obseive how the cuives
bend upwaid at high V
Js
as the device bieaks down. The V
g
, 1 cuive has a negative slope at I
J
1.5e-4A as
the device enteis snap-back. It is possible to model this type of behavioi because impact ionization is included
in the model.
FIGURE 13.11 I
J
vs. V
Js
cuives geneiated by device simulation, cieated with TMA MEDICI.
o
o
o
i T
T
H T T
H H
n R
, ,
+ V
, ,
V
+
, ,
V + +
Figuie 13.12 shows the inteinal behavioi of the device with V
gs
3 V and I
J
3e-4A. The flled contouis
indicate impact ionization, with the highest iate being neai the edge of the diain iight beneath the gate. This
is to be expected because this is the iegion in which the electiic feld is laigest due to the diain depletion iegion.
The daik lines indicate cuiient ow fiom the souice to the diain. Some cuiient also ows fiom the diain to
the substiate. This substiate cuiient consists of holes geneiated by the impact ionization. The tiiangulai giid
used in the simulation can be seen in the souice, diain, and gate electiodes. A similai giid was used in the
oxide and silicon iegions.
Appendix
Circuit Ana!ysis Sultvare
SPICE2, SPICE3: Univeisity of Califoinia, Beikeley
PSPICE: MicioSim Coipoiation, Iivine, CA (used in this chaptei)
HSPICE: Meta Softwaie, Campbell, CA
IsSPICE: Intusoft, San Pedio, CA
SPECTRE: Cadence Design Systems, San Jose, CA
SABRE: Analogy, Beaveiton, OR
Prucess and Device Simu!aturs
SUPREM-4, PISCES: Stanfoid Univeisity, Palo Alto, CA
MINIMOS: Technical Univeisity, Vienna, Austiia
SUPREM-4, MEDICI, DAVINCI: Technology Modeling Associates, Palo Alto, CA (used in this chaptei)
SEMICAD: Dawn Technologies, Sunnyvale, CA
Re!ated Tupics
3.2 Node and Mesh Analysis 23.1 Piocesses 27.1 Ideal and Piactical Models
FIGURE 13.12 Inteinal behavioi of MOSFET undei bias, cieated with TMA MEDICI.
Relerences
P. Antognetti and G. Massobiio, SemtonJutor Dete MoJe|ng w| SPICE, New Yoik: McGiaw-Hill, 1988.
P. W. Tuinenga, SPICE, CuJe o Crtu Smu|aon anJ na|yss Usng PSPICE, Englewood Cliffs, N.J.:
Pientice-Hall, 1988.
J. A. Connelly and P. Choi, MatromoJe|ng w| SPICE, Englewood Cliffs, N.J.: Pientice-Hall, 1992.
S. Selbeiheii, na|yss anJ Smu|aon o[ SemtonJutor Detes, Beilin: Spiingei-Veilag, 1984.
R. Dutton and Z. Yu, Tet|no|ogy CD, Comuer Smu|aon o[ IC Protess anJ Detes, Boston: Kluwei Academic,
1993.
13.2 Parameter Extractiun lur Ana!ug Circuit Simu!atiun
Perer endx
Intruductiun
Dehnitiun ul Device Mude!ing
We use vaiious teims such as device chaiacteiization, paiametei extiaction, optimization, and model ftting
to addiess an impoitant engineeiing task. In all of these, we stait with a mathematical model that desciibes
the tiansistoi behavioi. The model has a numbei of paiameteis which aie vaiied oi adjusted to match the IV
(cuiient-voltage) chaiacteiistics of a paiticulai tiansistoi oi set of tiansistois. The act of deteimining the
appiopiiate set of model paiameteis is what we call device modeling. We then use the model with the paiticulai
set of paiameteis that iepiesent oui tiansistois in a ciicuit simulatoi such as SPICE
1
to simulate how ciicuits
with oui kinds of tiansistois will behave. Usually the models aie supplied by the ciicuit simulatoi we chose.
Occasionally we may want to modify these models oi constiuct oui own models. In this case we need access
to the ciicuit simulatoi model subioutines as well as the piogiam that peifoims the device chaiacteiization.
Steps Invu!ved in Device Characterizatiun
Device chaiacteiization begins with a test chip. Without the piopei test chip stiuctuies, piopei device modeling
cannot be done fiom measuied data. A good test chip foi MOS technology would include tiansistois of vaiying
geometiies, gate oxide capacitance stiuctuies, junction diode capacitance stiuctuies, and oveilap capacitance
stiuctuies. This would be a minimal test chip. Additional stiuctuies might include iing oscillatois and othei
ciicuits foi checking the AC peifoimance of the models obtained. It is veiy impoitant that the tiansistois be
well designed and theii geometiies be chosen appiopiiate foi the technology as well as the desiied device model.
Although a complete test chip desciiption is beyond the scope of this book, be awaie that even peifect device
models cannot coiiect foi a pooi test chip.
Next we need data that iepiesent the behavioi of a tiansistoi oi set of tiansistois of diffeient sizes. these data
can come fiom diiect measuiement oi they can be pioduced by a device simulatoi such as PISCES.
2
It is also possible to use a combination of a piocess simulatoi like SUPREM-IV
3
coupled to a device simulatoi,
to piovide the simulated iesults. The benefts of using simulation ovei measuiement aie that no expensive
measuiement equipment oi fabiicated wafeis aie necessaiy. This can be veiy helpful when tiying to piedict
the device chaiacteiistics of a new fabiication piocess befoie any wafeis have been pioduced.
Once the measuied (oi simulated) data aie available, paiametei extiaction softwaie is used to fnd the best
set of model paiametei values to ft the data.
1
SPICE is a ciicuit simulation piogiam fiom the Depaitment of Electiical Engineeiing and Computei Science at the
Univeisity of Califoinia at Beikeley.
2
PISCES is a piocess simulation piogiam fiom the Depaitment of Electiical Engineeiing at Stanfoid Univeisity, Stanfoid,
CA.
3
SUPREM-IV is a piocess simulation piogiam fiom the Depaitment of Electiical Engineeiing at Stanfoid Univeisity,
Stanfoid, CA.
Least-Squares Curve Fitting [Ana!ytica!)
We begin this section by showing how to do least-squaies cuive ftting by analytical solutions, using a simple
example to illustiate the method. We then mention least-squaies cuive ftting using numeiical solutions in the
next section. We can only fnd analytical solutions to simple pioblems. The moie complex ones must iely on
numeiical techniques.
Assume a collection of measuied data, m
1
, . . ., m
n
. Foi simplicity, let these measuied data values be functions
of a single vaiiable, , which was vaiied fiom
1
thiough
n
, measuiing each m
data point at each vaiiable value
, iunning fiom 1 to n. Foi example, the m
data points might be diain cuiient of an MOS tiansistoi, and

the
might be the coiiesponding values of gate voltage. Assume that we have a model foi calculating simulated
values of the measuied data points, and let these simulated values be denoted by s
1
, . . ., s
n
. We defne the least-
squaies, ioot mean squaie (RMS) eiioi as
(13.1)
wheie a weighting teim is included foi each data point. The goal is to have the simulated data match the
measuied data as closely as possible, which means we want to minimize the RMS eiioi. Actually, what we have
called the RMS eiioi is ieally the ielative RMS eiioi, but the two teims aie used synonymously. Theie is anothei
way of expiessing the eiioi, called the absolute RMS eiioi, defned as follows:
(13.2)
wheie we have used the teim m
min
in the denominatoi to iepiesent some minimum value of the measuied data.
The absolute RMS eiioi is usually used when the measuied values appioach zeio to avoid pioblems with small
oi zeio denominatois in (13.1). Foi eveiything that follows, we considei only the ielative RMS eiioi. The best
iesult is obtained by combining the ielative RMS foimula with the absolute RMS foimula by taking the
maximum of the denominatoi fiom (13.1) oi (13.2).
We have a simple expiession foi calculating the simulated data points, s
, in teims of the input vaiiable, ,

and a numbei of model paiameteis,
1
, . . .,
m
. That is,
s
[ (
,
1
, . . . ,
m
) (13.3)
wheie [ is some function. Minimizing the RMS eiioi function is equivalent to minimizing its squaie. Also, we
can ignoie the teim in the denominatoi of (13.1) as conceins minimizing, because it is a noimalization teim.
In this spiiit, we can defne a new eiioi teim,
(13.4)
and claim that minimizing Eiioi is equivalent to minimizing Eiioi
rms
. To minimize Eiioi, we set all paitial
deiivatives of it with iespect to each model paiametei equal to zeio; that is, wiite
Eiioi
weight
weight
ims

, , }
}
1
]
1
1
1
1
1
n
s m
m
2
1
2
1
1 2
Eiioi
weight
weight
ims
min

, , }
}
1
]
1
1
1
1
1
n
s m
m
2
1
2
1
1 2
Eiioi Eiioi weight
ims
, , }
1
]
1
1
2 2
1

n
m
(13.5)
Then solve the above equations foi the value of
,
.
Least-Square Curve Fitting [Numerica!)
Foi almost all piactical applications we aie foiced to do least-squaies cuive ftting numeiically, because the
analytic solutions as pieviously discussed aie not obtainable in closed foim. What we aie calling least-squaies
cuive ftting is moie geneially known as nonlineai optimization. Many fne iefeiences on this topic aie available.
We iefei the ieadei to Gill et al., 1981] foi details.
Extractiun [as Oppused tu Optimizatiun)
The teims extiaction" and optimization" aie, unfoitunately, used inteichangeably in the semiconductoi
industiy; howevei, stiictly speaking, they aie not the same. By optimization, we mean using geneialized least-
squaies cuive ftting methods such as the Levenbeig-Maiquaidt algoiithm Gill et al., 1981] to fnd a set of
model paiameteis. By extiaction, we mean any technique that does not use geneial least-squaies ftting methods.
This is a somewhat loose inteipietation of the teim extiaction. The main point is that we wiite the equations
we want and then solve them by whatevei appioximations we choose, as long as these appioximations allow
us to get the extiacted iesults in closed foim. This is paiametei extiaction.
Extractiun vs. Optimizatiun
Extiaction has the advantage of being much fastei than optimization, but it is not always as accuiate. It is also
much haidei to supply extiaction ioutines foi models that aie being developed. Each time you make a change
in the model, you must make suitable changes in the coiiesponding extiaction ioutine. Foi optimization,
howevei, no changes aie necessaiy othei than the change in the model itself, because least-squaies cuive ftting
ioutines aie completely geneial. Also, if anything goes wiong in the extiaction algoiithm (and no access to the
souice code is available), almost nothing can be done to coiiect the pioblem. With optimization, one can always
change the iange of data, weighting, uppei and lowei bounds, etc. A least-squaies cuive ftting piogiam can
be steeied towaid a coiiect solution.
Novices at device chaiacteiization fnd least-squaies cuive ftting somewhat fiustiating because a ceitain
amount of usei inteivention and intuition is necessaiy to obtain the coiiect iesults. These beginneis piefei
extiaction methods because they do not have to do anything. Howevei, aftei being buined by extiaction ioutines
that do not woik, a moie expeiienced usei will usually piefei the exibility, contiol, and accuiacy that opti-
mization piovides.
Commeicial softwaie is available that piovides both extiaction and optimization togethei. The idea heie is
to fist use extiaction techniques to make ieasonable initial guesses and then use these iesults as a staiting point
foi optimization, because optimization can give veiy pooi iesults if pooi initial guesses foi the paiameteis aie
used. Nothing is wiong with using extiaction techniques to piovide initial guesses foi optimization, but foi an
expeiienced usei this is iaiely necessaiy, assuming that the least-squaies cuive ftting ioutine is iobust (conveiges
well) and the expeiienced usei has some knowledge of the piocess undei chaiacteiization. Softwaie that ielies
heavily on extiaction may do so because of the noniobustness of its optimizei.
These comments apply when an expeiienced usei is doing optimization locally, not globally. Foi global
optimization (a technique we do not iecommend), the above compaiisons between extiaction and optimization
aie not valid. The following section contains moie detail about local vs. global optimization.
Strategies: Genera! Discussiun
The most naive way of using an optimization piogiam would be to take all the measuied data foi all devices,
put them into one big fle, and ft to all these data with all model paiameteis simultaneously. Even foi a veiy
high quality, iobust optimization piogiam the chances of this method conveiging aie slight. Even if the piogiam
does conveige, it is almost ceitain that the values of the paiameteis will be veiy unphysical. This kind of
appioach is an extieme case of global optimization. We call any optimization technique that tiies to ft with
paiameteis to data outside theii iegion of applicability a global appioach. That is, if we tiy to ft to satuiation
o
o
Eiioi
foi
, ,

, m
,
0 1 , , . . .,
iegion data with lineai iegion paiameteis such as thieshold voltage, mobility, etc., we aie using a global
appioach. In geneial, we advise avoiding global appioaches, although in the stiategies desciibed latei, sometimes
the iules aie bent a little.
Oui iecommended appioach is to ft subsets of ielevant paiameteis to coiiesponding subsets of ielevant
data in a way that makes physical sense. Foi example, in the MOS level 3 model, VT0 is defned as the thieshold
voltage of a long, wide tiansistoi at zeio back-bias. It does not make sense to use this paiametei to ft to a shoit
channel tiansistoi, oi to ft at nonzeio back-bias values, oi to ft to anywheie outside the lineai iegion. In
addition, subsets of paiameteis should be obtained in the piopei oidei so that those obtained at a latei step
do not affect those obtained at eailiei steps. That is, we would not obtain satuiation iegion paiameteis befoie
we have obtained lineai iegion paiameteis because the values of the lineai iegion paiameteis would inuence
the satuiation iegion fts; we would have to go back and ieoptimize on the satuiation iegion paiameteis aftei
obtaining the lineai iegion paiameteis. Finally, nevei use optimization to obtain a paiametei value when the
paiametei can be measuied diiectly. Foi example, the MOS oxide thickness, TOX, is a model paiametei, but
we would nevei use optimization to fnd it. Always measuie its value diiectly on a laige oxide capacitoi piovided
on the test chip. The iecommended pioceduie foi piopei device chaiacteiization follows:
1. Have all the appiopiiate stiuctuies necessaiy on youi test chip. Without this, the job cannot be peifoimed
piopeily.
2. Always measuie whatevei paiameteis aie diiectly measuiable. Nevei use otpimization foi these.
3. Fit the subset of paiameteis to coiiesponding subsets of data, and do so in physically meaningful ways.
4. Fit paiameteis in the piopei oidei so that those obtained latei do not affect those obtained pieviously.
If this is not possible, iteiation may be necessaiy.
Natuially, a good stiategy cannot be mounted if one is not intimately familiai with the model used. Theie is
no substitute foi leaining as much about the model as possible. Without this knowledge, one must iely on
stiategies piovided by softwaie vendois, and these vaiy widely in quality.
Finally, no one can piovide a completely geneial stiategy applicable to all models and all piocess technologies.
At some point the stiategy must be tailoied to suit the available technology and ciicuit peifoimance iequiie-
ments. This not only iequiies familiaiity with the available device models, but also infoimation fiom the ciicuit
designeis and piocess aichitects.
MOS DC Mude!s
Avai!ab!e MOS Mude!s
A numbei of MOS models have been piovided ovei time with the oiiginal ciicuit simulation piogiam, SPICE.
In addition, some commeicially available ciicuit simulation piogiams have intioduced theii own piopiietaiy
models, most notably HSPICE.
1
This section is concentiated on the standaid MOS models piovided by UC
Beikeley`s SPICE, not only because they have become the standaid models used by all ciicuit simulation
piogiams, but also because the piopiietaiy models piovided by commeicial vendois aie not well documented
and no souice code is available foi these models to investigate them thoioughly.
MOS Leve|s 1, 2, und J. Oiiginally, SPICE came with thiee MOS models known as level 1, level 2, and level 3.
The level 1 MOS model is a veiy ciude fist-oidei model that is iaiely used. The level 2 and level 3 MOS models
aie extensions of the level 1 model and have been used extensively in the past and piesent Vladimiiescu and
Liu, 1980]. These two models contain about 15 DC paiameteis each and aie usually consideied useful foi digital
ciicuit simulation down to 1 m channel length technologies. They can ft the diain cuiient foi wide tiansistois
of vaiying length with ieasonable accuiacy (about 5% RMS eiioi), but have veiy little advanced ftting capability
foi analog application. They have only one paiametei foi ftting the subthieshold iegion, and no paiameteis
foi ftting the deiivative of diain cuiient with iespect to diain voltage, C
Js
(usually consideied ciitical foi analog
applications). They also have no ability to vaiy the mobility degiadation with back-bias, so the fts to I
Js
in the
satuiation iegion at high back-bias aie not veiy good. Finally, these models do not inteipolate well ovei device
1
HSPICE is a commeicially available, SPICE-like ciicuit simulation piogiam fiom Meta Softwaie, Campbell, CA.
geometiy; e.g., if a ft it made to a wide-long device and a wide-shoit device, and then one obseives how the
models tiack foi lengths between these two extiemes, they usually do not peifoim well. Foi naiiow devices
they can be quite pooi as well. Level 3 has veiy little piactical advantage ovei level 2, although the level 2 model
is pioclaimed to be moie physically based, wheieas the level 3 model is called semiempiiical. If only one can
be used, peihaps level 3 is slightly bettei because it iuns somewhat fastei and does not have quite such an
annoying kink in the tiansition iegion fiom lineai to satuiation as does level 2.
Ber|e|ey Shvrt-Chunne| 1g]et Mvde| (BS1M). To oveicome the many shoit-comings of level 2 and level 3,
the BSIM and BSIM2 models weie intioduced. The most fundamental diffeience between these and the level 2
and 3 models is that BSIM and BSIM2 use a diffeient appioach to incoipoiating the geometiy dependence
Oustei et al., 1988; Jeng et al., 1987]. In level 2 and 3 the geometiy dependence is built diiectly into the model
equations. In BSIM and BSIM2 each paiametei (except foi a veiy few) is wiitten as a sum of thiee teims
(13.6)
wheie Pai
0
is the zeio-oidei teim, Pai
L
accounts foi the length dependence of the paiametei, Pai
W
accounts
foi the width dependence, and L
eff
and W
eff
aie the effective channel width and length, iespectively. This appioach
has a laige inuence on the device chaiacteiization stiategy, as discussed latei. Because of this tiipling of the
numbei of paiameteis and foi othei ieasons as well, the BSIM model has about 54 DC paiameteis and the
BSIM2 model has ovei 100.
The oiiginal goal of the BSIM model was to ft bettei than the level 2 and 3 models foi submicion channel
lengths, ovei a widei iange of geometiies, in the subthieshold iegion, and foi nonzeio back-bias. Without
question, BSIM can ft individual devices bettei than level 2 and level 3. It also fts the subthieshold iegion
bettei and it fts bettei foi nonzeio back-biases. Howevei, its gieatest shoitcoming is its inability to ft ovei a
laige geometiy vaiiation. This occuis because (13.6) is a tiuncated Tayloi seiies in 1/L
eff
and 1/W
eff
teims, and
in oidei to ft bettei ovei vaiying geometiies, highei powei teims in 1/L
eff
and 1/W
eff
aie needed. In addition,
no piovision was put into the BSIM model foi ftting C
Js
, so its usefulness foi analog applications is questionable.
Many of the BSIM model paiameteis aie unphysical, so it is veiy haid to undeistand the signifcance of these
model paiameteis. This has piofound implications foi geneiating skew models (fast and slow models to
iepiesent the piocess coineis) and foi incoipoiating tempeiatuie dependence. Anothei aw of the BSIM model
is its wild behavioi foi ceitain values of the model paiameteis. If model paiameteis aie not specifed foi level 2
oi 3, they will default to values that will at least foice the model to behave well. Foi BSIM, not specifying ceitain
model paiameteis, setting them to zeio, oi vaiious combinations of values can cause the model to become veiy
ill-behaved.
BS1M2. The BSIM2 model was developed to addiess the shoitcomings of the BSIM model. This was basically
an extension of the BSIM model, iemoving ceitain paiameteis that had veiy little effect, fxing fundamental
pioblems such as cuiients vaiying the wiong way as a function of ceitain paiameteis, adding moie unphysical
ftting paiameteis, and adding paiameteis to allow ftting C
Js
. BSIM2 does ft bettei than BSIM, but with moie
than twice as many paiameteis as BSIM, it should. Howevei, it does not addiess the ciucial pioblem of ftting
laige geometiy vaiiations. Its majoi stiengths ovei BSIM aie ftting the subthieshold iegion bettei, and ftting
C
Js
bettei. Most of the othei shoitcomings of BSIM aie also piesent in BSIM2, and the laige numbei of
paiameteis in BSIM2 makes it a ieal choie to use in device chaiacteiization.
BS1MJ. Realizing the shoitcomings of BSIM2, UC Beikeley iecently intioduced the BSIM3 model. This is an
unfoitunate choice of name because it implies BSIM3 is ielated to BSIM and BSIM2. In ieality, BSIM3 is an
entiiely new model that in some sense is ielated moie to level 2 and 3 than BSIM oi BSIM2. The BSIM3 model
abandons the length and width dependence appioach of BSIM and BSIM2, piefeiiing to go back to incoipo-
iating the geometiy dependence diiectly into the model equations, as do level 2 and 3. In addition, BSIM3 is
a moie physically based model, with about 30 ftting paiameteis (the model has many moie paiameteis, but
Paiametei - Pai
Pai
L
Pai
W
0
L
eff
W
eff
+ + ,
the majoiity of these can be left untouched foi ftting), making it moie manageable, and it has abundant
paiameteis foi ftting C
Js
, making it a stiong candidate foi analog applications.
It is an evolving model, so peihaps it is unfaii to ciiticize it at this eaily stage. Its gieatest shoitcoming is,
again, the inability to ft well ovei a wide iange of geometiies. It is hoped that futuie modifcations will addiess
this pioblem. In all faiiness, howevei, it is a laige oidei to ask a model to be physically based, have not too
many paiameteis, be well behaved foi all default values of the paiameteis, ft well ovei tempeiatuie, ft C
Js
, ft
ovei a wide iange of geometiies, and still ft individual geometiies as well as a model with ovei 100 paiameteis,
such as BSIM2. Some of these featuies weie compiomised in developing BSIM3.
PrvprIetury Mvde|s. A numbei of othei models aie available fiom commeicial ciicuit simulatoi vendois, the
liteiatuie, etc. Some ciicuit simulatois also offei the ability to add a ieseaichei`s own models. In geneial, we
caution against using piopiietaiy models, especially those which aie supplied without souice code and complete
documentation. Without an intimate knowledge of the model equations, it is veiy diffcult to develop a good
device chaiacteiization stiategy. Also, incoipoiating such models into device chaiacteiization softwaie is almost
impossible. To ciicumvent this pioblem, many chaiacteiization piogiams have the ability to call the entiie
ciicuit simulatoi as a subioutine in oidei to exeicise the piopiietaiy model subioutines. This can slow piogiam
execution by a factoi of 20 oi moie, seiiously impacting the time iequiied to chaiacteiize a technology. Also,
if piopiietaiy models aie used without souice code, the ciicuit simulatoi iesults can nevei be checked against
othei ciicuit simulatois. Theiefoie, we want to stiess the impoitance of using standaid models. If these do not
meet the individual iequiiements, the next best appioach is to incoipoiate a piopiietaiy model whose souice
code one has access to. This iequiies being able to add the individual model not only to ciicuit simulatois, but
also to device chaiacteiization piogiams; it can become a veiy laige task.
MOS Leve! 3 Extractiun Strategy in Detai!
The stiategy discussed heie is one that we considei to be a good one, in the spiiit of oui eailiei comments.
Note, howevei, that this is not the only possible stiategy foi the level 3 model. The idea heie is to illustiate
basic concepts so that this stiategy can be iefned to meet paiticulai individual iequiiements.
In oidei to do a DC chaiacteiization, the minimum iequiiement is one each of the wide-long, wide-shoit,
and naiiow-long devices. We list the steps of the pioceduie and then discuss them in moie detail.
STEP 1. Fit the wide-long device in the lineai iegion at zeio back-bias at V
gs
values above the subthieshold
iegion, with paiameteis VT0 (thieshold voltage), U0 (mobility), and THETA (mobility degiadation with V
gs
).
STEP 2. Fit the wide-shoit device in the lineai iegion at zeio back-bias, at V
gs
iegion, with paiameteis VT0, LD (length encioachment), and THETA. When fnished with this step, ieplace
VT0 and THETA with the values fiom step 1, but keep the value of LD.
STEP J. Fit the naiiow-long device in the lineai iegion at zeio back-bias, at V
gs
iegion, with paiameteis VT0, DW (width encioachment), and THETA. When fnished with this step, ieplace
VT0 and THETA with the values fiom step 1, but keep the value of DW.
gs
iegion, with paiameteis RS and RD (souice and diain seiies iesistance).
STEP 3. Fit the wide-long device in the lineai iegion at all back-biases, at V
gs
iegion, with paiametei NSUB (channel doping affects long channel vaiiation of thieshold voltage with
back-bias).
gs
iegion, with paiametei XJ (eiioneously called the junction depth; affects shoit-channel vaiiation of thieshold
voltage with back-bias).
STEP 7. Fit the naiiow-long device in the lineai iegion at zeio back-bias, at V
gs
iegion, with paiametei DELTA (naiiow channel coiiection to thieshold voltage).
STEP 8. Fit the wide-shoit device in the satuiation iegion at zeio back-bias (oi all back-biases) with paiam-
eteis VMAX (velocity satuiation), KAPPA (satuiation iegion slope ftting paiametei), and ETA (V
Js
dependence
of thieshold voltage).
STEP 9. Fit the wide-shoit device in the subthieshold iegion at whatevei back-bias and diain voltage is
appiopiiate (usually zeio back-bias and low V
Js
) with paiametei NES (subthieshold slope ftting paiametei).
One may need to ft with VT0 also and then VT0 is ieplaced aftei this step with the value of VT0 obtained
fiom step 1.
This completes the DC chaiacteiization steps foi the MOS level 3 model. One would then go on to do the
junction and oveilap capacitance teims (discussed latei). Note that this model has no paiameteis foi ftting
ovei tempeiatuie, although tempeiatuie dependence is built into the model that the usei cannot contiol.
In Step 1 VT0, U0, and THETA aie defned in the model foi a wide-long device at zeio back-bias. They aie
zeio-oidei fundamental paiameteis without any shoit oi naiiow channel coiiections. We theiefoie ft them to
a wide-long device. It is absolutely necessaiy that such a device be on the test chip. Without it, one cannot
obtain these paiameteis piopeily. The subthieshold iegion must be avoided also because these paiameteis do
not contiol the model behavioi in subthieshold.
In Step 2 we use LD to ft the slope of the lineai iegion cuive, holding U0 fxed fiom step 1. We also ft with
VT0 and THETA because without them the ftting will not woik. Howevei, we want only the value of LD that
fts the slope, so we thiow away VT0 and THETA, ieplacing them with the values fiom step 1.
Step 3 is the same as step 2, except that we aie getting the width encioachment instead of the length.
In Step 1 the value of THETA that fts the high V
gs
poition of the wide-long device lineai iegion cuive was
found. Because the channel length of a long tiansistoi is veiy laige, the souice and diain seiies iesistances have
almost no effect heie, but foi a shoit-channel device, the seiies iesistance will also affect the high V
gs
poition
of the lineai iegion cuive. Theiefoie, in step 4 we fx THETA fiom step 1 and use RS and RD to ft the wide-
shoit device in the lineai iegion, high V
gs
poition of the cuive.
In Step 5 we ft with NSUB to get the vaiiation of thieshold voltage with back-bias. We will get bettei iesults
if we iestiict ouiselves to lowei values of V
gs
(but still above subthieshold) because no mobility degiadation
adjustment exists with back-bias, and theiefoie the ft may not be veiy good at highei V
gs
values foi the nonzeio
back-bias cuives.
Step 6 is just like step 5, except we aie ftting the shoit-channel device. Some people think that the value of
XJ should be the tiue junction depth. This is not tiue. The paiametei XJ is loosely ielated to the junction depth,
but XJ is ieally the shoit-channel coiiection to NSUB. Do not be suipiised if XJ is not equal to the tiue junction
depth.
Step 7 uses DELTA to make the naiiow channel coiiection to the thieshold voltage. This step is quite
stiaightfoiwaid.
Step 8 is the only step that fts in the satuiation iegion. The use of paiameteis VMAX and KAPPA is obvious,
but one may question using ETA to ft in the satuiation iegion. The paiametei ETA adjusts the thieshold voltage
with iespect to V
Js
, and as such one could aigue that ETA should be used to ft measuiements of I
Js
sweeping
V
gs
and stepping V
Js
to high values. In doing so, one will coiiupt the ft in the satuiation iegion, and usually
we want to ft the satuiation iegion bettei at the expense of the lineai iegion.
Step 9 uses NFS to ft the slope of the log(I
Js
) vs. V
gs
cuive. Often the value of VT0 obtained fiom step 1 will
pievent one fiom obtaining a good ft in the subthieshold iegion. If this happens, tiy ftting with VT0 and
NFS, but ieplacing the fnal value of VT0 with that fiom step 1 at the end, keeping only NFS fiom this fnal step.
The above steps illustiate the concepts of ftting ielevant subsets of paiameteis to ielevant subsets of data to
obtain physical values of the paiameteis, as well as ftting paiameteis in the piopei oidei so that those obtained
in the latei steps will affect those obtained in eailiei steps minimally. Please iefei to Figs. 13.13 and 13.14 foi
how the iesulting fts typically appeai (all giaphs showing model fts aie piovided by the device modeling
softwaie package Auioia, fiom Technology Modeling Associates, Inc., Palo Alto, CA).
An expeiienced peison may notice that we have neglected some paiameteis. Foi example, we did not use
paiameteis KP and GAMMA. This means KP will be calculated fiom U0, and GAMMA will be calculated fiom
NSUB. In a sense U0 and NSUB aie moie fundamental paiameteis than KP and GAMMA. Foi example, KP
depends on U0 and TOX; GAMMA depends on NSUB and TOX. If one is tiying to obtain skew models, it is
much moie advantageous to analyze statistical distiibutions of paiameteis that depend on a single effect than
those that depend on multiple effects. KP will depend on mobility and oxide thickness; U0 is theiefoie a moie
fundamental paiametei. We also did not obtain paiametei PHI, so it will be calculated fiom NSUB. The level 3
model is veiy insensitive to PHI, so using it foi cuive ftting is pointless. This illustiates the impoitance of
being veiy familiai with the model equations. The kind of judgments desciibed heie cannot be made without
such knowledge.
FIGURE 13.13 Typical MOS level 3 lineai iegion measuied and simulated plots at vaiious V
|s
values foi a wide-shoit device.
FIGURE 13.14 Typical MOS level 3 satuiation iegion measuied and simulated plots at vaiious V
g s
and V
|s
values foi a
wide-shoit device.
Test ChIp WurnIngs. The following hints will gieatly assist in piopeily peifoiming device chaiacteiization.
1. Include a wide-long device; without this, the iesults will not be physically coiiect.
2. All MOS tiansistois with the same width should be diawn with theii souices and diains identical. No
diffeience should be seen in the numbei of souice/diain contacts, contact spacing, souice/diain contact
oveilap, poly gate to contact spacing, etc.
3. Diaw devices in paiis. That is, if the wide-long device is W/L 20/20, make the wide-shoit device the
same width as the wide-long device; e.g., make the shoit device 20/1, not 19/1. If the naiiow-long device
is 2/20, make the naiiow-shoit device of the same width; i.e., make is 2/1, not 3/1, and similaily foi the
lengths. (Make the wide-shoit and the naiiow-shoit devices have the same length.)
BSIM Extractiun Strategy in Detai!
All MOS model stiategies have basic featuies in common; namely, ft the lineai iegion at zeio back-bias to get
the basic zeio-oidei paiameteis, ft the lineai iegion at nonzeio back-bias, ft the satuiation iegion at zeio
back-bias, ft the satuiation iegion at nonzeio back-bias, and then ft the subthieshold iegion. It is possible to
extend the type of stiategy we coveied foi level 3 to the BSIM model, but that is not the way BSIM was intended
to be used.
The tiiplet sets of paiameteis foi incoipoiating geometiy dependence into the BSIM model, (13.6), allow
an alteinate stiategy. We obtain sets of paiameteis without geometiy dependence by ftting to individual devices
without using the Pai
L
and Pai
V
teims. We do this foi each device size individually. This pioduces sets of
paiameteis ielevant to each individual device. So, foi device numbei 1 of width W(1) and length L(1) we would
have a value foi the paiametei VFB which we will call VFB(1); foi device numbei n of width W(n) and length
L(n) we will have VFB(n). To get the Pai
0
, Pai
L
, and VFB
V
we ft to the data points" VFB(1), . . .,VFB(n) with
paiameteis VFB
0
, VFB
L
, and VFB
V
using (13.6) wheie L
eff
and W
eff
aie diffeient foi each index, 1 thiough n.
Note that as L and W become veiy laige, the paiameteis must appioach Pai
0
. This suggests that we use the
paiametei values foi the wide-long device as the Pai
0
teims and only ft the othei geometiy sizes to get the
Pai
L
and Pai
V
teims. Foi example, if we have obtained VFB(1) foi oui fist device which is oui wide-long
device, we would set VFB
0
VFB(1), and then ft to VFB(2), . . .,VBF(n) with paiameteis VFB
L
and VFB
V
, and
similaily foi all the othei tiiplets of paiameteis. In oidei to use a geneial least-squaies optimization piogiam
in this way the softwaie must be capable of specifying paiameteis as taigets, as well as measuied data points.
We now list a basic stiategy foi the BSIM model:
STEP 1. Fit the wide-long device in the lineai iegion at zeio back-bias, at V
gs
iegion, with paiameteis VFB (atband voltage), MUZ (mobility), and U0 (mobility degiadation), with DL
(length encioachment) and DW (width encioachment) set to zeio.
gs
iegion, with paiameteis VFB, U0, and DL.
STEP J. Fit the naiiow-long device in the lineai iegion at zeio back-bias, at V
gs
iegion, with paiameteis VFB, U0, and DW.
STEP 4. Reft the wide-long device in the lineai iegion at zeio back-bias, at V
gs
iegion, with paiameteis VFB, MUZ, and U0, now that DL and DW aie known.
gs
iegion, with paiameteis VFB, RS, and RD. When fnished, ieplace the value of VFB with the value found in step 4.
STEP 6. Fit the wide-long device in the lineai iegion at all back-biases, at V
gs
iegion, with paiameteis K1 (fist-oidei body effect), K2 (second-oidei body effect), U0, and X2U0 (V
|s
dependence of U0).
STEP 7. Fit the wide-long device in the satuiation iegion at zeio back-bias with paiameteis U0, ETA (V
Js
dependence of thieshold voltage), MUS (mobility in satuiation), U1 (V
Js
dependence of mobility), and X3MS
(V
Js
dependence of MUS).
STEP 8. Fit the wide-long device in the satuiation iegion at all back-biases with paiametei X2MS (V
|s
dependence of MUS).
STEP 9. Fit the wide-long device in the subthieshold iegion at zeio back-bias and low V
Js
value with paiametei
N0; then ft the subthieshold iegion nonzeio back-bias low V
Js
data with paiametei NB; and fnally ft the
subthieshold iegion data at highei V
Js
values with paiametei ND. Oi, ft all the subthieshold data simultaneously
with paiameteis N0, NB, and ND.
Repeat Steps 6 thiough 10 foi all the othei geometiies, with the iesult of sets of geometiy-independent
paiameteis foi each diffeient size device. Then follow the pioceduie desciibed pieviously foi obtaining the
geometiy-dependent teims Pai
0
, Pai
L
, and Pai
V
.
In the above stiategy we have omitted vaiious paiameteis eithei because they have minimal effect oi because
they have the wiong effect and weie modifed in the BSIM2 model. Because of the highei complexity of the
BSIM model ovei the level 3 model, many moie stiategies aie possible than the one just listed. One may be
able to fnd vaiiations of the above stiategy that suit the individual technology bettei. Whatevei modifcations
aie made, the geneial spiiit of the above stiategy piobably will iemain.
Some piefei to use a moie global appioach with BSIM, ftting to measuied data with Pai
L
and Pai
V
teims
diiectly. Although this is ceitainly possible, it is defnitely not a iecommended appioach. It iepiesents the woist
foim of blind cuive ftting, with no iegaid foi physical coiiectness oi undeistanding. The BSIM model was
oiiginally developed with the idea of obtaining the model paiameteis via extiaction as opposed to optimization.
In fact, UC Beikeley piovides softwaie foi obtaining BSIM paiameteis using extiaction algoiithms, with no
optimization at all. As stated pieviously, this has the advantage of being ielatively fast and easy. Unfoitunately,
it does not always woik. One of the majoi diawbacks of the BSIM model is that ceitain values of the paiameteis
can cause the model to pioduce negative values of C
Js
in satuiation. This is highly undesiiable, not only fiom
a modeling standpoint, but also because of the conveigence pioblems it can cause in ciicuit simulatois. If an
extiaction stiategy is used that does not guaiantee non-negative C
Js
, veiy little can be done to fx the pioblem
when C
Js
becomes negative. Of couise, the extiaction algoiithms can be modifed, but this is diffcult and time
consuming. With optimization stiategies, one can weight the ftting foi C
Js
moie heavily and thus foice the
model to pioduce non-negative C
Js
. We, theiefoie, do not favoi extiaction stiategies foi BSIM, oi anything
else. As with most things in life, minimal effoit piovides minimal iewaids.
BSIM2 Extractiun Strategy
We do not covei the BSIM2 stiategy in complete detail because it is veiy similai to the BSIM stiategy, except
moie paiameteis aie involved. The majoi diffeience in the two models is the inclusion of extia teims in BSIM2
foi ftting C
Js
(iefei to Fig. 13.15, which shows how badly BSIM typically fts 1/C
Js
vs. V
Js
). Basically, the BSIM2
stiategy follows the BSIM stiategy foi the extiaction of paiameteis not ielated to C
Js
. Once these have been
obtained, the last pait of the stiategy includes steps foi ftting to C
Js
with paiameteis that account foi channel
length modulation and hot election effects. The way this pioceeds in BSIM2 is to ft I
Js
fist, and then paiameteis
MU2, MU3, and MU4 aie used to ft to 1/C
Js
vs. V
Js
cuives foi families of V
gs
and V
|s
. This can be a veiy time
consuming and fiustiating expeiience, because ftting to 1/C
Js
is quite diffcult. Also, the equations desciibing
how C
Js
is modeled with MU2, MU3, and MU4 aie veiy unphysical and the inteiplay between the paiameteis
makes ftting awkwaid. The ieadei is iefeiied to Fig. 13.16, which shows how BSIM2 typically fts 1/C
Js
vs. V
Js
.
BSIM2 is ceitainly bettei than BSIM but it has its own pioblems ftting 1/C
Js
.
BSIM3 Cumments
The BSIM3 model is veiy new and will undoubtedly change in the futuie Huang et al., 1993]. We will not list
a BSIM3 stiategy heie, but focus instead on the featuies of the model that make it appealing foi analog modeling.
BSIM3 has teims foi ftting C
Js
that ielate to channel length modulation, diain-induced baiiiei loweiing,
and hot election effects. They aie incoipoiated completely diffeiently fiom the C
Js
ftting paiameteis of BSIM2.
In BSIM3 these paiameteis entei thiough a geneialized Eaily voltage ielation, with the diain cuiient in
satuiation wiitten as
(13.7)
wheie V
is a geneialized Eaily voltage made up of thiee teims as

(13.8)
FIGURE 13.15 Typical BSIM 1/C
J
vs. V
Js
measuied and simulated plots at vaiious V
g s
FIGURE 13.16 Typical BSIM2 1/C
J
vs. V
Js
g s
I I
V V
V
Js J
Js J
+

, ,
1
]
1
1
sat
sat
1
1 1 1 1
V V V V

+ +
CLM DIBL HCE
with the teims in (13.8) iepiesenting geneialized Eaily voltages foi channel length modulation (CLM), diain-
induced baiiiei loweiing (DIBL), and hot caiiiei effects (HCE). This foimulation is moie physically appealing
than the one used in BSIM2, making it easiei to ft 1/C
Js
vs. V
Js
cuives with BSIM2. Figuies 13.17 and 13.18
show how BSIM3 typically fts I
Js
vs. V
Js
and 1/C
Js
vs. V
Js
.
Most of the model paiameteis foi BSIM3 have physical signifcance so they aie obtained in the spiiit of the
paiameteis foi the level 2 and 3 models. The incoipoiation of tempeiatuie dependence is also easiei in BSIM3
because the paiameteis aie moie physical. All this, coupled with the fact that about 30 paiameteis exist foi
BSIM3 as compaied to ovei 100 foi BSIM2, makes BSIM3 a logical choice foi analog design. Howevei, BSIM3
is evolving, and shoitcomings to the model may still exist that may be coiiected in latei ievisions.
FIGURE 13.17 Typical BSIM3 satuiation iegion measuied and simulated plots at vaiious V
g s
FIGURE 13.18 Typical BSIM3 1/C
J
vs. V
Js
g s
Which MOS Mude! Tu Lse!
Many MOS models aie available in ciicuit simulatois, and the novice is bewildeied as to which model is
appiopiiate. No single answei exists, but some questions must be asked befoie making a choice:
1. What kind of technology am I chaiacteiizing:
2. How accuiate a model do I need:
3. Do I want to undeistand the technology:
4. How impoitant aie the skew model fles (fast and slow paiametei fles):
5. How expeiienced am I: Do I have the expeitise to handle a moie complicated model:
6. How much time can I spend doing device chaiacteiization:
7. Do I need to use this model in moie than one ciicuit simulatoi:
8. Is the subthieshold iegion impoitant:
9. Is ftting C
Js
impoitant:
Let us appioach each question with iegaid to the models available. If the technology is not submicion, peihaps
a simplei model such as level 3 is capable of doing eveiything needed. If the technology is deep submicion,
then use a moie complicated model such as BSIM, BSIM2, oi BSIM3. If high accuiacy is iequiied, then the
best choice is BSIM3, mainly because it is moie physical than all the othei models and is capable of ftting bettei.
Foi a good physical undeistanding of the piocess being chaiacteiized. BSIM and BSIM2 aie not good choices.
These aie the least physically based of all the models. The level 2 and 3 models have good physical inteipietation
foi most of the paiameteis, although they aie ielatively simple models. BSIM3 is also moie physically based,
with many moie paiameteis than level 2 oi 3, so it is piobably the best choice.
If meaningful skew models need to be geneiated, then BSIM and BSIM2 aie veiy diffcult to use, again,
because of theii unphysical paiametei sets. Usually, the simplest physically based model is the best foi skew
model geneiation. A moie complicated physically based model such as BSIM3 may also be diffcult to use foi
skew model geneiation.
If the usei is inexpeiienced, none of the BSIM models should be used until the usei`s expeitise impioves.
Oui advice is to piactice using simplei models befoie tackling the haidei ones.
If time is ciitical, the simplei models will defnitely be much fastei foi use in chaiacteiization. The moie
complicated models iequiie moie measuiements ovei widei ianges of voltages as well as widei ianges of
geometiies. This, coupled with the laigei numbei of paiameteis, means they will take some time with which
to woik. The BSIM2 model will take longei than all the iest, especially if the C
Js
ftting paiameteis aie to be used.
The chaiacteiization iesults may need to be used in moie than one ciicuit simulatoi. Foi example, if a
foundiy must supply models to vaiious customeis, they may be using diffeient ciicuit simulatois. In this case
piopiietaiy models applicable to a single ciicuit simulatoi should not be used. Also, ciicuit designeis may want
to check the ciicuit simulation iesults on moie than one ciicuit simulatoi. It is bettei to use standaid Beikeley
models (level 2, level 3, BSIM, BSIM2, and BSIM3) in such cases.
If the subthieshold iegion is impoitant, then level 2 oi level 3 cannot be used, and piobably not even BSIM;
BSIM2 oi BSIM3 must be used instead. These two models have enough paiameteis foi ftting the subthieshold
iegion.
If ftting C
Js
is impoitant, BSIM2 and BSIM3 aie, again, the only choices. None of the othei models have
enough paiameteis foi ftting C
Js
.
Finally, if a veiy unusual technology is to be chaiacteiized, none of the standaid models may be appiopiiate.
In this case commeicially available specialized models oi the usei`s own models must be used. This will be a
laige task, so the goals must justify the effoit.
Skev Parameter Fi!es
This chaptei discussed obtaining model paiameteis foi a single wafei, usually one that has been chosen to
iepiesent a typical wafei foi the technology being chaiacteiized. The paiametei values obtained fiom this wafei
coiiespond to a typical case. Ciicuit designeis also want to simulate ciicuits with paiametei values iepiesenting
the extiemes of piocess vaiiation, the so-called fast and slow coineis, oi skew paiametei fles. These iepiesent
the best and woist case of the piocess vaiiation ovei time.
Skew paiametei values aie obtained usually by tiacking a few key paiameteis, measuiing many wafeis ovei
a long peiiod of time. The standaid deviation of these key paiameteis is found and added to oi subtiacted
fiom the typical paiametei values to obtain the skew models. This method is extiemely ciude and will not
noimally pioduce a iealistic skew model. It will almost always oveiestimate the piocess spiead, because the
vaiious model paiameteis aie not independent-they aie coiielated.
Obtaining iealistic skew paiametei values, taking into account all the subtle coiielations between paiameteis,
is moie diffcult. In fact, skew model geneiation is often moie an ait than a science. Many attempts have been
made to utilize techniques fiom a bianch of statistics called multivaiiate analysis Dillon and Goldstein, 1984].
In this appioach piincipal component oi factoi analysis is used to fnd paiameteis that aie lineai combinations
of the oiiginal paiameteis. Only the fist few of these new paiameteis will be kept; the otheis will be discaided
because they have less signifcance. This new set will have fewei paiameteis than the oiiginal set and theiefoie
will be moie manageable in teims of fnding theii skews. The usei sometimes must make many choices in the
way the common factois aie utilized, iesulting in diffeient useis obtaining diffeient iesults.
Unfoitunately, a gieat deal of physical intuition is often iequiied to use this appioach effectively. To date,
we have only seen it applied to the simplei MOS models such as level 3. It is not known if this is a viable
appioach foi a much moie complicated model such as BSIM2 Powei et al., 1993].
Re!ated Tupic
24.3 The Metal-Oxide Semiconductoi Field-Effect Tiansistoi (MOSFET)
Relerences
W. R. Dillon and M. Goldstein, Mu|arae na|yss Me|oJs anJ |taons, New Yoik: John Wiley & Sons,
1984.
P. E. Gill, W. Muiiay, and M. Wiight, Pratta| Om:aon, Oilando, Fla.: Academic Piess, 1981.
J. S. Dustei, J.-C. Jeng, P. K. Ko, and C. Hu, Usei`s Guide foi BSIM2 Paiametei Extiaction Piogiam and The
SPICE3 with BSIM Implementation," Electionic Reseaich Laboiatoiy, Beikeley: Univeisity of Califoinia,
1988.
J.-H. Huang, Z. H. Liu, M.-C. Jeng, P. K. Ko, and C. Hu, BSIM3 Manual," Beikeley: Univeisity of Califoinia,
1993.
M.-C. Jeng, P. M. Lee, M. M. Kuo, P. K. Ko, and C. Hu, Theoiy, Algoiithms, and Usei`s Guide foi BSIM and
SCALP," Veision 2.0, Electionic Reseaich Laboiatoiy, Beikeley: Univeisity of Califoinia, 1987.
J. A. Powei, A. Mathewson, and W. A. Lane, An Appioach foi Relating Model Paiametei Vaiiabilities to Piocess
Fluctuations," Prot. IEEE In. Con[. Mtroe|etront Tes Srut., vol. 6, Mai. 1993.
W. H. Piess, B. P. Flanneiy, S. A. Teukolsky, and W. T. Vetteiling, Numerta| Retes n C, Cambiidge, U.K.:
Cambiidge Univeisity Piess, 1988.
B. J. Sheu, D. L. Schaifettei, P. K. Ko, and M.-C. Jeng, BSIM: Beikeley Shoit-Channel IGFET Model foi MOS
Tiansistois," IEEE J. So|J-Sae Crtus, vol. SC-22, no. 4, Aug. 1987.
A. Vladimiiescu and S. Liu, The Simulation of MOS Integiated Ciicuits Using SPICE2," memoiandum no.
UCB/ERL M80/7, Beikeley: Univeisity of Califoinia, 1980.
Further Inlurmatiun
Othei iecommended publications which aie useful in device chaiacteiization aie
L. W. Nagel, SPICE2: A Computei Piogiam to Simulate Semiconductoi Ciicuits," memoiandum no.
ERL-M520, Beikeley: Univeisity of Califoinia, 1975.
G. Massobiio and P. Antognetti, SemtonJutor Dete MoJe|ng w| SPICE, New Yoik: McGiaw-Hill,
1993.

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Computer Software for Circuit Analysis and Design

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