STM-103STK development board Users Manual

Rev.A, April 2008

op!ri"#t$%& 2008, '()M*+ (td, All ri"#ts reserved

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The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MC implementation! with a red"ced pin co"nt and low-power cons"mption! while delivering o"tstanding comp"tational performance and an advanced system response to interr"pts. The ARM Cortex-M3 3#-bit RI$C processor feat"res exceptional code-efficiency! delivering the high-performance expected from an ARM core in the memory si%e "s"ally associated with &- and '(-bit devices. The $TM3#)'*3 +erformance ,ine family has an embedded ARM core and is therefore compatible with all ARM tools and software. It combines the high performance ARM Cortex-M3 C+ with an extensive range of peripheral f"nctions and enhanced I-. capabilities. STM32-103STK is starter-/it board which allow yo" to explore the complete feat"res of the new ARM Cortex M3 $TM3#)'*3R0T( microcontrollers prod"ced by $T Microelectronics Inc. It have 1.2IA 33'* 03 &4x4& ,C5! b"ttons! $5-MMC card! 3-axis digital accelerometer! #.46h% R) transciever! A"dio Inp"t and ."tp"t! the power s"pply is made from single '.78 AA cell battery. $ome applications are $0 Mass $torage device! A"dio class device! 9I5 mo"se device! C5C 8irt"al com port device! $0 3ireless R) lin/.The :T connector allow access to all other ;:T mod"les prod"ced by .,IM;: li/e M.5-M+3! M.5-1R)#4,R! M.5-1.2IA(('* etc to be connected easily. In the prototype area c"stomer can solder his own c"stom circ"its and to interface them to $0! CA1! R$#3# etc.

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MC < $TM3#)'*3R0T( ARM 3# bit C.RT;: M3= with '#&2 0ytes +rogram )lash! #*2 0ytes RAM! $0! CA1! x# I#C! x# A5C '# bit! x3 ART! x# $+I! x3 TIM;R$! "p to >#Mh% operation standard ?TA6 connector with ARM #x'* pin layo"t for programming-deb"gging with ARM-?TA6 $0 mini connector ,C5 1.2IA 33'* 03 &4x4& pixels '.78 battery connector with step-"p converter 3-axis accelerometer $5-MMC card #.4 6h% transciever with 1ordic nR)#4,*' A"dio inp"t A"dio o"tp"t "ser b"ttions x# ?oystic/ with 4 directions and p"sh action ;:T connector for other .limex@s mod"les connection li/e M.5-M+3! etc. R;$;T b"tton stat"s ,;5 & Mh% crystal oscillator 3#>(& 9% crystal and RTC bac/"p battery connector extension headers for all "C ports +C0< )R-4! '.7 mm A*!*(#BC! soldermas/! sil/screen component print 5imensions< D* x (7mm A3.7 x #.7BC

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The STM32-103STK board is shipped in protective anti-static pac/aging. The board m"st not be s"bEect to high electrostatic potentials. 6eneral practice for wor/ing with static sensitive devices sho"ld be applied when wor/ing with this board.

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Cables: Hardware: Software: '.& meter A-to-mini $0 cable to connect to $0 host.

ARM-?TA6! ARM- $0-.C5! ARM- $0-TI1F or other ARM ?TA6 compatible tool ARM C compiler and deb"gger software! the possible options are< - free open so"rce platform< 61 C compiler G .pen.C5 and ;clipse As"pport all low cost .limex ?TA6 deb"ggersC - commercial sol"tion ;3-ARM from IAR $ystems A0! reH"ire expensive ?-,I12 deb"gger - Cross3or/s from Rowley As"pports all .limex low cost ?TA6 deb"ggersC.

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STM-103STK board "se ARM 3#-bit Cortex=-M3 C+ from $T Microelectronics with these feat"res< STM32F103RBT6

CPU clock up to 72Mhz FLASH 128KB RAM 20KB DMA x7 chann l! R"C #D" "$% &! x'(1 SP) x2 )2C x2 USAR" x' USB x1
CA1 x' Am"ltiplexed with $0 so both can@t be "sed in same timeC

*P)+ up to ,1 -%ult$pl x . /$th p &$ph &$al!0 2 ADC 1212$t op &at$n3 4olta3 2501'567 t %p &atu& 180C (8,C

RS232.
$TM3#)'*3R0T( have 3 $ARTs which are available on the extension headers. .ne of them can operate "p to 4.7 Mbit-s! the other two "p to #.#7 Mbit-s. They provide hardware management of the CT$ and RT$ signals! Ir5A $IR ;15;C s"pport! are I$. >&'( compliant and have ,I1 Master-$lave capability. All $ART interfaces can be served by the 5MA controller.

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$TM3#)'*3R0T( have # $+Is which able to comm"nicate "p to '& Mbits-s in slave and master modes in f"lld"plex and simplex comm"nication modes. The 3-bit prescaler gives & master mode freH"encies and the frame is config"rable from &-bit to '(-bit. The hardware CRC generation-verification s"pports basic $5 Card-MMC modes. 0oth $+Is can be served by the 5MA controller.

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$TM3#)'*3R0T( have two IIC b"s interfaces which can operate in m"ltimaster and slave modes. They can s"pport standard and fast modes. They s"pport d"al slave addressing A>-bit onlyC and both >-'*-bit addressing in master mode. A hardware CRC generation-verification is embedded. They can be served by 5MA and they s"pport $M 0"s #.*-+M 0"s.

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The $TM3#)'*3R0T( CA1 is compliant with specifications #.*A and 0 AactiveC with a bit rate "p to ' Mbit-s. It can receive and transmit standard frames with ''-bit identifiers as well as extended frames with #D-bit identifiers. It has three transmit mailboxes! two receive )I).s with 3 stages and '4 scalable filter ban/s. The CA1 and $0 share same pins +A'' and +A'#! so yo" canJt "se both CA1 and $0 on same time.

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The $TM3#)'*3R0T( embeds a $0 device peripheral compatible with the $0 )"ll-speed '# Mbs. The $0 interface implements a f"ll speed A'# Mbit-sC f"nction interface. It has software config"rable endpoint setting and s"spend-res"me s"pport. The dedicated 4& M9% cloc/ so"rce is generated from the internal main +,,. The CA1 and $0 share same pins +A'' and +A'#! so yo" canJt "se both CA1 and $0 on same time.

A- .
$TM3#)'*3R0T( have two '#-bit Analog to 5igital Converters which share "p to '( external channels! performing conversions in singleshot or scan modes. In scan mode! a"tomatic conversion is performed on a selected gro"p of analog inp"ts. Additional logic f"nctions embedded in the A5C interface allow< - $im"ltaneo"s sample and hold - Interleaved sample and hold - $ingle sh"nt The A5C can be served by the 5MA controller. An analog watchdog feat"re allows very precise monitoring of the converted voltage of one! some or all selected channels. An interr"pt is generated when the converted voltage is o"tside the programmed thresholds. The events generated by the standard timers ATIMxC and the Advanced Control timer ATIM'C can be internally connected to the A5C start trigger! inEection trigger! and 5MA trigger respectively! to allow the application to synchroni%e A-5 conversion and timers.

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STM32-103STK can ta/e power from these so"rces< '.78 battery with 5C-5C step "p converter 8in signal on ;:T'-'' pin. - ?TA6 pin.' or # The board power cons"mption is< abo"t 3* mA when powered from the $0 port and '3*mA when powered from '.78 battery with all peripherials and MC r"nning at f"ll speed! there are different power saving modes which may p"t $TM3#)'*3R0T( in power sleep mode and in these modes the cons"mption of the MC is only few microampers.

R*S*T )R U)T.
STM32-103STK reset circ"it is made with RC gro"p R& - '*2 and C#&'**n). Altho"gh on the schematic is made provision for external reset IC s"ch is not necessary as $TM3# have b"ild-in brown o"t detector. Man"al reset is possible by the R;$;T b"tton.

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K"art% crystal &Mh% is connected to $TM3#)'*3R0T(. Internal +,, circ"it can m"ltiply this freH"ency "p to >#Mh%. 3#.>(& 29% H"art% crystal is connected to $TM3#)'*3R0T( for itJs internal Real Time Cloc/.

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EXT/BAT ' p$n9 po/ & !uppl: ! l ct ;u%p &5 EXT po!$t$on EXT/BAT Allo/ po/ & !uppl: <&o% %$n$1USB conn cto& o& =>"1-p$n1105 "h 4olta3 !uppl$ . to =>"1-p$n 110 %u!t 2 2 t/ n ,7DC an. ?7DC5 BAT po!$t$on EXT/BAT Allo/ po/ & !uppl: <&o% 15,7 AA -R609 no cha&3 2att &:9 plu3 . $n th BA" conn cto&5 R-T BAT_E Conn ct! @"A* "RS" !$3nal to S"M'2F10'RB"6 R=S=" D <ault !tat clo! . -!ho&t .0 Conn ct! '5'7 to S"M'2F10'RB"6 72at p$n51 D <ault !tat clo! . -!ho&t n09 72at !$3nal $! al!o a4a$la2l to =>"1 -p$n 10 conn cto&9 !o $< :ou /ant to conn ct xt &nal 2ackup 2att &: to th S"M'2F10'RB"6 th$! ;u%p & !houl. 2 op n . -un!ho&t .0 an. th xt &nal 2att &: to 2 conn ct . to =>"1 -p$n 10 conn cto&-! conn cto& . !c&$pt$on <o& =>"1 conn cto& p$n$n35057BA" acc pt 2 1 '5675

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Conn ct! USB po/ & !uppl: to S"M'2F10'RB"6 p$n 28 PC8A ADC18 an. allo/ to . t ct $< th 2oa&. $! conn ct . to USB ho!t5 D <ault !tat clo! . -!ho&t n0 Conn ct! S"A"US L=D to S"M'2F10'RB"6 p$n ,' PC12 D <ault !tat clo! . -!ho&t n0

LED-E

BOOT0, BOOT1 2oot ! Bu nc ! l ct B1CHAB1CL -Boot1CH$3hABoot1CLo/0 B0CLAB0CH -Boot0CLo/ ABoot0C H$3h0 B1CHAB1CL D <ault po!$t$onD Boot1 $! lo35 0 B0CLAB0CH Boot0 $! lo35 0

CP_E

WP_E

3.3V_E

Ca&. P& ! nt =na2l E Allo/ PC1-p$n ?0 to . t ct Mult$ M .$a Ca&. p& ! nt $n !ock t5 Lo35 1 o< PC1 E MMC p& ! nt5 Lo350 o< PC1 E Ca&. a2! nt5 D <ault !tat clo! . -!ho&t n0 #&$t P&ot ct =na2l E Allo/ PC2-p$n 100 to . t ct /&$t p&ot ct . !tat o< Mult$ M .$a Ca&.5 Lo35 1 o< PC2 E MMC no /&$t p&ot ct . 5 Lo350 o< PC2 E MMC $! /&$t p&ot ct .5 D <ault !tat clo! . -!ho&t n0 Conn ct '5'7 & 3ulat . 4olta3 to S"M'2F10'RB"6 po/ & p$n!5 3.3V_E ;u%p & $! u! . $< :ou n . to % a!u& cu&& nt con!u%pt$on o< th %$c&ocont&oll &5 D <ault !tat clo! . -!ho&t n0

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JOYST CK this is 4 directions pl"s center b"tton! in the schematic the Eoystic/ fo"r directions switches are connected thro"gh resistors with different val"es to +C7-A5C'7 ! the center b"tton is connected to +C(L B!TTO" B1 B!TTO" B2 #C$ ,eft b"tton connected to +C'3-TAM+;R portL Right b"tton connected to +A*-3A2;- + portL

1.2IA33'* &4x4& pixel blac/ and white ,C5 to $+I' portL 3-axis accelerometer connected to I#C' portL

%CC&#&ROM&T&R %'d(o )

microphone with pre-amplifier connected to +A' A5CL

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a"dio amplifier connected to +A& +3M o"tp"tL

S$-MMC card connected to $+I#L )RF2*#01 connected to $+I'L

+ower s"pply red ,;5 with name +,R M indicates that 3.38 power s"pply is applied.

CONNECTOR DESCRIPTION: 7TA2.

?TA6 C.11;CT.R +I1 5;$CRI+TI.1$ +() ' 3 7 > D '' '3 '7 '> 'D S(.)al "a/e T8CC 3.38 TR$T T5I TM$ TC2 1C T5. R$T 1C 1C +() # 4 ( & '* '# '4 '( '& #* S(.)al "a/e T8CC 3.38 615 615 615 615 615 615 615 615 615

TMS TCK TDI TD" T#ST

Input Input

Test Mode Select. The TMS pin selects the next state in the TAP state machine. Test Clock. This allows shifting of the data in, on the TMS and TDI pins. It is a positive edget igge ed cloc! with the TMS and TCK signals that define the inte nal state of the device. Input Test Data In. This is the se ial data input fo the shift egiste . "utput Test Data Output. This is the se ial data output f om the shift egiste . Data is shifted out of the device on the negative edge of the TCK signal. Input Test Reset. The T#ST pin can $e used to eset the test logic within the %m$eddedIC% logic.

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+() ' 3 7 > D '' '3 S(.)al "a/e 80AT +AD- $ART'NT:TIM'NC9# R5*-.$CNI1 +C4-A5C'4$0N+R;$;1T +A#- $ART#NT:A5C#-ITIM#NC93 8I1 3.38 +() # 4 ( & '* '# '4 S(.)al "a/e +A3- $ART#NR:A5C3-TIM#NC94 +A'*- $ART'NR:TIM'NC9# +C'#-,;5 +C3-A5C'3$T10F 1R$T G7.*8 615

=>"2
+() ' 3 7 > D '' '3 S(.)al "a/e +0*-A5C&-TIM3NC93 +0&-TIM4NC93 $C,# +C*-A5C'* 3+ A615 3.38 +() # 4 ( & '* '# '4 S(.)al "a/e +0'-A5CD-TIM3NC94 +0D-TIM4NC94 $5A# C+ 3.38NA G7.* 615

U*+T
+() ' 3 7 > D S(.)al "a/e 8CC 3.38 T:# $C,# $+I#NMI$. $+I#N$C2 +() # 4 ( & '* S(.)al "a/e 615 R:# $5A# $+I#NM.$I $+I#N1$$

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+() ' 3 7 > D '' '3 '7 S(.)al "a/e $+I#N1$$ 615 $+I#N$C2 $+I#NMI$. '*2 to 3.38 to pin '4 C+N; #2 to 3.38 +() # 4 ( & '* '# '4 S(.)al "a/e $+I#NM.$I 8CC 615 '*2 to 3.38 3+N; to pin '7 #2 to 3.38

US/
+() ' # 3 4 7 S(.)al "a/e 80 $ $05M $05+ 1C 615

A9A)(A/(* -*M' S'0T1AR*.

$0 mo"se with the 3-axis accelerometer $0 class A"dio device $0 mass storage $0 8irt"al com port $0 R) 8irt"al com port bridge 0all game with accelerometer .pen.C5 demo proEect

'R-*R '-*. STM32-103STK : assembled and tested $no ;it, no solderin" re<uired&
5o= to order> 4ou %an order to us dire%tl! or b! an! o? our distributors. #e%; our =eb ===.olime@.%om8dev ?or more in?o.

All boards prod"ced by .limex are R.9$ compliant

Revision history: #%&.A ' c eate Ap il ())*

Disclaimer+ , ())* "limex -td. All ights ese ved. "limex., logo and com$inations the eof, a e egiste ed t adema !s of "limex -td. "the te ms and p oduct names ma/ $e t adema !s of othe s. The info mation in this document is p ovided in connection with "limex p oducts. 0o license, exp ess o implied o othe wise, to an/ intellectual p ope t/ ight is g anted $/ this document o in connection with the sale of "limex p oducts. 0eithe the whole no an/ pa t of the info mation contained in o the p oduct desc i$ed in this document ma/ $e adapted o ep oduced in an/ mate ial f om except with the p io w itten pe mission of the cop/ ight holde . The p oduct desc i$ed in this document is su$1ect to continuous development and imp ovements. All pa ticula s of the p oduct and its use contained in this document a e given $/ "-IM%2 in good faith. 3oweve all wa anties implied o exp essed including $ut not limited to implied wa anties of me chanta$ilit/ o fitness fo pu pose a e excluded. This document is intended onl/ to assist the eade in the use of the p oduct. "-IM%2 -td. shall not $e lia$le fo an/ loss o damage a ising f om the use of an/ info mation in this document o an/ e o o omission in such info mation o an/ inco ect use of the p oduct.