Copyright 2001-2003,

Model Technology SITAL

SITAL
T e c h n o l o g y
T e c h n o l o g y 1
A Taste of PSL
Property Specification
Language
Nir Hamzani, SITAL Technology
ASIC & FPGA Conference, May/17/2004
www.sital.co.il 09-9559166
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What is The Problem?
The Verification Gap:
* Source: SIA Roadmap 2001
0
20
30
40
50
60
70
80
1988 1992 1996 2000 2004
10
A
b
i
l
i
t
y

t
o

F
a
b
r
i
c
a
t
e

*
A
b
i
l
i
t
y

t
o

D
e
s
i
g
n
A
b
ility to V
erify
Verification
Gap
Design
Gap
Silicon FAB capabilities are way ahead of current design capabilities.
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Why the Gap Exists?
Moores Law
Verification Productivity
Exhaustive simulation is almost impossible
What stimulus to generate and how to control it?
Block and system verification disconnects
Creating testbenchs & tests as challenging as chip design
Verification Completeness
Traditional source and toggle coverage != functional coverage
Debug Productivity
Did error propagate to output?
How long after cause was error seen on output?
Where did the error occur?
Lack of Standards
No portability between projects or companies
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Can we Narrow the Gap?
Enhance Productivity?
Shorten time?
Functional coverage?
Improve Debug?
All Test Passes!

Output file is empty?!?!

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Limitation of HDL Monitor
Lets face the limitations of current
Verification Techniques through a simple
example.
All Test Passes!

Output file is empty?!?!

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Limitation of HDL Monitor
Upon a req and concatenated ack, a sequence of
concatenated start, busy and end should exist.
if
then
Such a VHDL/Verilog Monitor
is quite complicated and
will require at least
10-20 lines of code
(+time, +debugging)
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Limitation of HDL Monitor
Upon a req and concatenated ack, a sequence of
concatenated start, busy and end should exist.
if
then
if
then
Consider Overlapping,
and a VHDL/Verilog monitor
become almost impossible
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Lets Taste some PSL
Now, lets build the same Monitor using PSL.
Since you are not familiar with PSL, lets
have a few minutes on PSL basics...
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PSL Key Attributes
PSL is an intuitive, declarative language for
describing behavior over time.
Uses of PSL:
For documentation: easy to read, yet precise
specification.
For driving assertion-based verification (ABV):
Formal verification tools
Simulation tools
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The Structure of PSL
Boolean layer
Describe states of design - Boolean Expressions (True or False)
Temporal layer
Describe behavior of design over time - Temporal Expressions
Property layer
Specification of the required behavior
Can describe good (always) or bad (never) behavior
Modeling layer
Directives to the verification tool about a property:
assert/assume/cover
Boolean
Temporal
Property
Modeling
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The Structure of PSL
PSL comes in flavors
VHDL
Verilog
GDL (General Design Language)
The HDL flavors is used to identify Boolean Expressions
compatible with the relevant language + some syntactic
differences:
Syntax Verilog VHDL
Declaration = is
Range [n:m] [n to m]
Path separator . :
Comment // --
Operators && and
Everything else is PSL-specific and independent
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PSL Basics SEREs Example1
A SEREs (Sequential Extended Regular Expressions) (Sequence )
describes a set of sequences of states (which we
represent using timing diagrams):
This diagram is
described by the
above SERE
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PSL Basics SEREs Example1
A SEREs (Sequential Extended Regular Expressions) (Sequence )
describes a set of sequences of states (which we
represent using timing diagrams):
But, this diagram is
also described by
the same SERE
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PSL Basics SEREs Example1
If we want to
describe only this
diagram, we have to
use the SERE on
the right..
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PSL Basics SEREs Example2
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PSL Basics SEREs Example2
Signal busy
holds 4 times
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PSL Basics SEREs Example3
Signal busy holds
any number of
times between
3 to 5
Signal busy holds
any number of
times
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PSL Basics
Until now we saw examples for SEREs,
which are not properties on their own, but
rather building blocks of properties.
We will now see examples of properties
composed from the SERE building blocks.
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PSL Basics Properties
The next suffix implication operator
if
if the path
starting now
starting now matches
then
then its
continuation
continuation should match
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PSL Basics Properties Example
if
then
But the property
makes a requirement
only for req that holds
at the very first cycle
Add true[*]
to the beginning
of the first SERE
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PSL Basics Properties Example
Now the property makes a
requirement for every
req no matter the cycles
where it holds
if
then
Note that the
requirement is made
for more than one (the
first) req
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PSL Basics Properties Example
if
then
if
then
and
Overlapping is
also possible!
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PSL Basics Properties Example
if
then
if
then
1 line of PSL code!
Such a VHDL/Verilog Monitor
is quite complicated and
will require at least
10-20 lines of code
(and overlapping is almost
impossible)
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PSL Basics Properties Example
1 line of PSL code!
PSL is an intuitive, declarative language for describing
behavior over time.
Uses of PSL:
For documentation: easy to read, yet precise
specification.
For driving assertion-based verification (ABV):
Formal verification tools
Simulation tools
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Lets Taste some more PSL, Properties Example2
if
then
But what if data
does not hold in
contiguous cycles?
Use [=8]
instead of [*8]
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PSL Basics Properties Example2
if
then
1
2 3 4 5 6 7
8
But what if the
signals are only
sampled when
clk holds?
Apply @clk to
the property
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PSL Basics Properties Example2
@ (posedge clk)
if
then
1 3 2
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Other Temporal Operators: Never
never (read_enable && write_enable)
read_enable and
write_enable are never
asserted together
read_enable
write_enable
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Other Temporal Operators: Always
always (req -> next ack)
Whenever req is
asserted, ack must
be asserted at the
next cycle
req
ack
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Other Temporal Operators: Forall
Using the forall operator, we can examine several
values in a single property
always (req && data_in=='b000 -> next data_out=='b000)
always (req && data_in=='b001 -> next data_out=='b001)
always (req && data_in=='b010 -> next data_out=='b010)
...
Can be written concisely
forall i in 0..7:
always (req && data_in==i -> next data_out==i)
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PSL Final Example
Spec: If signal req is granted with signal grant and signal frame is not received within
64 cycles while grant remains asserted, then signal time_out shall be asserted.
If frame is asserted within 64 cycles, then signal acquired shall be asserted.
clk
req
grant
frame
timeout
acquired
63
Property ReqGrantTimeout =
always {req && rose(grant); {!frame && grant}[*63]} |-> {time_out}
Property ReqGrantAcquired =
always {req && rose(grant); {!frame && grant}[*0:62]; frame} |-> {acquired}
clk
req
grant
frame
timeout
acquired
<=62
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Conclusions: PSL Bridges the Gap
1st standard property specification language
For Static & Dynamic verification
Increases verification productivity
Documents requirements and assumptions
Guide & direct stimulus generation
System and block verification
Measuring Verification Completeness
Functional coverage not code coverage
Check corner cases and deep states
Increases Debug Productivity
Bugs identified earlier
And closer to the source of the problem
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ABV Methodology
Architectural Design
Proc
arbiter
FIFO
Controller
FSM
English Specs
All bus requests
shall receive an
acknowledge-
ment
RTL Design
ent i t y FSM i s
por t ( ) ;
end FSM; Syn-
the-
sis +
P&R
Implementation
Formal spec,
functional test
points,
transactions
Operational constraints &
assumptions
Interfaces & Protocols
Structural Properties
& Assertions
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Using PSL with ModelSim (ver 5.8 and above)
Assertion Browser
Add to wave window from assertion window
Expanded Assertion
Advanced Settings
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Assertions in the Wave Window
Red inverted triangle
indicates assertion
failure
Simply D&D Assertions from Assertion Browser into Wave Window to view assertions,
Assertions can be expanded to view all signals associated with the assertion
Right click on we_n
signal in the wave
window to further debug
Green triangle
indicates assertion
passed
Green mid-line indicates
assertion is active
Blue low-line indicates
assertion is inactive
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Assertion failure
PSL Debug
From Wave add to Dataflow
Assertions find failure =>Use GUI to find source of failure
Dataflow to Source of error
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Acknowledgements to the "PSL/Sugar Development Team at
the IBM Haifa Labs" for helping me with this presentation.
Training
A 3 days PSL course by Sital Technology and IBM Israel Haifa Labs will be
available in ~3 months. Registration at Sela Youniversity: 03-6176133.
Register at Sital Booth to get this Presentation and
White Papers about Assertions and PSL vs. SVA.
Book: Using PSL/Sugar for Formal and Dynamic Verification
Book by Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari
www.vhdlcohen.com
PSL LRM:
http://www.accellera.org/pslv101.pdf
PSL Resources and Acknowledgements