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Published in IET Power Electronics Received on 12th October 2010 Revised on 18th April 2011 doi: 10.1049/iet-pel.2010.0363

ISSN 1755-4535

Flyback converter with novel active clamp control and secondary side post regulator for low standby power consumption under high-efciency operation
J.-H. Jung1 S. Ahmed2
New and Renewable Energy System Research Center, Smart Grid Research Division, Korea Electrotechnology Research Institute, Changwon, Republic of Korea 2 Department of Electrical and Computer Engineering, Texas A&M University at Qatar, PO Box 23874, Education City, Doha, Qatar E-mail: jeehoonjung@keri.re.kr
1

Abstract: Flyback converters are widely used in industrial and commercial products because of their advantages of simple structure and low cost. Energy and environmental conservation have prompted interest in high efciency and low standby power consumption in switch mode power supply applications. However, it is difcult to satisfy both conditions simultaneously because of conicting design considerations. A novel active clamp control method is proposed for improving power conversion efciency and reducing standby power consumption in a yback converter. In addition, an asynchronoustype secondary side post regulator is applied to the converter for minimising standby energy leakage and improving crossregulation performance for a multiple output channel yback converter. Operational principles, control schemes, switch stresses and power consumptions are analysed using a converter small signal model and mathematical equations of converter waveforms. The superiority of the proposed converter is veried using experimental results on 110 W prototype.

Introduction

Single-ended active clamp converters have recently gained widespread acceptance for many medium power ofine dc dc converter applications. The active clamp technique for absorbing leakage energy offers many well-documented advantages over traditional single-ended reset techniques, including lower voltage stress on the main switch, the ability to switch at zero voltage, reduced electromagnetic interference (EMI) and duty cycle operation above 50%. Typically, the clamp switch is kept on during the off-time of the main switch. As a result, the clamp capacitor absorbs and returns parasitic energy during every cycle with minimal losses. Several publications have compared the performance advantages of the active clamp over the more widely used RCD clamp [1 3]. In addition, theory, operation and applications of these converters have been reported in many previous publications [4 14]. Many small switch mode power supplies (SMPSs) have been designed with a single controller and multiple output channels to meet the needs of multiple voltages and low cost under various loading conditions including standby mode. In this case, only a single output can be tightly controlled while others not. Using multiple output sensing methods, a single controller can control several sensed outputs, however, it cannot tightly regulate the output voltage. This cross-regulation problem is especially signicant when output channel loads are extremely
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unbalanced; a phenomenon that can lead to output voltage uctuations. To improve the cross-regulation performance, magnetic ampliers (magamp) have been developed [15 18]. The magamp is a well-known post-regulation method. A saturable core in the inductive component is utilised for post-regulation. A synchronous post regulator (SPR) was also proposed as another method to improve crossregulation performance [19]. Researches have addressed its control methods [20 23], analysis [24] and application [25]. The SPR uses series metal oxide semiconductor eldeffect transistors (MOSFETs) connected between the cathode of the rectifying diodes and the output capacitors. It is controlled using a pulse-width modulation (PWM) algorithm synchronised with the main switch of the converter. The additional inductive component in the magamp will also contribute to loss in efciency. The SPR needs a complex control scheme and an elaborate drive circuit, which makes the SPR more expensive. There is research to improve the cross-regulation of a switched resonant converter [26, 27]. It uses a secondary side post regulator (SSPR) controlled by asynchronous gate voltage levels and a simple control circuit, however, falls short of considering standby-mode operation. In this paper, a novel control method of the active clamp switch and the SSPR are proposed. The active clamp technique can save leakage energy in its clamp capacitor during normal power conversion, however, conduction loss
IET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067 doi: 10.1049/iet-pel.2010.0363

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caused by continuous primary current and additional switching loss consumed by the active clamp switch induce high power loss in standby-mode operation. The active clamp switchs proposed control method can reduce the conduction and switching losses using a switch disable signal in standby mode. Additionally, the proposed SSPR prevents energy leakage in standby mode by disconnecting unused output channels from the load. Cross-regulation performance is also improved by the SSPR without additional switching operations, complicated control and drive circuits. Operational principles, design considerations and proposed control schemes of the active clamp switch and the SSPR will be presented. Improvements in power conversion efciency and cross-regulation performance in the normal and standby modes will be veried experimentally on 110 W prototype converter.

2 Operational principles and design considerations

2.1 Flyback converter with active clamp

The incorporation of an active clamp circuit into the yback topology is shown in the primary side in Fig. 1a. In this gure, the yback transformer is replaced with an equivalent circuit model showing the magnetising and leakage inductances on the primary side, Lm and Llk , respectively. Explanations of the topological states, operational waveforms and design guidelines of the active clamp yback converter are well documented in the literature [4 14]. The proposed converter uses a high-side clamp structure to decrease the voltage across the clamp capacitor and reduces MOSFET cost compared to a low-side clamp structure. In the case of a low-side clamp structure as shown in Fig. 1b, the maximum voltage of the clamp capacitor, vc,max , can be derived from (1) vc, max = Vi 1 Dmax
Fig. 1 Schematics of the proposed converter and circuits

(1)

where Vi is the dc input voltage and Dmax is the maximum duty ratio of S1 as shown in (2) Dmax = nVo1 nVo1 + Vi,min (2)

a b c d

Flyback with high-side active clamp circuit and SSPR Low-side active clamp circuit Self-driven gate driver for active clamp MOSFET Standby control for active clamp gate driver

where n is the turn ratio between the transformer primary winding and secondary winding, Vo1 is the controlled main output voltage and Vi,min is the minimum dc input voltage, respectively. Since clamp capacitor voltage stress is proportional to the input voltage, low-side clamps are disadvantageous to their high-side counterpart. Additionally, a more expensive P-channel MOSFET is also needed because of the body diode direction. The maximum clamp capacitor voltage vc,max of the highside clamp structure can be calculated as in (3) vc,max = Dmax V 1 Dmax i (3)

Here, the input voltage is scaled down by the duty cycle; hence, the clamp capacitor has lower voltage stress. Additionally, a cheaper N-channel device can be used as a clamp MOSFET. Another consideration is the complexity
IET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067 doi: 10.1049/iet-pel.2010.0363

of the gate drive of the active clamp MOSFET. Typically, a high-side clamping MOSFET requires an additional bootstrap driver or gate transformer, however, the proposed converter uses a self-driven gate driver merged with the transformer. It does not require the boot-strap driver or gate transformer but needs an additional transformer winding, resistor and zener diode. The schematic of the self-driven gate driver and its standby control used in the converter are shown in Figs. 1c and d, respectively. A design procedure of the gate driver is suggested covering the additional gate drive winding included in the transformer T, gate resistor Rg , and zener diode Dz . First, the winding turn ratio should consider average and peak voltages applied to the primary winding of the transformer because the induced voltage on the primary winding determines the gate voltage of the active clamp MOSFET, S2 . This induced voltage is transferred through the gate winding. Second, the gate resistance should consider the gate-source capacitance of S2 to obtain a proper switching speed. The switching speed of S2 is determined by the multiplication value of Rg and the gatesource capacitance. Finally, the zener breakdown voltage of
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Dz should consider the maximum rating of the gate voltage of S2 to protect the switch. The standby controller of the active clamp gate driver in Fig. 1d will be discussed in the next section. 2.2 Secondary side post regulator The principle of operation of the SSPR is as follows: the difference between the output voltage controlled by the SSPR and the reference voltage set by the voltage reference circuit is amplied by the error amplier to generate the gate voltage of the SSPRs series MOSFET. Fig. 2b illustrates the relation between the gate voltage level and the operating point of the SSPR series MOSFET. By controlling the operating point, the SSPR can regulate the output voltage by changing its drain-source impedance. In Fig. 2b, the drain-source impedance, RQ , at the operating point Q, can be obtained from (6) RQ = VSQ ISQ (6)

Fig. 2a shows the control and drive circuits of the proposed SSPR. This circuit is composed of three parts: voltage reference generation, intelligent function control and gate voltage control. The voltage reference circuit is designed using a shunt voltage regulator to generate the output reference voltage. In Fig. 2a, this circuit is composed of the shunt regulator, R4 , R5 and R6 . The anode and reference of the shunt regulator are connected to the output voltage, Vo2 , and its cathode, respectively. Resistor R4 supplies the operating energy of the shunt regulator from a secondary auxiliary winding. If the reference voltage of the shunt regulator is Vsr , then the output reference voltage, Vr2 , is determined by R5 and R6 as in (4) Vr2 = R6 (V + Vsr ) R5 + R6 o2 (4)

where VSQ and ISQ are the operating voltage and current of the SSPR MOSFET, respectively. Therefore in Fig. 1a, the output voltage, Vo2 , which is regulated by the proposed SSPR can be expressed as in (7) Vo2 = VCs Rs Is (7)

The error amplier is implemented using an opamp and a proportional integral (PI) feedback loop. If the entire system is stable, the output voltage, Vo2 , will equal the reference voltage, Vr2 , at steady state. In this case, the two opampinputs become virtually shorted. Therefore the output voltage regulated by the SSPR can be calculated from (5) accounting for the ratio of the resistances R5 and R6 , k R6/(R5 + R6). Vo2 = Vr2 = Vsr 1k (5)

where VCs is the voltage across the stabilising capacitor Cs , and Rs and Is are the drain-source resistance and current of Ss , respectively. From (7), the output voltage, Vo2 , can be regulated by proper selection of the series MOSFET resistance, Rs , controlled by the SSPR.

3
3.1

Novel control schemes

Control scheme of the active clamp switch

From (5), the voltage reference circuit can be designed to set the required output voltage.

Fig. 2 Control and operation of the proposed SSPR

a Drive circuit b Operating point of the SSPR series MOSFET 1060 & The Institution of Engineering and Technology 2011

The active clamp circuit contributes to the switching power loss of the two MOSFETs and increased conduction loss due to the primary current. In standby mode, a limited switching operation such as burst mode or skip cycle operation is required to reduce power losses. The selfdriven active clamp gate driver with the proposed standby control input was illustrated in Fig. 1c. The gate transformer winding of the self-driven driver is coupled to main power transformer windings. When the primary switch S1 turns on, the zener diode Dz in the gate driver conducts and the active clamp switch S2 turns off. In contrast, when S1 turns off, the current generated by the gate transformer winding passes through the gate resistor Rg and gate voltage is induced, consequently S2 turns on. Gate resistance Rg limits the gate current and the switching speed of S2 . The zener diode Dz clamps the maximum gate voltage of S2 to its breakdown voltage. In Fig. 1c, the proposed active clamp switch can be controlled using the standby control signal. If the standby control signal is high, the photo coupler turns on and the gate voltage of S2 becomes zero, disabling the active clamp circuit. When the control signal is low, the active clamp circuit will operate with the gate voltage generated by the self-driven gate driver. The standby control circuit uses the photo coupler due to galvanic isolation between the primary and secondary sides. Standby-mode information is usually obtained from the converters secondary side. A microcontroller can be used to measure the output channel voltage and to issue the needed control signals. When the active clamp switch is disabled, the converter can operate under the burst or skip cycle modes to reduce switching losses in standby mode. The voltage clamping operation is not required in standby mode, since a much smaller leakage
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current induces much lower voltage spikes on the power switch. 3.2 Control scheme of SSPR where Zc is the impedance of the controllers feedback loop and can be expressed as in (10). Zc (s) = sC1 R2 s(C1 + C2 )(1 s(C1 C2 /(C1 + C2 )R2 )) (10)

In this subsection, output voltage control of the SSPR is analysed using a small signal model. Assuming that the stabilising capacitor, Cs , is large enough to emulate a stiff voltage source, the power stage of the second output channel can be changed to the small signal model in Fig. 3a, where the input voltage source is Vin , the series MOSFET current is Is , the effective series resistance (ESR) of Co2 , rc2 and the series MOSFET channel resistance, Rs . The variables vin , rs , is and vo2 are the small signals of Vin , Rs , Is and Vo2 , respectively. Ze is the output lter impedance seen from the series MOSFETs side. The transfer function between vo2 and rs , Gr(s), can be derived by assuming time-invariant Vin ( vin = 0) and small rc2 as in (8). G r ( s) = vo2 rs Vo2 1 + sCo2 Ro2 Ro2 + Rs 1 + s(Co2 Ro2 (Rs + rc2 )/(Ro2 + Rs )) (8) In Fig. 2a, the PI controllers gain is determined by C1 , C2 and R2 . Assuming that the SSPR operates at steady state, the two opamp-inputs are virtually shorted. Then, using (5), the amplied gate voltage of the series MOSFET, Vg , can be obtained in the Laplace domain as in (9) Vg (s) = Zc (s) Z (s) Vsr Vo2 + 1 c R1 R1 1 k (9)

Because Vsr is a time-invariant reference voltage, the PI controller transfer function, Gc(s), can be obtained using small signal modelling as in (11) G c ( s) = vg 1 + sC1 R2 (11) = s(C1 + C2 )R1 [1 + s(C1 C2 /(C1 + C2 ))R2 ] vo2

where vg is the small signal of Vg . Fig. 3b shows the entire small signal model of the closedloop SSPR system. In Fig. 3b, Gm is the small signal gain of the MOSFET channel resistance, Rs , for different gate voltage, Vg , as in (12) Gm = rs vg (12)

where rs is the small signal of Rs . Gm can be obtained from the turn-on drain-source resistance against gate voltage data in the manufacturers data sheets. From (8), (11) and (12), the closed-loop gain of the entire SSPR, T (s), can be derived as in (13). T ( s) = G r ( s) G m G c ( s) (13)

Table 1 shows the SSPR parameters of the passive components used in the prototype 110 W converter. From (13) and the parameters, the stability and dynamics of the overall SSPR system can be analysed. Fig. 4 shows the bode diagram of T (s) with the designed parameters. The gain and phase margins of the SSPR overall system are innite and 1528, respectively. The SSPR is a highly stable system whose stability is not affected by its gain. It also possesses considerable phase margin. Hence, it is theoretically acceptable for the controllers gain to tend to innity since overshoots and/or oscillations will be damped by the high phase margin.

4
4.1

Performance improvements
Improvements in normal mode

The leakage energy, Elk , not transferred to the secondary power stage can be calculated from (14) 1 Elk = Llk i2 p,max 2
Table 1
Parameter Ro Rs R1 R2 R5 R6 Parameters of the SSPR control and drive circuit Value, V 1.0 10 10 1.0 104 1.2 102 2.0 103 2.0 104
3

(14)

Parameter Co C1 C2 Vo Vsr rc

Value 1.5 1023 F 4.7 1026 F 4.7 1027 F 2.4 101 V 2.5 V 1.0 1022 V

Fig. 3 Small signal models of the output channel and SSPR

a Power stage b Entire power and control stage IET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067 doi: 10.1049/iet-pel.2010.0363

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Without any power loss in the active clamp circuit, the voltage spike on the power switch is limited by the active clamping operation. From (7), the SSPR can regulate the uncontrolled output voltage; therefore it can improve cross-regulation performance among multiple output channels. Moreover, the operating power consumption of the SSPR is lower than the power consumption of conventional SPRs. The switching loss of the SPR series MOSFET, Ploss,SS , is given by (20) [28] 1 2 Ploss,SS = Qg Vgr fs + Css Vss fs 2 (20)

Fig. 4 Bode plot of the SSPR with gain and phase margins

where ip,max is the maximum primary current. The active clamp circuit can save this energy in the clamp capacitor and transfer it to the secondary side during the turn-off phase of the main power switch, S1 . Additionally, the active clamping operation can suppress voltage spikes of the power switch in a lossless fashion. Without the clamp circuit, the leakage energy charges the output capacitance, Cs1 , with a high voltage spike. The maximum voltage of S1 including the voltage spike can be calculated using (14) as shown in (15) Vs1,max = Vi + nVo1 + ip,max Llk Cs1

where Qg is the total gate charge, Vgr is the gate voltage, Css is the equivalent output capacitance and Vss is the drain-source voltage of the series MOSFET, respectively. Since Vss depends on the output voltage, it is relatively low for low output voltages. The main switching loss component is caused by the rst term of (20), which is governed by Qg and fs . The power loss of a SPRs control circuit, Ploss,SC , is given by (21) Ploss,SC = Vcc Iop (21)

(15)

Compared to the output voltage, Vo1 , the forward voltage drop of the rectier is small enough and can be ignored. If a conventional RCD clamp circuit is used, the maximum switch voltage can be calculated from (16), where Rc is the clamp resistor and fs is the switching frequency, respectively. Vs1,max = Vi + nVo1 1 + 2 2 (nVo1 )2 2Rc Llk i2 p,max fs (16)

The RCD clamp capacitor, Ccl , is selected using (17). Ccl = Cs1 Vs1,max Vi Llk ip,max fs Rc (17)

where Vcc is the supply voltage and Iop is the average operating current of SPRs control circuit. This control circuit consumes operating energy comparable to that of the PWM controller because of its synchronous switching. Iop will be in the order of mA, and Ploss,SC will also be hundreds of mW. Therefore Ploss,SC as well as Ploss,SS are signicant power loss components in the SPR. On the other hand, the proposed SSPR consumes much less energy than the SPR. Switching losses do not exist because there are no switching operations in the SSPR, instead, the controller only changes the value of gate voltage. Therefore the power loss caused by Qg is much smaller than that of the SPR. In the SSPR control circuit, power consumption is determined by the opamp adopted for the error amplier. In the proposed SSPR, the ON Semiconductor MC33072 is used. This device consumes 50 mW when powered using a 12 V rail. Consequently, the drive and control circuit of the proposed SSPR consume much less operating power than the SPR case. The output voltage regulation of the proposed SSPR is similar to the regulation action of the conventional linear low-dropout (LDO) regulator. However, there is no consideration of the reduction of standby power consumption in the LDO regulator. 4.2 Improvements in standby mode

By proper resistor and capacitor selection, voltage spikes on the power switch can be suppressed. However, the power dissipation from the RCD clamp circuit, Pc , increases proportionally with the square of the maximum primary current as shown in (18) Vs1,max Vi 1 Pc = i2 p, max Llk fs Vs1,max Vi nVo1 2 (18)

Therefore the RCD clamp reduces the power conversion efciency. The maximum switch voltage with the active clamp is given by (19). Vs1,max = Vi 1 Dmax (19)

With the active clamp topology, zero voltage switching of the main power switch S1 requires sufcient energy stored in the leakage inductance to completely discharge the MOSFET output capacitance [4, 7]. However, this leakage energy is not enough to fully discharge the capacitance in standby mode because the primary current becomes minimal. Under this situation, the summation of turn-on switching and gate drive losses of the main and active clamp MOSFETs, Psw,AC , can be calculated as in (22) 1 Vi Psw,AC = Cs1 1D 2
2

fs + 2Qgs Vgs fs

(22)

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where D is the duty ratio of S1 , Qgs and Vgs are the total gate charge and gate voltage of S1 and S2 , respectively. From (22), the switching loss of the MOSFET is proportional to the switching frequency. In addition, the conduction loss of the primary side, Pc,AC , can be calculated using the rms value of the primary current as in (23) Pc,AC Req Vi D3 = 3fs (Lm + Llk ) (23) ripple voltage PD2 = 2Co2 Vf Vo2,r fs + Vf Vo2 Ro2,st (27)

The output voltage, Vo2 , has DC and AC components because of the converters switching operation. Vo2 can be described in terms of these two components as follows Vo2 = Vo2,DC + Vo2,r 2 (28)

where Req is the equivalent series resistance of the primary side, including winding resistance of the transformer and drain-source turn-on resistance of the power MOSFET. In burst mode, the summation of turn-on switching and gate drive losses of the power switch, Psw,BM is as shown in (24), where fb is the switching frequency of the burst mode. 1 Psw,BM = Cs1 Vi2 fb + Qgs Vgs fb 2 (24)

where Vo2,DC is the DC value of Vo2 . From (27) it is observed that the load impedance and the voltage ripple caused by the PWM switching affect the power consumption in the output rectier, D2 . The load impedance is also a dominant factor in PD2 because Vo2,r is much smaller than Vo2 . Prc2 can be calculated as in (29)
2 2 Vo2,r fs2 rc2 Prc2 = 4Co2

fb is usually several orders of magnitude lower than the normal switching frequency fs . Therefore the total switching loss in burst mode is signicantly lower than the switching loss of the active clamping operation. Additionally, the conduction loss in burst mode can be calculated as in (25) Pc,BM = Req Vi D3 b 3fb (Lm + Llk ) (25)

(29)

From (29), Prc2 will be a relatively small value since rc2 is small and Vo2,r is also small in standby mode. Po2,st is given by (30) Po2,st =
2 Vo2 Ro2,st

(30)

where Db is the duty ratio of S1 under burst mode. Although fb is lower than fs , Pc,BM is less than Pc,AC because Db is smaller than the normal mode duty ratio, D, and the conduction loss is proportional to the duty ratio cubed. Figs. 5a and b show the converters secondary circuit with and without the proposed SSPRs turn-off function, respectively. Without disconnection of the unused output channels in Fig. 5a, the additional power loss in standby mode, Ploss,S , can be calculated from (26) Ploss,S = PD2 + Prc2 + Po2,st (26)

where PD2 , Prc2 and Po2,st are the power losses due to the forward voltage drop of the output diode, Vf , the ESR of the output capacitor, rc2 , and the output resistance in standby mode, Ro2,st , respectively. PD2 can be derived as in (27), where Vo2,r is the peak-to-peak value of the output

Therefore the disconnection of unused output channels by the SSPR is an important and efcient method to eliminate power leakage through the output channels. In Fig. 5b, there is no power loss in the unused output channel when the SSPR turns off. It is assumed that the power losses caused by the ESR of the stabilising capacitor, Cs , and by the output rectier, D2 , are negligible. This is due to the fact that the stabilising capacitor will have very low ripple voltage, hence capacitor ESR will have little effect. Additionally, only the capacitor discharge current passes through D2 , which is also negligible. Thus, compared to the case without a SSPR, apparent power loss advantages exist. 4.3 Soft turn-on function of the SSPR

Fig. 5 Output power loss comparison in standby mode

a Without the SSPR b With the SSPR IET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067 doi: 10.1049/iet-pel.2010.0363

In Fig. 2a, there are two switches controlled by the standby control signal to turn on and off the SSPR. The turn-off function can disconnect the unused output channel(s) from the load to eliminate the power leakage in standby mode. A soft turn-on is also required to protect power devices of the SSPR from high voltage or current stress. An instant turnon of the secondary regulator can cause electrical damage to the load devices and the regulator itself due to current and voltage spikes. The proposed SSPR uses a soft turn-on function to prevent high voltage and current pulses caused by discharged output capacitors in the converters output channels. Degradation and/or damage of the output capacitors, the SSPRs MOSEFT and diode may otherwise result. Voltage uctuation of other output channels caused by the inrush current is also prevented using the soft turn-on. This function can be realised using the soft turn-on capacitor, C3 , in Fig. 2a. The voltage across R6 , VR6 , can be
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calculated from (31) VR6 (t ) = k (Vo2 + Vsr ) 1 exp t R6 C3 (31)

where t is the time parameter. The time duration of the soft turn-on, tst , can be evaluated using (32). Larger values of R6 and C3 will result in a long turn-on time duration. tst = R6 C3 (32)

5
5.1

Experimental results
Switch voltage and efciency

Figs. 6a and b show the prototype 110 W SMPS and the SSPR printed circuit board (PCB) layout used in the experiment, respectively. This converter has a single controller, two outputs, an active clamp circuit, and its nonfeedback controlled output channel is regulated using the proposed SSPR. In normal operation, the active clamp circuit suppresses voltage spikes of the main switch and the SSPR regulates the voltage of the non-feedback output channel. In standby mode, the active clamp switch and SSPR turn off to reduce unnecessary power consumption. Figs. 7a and b show voltage and current waveforms of the conventional quasi-resonant (QR) yback converter with the RCD clamp and the proposed converter with the active clamp and SSPR. Input voltage of the two converters was 220 Vrms
Fig. 7 Voltage and current waveforms under full-load condition
a With RCD clamp b With active clamp

and rated output power was 110 W. In Fig. 7b, the maximum drain-source voltage stress of S1 is limited to 512 V by the active clamp operation. In Fig. 7a, the RCD clamp suppresses the voltage spike to 580 V. A clamp resistance can suppress the voltage spike of S1 to less than 580 V; however, it consumes more energy. A lower value clamp resistance reduces power conversion efciency in normal operation and standby modes. Fig. 8 shows power conversion efciency curves of the QR yback converter with the RCD clamp and the SSPR, and the proposed active clamp yback converter with the SSPR according to the level of output power. Under low to mid-load conditions, the efciency of the converter including the proposed methods is lower than the efciency of the

Fig. 6 Photograph of real circuit

a 110 W converter sample b PCB assembly of the SSPR 1064 & The Institution of Engineering and Technology 2011

Fig. 8 Efciency curves of the proposed and RCD clamp yback converters
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conventional QR yback converter with the RCD clamp because of additional power losses caused by the drive circuits of the active clamp and the SSPR. The power conversion efciency of the converter containing the RCD clamp and the SSPR is located between the efciencies of the other two converters, since no power loss is caused by an active clamp. However, the power conversion efciency of the proposed converter is similar to the efciency of the conventional converter under high loads. Even though the conduction loss of the SSPRs series MOSFET increases the power loss during the power conversion, the active clamping operation can compensate this power loss by recycling leakage energy. Compared to the efciency of the conventional RCD clamped converter including the SSPR, the proposed converter shows 3.3% efciency improvement at 110 W rated output power. From Fig. 8, the power loss caused by the SSPR increases proportionally with load current because of its conduction loss. Using the active clamp circuit, however, the power loss can be compensated under high loads. Additionally, the next subsection will illustrate how employing the SSPR can save standby power consumption. 5.2 Standby power consumption voltage stress of the power switch is limited to 512 V without any clamp circuits because of the extremely low leakage current. Table 2 shows the power consumption of the SMPS under the no load and standby mode conditions for a laser printer application. The output power consumption in standby mode is almost 0.3 W (5 V/60 mA) in this application. The left side of Table 2 shows the power consumption using a conventional converter without the proposed switch control method and SSPR. The right side is the standby power consumption when the proposed techniques are used. Standby power is saved by inhibiting the active clamp operation, reducing the switching frequency using burst mode and preventing energy leakage using the SSPR. Reduction ratios at the no load and standby mode conditions are 83 and 63.7 %, respectively. From Table 2 it can be concluded that power consumption due to the active clamps increased conduction current, and power leakage through the unused channel is approximately 2.2 W for this laser printer. Without preventing these power losses, it would be very challenging to reduce standby mode power consumption. 5.3 Cross-regulation and soft turn-on

Figs. 9a and b show voltage and current waveforms of the active clamp and burst operation cases in standby mode. The operating frequency of the burst mode is 2.94 kHz, which is much lower than the 40 kHz switching frequency of the active clamp operation. In Fig. 9b, the maximum

Table 3 shows the specic cross-regulation performance data for the worst-case scenario. Since the rst output voltage, Vo1 , is always tightly controlled by the PWM controller, only variations in the second output voltage, Vo2 , are regulated by the SSPR in Table 3. When the Vo1 load is maximum and the Vo2 load is zero, the regulation of Vo2 deteriorates drastically. The actual output voltage shows 150% increase against the 24 V reference for Vo2 under these conditions. The proposed SSPR suppressed this non-feedback controlled output voltage to under 25 V. Thus, the SSPR can regulate its output voltage to within 4%. Figs. 10a and b show the output voltage and current waveforms of the SSPR in the hard and soft turn-on cases. From (31) and (32), larger values of R6 and C3 will result in a long turn-on time duration. Without the soft turn-on function of the SSPR, there is a high is current spike up to 28 A. In addition, the voltage uctuation of Vo1 and the overshoot of Vo2 are shown. The abnormal current spike caused by the hard turn-on of the SSPRs MOSFET inuences the regulation of Vo1 since this disturbance can be transferred to another output channel through the transformer. However, the current spike is limited to 15 A by the soft turn-on function of the SSPR, as shown in Fig. 10b, and no uctuation and/or overshoot occurs on the output voltages.
Table 2
Standby power consumption Burst mode with SSPR No load 0.45 W Standby 0.86 W

Active clamp No load 2.65 W Standby 3.04 W

Table 3

Cross-regulation performance Load conditions 5 V/0 A, 24 V/4 A 5 V/3 A, 24 V/0 A 36.2 V 24.9 V

Output voltage (Vr2 24 V)

Fig. 9 Voltage and current waveforms under standby mode

a Active clamp operation case b Burst mode operation case with active clamp turned-off IET Power Electron., 2011, Vol. 4, Iss. 9, pp. 10581067 doi: 10.1049/iet-pel.2010.0363

without SSPR with SSPR

22.8 V 22.7 V

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Division of SAMSUNG Electronics Co., Ltd, and by the support of an NPRP grant from the Qatar National Research Fund.

References

Fig. 10 Voltage and current waveforms of the SSPR

a Without the soft turn-on function b With the soft turn-on function

Conclusions

This work proposes control schemes for an active clamp switch and a SSPR for multiple output yback converters. The active clamp circuit is adopted to reduce the voltage stress on the main power switch and recycle leakage energy to increase power conversion efciency in the mid to highload ranges. The active clamp switch is turned off during burst-mode operation to decrease the converters switching and conduction losses in standby mode. The proposed SSPR improves the cross-regulation performance and prevents energy leakage from the unused output channel. Soft turn-on of the SSPR is employed to reduce output voltage distortions and inrush current stress of the SSPRs series MOSFET. The prototype 110 W converter consumed only 0.45 and 0.86 W in the no load and standby modes, respectively. The second output voltage was regulated to within 4% perturbation. A 54% reduction in the SSPRs MOSFET current stress was achieved without output voltage distortions. Finally, the conduction loss caused by the SSPR was compensated using the active clamping operation in the mid to full-load ranges, and the proposed converter showed 3.3% efciency improvement at the rated load.

Acknowledgment

This work was made possible by the advanced research project The Standardisation of Next Generation SMPSs for Laser Printers, which was supported by the Digital Printing
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