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PERI INSTITUTE OF TECCHNOLOGY

MANNIVAKKAM, CHENNAI-48.
( DEPARTMENT OF ECE )

CONTINUOUS ASSESSMENT TEST - II
AP9212 ADVANCED DIGITAL SYSTEM DESIGN

Class: I M.E. (Applied Electronics) Date: 11-12-12
Semester: 01 Duration: 3 Hrs.
0
Answer ALL Questions

PART-A (10 X 2 = 20)

1. What are the two common types of faults that
occur in digital circuits?
2. State the conditions for faults to be equivalent and
for faults to be redundant.
3. What is the need for self-test in Digital System?
4. State any two properties of Boolean difference.
5. Define MTBF.
6. What is propagation D-cuts?
7. Give an example for the process statement.
8. What is a Test Bench?
9. Write a VHDL code for a 2 1 multiplexer using
data flow modeling.
10. What are named and positional associations in
structural modeling?


PART - B (5 X 16 = 80)

11. (a) Explain the procedure for designing fault-
secure PLA with suitable example. (16)

OR

(b) i) Explain how the Boolean difference method
is used for test generation with example. (08)

ii) Derive the test vector to detect the stuck-at-0
fault at line 3 of the following logic circuit using path
sensitization method. (08)




12. (a) Explain about BIST. (16)

OR

(b) Explain the path sensitization method. Derive
the test vectors to detect the following stuck-at-faults in
the given circuit : line a s-a-0, line a s-a-1, line f s-a-1,
line w s-a-1. (16)



13. (a) Using structural modeling write a VHDL for a
4 bit shift register. Also write a test bench for it. (16)

OR

(b) (i) Discuss the test generation using any
programmable devices. (08)

(ii) Explain about fault table method with example.
(08)

14. (a) i) Explain structural modeling with a suitable
example. (08)
ii) Explain behavioral modeling with suitable example.
(08)

OR

(b) Design a simple Microprocessor using VHDL.
(16)

15. (a) Write the VHDL code for 3x3 multiplier and test
bench to test its functionality. (16)

OR

(b) Write a VHDL code for the following circuits:
i) 1 : 8 Demultiplexer (06)
ii) What is a generate statement? Write the VHDL code
for 4-bit parallel adder using generate statement. (10)