Lesson 18 Finite State Machine (FSM) with VHDL

1. Overview of FSM Recall that FSM is used to model a sequential logic circuit. A sequential logic circuit has three main parts: 1. Present state of the system 2. Next state logic 3. Output logic The states of the system are represented by flip-flops (or registers). Both next state logic and output logic are entirely combinational logic. A simple block diagram for a state machine is shown in Fig. 1 which contains a Present State Logic section, Present State section, and an Output Logic section.
Next State Present State

Inputs

Next State Logic

Present State (Register)

Output Logic

Outputs

Fig. 1. Block diagram of a state machine.

2. FSM with VHDL We will now introduce a VHDL template to implement a state machine based on the model shown in Fig. 1. The VHDL file will include 3 main sections: Present State section: o The function of this section is to assign the next state to the present state at the active clock edge. o An asynchronous reset signal should be included to initialize the system to the default first state of the system. o This section is implemented with sequential (behavioral) VHDL code with a PROCESS. Next State Logic section: o The function of this section is to establish the next state of the system. o This section is implemented with sequential (behavioral) VHDL code with a PROCESS.
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Output Logic section: o The function of this section is to generate the outputs of the system. o This section is implemented with concurrent VHDL code with conditional assignment statements.

Example: Implement the following ASM diagram using VHDL.

Input: x Output: z

Fig. 2. ASM diagram example 1.

VHDL code:

3. Implementing Digital Filters with VHDL When data is transmitted, a certain amount of noise is mixed with the actual digital signals. For applications that require accurate values from digital inputs (e.g. obstacle avoidance robot lab), it is necessary to incorporate digital filters into the circuits to remove noise from the input signals. One of the simplest ways to implement such a filter is to use a counter to determine if the input signals have been continuously active for a fixed period of time. An example of the noisy input x of the system is depicted in Fig. 3. A counter is incremented every clock cycle if the input x is active (1 in this example); else it is reset to 0. When the counter reaches a fixed value, it is considered stable and a new signal called filtered_x is set to the active state (1 in this case) as shown in Fig. 3. The filtered_x is reset to 0 if the actual input x signal is 0. The filtered_x signal is then used in the state machine instead of the actual input x signal. The digital filter is used to generate a more stable input before it is fed to the Next State Logic and the Output Logic section of the state machine as shown in Fig. 4.

Fig. 3. Noisy input and filtered input.

Filtered Inputs

Next State

Present State

Inputs

Digital Filter

Next State Logic

Present State

Output Logic

Outputs

Fig. 4. Block diagram of a state machine with a digital filter.

VHDL code (ASM shown in Fig. 2, with a digital filter):

The Present State section is the same. The Output Logic section is the same since this is a Moore state machine.

A digital filter is used to generate more stable signal (filtered_x) based on the input signal (x):

The filtered signal is then used in the Next State Logic section:

4. FSM with Time Delay Design a sequential system with one input, x, and a 2-bit output z(1:0). The circuit outputs the sequence: 1, 2, 3, 1, 2, . when x = 0 1, 3, 2, 1, 3, . when x = 1 In addition, the circuit should behave based on the following characteristics: Number 1 (012) should be outputted for 1 second. Number 2 (102) should be outputted for 2 seconds.
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Number 3 (112) should be outputted for 3 seconds. One asynchronous, active high reset signal that puts the system in the initial state (number 1). The system is operated with a 5 Hz clock signal.

The state diagram of the system is (without timing information).

Input: x Output: z(1:0)

S0 01 0

0 1 1 S2 11 0
Fig. 5. State diagram example 2.

S1 10

For timing consideration, we will use a counter to determine the delay periods. The clock frequency is 5 Hz, so the clock period is 200ms. The relationship between time delay and the corresponding count value is summarized in the table below.
State 1 2 3 Delay 1 second 2 seconds 3 seconds Count Value

The time delay for each state now can be represented by CONSTANTs in VHDL code. VHDL code:

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