CH 02

Chapter 2 Fault Modeling
Jin-Fu Li
Advanced Reliable Systems (ARES) Lab.
Department of Electrical Engineering
National Central University
Jungli, Taiwan
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
Why Model Faults?
Fault Models (Faults)
Test, Test Set, and Testing
Fault Collapsing & Test Compaction
Outline
Test Process
The testing problem
Given a set of faults in the circuit under test (or
device under test), how do we obtain a certain
(small) number of test patterns which guarantees a
certain (high) fault coverage?
Test process
What faults to test? (fault modeling)
How are test pattern obtained? (test pattern
generation)
How is test quality (fault coverage) measured?
(fault simulation)?
How are test vectors applied and results evaluated?
(ATE/ BI ST)
Defect categories
Random defects, which are independent of designs
and processes
Systematic defects, which depend on designs and
processes used for manufacturing
For example, random defects might be caused by
random particles scattered on a wafer during
manufacturing
Defect Categories
Logical Fault Models
Systematic defects might be caused by process
variations, signal integrity, and design integrity
issues
It is possible both random and systematic defects
could happen on a single die
With the continuous shrinking of feature sizes,
somewhere below the 180nm technology node,
system defects have a larger impact on yield than
random defects
Logical faults
Logical faults represent the physical defects on the
behaviors of the systems
Why Model Faults
I/O function tests inadequate for manufacturing
(functionality versus component and
interconnection testing)
Real defects (often mechanical) too numerous
and often not analyzable
A fault model identifies targets for testing
A fault model makes analysis possible
Effectiveness measurable by experiments
Fault Nature
Logical fault
One that causes the logic function of a circuit element
to be changed to some other function
Parametric fault
One that alters the magnitude of a circuit parameter,
causing a change in some factor such as resistance,
capacitance, current, etc.
Delay fault
One that relates to circuit delays such as slow gates,
usually affecting the timing of the circuit, which may
cause hazards, or performance degradation, etc.
Fault Duration
Permanent fault
A lasting fault that is continuous and stable, whose nature
does not change before, during, and after testing. E.g., a
broken wire, an incorrect bonding, etc.
A.k.a hard fault or solid fault
Temporary fault
A fault that is present only part of the time, occurring at
random moments and affecting the system for finite, but
unknown, intervals of time
Transition fault
Caused by environmental conditions, e.g., cosmic rays, alpha-
particle, etc. A.k.a. soft error in RAMs
Intermittent fault
Caused by non-enviornmental conditions, e.g., marginal
values of component parameters, wear-out, or critical timing
Single Stuck-At Fault
Single (line) stuck-at fault
The given line has a constant value (0/1)
independent of other signal values in the circuit
Properties
Only one line is faulty
The faulty line is permanently set to 0 or 1
The fault can be at an input or output of a gate
Simple logical model is independent of technology
details
It reduces the complexity of fault-detection
algorithms
One stuck-at fault can model more than one
kind of defect
A circuit with single stuck-at fault
Single Stuck-At Fault Example
Output
Shorted
to 1
I N
OUT
GROUND
POWER
s/1
1
1
1
0
0 (1)
Number of Single Stuck-At Faults
Number of fault sites in a Boolean gate circuit
#PI + #gates + #(fanout branches)
Example: XOR circuit has 12 fault sites ( )
and 24 single stuck-at faults
a
b
c
d
e
f
1
0
g
h
i
1
s/0
j
k
z
0(1)
1(0)
1
Test pattern (vector) for h s/0 fault
Good circuit value
Faulty circuit value
Multiple Stuck-At Faults
Multiple stuck-at fault
Several single stuck-at faults occur at the same
time
Multiple stuck-at faults are usually not
considered in practice because of two reasons
The number of multiple stuck-at faults in a circuit
with k lines is 3
K
-1, which is too large a number
even for circuits of moderate size
Tests for single stuck-at faults are known to cover a
very high percentage (greater than 99.6%) of
multiple stuck-at faults when the circuit is large and
has several outputs
Bridging Faults
Bridging fault
Two or more normally distinct points (lines) are
shorted together
Two types of bridging faults
Input bridging
Can form wired logic or voting model
Feedback (input-to-output) bridging
Can introduce feedback
Can cause oscillation or latching (additional memory)
F y
x
1
x
2
x
n
F y
x
1
x
2
x
n
F y
x
1
x
2
x
n
Input bridging
feedback bridging
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU
Bridging Faults
A
S
B
S
A
D
B
D
A dominates B
A
S
B
S
A
D
B
D
B dominates A
A
S
B
S
A
D
B
D
source
destination
bridging fault
A
D
B
D
A
S
B
S
Wired- AND
A
S
B
S
A
D
B
D
Wired- OR
A
D
B
D
A
S
B
S
A dominate- AND B
B
S
A
D
A
S
B
D
A dominate- OR B
A
D
B
D
A
S
B
S
A
S
A
D
B
D
B
S
B dominate- AND A B dominate- OR A
Pattern-Sensitive Faults
Pattern-sensitive fault
The presence of a faulty signal depends on signal
values of nearby points
Most common in DRAM (dynamic random access
memory)
Coupling fault
Pattern sensitivity between a pair of cells
0
0
0
0
0
0 0
0
0 0
0
0
0
a
b c
a=b=0, c=0
a=b=1, c=1
Single Cell Fault
Cells can have any implementation
All possible (combinational) cell faults are
allowed; truth table can change in any way
C-testability: constant number of test patterns,
independent of circuit size (Ripple-carry adder
needs only 8 test patterns for all single stuck-
at faults)
Source: K. Chakrabarty
FA
x
1
y
1
z
1
c
0
FA
x
2
y
2
z
2
FA
x
3
y
3
z
3
FA
x
4
y
4
z
4
c
4
Transistor Faults
MOS transistor is considered an ideal switch
and two types of faults are modeled
Stuck- open -- a single transistor is permanently
stuck in the open state
Turn the circuit into a sequential one
Need a sequence of at least 2 tests to detect a single
fault
Unique to CMOS circuits
Stuck- on -- a single transistor is permanently
shorted irrespective of its gate voltage
Detection of a stuck-open fault requires two
vectors
Detection of a stuck-on fault requires the
measurement of quiescent current (I
DDQ
)
Transistor Stuck-Open Fault
Example:
Two-vector stuck-open test
can be constructed by
ordering two stuck-at tests
A
B
V
DD
C
pMOS
nMOS
Stuck-open
1
0
0
0
0 1(Z)
Good circuit states
Faulty circuit states
Vector 1: test for A s/0
(Initialization vector)
Vector 2 (test for A s/1)
Test Stuck-On Fault Using I
DDQ
Example:
A
B
V
DD
C
pMOS
nMOS
Stuck-on
1
0
0 (X)
Good circuit state
Faulty circuit state
Test vector for A s/0
I
DDQ
path in
faulty circuit
I
DDQ
Test in Nano-scale Era
Major problem: may result in unacceptable
yield loss
I
DDQ
density function
Density
Mean of fault-free
current
Mean of faulty
current
Crosspoint Fault
A PLA has a device (diode or transistor) at
every crosspoint in the AND and OR arrays.
The connection of each transistor is
programmed to realize the desired logic
A crosspoint fault can be caused by an extra
or a missing device
Z=X
1
X
2
+X
1
X
2
X
1
X
1
X
2
X
2
AND array
OR array
o
2 1
x x Z =
o
|
2 2 1
x x x Z + =
|
Delay Fault
Delay fault
Propagation delays along a path (gate) fall outside
the desired limits.
Two types of delay faults: path delay fault or gate
delay fault
Example:
X
1
X
2
X
3
0 0
1 0
1 1
Z=X
1
X
2
+X
2
X
3
Transition Delay Fault
Transition delay fault
A gate output may be slow-to-rise or slow-to-fall and
that this time is longer than a predefined level
If the delay fault is large enough, the transition
delay fault behaves as a SAF and can be modeled
using that method
The primary weakness of transition delay
fault
Two pattern sequences for initialization and
transition detection are needed
The minimum achievable delay fault size is difficult
to determine because of timing hazards.
Consequently, a whole mission clock cycle is usually
used
Crosstalk Defects
Wire aspect scaling with technology
Capacitive crosstalk noise results from
parasitic coupling between two signal nets
[Source: S.-T. Zachariah, DATE03]
Maximal Aggressor Fault Model
Y
1
Y
i-1
Y
i
Y
i+1
Y
N
0
Victim
1
Victim
Victim
Victim
Y
1
Y
i-1
Y
i
Y
i+1
Y
N
Y
1
Y
i-1
Y
i
Y
i+1
Y
N
Y
1
Y
i-1
Y
i
Y
i+1
Y
N
Victim Victim
Victim
Victim
Positive glitch Negative glitch Slow to fall Slow to rise
Test & Test Set
A test for a fault in a circuit C is an input
combination for which the output(s) of C is
different when is present than when it is not.
A.k.a. test pattern or test vector
X detect then
A test set for a class of faults A is a set of
tests T such that and detects
The test set for a fault is
For example,
o
o 1 ) ( ) ( = X f X f
o
o T t A e - e , o
t
o
o o
f f T =
X
1
X
2
X
3
X
4
f=X
1
X
2
+X
3
X
4
s/0
} 1011 , 0111 , 0011 {
) (
4 3 2 4 3 1
2 1 4 3 2 1
=
+ =
+ =
=
X X X X X X
X X X X X X
f f T
o o
o
Testing & Diagnosis
Testing is a process which includes test
pattern generation, test pattern application,
and output evaluation.
Fault detection tells whether a circuit is
fault-free or not
Fault location provides the location of the
detected fault
Fault diagnosis provides the location and the
type of the detected fault
The input X distinguishes a fault from another
fault iff , i.e.,
o
|
1 ) ( ) ( = X f X f
| o
) ( ) ( X f X f
| o
=
Testing & Diagnosis
Example:
C
a/0
and C
c/0
are detected by the test pattern
(1,0)
If we apply two test patterns: (1,0) & (0, 1)
Two corresponding outputs are faultyC
c/0
Only the output with respect to the input (1,0) is
faultyC
a/0
a
b
c
c
a/0
a b c
0 0 0
0 1 1
1 0 1
1 1 1
c
a/1
c
b/0
c
b/1
c
c/0
c
c/1
0
1
0
1
1
1
1
0
1
0
1
0
0 1
0
0
1
1
1
1
1
1
1
1
Fault Collapsing
To generate tests for digital circuits, the test
tools are provided with a circuit description, a
netlist. The tool then creates a list of all faults
(fault list) to be detected
For large circuits, the list can be quite long. It
is thus beneficial to minimize the list whenever
possible
Some faults may be detected by the same test
patterns. Therefore, only one of these faults
needs to be included in the fault list
Fault collapsing can reduce the size of fault list
with two concepts: equivalence and
dominance
Equivalent Fault Collapsing
Definition
Two faults are called equivalent if every pattern
that detects one of the faults also detects the other.
That is, their test sets, T
1
and T
2
, are identical:
and
Example:
Summary
AND gate: all s/0 faults are equivalent
OR gate: all s/1 faults are equivalent
For an n-input gate, only n+2 faults need to be
considered with equivalence fault collapsing
C
A
B
Original fault list={A/0, A/1, B/0, B/1, C/0, C/1}
Therefore, reduced fault list=
{A/1, B/1, C/1, (C/0 or A/0 or B/0)}
But A/0, B/0, and C/0 are equivalent
Dominance Fault Collapsing
Definition
A fault, f
1
, dominates another fault, f
2
, if the test
set of the latter, T
2
, is a subset of the test set of the
former, T
1
; that is, . Any test pattern that
detects f
2
will also detect f
1
. Therefore, f
2
implies f
1
and it is sufficient to include f
2
in the fault list
Consider a two-input (A and B) AND gate, a test
pattern for the S/1 fault on any of the inputs
detects S/1 fault on the output (C). Then C/1 can
be dropped from the fault list. Therefore, the fault
list is reduced to {A/0,A/1,B/1}
Summary
For an n-input AND gate, dominates
For an n-input OR gate, dominates
1 2
T T _
1 /
1 + n
l
0 /
1 + n
l
i l
i
, 1 /
i l
i
, 0 /
Collapsing by Fault Diagrams
Represent each line x by a pair of circles: the
upper circle stands for x/1, and the lower circle for
x/0
Two circles are connected by an edge if they are
equivalent
Each net on the diagram represents a single fault
equivalence class
&
a
b
c
a/1
a/0
b/1
b/0
c/1
c/0
{a/0,b/0,c/1}
{a/1}
{b/1}
{c/0}
Fault equivalent diagrams for primitive logic gates
For example
a
c
e
&
AND OR NOR NOT
&
I
b
d
f
a
c
e
b
d
f
6 equivalent classes (6 tests)
Add directed arcs from the dominating faults
toward the dominated faults
For fanouts, view the stem and branch as a
separate line. Direction of dominance is opposite
that of the gates
AND OR
NOR NAND
Equivalence
network
Two tests
Example
a
b
c
&
&
|
d
e
f
g
h
a
b
c
d
e
f
g
h
16 single faults
10 equivalent classes
6 tests
Test Compaction
Equivalence fault collapsing + dominance fault
collapsing
Only n+1 faults on any n-input gate need be
considered
Definition
Test compaction refers to the process of reducing
the number of test patterns in a test set without
reducing its fault coverage
Equivalence fault collapsing and dominance fault
collapsing can be used to aid test compaction
Theorem
In a fanout-free combinational circuit, any test set
which detects all stuck faults on primary inputs will
detect all stuck at faults
Test Compaction
Definition
The set of all primary inputs and all fanout branches
are called checkpoints of the circuit
Example,
Theorem
In a combinational circuit, any test set which
detects all single (multiple) stuck faults on
checkpoints will detect all single (multiple) stuck
faults.
Primary inputs
Primary outputs
stem
branches
Fault Masking
Let T
X
be the test that detects a fault X . We
say that a fault Y functionally masks the fault
X iff the multiple fault {Y, G} is not detected
by any test in T
X
E.g., as the following figure shows, the test
011 is the only test that detects the fault c/0.
The same test does not detect the multiple
fault {c/0, a/1}. Thus a/1 masks c/0
&
&
&
a
b
c
0
1
1/0
1
0
0/1
Basic fault models
Single stuck-at fault
Bridging fault
Pattern-sensitive fault
Delay fault

Fault modeling can simplify the complexity of
testing
Test compaction is usually used to reduce the
number of test patterns
Summary

CH 02

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

CH 02

Загружено:

Авторское право:

Доступные форматы

Chapter 2 Fault Modeling

Вам также может понравиться