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FACULTY OF ENGINEERING AND ARCHITECTURE

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

ASIC DIGITAL CELL LIBRARY DEVELOPMENT

A GRADUATION PROJECT

submitted by

ENES MAHMUT OUZHAN TRK

in partial fulllment of the requirements for the degree of

BACHELOR OF SCIENCE

AUGUST 2012

Program: Electrical and Electronics Engineering

ASIC DIGITAL CELL LIBRARY DEVELOPMENT

A GRADUATION PROJECT

by

ENES MAHMUT OUZHAN TRK

submitted to the Department of Electrical and Electronics Engineering of


OKAN UNIVERSITY

in partial fulllment of the requirements for the degree of


BACHELOR OF SCIENCE

Approved by:

Asst. Prof. Burak Kelleci


Supervisor

AUGUST 2012

Program: Electrical and Electronics Engineering

ii

ABSTRACT
ASIC DIGITAL CELL LIBRARY DEVELOPMENT

An application-specic integrated circuit, or ASIC, is an integrated circuit (IC)


customized for a specic use, rather than general-purpose use. As chip sizes have
shrunk and design tools improved over the years, the maximum number of gates
in an ASIC has grown from 5,000 gates to over 100 million. In the mid 1980s, a
designer would choose an ASIC manufacturer and implement his design using the
design tools available from the manufacturer.

A solution to this problem, which

also produced a much higher density device, was the implementation of standard cells. Owing to standard cells evolution, manufacturers can create functional
blocks with known electrical characteristics. In order to handle this kind of development, logic synthesis tools became available by the late 1990s. In this thesis, the
objectives are creation of standard cells 0.35

Austria Microsystems process.

Developed synthesis library is compatible with Cadence RTL Compiler.

Keywords: Logic Synthesis, ASIC, Application Specic Integrated Circuit, Digital


Cell Library

iii

KISA ZET
ASIC SAYISAL HCRE KTPHANES GELTRLMES

Uygulamaya ynelik ykseltilmi devreler, yani ASIC, genel-amal kullanmlarn


yerine zel uygulamalar da kullanlmak zere retilmi ykseltilmi devrelerdir.
Yllar getike, ip boyutlar klm ve tasarm aralar daha ok gelimitir. Bu
sayede ASIC'in fonksiyonellii maksimum dzeye ulam, ve yaklak 5000 kapl
devrelerden 100 milyon kapl devrelere kadar artmtr.

1980'lerin ortalarnda,

bir tasarmcnn tasarmn gerekletirebilmesi iin, kendisine bir retici rma


semesi ve retici rmann kendisine salam olduu tasarm aralarn kullanmas
gerekiyordu, bu probleme zm olarak, standart hcreler gelitirildi.

Standart

hcrelerin gelimesi sayesinde, reticiler elektriksel karakterleri belirli olan fonksiyonel bloklar retebildiler. Byle bir gelimeyi daha kullanlabilir hale getirmek iin,
1990 larn sonunda Mantk Sentez Aralar gelitirildi. Bu tezde hedeenen standart hcreler oluturmak ve saysal hcre teknolo ji ktphanesini gelitirmektir.
Bu ilemler sresince Austria Microsystems tarafndan hazrlanm standart hcre
ktphanesini kullanan, Cadence mantk sentez arac kullanlmtr.

Anahtar Kelimeler: Lojik Sentez, ASIC, Uygulamaya Ynelik Tmdevre, Saysal


Hcre Ktphanesi

iv

To my Family...

ACKNOWLEDGMENTS
I want to thank my supervisor Assistant Professor Burak KELLEC who inspired
me to be a researcher in the rst place and also for his endless eorts which
enlightened and encouraged me to be an Electronics Engineer.

I also want to

thank to Dean Professor Ramazan Nejat TUNAY who provided the possibility
of using the Electronics Communication Laboratory for 7/24.

I would like to

thank all my colleagues Berkin Ayberk, Ergn Cmert, lker in, Umut nal for
their supports and strong friendship. My deepest gratitude goes to my family for
their never-ending love and support throughout my life.
impossible without their participation.

This success is simply

vi

TABLE OF CONTENTS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . .

LIST OF FIGURES

ACRONYMS

1.

LOGIC SYNTHESIS

1.1. Brief History of the Logic Synthesis

. . . . . . . . . . . . . . .

1.2. What is Logic Synthesis . . . . . . . . . . . . . . . . . . . . . .

1.3. Impact of the Logic Synthesis

. . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

1.4.1.

RTL Description . . . . . . . . . . . . . . . . . . . . . .

1.4.2.

Translation . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.3.

Logic Optimization

1.4.4.

Technology Mapping and Optimization

1.4.5.

Technology Library

1.4. Synthesis Design Flow

2.

. . . . . . . . . . . . . . . . . . . .
. . . . . . . . .

. . . . . . . . . . . . . . . . . . . .

1.4.6.

Design Constraints . . . . . . . . . . . . . . . . . . . . .

1.4.7.

Optimized Gate-Level Description

. . . . . . . . . . . .

1.5. Outcomes of the Logic Synthesis . . . . . . . . . . . . . . . . .

. . . . . . .

. . . . . . . . . . . . . . . . . .

IMPLEMENTATION OF FINITE STATE MACHINE

2.1. Introduction to Cadence EDA

2.2. Starting Cadence and Making a new Working Library


2.3. Creating A New Cell
2.3.1.

. . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . .

2.4. Verilog Simulation . . . . . . . . . . . . . . . . . . . . . . . . .

10

Creating the RTL Description of the Cell

2.4.1.

Verilog XL Virtuoso . . . . . . . . . . . . . . . . . . . .

11

2.4.2.

SimVision Waveform Viewer

. . . . . . . . . . . . . . .

11

2.5. Cadence RTL Compiler . . . . . . . . . . . . . . . . . . . . . .

11

2.5.1.

3.

. . . . .

Scripted Synthesis

. . . . . . . . . . . . . . . . . . . . .

12

. . . . . . . . . . . . . . . . . . . .

17

. . . . . . . . . . . . . . . . . . . . . . .

17

CELL CHARACTERIZATION

3.1. Cell Characterization


3.1.1.

Liberty File Format

. . . . . . . . . . . . . . . . . . . .

3.2. Cell Characterization with ELC

. . . . . . . . . . . . . . . . .

17
19

3.2.1.

Generating ELC Netlist . . . . . . . . . . . . . . . . . .

19

3.2.2.

Best, Typical and Worst Case Characterization . . . . .

28

vii

. . . . . . . . . . . . . . . . . .

29

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31

APPENDIX A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32

APPENDIX B

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

33

APPENDIX C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

34

APPENDIX D

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

36

APPENDIX E

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

38

APPENDIX F

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39

APPENDIX G

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

42

APPENDIX H

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

46

APPENDIX I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

47

APPENDIX J

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48

APPENDIX K

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

72

4.

SUMMARY AND CONCLUSION

REFERENCES

VITA

viii

LIST OF FIGURES
. . . . . . . . . . . . . . . . . . .

10

. . . . . . . . . . . . . . . . .

12

. . . . . . . . . . . . . . . .

13

Verilog XL Virtuoso Step 1

. . . . . . . . . . . . . . . . . . . . . .

14

2.5.

Verilog XL Virtuoso Step 2

. . . . . . . . . . . . . . . . . . . . . .

15

2.6.

SimVision Waveforms

. . . . . . . . . . . . . . . . . . . . . . . . .

15

2.7.

RTL Compiler .tcl code

. . . . . . . . . . . . . . . . . . . . . . . .

16

3.1.

Symbol View of Inverter

. . . . . . . . . . . . . . . . . . . . . . . .

19

3.2.

Symbol View of D Flip-Flop

. . . . . . . . . . . . . . . . . . . . . .

20

3.3.

Symbol View of NAND

. . . . . . . . . . . . . . . . . . . . . . . .

20

3.4.

Symbol View of NOR

. . . . . . . . . . . . . . . . . . . . . . . . .

21

3.5.

Schematic View of Inverter

. . . . . . . . . . . . . . . . . . . . . .

21

3.6.

Schematic View of D Flip-Flop

. . . . . . . . . . . . . . . . . . . .

22

3.7.

Schematic View of NAND

. . . . . . . . . . . . . . . . . . . . . . .

22

3.8.

Schematic View of NOR

. . . . . . . . . . . . . . . . . . . . . . . .

23

3.9.

Layout View of Inverter

. . . . . . . . . . . . . . . . . . . . . . . .

23

3.10.

Layout View of D Flip-Flop

. . . . . . . . . . . . . . . . . . . . . .

24

3.11.

Layout View of NAND

. . . . . . . . . . . . . . . . . . . . . . . . .

24

3.12.

Layout View of NOR

. . . . . . . . . . . . . . . . . . . . . . . . . .

25

3.13.

AV Extracted View of Inverter

. . . . . . . . . . . . . . . . . . . .

25

3.14.

AV Extracted View of D Flip-Flop

. . . . . . . . . . . . . . . . . .

26

3.15.

AV Extracted View of NAND

. . . . . . . . . . . . . . . . . . . . .

26

2.1.

Verilog code of the example FSM

2.2.

Verilog Testbench for FSM Example

2.3.

Verilog XL Virtuoso for FSM Example

2.4.

ix

3.16.

AV Extracted View of NOR

. . . . . . . . . . . . . . . . . . . . . .

27

ACRONYMS
ASIC
IC

Application Specic Integrated Circuit

Integrated Circuit

CMOS
RTL

Complementary Metal Oxide Semiconductor

Register Transfer Level

HDL

Hardware Description Language

CAD

Computer Aided Design

MUX
AMS

Multiplexer

Austria Micro Systems

HIT-KIT
DRC
LVS
FSM
ELC

Multiplexer

Design Rule Check

Layout Versus Schematic

Finite State Machine

Encounter Library Characterizer

I. LOGIC SYNTHESIS

1.1.

Brief History of the Logic Synthesis

Digital circuit design has evolved rapidly over the last 35 years.

The earliest

digital circuits were designed with vacuum tubes and transistors. Integrated circuits were invented where logic gates were placed on a single chip. In 1958, Jack
Kilby who was an American engineer took part in the realization of the rst integrated circuit while working at Texas Instruments (TI). The rst integrated
circuits contained only a few transistors called small-scale integration (SSI). SSI
Digital circuits containing transistors numbering in the tens which can provide
few logic gates.

As technologies became sophisticated by years, designers were

able to place circuits with hundreds of gates on a chip which is called Medium
Scale Integration (MSI).With the advantage of the Large Scale Integration (LSI);
designers could put thousands of gates on a single chip. At this point, design synthesis processes started getting very complicated, and designers felt the need to
automate these processes.

Electronic Design Automation (EDA) Techniques be-

gan to evolve. Chip designers began to use circuit and logic simulation techniques
to verify the functionality of building blocks of the order of about 100 transistors.
The circuits were still tested on the breadboard, and the layout was done on paper
or by hand on a graphic computer terminal. With the advent of VLSI (Very Large
Scale Integration) technology, designers could design single chips with more than
100,000 transistors. Because of the complexity of these circuits, it was not possible to verify these circuits on a breadboard. Computer aided techniques became
critical for verication and design of VLSI digital circuits.

Computer programs

to do automatic placement and routing of circuit layouts also became popular.


The designers were now building gate-level digital circuits manually on graphic
terminals.

They would build small building blocks and then derive higher-level

blocks from them. This process would continue until they had built the top-level
block. Logic synthesis tools came into existence to verify the functionality of these
circuits before they were fabricated on chip. In my graduation pro ject, I examine
all these chip creation process.

1.2.

What is Logic Synthesis

Simply speaking, logic synthesis is the process of converting a high-level design


into optimized gate-level presentation by using a given standard cell library. This
process uses standard cell library (technology library) which includes basic cells
and gates such as AND, NAND, OR, NOR and more complex cells like muxes,
half or full adders and ip-ops. Before the existence of the CAD Logic Synthesis
Tools, everything was considered and done by the designers mind.

Firstly, de-

signer must understand the architectural presentation, which requires considering


design constraints such as timing, area and power. The designer would partition
the design into level-blocks on a piece of paper or a computer terminal, and describe the functionality of the circuit.

Then by using the standard cell library,

each block must be implemented on a hand-drawn schematic. At last, in order to


obtain the optimized gate-level representation, design needs several time, power
and area iterations to meet all the design constraints. The handy side of the CAD
logic synthesis tool is to convert the high-level description to gate-level conversion.

Instead of performing logic synthesis manually, designers can concentrate

on optimizing the high-level design description, architectural trade-os and design


constraints. Another innovation of the CAD Logic synthesis tool is to simplifying
the description of the high-level design. Instead of drawing the high-level design
on a paper, designers can use a special language to dene the design in terms
of HDLs.

In my thesis, it is preferred to use Verilog in designs.

Due to auto-

mated logic synthesis a signicant amount of time is gained during the high-level
to gates conversion. This gain allows the designer to give more consideration on

higher level of representation.

1.3.

Impact of the Logic Synthesis

Logic synthesis has evolved the digital design industry by improving productivity
and process duration.

Manual Synthesis has the following disadvantages

In large designs, manual conversion is prone to designers error. Misplacing


of a small gate can cause the redesign of the whole project.

Designer can never be sure of if the design constraints will met or not until
the gate-level implementation is completed and tested.

Most of the time is spent on converting the high-level design into gates.

If the gate-level design did not meet the requirements, designer must turn
all the way back to the redesigning of blocks which consumes time.

To satisfy the what-if scenarios like trying 15ns cycling timing, in a design
that already runs properly at a cycle time of 20ns, requires redesigning of
many blocks.

Timing, area and power dissipation in library cells are specic, any change in
the companys vendor, it means all the circuit designs can possibly change.

CAD Logic Synthesis tools gured out the following problems

High-level design is less prone to the designers error because it is described


with dierent term.

High-level design constraints are less concerning.

Logic synthesis converts

a high-level design to gate-level netlist and ensure that all the constraints

are met. If not, designer should only change the HDL code until the design
satises the required constraints and netlist.

What-if scenarios are easy to verify. The synthesis tool optimizes and resynthesizes the design to get the new level netlist.

High-level designs are prepared without the concern of IC fabrication vendor


changes.

Because the HDL is independent from the standard cell library,

designer simply retargets the logic synthesis tool to the updated technology
library.

1.4.

Synthesis Design Flow

In this section, CAD Logic Synthesis Tools components will be discussed. To fully
utilize the benets of logic synthesis, the designer must understand the ow from
RTL Description to Gate-Level representation.Reference to subsection 1.2.

1.4.1.

RTL Description

The use of structure to control the synthesis process is the main ingredient for
success when writing RTL descriptions. Structure is dened as the way in which
parts are arranged or put together to form a whole, and it is created through
the use of modules and cell instantiation.

The designer should code the RTL

to reect the desired hardware structure.

Why do designers use Verilog HDL

instead of schematic capture?


more productive.

The main reason is to make the logic designer

Quality is also improved because more time can be spent on

logic verication rather than on the detailed gate-level implementation.

And a

more exact and readable design makes it easier for the design to be reused by
other designers.

Optimized functions such as decoders, adders, and multi-bit

multiplexers become building blocks for the desired design.

These functions can

be hand-crafted by the designer and then reused in many places, or they can be

referenced or instantiated from the cell library supplied by vendor. The quality of
the synthesized design can be improved using the following techniques:

Module partitioning

Adding structure

Horizontal partitioning

Adding hierarchy (vertical partitioning)

Performing operations in parallel

Use multiplexers for logic implementation

1.4.2.

Translation

RTL description is converted to an unoptimized intermediate representation by


the logic synthesis tool. The translator basically understands Verilog commands
and interprets them into gates.

In this translation level, design constraints such

as area, timing and power are not considered.

1.4.3.

Logic Optimization

Logic optimization is a part of logic synthesis, and the process of nding an


equivalent representation of the specied logic circuit under one or more specied constraints. Now, the logic is optimized to remove unnecessary logic which is
translated without optimization.

Various Boolean logic optimization techniques

are used. This state is very signicant in logic synthesis and provides an optimized
representation of the design.

1.4.4.

Technology Mapping and Optimization

Technology mapping is the phase of logic synthesis when gates are selected from
a technology library to implement the circuit. Until this step all the design pro-

cesses are independent of a specic technology.

In this step, the logic synthesis

tool takes all the internal representation of RTL to gates, using the cells which are
provided by a specic technology library.
to the desired target technology.

In other words, the design is mapped

Suppose that the designer wants to get his IC

chip fabricated at XYZ Inc. XYZ Inc. has 0.35 micron CMOS technology, which
is called xyz_350 technology. This xyz_350 technology becomes the target technology. Therefore the designer must implement his internal design representation
gates, using the cells from the xyz_350 technology library.
nology mapping.

This is called tech-

Also, the implementation should satisfy the design constraints

such as timing, area and power.

In some cases, in order to achieve best results,

some local optimizations are done to the target libraries. This is called technology
optimization or technology-dependent optimization.

1.4.5.

Technology Library

The technology library contains library cells provided by the vendor.

To build

a technology library, the vendor decides the range of functionality of the cells.
Library can be consisted of basic logic gates or macro cells such as adders, ALUs,
multiplexers and special ip-ops. The library cells are the basic building blocks
that vendor will use for IC fabrication. Physical layouts of library cells are done
rstly.

Then, the area of each cell is computed from the cell lay-out.

Next,

modeling techniques are used to estimate the timing and power characteristics of
each library cell which is called characterization.

Finally, each cell is described

in a format that is understood by the logic synthesis tool.


contains information about the following:

Functionality of the cell

Area of the cell layout

Timing information about the cell

This cell description

Power information about the cell

A collection of these cells is called technology library.

The synthesis tool uses

these cells to implement the design. The quality of results from synthesis tools are
dominated by the variety (functionality) of the cells available in the technology
library. If the choices are limited in the technology library, the synthesis tool cant
do much optimization in order to satisfy the constraints such as timing, area and
power.

1.4.6.

Design Constraints

In general, there is an inverse relationship between area and timing constraints.


For a given technology library, to optimize timing (faster circuits), the design has
to build in parallel, which need to be built larger circuits. To build smaller circuits,
designer must sacrice on circuit speed. This inverse relationship can be seen in
following gure. On top of design constraints, operating environment and physical
factors, such as input and output delays, and loads, will aect the optimization
for the technology library.

1.4.7.

Optimized Gate-Level Description

After the technology mapping is complete, an optimized gate-level netlist is described by using the target technology le components. If the netlist satises the
constraints, the design is ready for nal layout. If not, the designer should modify
the RTL or change the design constraints in order to achieve pure results.

This

process can be iterated until the netlist meets the required constraints. The vendor
will do the layout, do the timing checks to ensure that the circuit meets required
timing, and then fabricate the IC chip for the designer.

1.5.


Outcomes of the Logic Synthesis

Logic synthesis is the process of converting a high-level description of the


design into an optimized, gate-level representation, using the cells in the
technology library.

Computer-Aided Logic Synthesis tools have greatly reduced the design cycle time and improved the productivity.

They allow designers to write

technology-independent, high-level descriptions and produce technology-dependent,


optimized, gate-level netlists.

A logic synthesis tool accepts an RTL description, design constraints and


technology library and produces an optimized gate-level netlist. Translation,
logic optimization, and technology mapping are the internal processes in a
logic synthesis tool and normally invisible to the user.

Accurate specication of design constraints is an important part of logic


synthesis.

II. IMPLEMENTATION OF FINITE STATE


MACHINE

Before the library development, it was a must to understand the designer/s course
during the process. In this chapter a simple Finite State Machine will be implemented via using Cadence.

2.1.

Introduction to Cadence EDA

The Cadence toolset is a complete microchip EDA (Electronic Design Automation) system, which is intended to develop professional, full-scale, mixed-signal microchips. The modules included in the toolset are for schematic entry, design simulation, data analysis, physical layout, and nal verication. The Cadence tools at
our university are the same as those at most every professional mixed-signal microelectronics company in the Turkey and the United States. The strength of the Cadence tools is in its analog design/simulation/layout and mixed-signal verication
and is often used in tandem with other tools for digital design/simulation/layout,
where complete top-level verication is done in the Cadence tools.

2.2.

Starting Cadence and Making a new Working Library

In order to build our own Schematic, Layout, Symbol, Functional and the analogextracted views, it is needed to dene our own library to keep our own circuits
in.

2.3.
2.3.1.

Creating A New Cell


Creating the RTL Description of the Cell

This is the le whose behavior designer would like to synthesize into a circuit.It can
contain purely behavioral code or a mixture of behavioral and structural code.This

10

should be linked to the directory which will be used for running the RTL Compiler.

Fig. 2.1. Verilog code of the example FSM

2.4.

Verilog Simulation

Verilog HDL was traditionally used both as a simulation modeling language and
as a hardware description language. Verilog HDL was heavily used in verication
and simulation for testbenches, test environments, simulation models, and architectural models.

This approach worked well for smaller designs and simpler test

environments.In order to understand the behavior of the created cell it is needed


to be simulated.A testbench code is written and simulated via using Verilog XL
Virtuoso.

11

2.4.1.

Verilog XL Virtuoso

Verilog XL, an interpreted Verilog simulator from Cadence, is the reference simulator for the Verilog-1995 standard. This means that Verilog constructs from later
versions of the standard will not run with this simulator. In this testbench loops
are used to test the nite state machine, and checks every possible case. When the
testbench code is saved, the system would check the Verilog for correct syntax. If
it does not pass the syntax check, it is needed to reopen the testbench and x the
errors.

Once the test bench passes the syntax check and have set up the signals

that designer wanted to record, simulation can run.

This process has two steps,

rst it netlists our design, checks the netlist for errors, and prepares the netlist and
testbench for the simulation.After design passes this step, now interactive mode
is on, this mode runs the testbench on the Composer generated netlist.

2.4.2.

SimVision Waveform Viewer

Waveforms are a good way to get certain types of information from the simulation and a good place for debugging the design.

Every variables behaviors were

observed from the SimVision. Record All Signals option is used for the waveform
viewer and the navigation system to look signals deep inside the circuit to see
where things have started to fail.

2.5.

Cadence RTL Compiler

Now it was time to create a synthesis folder which is the process of taking a behavioral Verilog le and converting it to a structural le using cells from a standard
cell library. In other words, the behavior that is captured by the Verilog program
is synthesized into a circuit that behaves in the same way. The synthesized circuit
is described as a collection of cells from the target cell library.The HDL synthesis
program form Cadence is called RTL Compiler.

12

Fig. 2.2. Verilog Testbench for FSM Example

2.5.1.

Scripted Synthesis

The scripts that drive RTL Compiler are written in Tcl.

The basic steps of the

script are :

Set some parameters that will apply during the synthesis run. In particular,
set where the HDL les are and which target library to use.

Read and analyze the HDL code.

Dene the constraints on the circuit in terms of clock period and input and
output delays.

Synthesize the behavioral code into a circuit (structural code).

13

Fig. 2.3. Verilog XL Virtuoso for FSM Example

Write report les on the timing, power, area, etc., of the resulting circuit.

Write the circuit as structural Verilog le using cells from the target library.

The script rst sets the hdl_search_path and lib_search_path in order to execute the design with the hdl code and technology library.

The directories must

have pure matches in order to synthesize the design correctly. Then the behavioral
Verilog les are listed along with the
that we'd like to synthesized.

basename which is the name of the module

Once the basename FSM_example is dened, the

script reads and elaborates the behavioral Verilog les, and sets the timing information for the clock, inputs and outputs.

At this point a check is run to make

sure that all the important pieces are there.

Finally, the

synthesize

command

does the actual synthesis from behavioral to structural. The -to_mapped switch

14

Fig. 2.4. Verilog XL Virtuoso Step 1

says to use the cells in the target library rather than some generic built-in cells.
Finally, the script writes out the reports and the structural Verilog synthesized
circuit.

15

Fig. 2.5. Verilog XL Virtuoso Step 2

Fig. 2.6. SimVision Waveforms

16

Fig. 2.7. RTL Compiler .tcl code

III. CELL CHARACTERIZATION

3.1.

Cell Characterization

Since now an example of nite state machine is studied and the synthesis design
ow is observed and followed. During implementation of the nite state machine
example, a tutorial is prepared for the students that will use Cadence.

In this

section, a liberty le will be composed for four cells that created for this project.
An inverter, a D Flip-Flop, a NAND and a NOR gates were created by Ergn
Cmert.

Cell characterization is a process of simulating a standard cell with an

analog simulator to extract this information in a way that the other tools can
understand. This process can be applied by using schematic and layout views of
our cells.

The tool will understand the transistor netlist and the layout of the

cells.

3.1.1.

Liberty File Format

There should be a standard format for the synthesis tools to understand all this
characterization data. The most standard format is called
usually uses

.lib

le extension.

liberty

Liberty format in an ASCII le that describes a

cell's characterized data.

/*general syntax of a technology library*/


library(nameoflibrary) {
... /* Library level simple and complex attributes */
... /* Library level group statements */
... /* Default attributes */
... /* Scaling factors for delay calculation */

/* Cell Definitions */

format, which

18

cell (cell_name) {
... /* cell level simple attributes */

/* pin groups within the cell */


pin (pin_name) {
... /* pin level simple attributes */

/* timing group within the pin level */


timing (){
... /* timing level simple attributes */
} /* end of timing */

... /* additional timing groups */


} /* end of pin */

... /* more pin descriptions */


} /* end of cell */
... /* more cells */
} /* end of library */

This level of detail simply describes the overall structure of the le. As it might
be seen, the le is very complex, it contains huge number of special statements
that can describe all sort of parameters relevant to the Cadence Logic Synthesis
tool which uses this format for information about the cells in he standard cells in
library. Each eld has lots of detail that can be added by hand, or details can be
generated by Encounter Library Characterizer.
generating the Liberty le of four gates.

In this thesis ELC was used for

19

3.2.

Cell Characterization with ELC

Encounter Library Characterizer is a tool from Cadence that uses Spectre to characterize cells and produces results in a format that can be converted into

Liberty

format.

3.2.1.

Generating ELC Netlist

ELC requires a netlist of all the cells that would be characterized. These netlists
were generated by Cadence from the schematics. In addition, it needs a transistorlevel schematic view, along with a layout of each cell.
both

The layouts have passed

DRC and LVS, as a result of that an analog-extracted view was created.

Here are the Schematic, Layout, Symbol and the analog-extracted views of an
Inverter, a D Flip-Flop, a NAND and a NOR gates:

Fig. 3.1. Symbol View of Inverter

Firstly, cells that would like to be characterized were created as schematics. They
do not need to be connected, just placing them as an instance in the schematic.
From the Tools menu Analog Environment option is selected and necessary modications that listed below were made

20

Fig. 3.2. Symbol View of D Flip-Flop

Fig. 3.3. Symbol View of NAND

From Setup, Directory/host menu was selected in order to open dialog box.
Simulator was selected as Spectre. This action will force the analog netlister
to use Spectre format when it generates the netlist.

From Setup, Environment menu was selected in order to open dialog box
and add analog-extracted to the front of the Switch View list. This action

21

Fig. 3.4. Symbol View of NOR

Fig. 3.5. Schematic View of Inverter

will tell the netlister to look for the analog-extracted view rst to nd the
transistor netlists for each cell.

Now the netlist was generated and Spectre netlist of the schematic window opened.
This le needed to be hand edited because the netlister from NCSU was nor de-

22

Fig. 3.6. Schematic View of D Flip-Flop

Fig. 3.7. Schematic View of NAND

signed to make perfect ELC les. ELC wants a le that contains subckt denitions
which are the descriptions of each cell as sub-circuit. The subckt le starts with
some control statements, the denes each cell as a subckt, then includes an instance of each of those sub-circuits and nishes some additional control statements
for the simulator. After modifying the .scs le with subckt denitions for the cells

23

Fig. 3.8. Schematic View of NOR

Fig. 3.9. Layout View of Inverter

which were characterized, the ELC was run. The main setup le used by ELC is
called elccfg, this le simply sets up defaults for where the other setup and process
les are.

# Setup stuff

24

Fig. 3.10. Layout View of D Flip-Flop

Fig. 3.11. Layout View of NAND

SETUP = "/home/enes/enes_newcell/elc/setup.ss"
PROCESS = "typical"
SUBCKT = "newcellnetlist.scs"
MODEL = "/home/enes/enes_newcell/elc/cmos53.scs"

25

Fig. 3.12. Layout View of NOR

Fig. 3.13. AV Extracted View of Inverter

This simple elccfg le, points another setup le called setup.ss.

This le denes

a number of controls for the characterization, including denitions for electrical


and temperature parameters for the simulation, default loads and slews for the
tables of performance, and other things of that sort.

The setup.ss le is shown

in Appendix G. Assuming three scripts which contain a package of commands

26

Fig. 3.14. AV Extracted View of D Flip-Flop

Fig. 3.15. AV Extracted View of NAND

that drives ELC. These scripts are used one at a time in sequence, but they
represent three important steps in the process where the designer may need to
stop and x errors. With this les in place, the characterization can be run with
the following steps.

The syntax for the running script called step1 is shown in

Appendix H. This script will open a database called foo to hold data with the

27

Fig. 3.16. AV Extracted View of NOR

ELC command db_open.

The script then sets some ags to control how ELC

works, and uses db_prepare to install a set of transistor models and .scs le with
the subckt descriptions into database.

It also evaluates the transistor networks

to understand what they are, and generates test vectors for characterization.

In

this phase, ELC applies all possible input vectors to the circuit to try to gure
out what it is. The db_gate command prints out what gate thinks your cell is so
that designer can verify that ELC got it right. Finally, db_close closes database.
The step2 script that is shown in Appendix I, starts by opening the database
named foo that was created in step1.
simulation action happens.

The db_spice command is where all the

By using this command the subckt denitions that

supplied in .scs an the test vectors that were derived in step1 to simulate and
extract timing and power numbers using Spectre. Once the step2 was completed,
the characterization data is in the foo database. The results of the step2 gathered
into a le named foo.alf by step3 script. The step3 script is shown in Appendix J.
The .alf le contains all characterization data that was generated by ELC. After
the .alf le was converted into a Liberty format via using laf2lib script, that is the

28

characterized library.

3.2.2.

Best, Typical and Worst Case Characterization

Commercial libraries are almost always characterized for three dierent versions
of cell timings:

best case, typical case and worst case.

These are supposed to

represent three dierent variations on how the circuits are likely to work.

Best

case timings are usually feasible but quite optimistic because the transistors are
predicted to operate in fast region.

Typical case timings are supposed to model

what designer will usually see in the fabricated circuit. The transistor models are
taken from the middle of the performance distribution.

Worst case timings are

taken from the slow end of the performance distribution.

The step1, step2 and

step3 scripts were designed to measure typical timing for the created cells.
Liberty le generated by ELC is shown in Appendix K.

The

IV. SUMMARY AND CONCLUSION

In this work, the Logic Synthesis was studied. Important progresses of the Logic
Synthesis history were discussed, as a result of this, pre and post logic synthesis design were compared. In order to understand the synthesis operation deeply, phases
of the Design Flow were described. By dealing with a great deal of operations, it
gave a chance to gain favor of specializing in Linux Operating Systems. A tutorial
was prepared for guiding the beginners who desire to comprehend the fundamental
properties of Synthesis Flow. An example of Finite State Machine was processed
entirely with all design keystones, tricks and signicant details in a body. To give
more information about this tutorial, the stages are listed above

Learning the basics of Cadence

Creating a New Cell Library

Creating Technology File

Creating Cell View

Creating a Functional View of Cell via Verilog

Composing testbenches via Verilog XL

Simulating the created Cell via Virtuoso

Observing the simulation results via Simvision Waveform Viewer

Creating a script based Synthesis File for launching RTL Compiler

Additionally RC GUI is used for modifying the .tcl le for RTL Compiler

Examining the output reports of the RTL Compiler

30

Using Encounter

Creating First Encounter Input Conguration File

Creating Clocktree File

Creating Encounter Command File

Examining the GDSII View of the Finite State Machine that composed by
Encounter

Using Virtuoso Verilog In and Stream In Options

Examining the Layout View of the Finite State Machine composed by GDSII

Secondly, the digital cell library which is one of the most important components of
the IC design and fabrication, willed to be developed. In order to make the required
developments, the general structure of an Liberty File must be comprehended. An
inverter, a D Flip-Flop, a NAND and a NOR gates were chosen to be optimized
and developed in this thesis. The

Schematic, Layout, Symbol and the analog-

extracted views of an Inverter, a D Flip-Flop, a NAND and a NOR gates created


by Ergn Cmert.
operation.

Cadence has Encounter Library Characterizer tool for this

The gates were processed with the ELC via using the

Layout, Symbol

and the

analog-extracted

views of the cells.

Schematic,

As a result a

Liberty le has generated by Cadence Encounter Library Characterizer.

REFERENCES

[1] Eric Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD
Tools, vol. 1. School of Computing, University of Utah, Addison Wesley, 2009.

[2] Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis,
vol. 2. Sun Microsystems Inc., California, Prentice Hall PTR, 2003.

32

APPENDIX A
VERILOG HDL OF FINITE STATE MACHINE

This is the Verilog HDL code of Finite State Machine.

//Verilog HDL for "HDL_tutorial", "FSM_example" "functional"


module FSM_example (clk, clr, insig, outsig);
input clk, clr, insig;
output outsig;
parameter [1:0] s0=2'b00, s1 = 2'b01, s2=2'b10, s3=2'b11;
reg [1:0] state, next_state;
always @ (posedge clk or negedge clr)
begin
if (clr==0) state=s0;
else state = next_state;
end
always @ (insig or state)
begin
case (state)
s0: if (insig) next_state = s1; else
s1: if (insig) next_state = s2; else
s2: if (insig) next_state = s3; else
s3: if (insig) next_state = s1; else
default: next_state=s0;
endcase
end
assign outsig=((state==s1) || (state==s3));
endmodule

next_state
next_state
next_state
next_state

=
=
=
=

s0;
s1;
s2;
s0;

33

APPENDIX B
VERILOG TESTBENCH FOR FSM EXAMPLE

This is the Verilog Testbench of Finite State Machine.

// Verilog stimulus file.


// Please do not create a module in this file.
// Default verilog stimulus.
initial
begin
clk = 1'b0;
clr = 1'b0;
insig = 1'b0;
#100
#100
#100
#100
#100
#100

clr = 1'b1;
insig = 1'b1;
insig = 1'b0;
insig = 1'b1;
insig = 1'b0;
$finish;

end
always
begin
#10 clk = 1'b0;
#10 clk = 1'b1;
end

34

APPENDIX C
RTL COMPILER SCRIPT OF EXAMPLE FSM

# Script for Cadence RTL Compiler


set_attribute lib_search_path /opt/design_kits/HITKIT370/liberty/c35_3.3V;
set_attribute hdl_search_path /home/enes/work_tutorial/
HDL_tutorial/FSM_example/functional
set_attribute library c35_CORELIB.lib;
set_attribute information_level 6;
set_attribute operating_condition WORST-MIL;
set
set
set
set
set
set
set

myFiles [list verilog.v];


basename FSM_example;
myClk clk;
myPeriod_ps 100000;
myInDelay_ps 500;
myOutDelay_ps 500;verilog_code
runname RTL;

read_hdl ${myFiles}
elaborate ${basename}
set clock [define_clock -period ${myPeriod_ps}
-name ${myClk} [clock_ports]]
external_delay -input $myInDelay_ps -clock ${myClk}
[find / -port ports_in/*]
external_delay -output $myOutDelay_ps -clock ${myClk}
[find / -port ports_out/*]
dc::set_clock_transition .4 $myClk
check_design -unresolved
report_timing -lint
synthesize -to_mapped -csa_effort high -incremental
report
report
report
report
report

timing > ${basename}_${runname}_timing.rep


gates > ${basename}_${runname}_cell.rep
power > ${basename}_${runname}_power.rep
yield > ${basename}_${runname}_yield.rep
area > ${basename}_${runname}_area.rep

set_attribute operating_condition BEST-MIL;


report timing > ${basename}_${runname}_timing_bc.rep

35

write_hdl -mapped > ${basename}_${runname}.v


write_sdc > ${basename}_${runname}.sdc
#quit

36

APPENDIX D
FIRSTENCOUNTER INPUT CONFIGURATION FILE

This is the c35b3_std.conf File of Finite State Machine.

global rda_Input
set cwd CWD
set rda_Input(import_mode) {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1 }
set rda_Input(ui_netlist) "FSM_example_RTL.v"
set rda_Input(ui_netlisttype) {Verilog}
set rda_Input(ui_ilmlist) {}
set rda_Input(ui_settop) {1}
set rda_Input(ui_topcell) {FSM_example}
set rda_Input(ui_celllib) {}
set rda_Input(ui_iolib) {}
set rda_Input(ui_areaiolib) {}
set rda_Input(ui_blklib) {}
set rda_Input(ui_kboxlib) {}
set rda_Input(ui_gds_file) {}
set rda_Input(ui_timelib,min) {}
set rda_Input(ui_timelib,max) {}
set rda_Input(ui_timelib)
"/opt/design_kits/HITKIT380/liberty/c35_3.3V/c35_CORELIB_BC.lib \
/opt/design_kits/HITKIT380/liberty/c35_3.3V/c35_CORELIB_WC.lib \
/opt/design_kits/HITKIT380/liberty/c35_3.3V/c35_CORELIB_TYP.lib \
/opt/design_kits/HITKIT380/liberty/c35_3.3V/c35_IOLIB_4M.lib"
set rda_Input(ui_smodDef) {}
set rda_Input(ui_smodData) {}
set rda_Input(ui_dpath) {}
set rda_Input(ui_tech_file) {}
set rda_Input(ui_io_file) {}
set rda_Input(ui_timingcon_file) {FSM_example_RTL.sdc}
set rda_Input(ui_latency_file) {}
set rda_Input(ui_scheduling_file) {}
set rda_Input(ui_buf_footprint) {}
set rda_Input(ui_delay_footprint) {}
set rda_Input(ui_inv_footprint) {}
set rda_Input(ui_leffile)
"/opt/design_kits/HITKIT380/artist/HK_C35/LEF/c35b3/c35b3.lef
/opt/design_kits/HITKIT380/artist/HK_C35/LEF/c35b3/CORELIB.lef
/opt/design_kits/HITKIT380/artist/HK_C35/LEF/c35b3/IOLIB_3M.lef"
set rda_Input(ui_core_cntl) {aspect}
set rda_Input(ui_aspect_ratio) {1.0}
set rda_Input(ui_core_util) {0.650}
set rda_Input(ui_core_height) {}
set rda_Input(ui_core_width) {}
set rda_Input(ui_core_to_left) {50}
set rda_Input(ui_core_to_right) {50}
set rda_Input(ui_core_to_top) {50}

37

set rda_Input(ui_core_to_bottom) {50}


set rda_Input(ui_max_io_height) {0}
set rda_Input(ui_row_height) {}
set rda_Input(ui_isHorTrackHalfPitch) {0}
set rda_Input(ui_isVerTrackHalfPitch) {1}
set rda_Input(ui_ioOri) {R0}
set rda_Input(ui_isOrigCenter) {0}
set rda_Input(ui_exc_net) {}
set rda_Input(ui_delay_limit) {1000}
set rda_Input(ui_net_delay) {1000.0ps}
set rda_Input(ui_net_load) {0.5pf}
set rda_Input(ui_in_tran_delay) {0.1ps}
set rda_Input(ui_captbl_file)
"-typical
/opt/design_kits/HITKIT380/artist/HK_C35/LEF/encounter/c35b3-typical.capTable -b
set rda_Input(ui_defcap_scale) {1.0}
set rda_Input(ui_detcap_scale) {1.0}
set rda_Input(ui_xcap_scale) {1.0}
set rda_Input(ui_res_scale) {1.0}
set rda_Input(ui_shr_scale) {1.0}
set rda_Input(ui_time_unit) {none}
set rda_Input(ui_cap_unit) {}
set rda_Input(ui_oa_reflib) {}
set rda_Input(ui_oa_abstractname) {}
set rda_Input(ui_oa_layoutname) {}
set rda_Input(ui_sigstormlib) {}
set rda_Input(ui_cdb_file) {}
set rda_Input(ui_echo_file) {}
set rda_Input(ui_xilm_file) {}
set rda_Input(ui_qxtech_file)
{/opt/design_kits/HITKIT380/assura/c35b3/c35b3/RCX-typical/qrcTechFile}
set rda_Input(ui_qxlayermap_file)
{/opt/design_kits/HITKIT380/artist/HK_C35/LEF/c35b3/qrclay.map}
set rda_Input(ui_qxlib_file) {}
set rda_Input(ui_qxconf_file) {}
set rda_Input(ui_pwrnet) {vdd! vdd3r1! vdd3r2! vdd3o!}
set rda_Input(ui_gndnet) {gnd! gnd3r! gnd3o!}
set rda_Input(flip_first) {1}
set rda_Input(double_back) {1}
set rda_Input(assign_buffer) {0}
set rda_Input(ui_pg_connections) ""
set rda_Input(ui_gen_footprint) {1}

38

APPENDIX E
CLOCKTREE FILE FOR FSM EXAMPLE

This is the Clocktree le of Finite State Machine.

AutoCTSRootPin
clk
MaxDelay
3000ps
MinDelay
1000ps
SinkMaxTran
1000ps
BufMaxTran
1000ps
MaxSkew
200ps
NoGating
NO
Buffer
BUF2 BUF4 BUF6 BUF8 BUF12 BUF15
INV0 INV1 INV2 INV3 INV4 INV8 INV10 INV12 INV15
CLKIN0 CLKIN1 CLKIN2 CLKIN3 CLKIN4 CLKIN6 CLKIN8
CLKIN10 CLKIN12 CLKIN15
CLKBU2 CLKBU4 CLKBU6 CLKBU8 CLKBU12 CLKBU15
End

39

APPENDIX F
FIRST ENCOUNTER TCL COMMAND FILE FOR FSM EXAMPLE

This is the gemma.tcl command le of Finite State Machine.

##Enable Multi-CPU
setMultiCpuUsage
##--- Load configuration file
loadConfig c35b3_std.conf 0
commitConfig
create_rc_corner -name typ -qx_tech_file /opt/design_kits/HITKIT370/
assura/c35b3/c35b3/RCX-typical/qrcTechFile
create_rc_corner -name worst -qx_tech_file /opt/design_kits/HITKIT370/
assura/c35b3/c35b3/RCX-worst/qrcTechFile
setOpCond -maxLibrary c35_CORELIB -max WORST-MIL
-minLibrary c35_CORELIB -min BEST-MIL
##--- Set user grids
setPreference ConstraintUserXGrid 0.1
setPreference ConstraintUserXOffset 0.1
setPreference ConstraintUserYGrid 0.1
setPreference ConstraintUserYOffset 0.1
setPreference SnapAllCorners 1
setPreference BlockSnapRule 2
##--- Define global Power nets - make global connections
clearGlobalNets
globalNetConnect vdd! -type pgpin -pin vdd! -inst * -module {}
globalNetConnect gnd! -type pgpin -pin gnd! -inst * -module {}
globalNetConnect vdd3o! -type pgpin -pin vdd3o! -inst * -module {}
globalNetConnect vdd3r1! -type pgpin -pin vdd3r1! -inst * -module {}
globalNetConnect vdd3r2! -type pgpin -pin vdd3r2! -inst * -module {}
globalNetConnect gnd3o! -type pgpin -pin gnd3o! -inst * -module {}
globalNetConnect gnd3r! -type pgpin -pin gnd3r! -inst * -module {}
fit
setDrawMode fplan
##-- Initialize floorplan
floorPlan -r 0.6 0.7 8 8 8 8
##--- Load corner io file to add corner cells (if necessary)
#loadIoFile corners.io

40

##-- Snap IO cells to user grid


#snapFPlanIO -usergrid
##-- Place Macros
##-- Create Placement Blockages
##createObstruct llx lly urx ury
##-- Cut Rows under Macros, Halos and Blockages
##cutCoreRow
#fit
##-- add CAP cells
addEndCap -preCap ENDCAPL -postCap ENDCAPR -prefix ENDCAP

##-- Route Power Ring


addRing -spacing_bottom 1.0 -spacing_top 1.0 -spacing_left 1.0 -spacing_right 1.
-width_bottom 20
-width_top 20
-width_left 20
-width_right 20 \
-layer_bottom MET1 -layer_top MET1 -layer_left MET2 -layer_right MET2 \
-offset_bottom 0.7 -offset_top 0.7 -offset_left 0.7 -offset_right 0.7 \
-stacked_via_bottom_layer MET1 -stacked_via_top_layer MET3 \
-center 1 \
-around core \
-jog_distance 0.7 \
-threshold 0.7 \
-nets { gnd! vdd! }
##-- Followpin routing
sroute -jogControl { preferWithChanges differentLayer } \
-nets { gnd! vdd! }
##-- Power Stripes
#addStripe -number_of_sets 2 \
#
-spacing 1.0 \
#
-layer MET2 \
#
-width 20 \
#
-xleft_offset 500 \
#
-xright_offset 500 \
#
-block_ring_top_layer_limit MET2 \
#
-block_ring_bottom_layer_limit MET2 \
#
-max_same_layer_jog_length 1.2 \
#
-padcore_ring_bottom_layer_limit MET2 \
#
-padcore_ring_top_layer_limit MET2 \
#
-stacked_via_top_layer MET3 \
#
-stacked_via_bottom_layer MET1 \
#
-merge_stripes_value 0.7 \
#
-nets {gnd! vdd! }
##-- Connect Power
sroute -noStripes -noCorePins -noPadRings -noBlockPins \
-jogControl { preferWithChanges differentLayer } \
-nets { gnd! vdd! }
##-- Placement
amoebaPlace
saveDesign verilog_D_latch_placed.enc

41

##-- Specify Clock tree


specifyClockTree -clkfile ctgen.const

##-- Run CTS


ckSynthesis -rguide verilog_D_latch_cts.guide -report verilog_D_latch_cts.ctsrpt
saveDesign verilog_D_latch_clkplaced.enc
##-- Add Core Filler cells
source fillcore.tcl
## or
##addFiller -cell FILL25 FILL10 FILL5 FILL2 FILL1 -prefix FILLER
##-- Add Peri Filler cells
source fillperi.tcl
##-- Run Routing
wroute
##-- Save Design
saveDesign verilog_D_latch.enc

##-- Write GDS2


streamOut verilog_D_latch_fe.gds2 -mapFile gds2.map -libName DesignLib -structur
-attachInstanceName -attachNetName -stripes 1 -units 1000 -mode ALL

##-- Extract detail parasitics


setExtractRCMode -detail -rcdb verilog_D_latch.rcdb -relative_c_t 0.01 -total_c_
setXCapThresholds -totalCThreshold 5.0 -relativeCThreshold 0.01
extractRC
rcOut -spef verilog_D_latch_fe.spef
##-- Write SDF File
delayCal -sdf verilog_D_latch.sdf
##-- End of First Encounter TCL command file

42

APPENDIX G
ELC SETUP FILE

// Encounter Library Characterizer setup file


// Define voltage and temp for process corners
Process typical{
voltage = 3.3;
temp = 25;
Corner = "TT";
Vtn = 0.67;
Vtp = 0.92;
};
// define measurement percentages for std_cell measurements
Signal std_cell {
unit = REL;
Vh=1.0 1.0;
Vl=0.0 0.0;
Vth=0.5 0.5;
Vsh=0.8 0.8;
Vsl=0.2 0.2;
tsmax=2.0n;
};
// Define special measurements for our flow
// (using 30/70 delay measurement)
Signal std_cell_6710 {
unit = REL;
Vh=1.0 1.0;
Vl=0.0 0.0;
Vth=0.3 0.7 0.7 0.3;
Vsh=0.8 0.8;
Vsl=0.2 0.2;
tsmax=2.0n;
};
Signal VDD5.0V {
unit = ABS;
Vh=3.3 3.3;
Vl=0.0 0.0;
Vth=1.65 1.65;
Vsh=2.0 2.0;
Vsl=0.5 0.5;
tsmax=2.0n;
};

43

// Set some parameters for how the simulation will proceed


Simulation std_cell{
transient = 0.1n 80n 10p;
dc = 0.1 4.5 0.1;
bisec = 6.0n 6.0n 100p;
resistance = 10MEG;
};
// Default indices for the look up tables
Index DEFAULT_INDEX{
Slew = 0.100n 0.30n 0.7n 1.0n 2.0n;
Load = 0.025p 0.05p 0.1p 0.3p 0.6p;
};
// Indices for cells that are named with Xn where
// n is the drive strength. X1 is a standard unit-sized
// inverter drive.
Index X1{
Slew = 0.100n 0.30n 0.7n 1.0n 2.0n;
Load = 0.025p 0.05p 0.1p 0.3p 0.6p;
};
Index X2{
Slew = 0.100n 0.30n 0.7n 1.0n 2.0n;
Load = 0.050p 0.10p 0.2p 0.6p 1.2p;
};
Index X4{
Slew = 0.100n 0.30n 0.7n 1.0n 2.0n;
Load = 0.1p 0.2p 0.4p 1.2p 2.4p;
};
Index X8{
Slew = 0.100n 0.30n 0.7n 1.0n 2.0n;
Load = 0.2p 0.4p 0.8p 2.4p 4.8p;
};
Index Clk_Slew{
bslew = 0.100n 0.5n 1.0n;
};
Index IO5x5{
Slew = 0.1n 0.3n 0.6n 1.3n 3.0n;
Load = 5p 10p 20p 50p 75p;
};
Group POWR{
PIN = *.Vdd *.Vdd2;
};
Group Core_Pins{
PIN = *.DO *.DI ;
};

44

Group Pad_Pins{
PIN = *.YPAD ;
};
// Define groups by cell names
// Cells not in these groups will get the default indices
Group X1{
CELL = *X1 ;
};
Group X2{
CELL = *X2 ;
};
Group X4{
CELL = *X4 ;
};
Group X8{
CELL = *X8 ;
};
Group Clk_Slew{
PIN = *.CLK ;
};
// Define derating coefficients for margins
// 1.0 means no margins.
Margin m0 {
setup
= 1.0 0.0 ;
hold
= 1.0 0.0 ;
release = 1.0 0.0 ;
removal = 1.0 0.0 ;
recovery = 1.0 0.0 ;
width
= 1.0 0.0 ;
delay
= 1.0 0.0 ;
power
= 1.0 0.0 ;
cap
= 1.0 0.0 ;
} ;
Nominal n0 {
delay = 0.5 0.5 ;
power = 0.5 0.5 ;
cap = 0.5 0.5 ;
} ;
set process(typical){
simulation = std_cell;
signal = std_cell_6710;
margin = m0;
nominal = n0;
};
set index(typical){
Group(X1) = X1;

45

};

Group(X2) = X2;
Group(X4) = X4;
Group(X8) = X8;
Group(Pad_Pins) = IO5x5;
Group(Core_Pins) = X4;
Group(Clk_Slew) = Clk_Slew;

set signal(typical){
Group(POWR) = VDD5.0V;
};

46

APPENDIX H
STEP1 SCRIPT

# Open a new database named foo


db_open newcell
# Set some variables to define how ELC does its stuff
set_var EC_SPICE_SIMPLIFY true
set_var EC_HALF_WIDTH_HOLD_FLAG true
set_var EC_SIM_NAME "spectre"
set_var EC_SIM_TYPE "spectre"
set_var EC_SPICE_SUPPLY1_NAMES "vdd"
set_var EC_SPICE_SUPPLY0_NAMES "gnd"
# run through the steps that read and parse the subckt file (defined
# in elccfg), and extracts the functionality of each cell
db_prepare -force
db_gate
db_close
exit

47

APPENDIX I
STEP2 SCRIPT

# open the database you used in step1


db_open newcell
# Remove the next 3 lines to use the ipsd/ipsc
# deamons for load balancing on multiple machines
set_var EC_SIM_USE_LSF 1
set_var EC_SIM_LSF_CMD ""
set_var EC_SIM_LSF_PARALLEL 10
# set up some things that let ELC know how to proceed
set_var EC_SIM_NAME "spectre"
set_var EC_SIM_TYPE "spectre"
set_var EC_SPICE_SUPPLY1_NAMES "vdd"
set_var EC_SPICE_SUPPLY0_NAMES "gnd"
set_var EC_HALF_WIDTH_HOLD_FLAG true
# run spice (Spectre in this case) to do the actual characterization
db_spice -s spectre -p typical -keep_log
db_close
exit

48

APPENDIX J
STEP3 SCRIPT

# re-open that database


db_open newcell
# output the results of the characterization as a .alf file
db_output -r newcell.alf.rep -alf newcell.alf -p typical
# output the results of the characterization as a .v file
db_verilog -r newcell.v
db_close
exit

49

APPENDIX K
ELC OUTPUT

This is the output of the ELC for the Inverter, D Flip-Flop, NAND and NOR
gates.

/*
delay model :
typ
check model :
typ
power model :
typ
capacitance model : typ
other model :
typ
*/
library(newcell) {
delay_model : table_lookup;
in_place_swap_mode : match_footprint;
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1mA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit (1,pf);
power_supply () {
default_power_rail : RAIL_VDD;
power_rail( RAIL_GND, 0 );
power_rail( RAIL_VDD, 3.3 );
}
slew_upper_threshold_pct_rise : 80;
slew_lower_threshold_pct_rise : 20;
slew_upper_threshold_pct_fall : 80;
slew_lower_threshold_pct_fall : 20;
input_threshold_pct_rise : 30;
input_threshold_pct_fall : 70;
output_threshold_pct_rise : 70;
output_threshold_pct_fall : 30;
nom_process : 1;
nom_voltage : 3.3;
nom_temperature : 25;
operating_conditions ( typical ) {
process : 1;
voltage : 3.3;
temperature : 25;
power_rail( RAIL_GND, 0 );
power_rail( RAIL_VDD, 3.3 );

50

}
default_operating_conditions : typical;
lu_table_template(delay_template_5x5) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
}
power_lut_template(energy_template_5x5) {
variable_1 : input_transition_time;
variable_2 : total_output_net_capacitance;
index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
}
lu_table_template(hold_template_5x3) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
index_2 ("1000.0, 1001.0, 1002.0");
}
power_lut_template(passive_energy_template_5x1) {
variable_1 : input_transition_time;
index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
}
lu_table_template(recovery_template_5x3) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
index_2 ("1000.0, 1001.0, 1002.0");
}
lu_table_template(recovery_template_5x5) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
}
lu_table_template(removal_template_5x3) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
index_2 ("1000.0, 1001.0, 1002.0");
}
lu_table_template(setup_template_5x3) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
index_2 ("1000.0, 1001.0, 1002.0");
}
lu_table_template(width_template_5x1) {
variable_1 : related_pin_transition;
index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
}
/* --------------- *

51

* Design : DFFSR0 *
* --------------- */
cell (DFFSR0) {
area : 0.0;
cell_leakage_power : 0.104625;
rail_connection( GND, RAIL_GND );
rail_connection( VDD, RAIL_VDD );
ff (NET9,NET81) {
next_state : "D";
clocked_on : "CLK";
clear : "(!RN)";
preset : "(!SN)";
clear_preset_var1 : L;
clear_preset_var2 : L;
}
pin(CLK) {
direction : input;
input_signal_level : RAIL_VDD;
capacitance : 0.00419551;
rise_capacitance : 0.00419297;
fall_capacitance : 0.00419551;
rise_capacitance_range ( 0.00418043, 0.0041972) ;
fall_capacitance_range ( 0.00418818, 0.0041972) ;
clock : true;
max_transition : 1.2;
internal_power() {
rise_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.15957, 0.161311, 0.171865, 0.181675, 0.22239");
}
fall_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.436253, 0.439861, 0.45298, 0.467471, 0.521014");
}
}
timing() {
related_pin : "CLK";
timing_type : min_pulse_width;
when : "!D&RN&SN";
sdf_cond : "D_EQ_0_AN_RN_EQ_1_AN_SN_EQ_1 == 1'b1";
rise_constraint(width_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("1.03689, 1.10723, 1.24184, 1.3318, 1.58947");
}
fall_constraint(width_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.834031, 0.912587, 1.0731, 1.19127, 1.55136");
}
}
}
pin(D) {
direction : input;
input_signal_level : RAIL_VDD;
capacitance : 0.00380672;
rise_capacitance : 0.00380672;

52

fall_capacitance : 0.00376325;
rise_capacitance_range ( 0.00380591, 0.00605658) ;
fall_capacitance_range ( 0.00375876, 0.00605839) ;
max_transition : 1.2;
internal_power() {
rise_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.167702, 0.169548, 0.178167, 0.186136, 0.216465");
}
fall_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.171646, 0.173594, 0.183607, 0.192509, 0.225856");
}
}
timing() {
related_pin : "CLK";
timing_type : hold_rising;
when : "RN&SN";
sdf_cond : "RN_EQ_1_AN_SN_EQ_1 == 1'b1";
rise_constraint(hold_template_5x3) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.06, 0.3, 0.6");
values ( \
"-0.01875, 0.1425, 0.27375", \
"-0.07125, 0.03375, 0.165", \
"-0.17625, -0.07125, 0.06", \
"-0.255, -0.15, 0.0375", \
"-0.46125, -0.35625, -0.225");
}
fall_constraint(hold_template_5x3) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.06, 0.3, 0.6");
values ( \
"0.20625, 0.31125, 0.49875", \
"0.15375, 0.25875, 0.39", \
"-0.0075, 0.0975, 0.285", \
"-0.1425, 0.01875, 0.15", \
"-0.46125, -0.3, -0.16875");
}
}
timing() {
related_pin : "CLK";
timing_type : setup_rising;
when : "RN&SN";
sdf_cond : "RN_EQ_1_AN_SN_EQ_1 == 1'b1";
rise_constraint(setup_template_5x3) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.06, 0.3, 0.6");
values ( \
"0.2625, 0.10125, -0.03", \
"0.315, 0.21, 0.0225", \
"0.47625, 0.315, 0.1275", \
"0.49875, 0.39375, 0.20625", \
"0.76125, 0.6, 0.4125");
}

53

fall_constraint(setup_template_5x3) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.06, 0.3, 0.6");
values ( \
"-0.01875, -0.18, -0.31125", \
"0.09, -0.07125, -0.25875", \
"0.25125, 0.09, -0.0975", \
"0.33, 0.16875, 0.0375", \
"0.705, 0.54375, 0.4125");
}

}
}
pin(Q) {
direction : output;
output_signal_level : RAIL_VDD;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
rise_capacitance_range ( 0, 0) ;
fall_capacitance_range ( 0, 0) ;
max_capacitance : 0.146246;
max_transition : 4.83222;
function : "NET9";
timing() {
related_pin : "CLK";
timing_sense : non_unate;
timing_type : rising_edge;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.757421, 0.958323, 1.35939, 2.9638, 5.36583", \
"0.826961, 1.02781, 1.42906, 3.03063, 5.43975", \
"0.965265, 1.16612, 1.56738, 3.1754, 5.58435", \
"1.05572, 1.25737, 1.6582, 3.26055, 5.67316", \
"1.31819, 1.51938, 1.92044, 3.52748, 5.92528");
}
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.248294, 0.445152, 0.844567, 2.4377, 4.83221", \
"0.248432, 0.446855, 0.844151, 2.43871, 4.82902", \
"0.248427, 0.446922, 0.844243, 2.43042, 4.81649", \
"0.248609, 0.445696, 0.843676, 2.43873, 4.83105", \
"0.24877, 0.448103, 0.844477, 2.43358, 4.83222");
}
cell_fall(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.89399, 1.02418, 1.26893, 2.24236, 3.70989", \
"0.964483, 1.09447, 1.33919, 2.30705, 3.78014", \
"1.09914, 1.22907, 1.47396, 2.43832, 3.9148", \
"1.18919, 1.3189, 1.56277, 2.53359, 4.0023", \

54

"1.44691, 1.5759, 1.82007, 2.79279, 4.25635");


}
fall_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.173456, 0.277356, 0.489332, 1.38531, 2.73612", \
"0.172818, 0.277447, 0.489342, 1.38417, 2.73855", \
"0.172473, 0.277249, 0.489434, 1.37954, 2.74626", \
"0.173107, 0.277317, 0.488187, 1.3857, 2.75084", \
"0.173338, 0.276146, 0.48524, 1.38688, 2.74272");
}

}
timing() {
related_pin : "RN";
timing_sense : positive_unate;
timing_type : clear;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.368395, 0.569414, 0.970495, 2.57535, 4.99027", \
"0.427776, 0.628396, 1.02953, 2.6343, 5.04983", \
"0.519096, 0.719034, 1.11968, 2.7242, 5.13899", \
"0.577495, 0.777725, 1.17754, 2.78474, 5.18831", \
"0.749402, 0.950262, 1.3508, 2.95076, 5.3602");
}
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.246474, 0.443001, 0.839588, 2.43027, 4.82474", \
"0.247049, 0.443044, 0.839629, 2.43026, 4.82532", \
"0.250536, 0.444849, 0.840016, 2.43025, 4.82465", \
"0.252587, 0.446402, 0.840782, 2.4331, 4.816", \
"0.262609, 0.45398, 0.846514, 2.42934, 4.81705");
}
cell_fall(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.362855, 0.490312, 0.732843, 1.69746, 3.15415", \
"0.443241, 0.570391, 0.813317, 1.77849, 3.2337", \
"0.611082, 0.738533, 0.981017, 1.94605, 3.40059", \
"0.731652, 0.859448, 1.1021, 2.06676, 3.5202", \
"1.1143, 1.24394, 1.48709, 2.4501, 3.90302");
}
fall_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.162046, 0.26787, 0.481753, 1.37632, 2.72652", \
"0.162598, 0.268416, 0.481816, 1.37499, 2.72628", \
"0.165703, 0.270125, 0.482169, 1.3761, 2.72804", \
"0.1703, 0.273462, 0.483367, 1.3759, 2.72027", \

55

"0.183732, 0.283708, 0.488798, 1.37689, 2.72818");

}
timing() {
related_pin : "SN";
timing_sense : negative_unate;
timing_type : preset;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.641025, 0.84142, 1.24129, 2.84672, 5.25447", \
"0.721983, 0.921367, 1.32271, 2.92584, 5.33757", \
"0.893598, 1.09318, 1.49412, 3.09872, 5.49891", \
"1.01892, 1.21825, 1.61999, 3.22168, 5.63359", \
"1.42054, 1.6193, 2.02169, 3.62733, 6.03369");
}
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.250505, 0.44545, 0.84194, 2.4347, 4.82025", \
"0.250028, 0.446389, 0.841654, 2.43728, 4.82052", \
"0.250224, 0.445929, 0.841264, 2.43524, 4.83129", \
"0.251051, 0.446364, 0.841992, 2.43625, 4.82421", \
"0.252215, 0.446915, 0.842899, 2.43444, 4.82624");
}
}
internal_power() {
related_pin : "CLK";
rise_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.34682, 0.414585, 0.550586, 1.09512, 1.91188", \
"0.347671, 0.415429, 0.551342, 1.09598, 1.91273", \
"0.354423, 0.422352, 0.558175, 1.10269, 1.91945", \
"0.360491, 0.428375, 0.564273, 1.10884, 1.92567", \
"0.385849, 0.453372, 0.589819, 1.1343, 1.95107");
}
fall_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.381694, 0.448874, 0.584322, 1.12827, 1.94481", \
"0.38279, 0.449996, 0.585497, 1.12928, 1.94583", \
"0.388742, 0.455942, 0.591423, 1.13524, 1.95179", \
"0.394484, 0.461672, 0.597128, 1.14101, 1.9575", \
"0.417526, 0.484735, 0.620221, 1.16404, 1.98059");
}
}
internal_power() {
related_pin : "RN";
rise_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");

56

index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");


values ( \
"0.330193, 0.46663, 0.73918, 1.82844, 3.46201", \
"0.344023, 0.480161, 0.752589, 1.84184, 3.47543", \
"0.39976, 0.534736, 0.806553, 1.89552, 3.52902", \
"0.45095, 0.585331, 0.856544, 1.94489, 3.57828", \
"0.641817, 0.774265, 1.04399, 2.13018, 3.76287");

}
fall_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.30558, 0.271361, 0.45764, 1.18992, 2.41507", \
"0.321371, 0.286969, 0.45179, 1.18098, 2.40613", \
"0.372796, 0.337933, 0.434516, 1.15591, 2.38101", \
"0.417026, 0.381921, 0.420916, 1.17509, 2.35999", \
"0.512271, 0.538582, 0.468641, 1.19111, 2.28566");
}

}
internal_power() {
related_pin : "SN";
rise_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.376787, 0.443317, 0.57801, 1.12097, 1.93715", \
"0.383572, 0.450102, 0.584871, 1.12778, 1.94391", \
"0.408982, 0.475228, 0.609859, 1.1527, 1.96881", \
"0.432335, 0.498185, 0.632497, 1.17511, 1.99116", \
"0.516861, 0.581481, 0.715038, 1.25677, 2.07261");
}
fall_power(scalar) {
values("0");
}
}

}
pin(QN) {
direction : output;
output_signal_level : RAIL_VDD;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
rise_capacitance_range ( 0, 0) ;
fall_capacitance_range ( 0, 0) ;
max_capacitance : 0.144559;
max_transition : 4.81638;
function : "NET81";
timing() {
related_pin : "CLK";
timing_sense : non_unate;
timing_type : rising_edge;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \

57

"1.03689, 1.2375, 1.63816, 3.24101, 5.6457", \


"1.10723, 1.30783, 1.70849, 3.31166, 5.71595", \
"1.24184, 1.44241, 1.84305, 3.44597, 5.85062", \
"1.3318, 1.53234, 1.93291, 3.53627, 5.94063", \
"1.58947, 1.79, 2.19062, 3.7939, 6.19761");

}
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.245237, 0.441332, 0.837401, 2.42583, 4.81007", \
"0.245279, 0.441331, 0.837401, 2.42641, 4.80999", \
"0.245275, 0.441327, 0.837348, 2.42626, 4.81007", \
"0.245291, 0.441321, 0.837257, 2.42651, 4.80986", \
"0.245311, 0.441374, 0.837335, 2.42653, 4.80957");
}
cell_fall(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.809119, 0.933568, 1.17533, 2.13856, 3.58318", \
"0.878672, 1.00308, 1.24484, 2.20789, 3.65301", \
"1.01696, 1.14136, 1.38312, 2.34742, 3.79144", \
"1.10762, 1.23206, 1.47394, 2.43684, 3.88206", \
"1.37044, 1.49465, 1.73665, 2.69969, 4.14504");
}
fall_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.153584, 0.258288, 0.474521, 1.3661, 2.70973", \
"0.153594, 0.258274, 0.474491, 1.36592, 2.71016", \
"0.153594, 0.258276, 0.474492, 1.3671, 2.71036", \
"0.153826, 0.258438, 0.474701, 1.36599, 2.7104", \
"0.153785, 0.25811, 0.47467, 1.3661, 2.71072");
}

}
timing() {
related_pin : "RN";
timing_sense : negative_unate;
timing_type : preset;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.546065, 0.746559, 1.14712, 2.74962, 5.15398", \
"0.626286, 0.826756, 1.22731, 2.82972, 5.23419", \
"0.792696, 0.992895, 1.39327, 2.99567, 5.40032", \
"0.911421, 1.11155, 1.51177, 3.11404, 5.51844", \
"1.28944, 1.48913, 1.88878, 3.4907, 5.89473");
}
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \

58

"0.250423, 0.443033, 0.837249, 2.42575, 4.80971", \


"0.250434, 0.443034, 0.837177, 2.42582, 4.80957", \
"0.25054, 0.443068, 0.837112, 2.42573, 4.80988", \
"0.250776, 0.443202, 0.837204, 2.42581, 4.80978", \
"0.25137, 0.443679, 0.837196, 2.42572, 4.8093");

}
}
timing() {
related_pin : "SN";
timing_sense : positive_unate;
timing_type : clear;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.414201, 0.615739, 1.01664, 2.62125, 5.02828", \
"0.46203, 0.663369, 1.06419, 2.66875, 5.07575", \
"0.550232, 0.750712, 1.15084, 2.75438, 5.16176", \
"0.608602, 0.80868, 1.20807, 2.81118, 5.21971", \
"0.776201, 0.977823, 1.3762, 2.97502, 5.38423");
}
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.257202, 0.447017, 0.838851, 2.42839, 4.81476", \
"0.256871, 0.446898, 0.83882, 2.42846, 4.81493", \
"0.259316, 0.448285, 0.83918, 2.42799, 4.81488", \
"0.261998, 0.449873, 0.839677, 2.428, 4.81638", \
"0.273691, 0.459501, 0.845035, 2.42662, 4.81588");
}
cell_fall(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.447221, 0.579058, 0.826528, 1.79004, 3.23546", \
"0.528367, 0.660067, 0.907661, 1.87123, 3.31618", \
"0.701312, 0.83274, 1.08012, 2.04368, 3.48905", \
"0.829508, 0.960805, 1.20788, 2.17115, 3.61649", \
"1.24101, 1.37275, 1.61966, 2.58228, 4.02747");
}
fall_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.178657, 0.280698, 0.491649, 1.36902, 2.7105", \
"0.178851, 0.280733, 0.491789, 1.36908, 2.71055", \
"0.179341, 0.280964, 0.491851, 1.36908, 2.71048", \
"0.181098, 0.281918, 0.492302, 1.36913, 2.7104", \
"0.191026, 0.289007, 0.495772, 1.36973, 2.71072");
}
}
internal_power() {
related_pin : "CLK";
rise_power(energy_template_5x5) {

59

index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");


index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.381694, 0.448874, 0.584322, 1.12827, 1.94481", \
"0.38279, 0.449996, 0.585497, 1.12928, 1.94583", \
"0.388742, 0.455942, 0.591423, 1.13524, 1.95179", \
"0.394484, 0.461672, 0.597128, 1.14101, 1.9575", \
"0.417526, 0.484735, 0.620221, 1.16404, 1.98059");

}
fall_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.34682, 0.414585, 0.550586, 1.09512, 1.91188", \
"0.347671, 0.415429, 0.551342, 1.09598, 1.91273", \
"0.354423, 0.422352, 0.558175, 1.10269, 1.91945", \
"0.360491, 0.428375, 0.564273, 1.10884, 1.92567", \
"0.385849, 0.453372, 0.589819, 1.1343, 1.95107");
}

}
internal_power() {
related_pin : "RN";
rise_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6,
index_2 ("0.025, 0.05, 0.1, 0.3,
values ( \
"0.372864, 0.440537, 0.576262,
"0.379601, 0.447177, 0.583022,
"0.405879, 0.473017, 0.608587,
"0.429132, 0.496005, 0.631286,
"0.512271, 0.577962, 0.712226,
}
fall_power(scalar) {
values("0");
}
}
internal_power() {
related_pin : "SN";
rise_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6,
index_2 ("0.025, 0.05, 0.1, 0.3,
values ( \
"0.337799, 0.473711, 0.745878,
"0.347001, 0.482627, 0.754635,
"0.385405, 0.519904, 0.791105,
"0.421535, 0.555031, 0.825574,
"0.559589, 0.691368, 0.959553,
}
fall_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6,
index_2 ("0.025, 0.05, 0.1, 0.3,
values ( \
"0.304412, 0.268552, 0.389335,
"0.313423, 0.277528, 0.385083,
"0.346136, 0.309861, 0.370573,

1.2");
0.6");
1.1205, 1.93727", \
1.12722, 1.94389", \
1.15255, 1.96916", \
1.17509, 1.99161", \
1.25504, 2.07134");

1.2");
0.6");
1.83469, 3.46815", \
1.8434, 3.47681", \
1.87942, 3.51271", \
1.91312, 3.54616", \
2.04424, 3.67649");
1.2");
0.6");
1.19591, 2.42103", \
1.19365, 2.41874", \
1.18659, 2.41169", \

60

"0.376039, 0.339187, 0.358129, 1.1803, 2.40555", \


"0.484509, 0.44608, 0.436683, 1.1304, 2.38293");

}
pin(RN) {
direction : input;
input_signal_level : RAIL_VDD;
capacitance : 0.0120229;
rise_capacitance : 0.0120229;
fall_capacitance : 0.0118438;
rise_capacitance_range ( 0.0120171, 0.0154066) ;
fall_capacitance_range ( 0.0118071, 0.0153854) ;
max_transition : 1.2;
internal_power() {
rise_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.07004, 0.070044, 0.070075, 0.070017, 0.069983");
}
fall_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.074469, 0.074132, 0.07401, 0.073987, 0.074016");
}
}
timing() {
related_pin : "RN";
timing_type : min_pulse_width;
when : "!D&!SN";
sdf_cond : "D_EQ_0_AN_SN_EQ_0 == 1'b1";
fall_constraint(width_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.379911, 0.461208, 0.632807, 0.758678, 1.16009");
}
}
timing() {
related_pin : "CLK";
timing_type : recovery_rising;
when : "D&SN";
sdf_cond : "D_EQ_1_AN_SN_EQ_1 == 1'b1";
rise_constraint(recovery_template_5x3) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.06, 0.3, 0.6");
values ( \
"-0.3, -0.46125, -0.5925", \
"-0.2475, -0.40875, -0.59625", \
"-0.08625, -0.2475, -0.435", \
"0.04875, -0.1125, -0.3", \
"0.3675, 0.20625, 0.01875");
}
}
timing() {
related_pin : "SN";
timing_type : recovery_rising;
when : "!D";
sdf_cond : "D == 1'b0";

61

rise_constraint(recovery_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ( \
"0.09375, 0.14625, 0.195, 0.27375, 0.42375", \
"0.04125, 0.09375, 0.19875, 0.22125, 0.37125", \
"-0.0075, 0.045, 0.09375, 0.1725, 0.26625", \
"-0.03, 0.0225, 0.07125, 0.09375, 0.24375", \
"-0.18, -0.1275, -0.07875, 0, 0.09375");
}

}
timing() {
related_pin : "CLK";
timing_type : removal_rising;
when : "D&SN";
sdf_cond : "D_EQ_1_AN_SN_EQ_1 == 1'b1";
rise_constraint(removal_template_5x3) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.06, 0.3, 0.6");
values ( \
"0.43125, 0.5925, 0.72375", \
"0.37875, 0.54, 0.7275", \
"0.38625, 0.49125, 0.67875", \
"0.36375, 0.525, 0.65625", \
"0.32625, 0.43125, 0.61875");
}
}

}
pin(SN) {
direction : input;
input_signal_level : RAIL_VDD;
capacitance : 0.0133192;
rise_capacitance : 0.0133192;
fall_capacitance : 0.0131477;
rise_capacitance_range ( 0.0133163, 0.0168236) ;
fall_capacitance_range ( 0.0131352, 0.0167909) ;
max_transition : 1.2;
internal_power() {
rise_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.082891, 0.082928, 0.082941, 0.082873, 0.082844");
}
fall_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.087863, 0.087279, 0.087169, 0.087125, 0.087137");
}
}
timing() {
related_pin : "SN";
timing_type : min_pulse_width;
when : "!D&!RN";
sdf_cond : "D_EQ_0_AN_RN_EQ_0 == 1'b1";
fall_constraint(width_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.442609, 0.52363, 0.696799, 0.825098, 1.23629");

62

}
}
timing() {
related_pin : "CLK";
timing_type : recovery_rising;
when : "!D&RN";
sdf_cond : "D_EQ_0_AN_RN_EQ_1 == 1'b1";
rise_constraint(recovery_template_5x3) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.06, 0.3, 0.6");
values ( \
"-0.24375, -0.405, -0.53625", \
"-0.19125, -0.29625, -0.48375", \
"-0.03, -0.19125, -0.37875", \
"0.04875, -0.1125, -0.3", \
"0.255, 0.09375, -0.09375");
}
}
timing() {
related_pin : "RN";
timing_type : recovery_rising;
when : "!D";
sdf_cond : "D == 1'b0";
rise_constraint(recovery_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ( \
"0.09375, 0.14625, 0.25125, 0.27375, 0.42375", \
"0.04125, 0.09375, 0.19875, 0.22125, 0.37125", \
"-0.0075, 0.045, 0.09375, 0.1725, 0.26625", \
"-0.03, -0.03375, 0.07125, 0.09375, 0.24375", \
"-0.18, -0.18375, -0.07875, -0.05625, 0.09375");
}
}
timing() {
related_pin : "CLK";
timing_type : removal_rising;
when : "!D&RN";
sdf_cond : "D_EQ_0_AN_RN_EQ_1 == 1'b1";
rise_constraint(removal_template_5x3) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.06, 0.3, 0.6");
values ( \
"0.375, 0.53625, 0.6675", \
"0.3225, 0.48375, 0.615", \
"0.2175, 0.37875, 0.56625", \
"0.195, 0.3, 0.4875", \
"-0.01125, 0.09375, 0.28125");
}
}

/* ------------- *
* Design : INV0 *

63

* ------------- */
cell (INV0) {
area : 0.0;
cell_leakage_power : 0.00612408;
rail_connection( GND, RAIL_GND );
rail_connection( VDD, RAIL_VDD );
pin(A) {
direction : input;
input_signal_level : RAIL_VDD;
capacitance : 0.00429321;
rise_capacitance : 0.00429144;
fall_capacitance : 0.00429321;
rise_capacitance_range ( 0.00427979, 0.00429519) ;
fall_capacitance_range ( 0.00429147, 0.00429663) ;
max_transition : 1.2;
}
pin(Q) {
direction : output;
output_signal_level : RAIL_VDD;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
rise_capacitance_range ( 0, 0) ;
fall_capacitance_range ( 0, 0) ;
max_capacitance : 0.0689865;
max_transition : 10.001;
function : "(!A)";
timing() {
related_pin : "A";
timing_sense : negative_unate;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.530123, 0.950103, 1.78883, 5.14668, 10.1705", \
"0.606428, 1.02655, 1.86684, 5.22045, 10.2447", \
"0.770793, 1.18417, 2.02035, 5.37519, 10.3909", \
"0.896783, 1.30747, 2.14001, 5.48902, 10.5087", \
"1.32439, 1.72842, 2.54788, 5.88727, 10.8895");
}
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.477346, 0.891777, 1.72018, 5.03736, 10.0006", \
"0.477279, 0.892931, 1.72342, 5.03673, 10.0006", \
"0.487722, 0.891577, 1.72429, 5.04409, 10.001", \
"0.510566, 0.896272, 1.72079, 5.03794, 10.0006", \
"0.617748, 0.964633, 1.73294, 5.04529, 10.0006");
}
cell_fall(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.303007, 0.529392, 0.98452, 2.8175, 5.50986", \

64

"0.372274,
"0.516469,
"0.617076,
"0.896263,

0.598356, 1.05153, 2.86158, 5.57678", \


0.738821, 1.18966, 3.01059, 5.71481", \
0.845895, 1.29561, 3.11847, 5.8189", \
1.18885, 1.65159, 3.46462, 6.16701");

}
fall_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.240939, 0.451634, 0.875181, 2.58221,
"0.243549, 0.451659, 0.873583, 2.55863,
"0.292306, 0.467595, 0.872961, 2.57108,
"0.341732, 0.502688, 0.880149, 2.57376,
"0.482985, 0.659704, 0.981951, 2.57083,
}

5.08624", \
5.08529", \
5.08867", \
5.08688", \
5.09119");

}
internal_power() {
related_pin : "A";
rise_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.182026, 0.318436, 0.590872, 1.68002, 3.31352", \
"0.182976, 0.318956, 0.59115, 1.68012, 3.31357", \
"0.192312, 0.325389, 0.594442, 1.68117, 3.31419", \
"0.19889, 0.330558, 0.599205, 1.68387, 3.31554", \
"0.232638, 0.357526, 0.61919, 1.69516, 3.32187");
}
fall_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.133691, 0.269731, 0.541917, 1.63086, 3.26435", \
"0.13285, 0.269087, 0.541497, 1.63069, 3.26426", \
"0.127273, 0.265191, 0.539049, 1.62993, 3.26381", \
"0.121702, 0.261551, 0.536336, 1.62829, 3.26295", \
"0.095781, 0.24177, 0.523325, 1.62116, 3.25959");
}
}

/* ---------------- *
* Design : NAND2_0 *
* ---------------- */
cell (NAND2_0) {
area : 0.0;
cell_leakage_power : 0.0113794;
rail_connection( GND, RAIL_GND );
rail_connection( VDD, RAIL_VDD );
pin(A) {
direction : input;
input_signal_level : RAIL_VDD;
capacitance : 0.00438654;
rise_capacitance : 0.00438654;

65

fall_capacitance : 0.00428174;
rise_capacitance_range ( 0.00438468, 0.00466744) ;
fall_capacitance_range ( 0.00427467, 0.00465859) ;
max_transition : 1.2;
internal_power() {
rise_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.018316, 0.018332, 0.018298, 0.018327, 0.0183");
}
fall_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.018911, 0.018678, 0.018645, 0.018645, 0.018649");
}
}

}
pin(B) {
direction : input;
input_signal_level : RAIL_VDD;
capacitance : 0.00319341;
rise_capacitance : 0.00316721;
fall_capacitance : 0.00319341;
rise_capacitance_range ( 0.00316563, 0.0047527) ;
fall_capacitance_range ( 0.00319127, 0.00474793) ;
max_transition : 1.2;
internal_power() {
rise_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.020398, 0.020386, 0.020397, 0.020404, 0.020399");
}
fall_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.022299, 0.022294, 0.022318, 0.022331, 0.022315");
}
}
}
pin(Q) {
direction : output;
output_signal_level : RAIL_VDD;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
rise_capacitance_range ( 0, 0) ;
fall_capacitance_range ( 0, 0) ;
max_capacitance : 0.0661078;
max_transition : 10.053;
function : "(!(A B))";
timing() {
related_pin : "A";
timing_sense : negative_unate;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.592439, 1.01444, 1.85526, 5.20938, 10.2333", \
"0.669983, 1.08844, 1.92918, 5.28271, 10.3054", \

66

"0.837835, 1.24874, 2.08586, 5.44074, 10.4567", \


"0.969028, 1.37718, 2.20678, 5.55287, 10.569", \
"1.41735, 1.81503, 2.626, 5.95252, 10.9576");

}
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.528531, 0.944808, 1.7751, 5.08877, 10.0522", \
"0.528475, 0.943736, 1.77554, 5.08958, 10.0522", \
"0.533603, 0.9431, 1.77671, 5.09576, 10.0529", \
"0.549498, 0.945116, 1.77213, 5.09016, 10.053", \
"0.631552, 0.997162, 1.7792, 5.09028, 10.0522");
}
cell_fall(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.284805, 0.485778, 0.886333, 2.48914, 4.89295", \
"0.334893, 0.535158, 0.935964, 2.53751, 4.94326", \
"0.437713, 0.636068, 1.03597, 2.63935, 5.04155", \
"0.507658, 0.713949, 1.1111, 2.71296, 5.11243", \
"0.707705, 0.952583, 1.36875, 2.96136, 5.3587");
}
fall_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.228686, 0.420043, 0.801635, 2.32881, 4.61923", \
"0.232829, 0.419292, 0.801235, 2.32726, 4.61976", \
"0.269691, 0.436516, 0.80301, 2.32964, 4.6192", \
"0.303951, 0.462626, 0.813595, 2.32785, 4.61489", \
"0.421533, 0.57954, 0.895068, 2.3323, 4.61298");
}

}
timing() {
related_pin : "B";
timing_sense : negative_unate;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.554929, 0.976479, 1.81616, 5.17228, 10.1974", \
"0.629978, 1.04934, 1.89074, 5.24558, 10.2703", \
"0.795079, 1.20666, 2.04109, 5.39734, 10.4204", \
"0.925071, 1.33446, 2.16913, 5.51393, 10.531", \
"1.36502, 1.76691, 2.5824, 5.91306, 10.92");
}
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.491132, 0.905994, 1.73427, 5.04952, 10.0136", \
"0.490454, 0.905396, 1.73657, 5.04979, 10.0136", \
"0.497818, 0.904821, 1.7334, 5.05064, 10.0136", \

67

"0.516587, 0.907567, 1.73579, 5.05051, 10.0122", \


"0.609389, 0.965452, 1.74177, 5.05042, 10.0136");

}
cell_fall(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.280459, 0.481118, 0.881526, 2.48354, 4.88639", \
"0.345653, 0.545813, 0.94576, 2.54842, 4.95094", \
"0.477669, 0.67722, 1.0766, 2.67771, 5.07867", \
"0.562143, 0.780184, 1.17489, 2.77453, 5.17513", \
"0.801546, 1.07407, 1.51321, 3.09244, 5.49962");
}
fall_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.2288, 0.419883, 0.801311, 2.3276, 4.61701", \
"0.233763, 0.419697, 0.801176, 2.32863, 4.61773", \
"0.287614, 0.444745, 0.801816, 2.32868, 4.61709", \
"0.330982, 0.486404, 0.816829, 2.32819, 4.61693", \
"0.467072, 0.634948, 0.944273, 2.33018, 4.61669");
}

}
internal_power() {
related_pin : "A";
rise_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.211461, 0.347829, 0.620221, 1.70934, 3.34284", \
"0.213685, 0.348766, 0.620457, 1.70923, 3.34261", \
"0.223269, 0.354603, 0.623488, 1.71045, 3.34328", \
"0.234123, 0.363938, 0.631198, 1.71416, 3.34455", \
"0.275467, 0.399396, 0.656958, 1.72936, 3.35421");
}
fall_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.12999, 0.265965, 0.538129, 1.62706, 3.26055", \
"0.129006, 0.265364, 0.537773, 1.62692, 3.26047", \
"0.122419, 0.261013, 0.534802, 1.62569, 3.25982", \
"0.115314, 0.255911, 0.531921, 1.62409, 3.2589", \
"0.083631, 0.230714, 0.514481, 1.61562, 3.25391");
}
}
internal_power() {
related_pin : "B";
rise_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.192587, 0.32959, 0.602377, 1.6918, 3.3254", \
"0.193535, 0.32954, 0.602024, 1.69183, 3.32561", \

68

"0.20171, 0.333647, 0.604009, 1.69262, 3.32604", \


"0.21182, 0.342728, 0.611681, 1.6958, 3.32697", \
"0.250299, 0.375565, 0.635476, 1.7106, 3.33587");

}
fall_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.129801, 0.265815, 0.537994, 1.62694, 3.26043", \
"0.128333, 0.264817, 0.537421, 1.62674, 3.26033", \
"0.122037, 0.2606, 0.534028, 1.62535, 3.25961", \
"0.114528, 0.254804, 0.530515, 1.6238, 3.25878", \
"0.084212, 0.231153, 0.513953, 1.61635, 3.25453");
}

/* --------------- *
* Design : NOR2_0 *
* --------------- */
cell (NOR2_0) {
area : 0.0;
cell_leakage_power : 0.00698316;
rail_connection( GND, RAIL_GND );
rail_connection( VDD, RAIL_VDD );
pin(A) {
direction : input;
input_signal_level : RAIL_VDD;
capacitance : 0.00486857;
rise_capacitance : 0.00470341;
fall_capacitance : 0.00486857;
rise_capacitance_range ( 0.00467616, 0.0050954) ;
fall_capacitance_range ( 0.00486512, 0.00511218) ;
max_transition : 1.2;
internal_power() {
rise_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.028821, 0.030323, 0.030833, 0.03098, 0.031082");
}
fall_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.034993, 0.035, 0.034995, 0.034949, 0.034958");
}
}
}
pin(B) {
direction : input;
input_signal_level : RAIL_VDD;
capacitance : 0.00318734;
rise_capacitance : 0.00318734;
fall_capacitance : 0.00315722;
rise_capacitance_range ( 0.00318693, 0.00535666) ;
fall_capacitance_range ( 0.00315692, 0.0053623) ;
max_transition : 1.2;

69

internal_power() {
rise_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.010381, 0.010379, 0.010379, 0.010378, 0.010374");
}
fall_power(passive_energy_template_5x1) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
values ("0.0128, 0.012808, 0.012815, 0.012802, 0.012802");
}
}

}
pin(Q) {
direction : output;
output_signal_level : RAIL_VDD;
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
rise_capacitance_range ( 0, 0) ;
fall_capacitance_range ( 0, 0) ;
max_capacitance : 0.0720316;
max_transition : 9.24144;
function : "(!(A+B))";
timing() {
related_pin : "A";
timing_sense : negative_unate;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.547516, 0.935139, 1.70782, 4.79785, 9.41791", \
"0.607189, 0.99352, 1.76694, 4.85419, 9.47698", \
"0.730444, 1.11342, 1.88155, 4.96637, 9.58888", \
"0.8289, 1.2062, 1.97174, 5.04814, 9.67208", \
"1.15975, 1.53611, 2.28407, 5.34648, 9.95796");
}
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.479529, 0.861839, 1.6248, 4.67723, 9.2414", \
"0.479473, 0.860809, 1.62476, 4.67433, 9.24102", \
"0.491936, 0.861785, 1.62247, 4.67348, 9.24138", \
"0.511461, 0.870286, 1.62249, 4.67063, 9.24144", \
"0.604523, 0.933556, 1.64376, 4.67335, 9.24137");
}
cell_fall(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.36032, 0.588062, 1.04263, 2.85164, 5.57359", \
"0.428871, 0.656374, 1.11063, 2.92244, 5.64175", \
"0.573686, 0.798145, 1.24974, 3.0561, 5.77683", \
"0.6853, 0.907117, 1.35665, 3.16031, 5.87216", \
"1.00879, 1.27302, 1.71962, 3.51885, 6.22358");
}

70

fall_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.285207, 0.496008, 0.917861, 2.60004, 5.13371", \
"0.284989, 0.495869, 0.917996, 2.60396, 5.13364", \
"0.319267, 0.505362, 0.916966, 2.59975, 5.1327", \
"0.36473, 0.532798, 0.920925, 2.60013, 5.12558", \
"0.512662, 0.679111, 1.00776, 2.60527, 5.1302");
}

}
timing() {
related_pin : "B";
timing_sense : negative_unate;
cell_rise(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.523833, 0.911446, 1.68209, 4.77115, 9.39446", \
"0.595737, 0.980745, 1.7532, 4.84106, 9.4627", \
"0.748447, 1.12926, 1.89752, 4.98111, 9.60084", \
"0.867411, 1.2462, 2.00908, 5.09015, 9.70583", \
"1.26375, 1.64437, 2.388, 5.44499, 10.0612");
}
rise_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.479645, 0.861849, 1.62267, 4.67392, 9.24096", \
"0.479437, 0.860848, 1.62454, 4.67539, 9.24102", \
"0.49385, 0.860117, 1.62398, 4.67573, 9.24143", \
"0.520064, 0.869252, 1.62295, 4.67769, 9.24102", \
"0.627383, 0.948604, 1.64593, 4.67366, 9.2407");
}
cell_fall(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.328274, 0.555783, 1.00882, 2.82096, 5.53864", \
"0.396904, 0.626276, 1.07833, 2.88763, 5.61916", \
"0.540911, 0.76628, 1.22074, 3.0358, 5.74272", \
"0.649312, 0.873882, 1.32423, 3.14082, 5.84489", \
"0.950883, 1.23134, 1.68361, 3.48605, 6.19619");
}
fall_transition(delay_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.253344, 0.464545, 0.885712, 2.57164, 5.10169", \
"0.25387, 0.465578, 0.886176, 2.57035, 5.11258", \
"0.292238, 0.475455, 0.888162, 2.58017, 5.10104", \
"0.338985, 0.504912, 0.889932, 2.58128, 5.10071", \
"0.478711, 0.655583, 0.980858, 2.57326, 5.10267");
}
}

71

}
}

internal_power() {
related_pin : "A";
rise_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.220287, 0.356725, 0.62923, 1.71828, 3.35181", \
"0.22072, 0.356877, 0.629226, 1.71832, 3.35185", \
"0.228853, 0.36284, 0.633007, 1.71991, 3.35269", \
"0.238745, 0.370162, 0.638044, 1.72205, 3.35387", \
"0.281126, 0.404795, 0.663779, 1.73584, 3.36201");
}
fall_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.112595, 0.248742, 0.521002, 1.61001, 3.24352", \
"0.112076, 0.248599, 0.521136, 1.61035, 3.24393", \
"0.105125, 0.243976, 0.518044, 1.6094, 3.24374", \
"0.097177, 0.238016, 0.513977, 1.60781, 3.24323", \
"0.059034, 0.208517, 0.494105, 1.59683, 3.23708");
}
}
internal_power() {
related_pin : "B";
rise_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.200357, 0.336886, 0.609404, 1.69861, 3.33216", \
"0.202477, 0.338043, 0.609988, 1.69881, 3.33225", \
"0.211584, 0.345112, 0.614656, 1.70059, 3.33317", \
"0.220795, 0.35305, 0.620215, 1.70324, 3.33462", \
"0.262322, 0.385368, 0.641783, 1.71262, 3.34237");
}
fall_power(energy_template_5x5) {
index_1 ("0.06, 0.18, 0.42, 0.6, 1.2");
index_2 ("0.025, 0.05, 0.1, 0.3, 0.6");
values ( \
"0.125769, 0.261388, 0.533315, 1.62207, 3.2555", \
"0.124656, 0.260271, 0.532446, 1.62159, 3.25494", \
"0.118955, 0.255914, 0.529145, 1.62009, 3.25453", \
"0.11133, 0.251194, 0.525336, 1.61841, 3.25395", \
"0.078347, 0.225373, 0.508564, 1.60749, 3.24715");
}
}

VITA

Enes Mahmut Ouzhan TRK was born in STANBUL, 1990.

He studied the

primary in Akasya College. After he completed his work at Akasya College High
School in 2007 with rank of 2nd, he entered to T.C. OKAN UNIVERSITY. He
studied in Electrical and Electronics Engineering and received his Bachelor of
Engineering degree by graduating with Certicate of Honor in 2012. During the
summers of 2009 and 2010 he worked as an intern to D&T Inc.
Inc.

and ATEKSIS