PHILIPS Service Manual

Published by KC-TE 0718 V&MA Printed in the Netherlands Subject to modication EN 3139 785 32804
DVDR3570H/75/97
DVDR3590H//75/97/93
HDD & DVD Recorder
CLASS 1
LASER PRODUCT
Contents Page
1 Technical Specications and Connection
Facilities 2
2 Safety Information, General Notes & Lead
Free Requirements 5
3 Directions for Use 7
4 Mechanical Instructions 10
5 Firmware Upgrading, Diagnostic Software,
Alignment and Test Procedures 14
6 Block Diagrams,Waveforms, Wiring Diagram 95
Overall block diagram 95
Wiring diagram 96
Waveforms of Analog Board 97
Waveforms of Digital Board 98
Waveforms of HDMI Board 99
Test Points Overview for HDMI Board 100
Test Points Overview for Analog Board 101
Test Points Overview for Digital Board 102
Contents Page
7 Circuit Diagrams and PWB Layout 103
Analog Circuit Diagrams 103
Analog Layout Diagrams 106
Front Circuit Diagrams 108
Front Display/Connector Layout Diagrams 110
Front Standby Circuit & Layout Diagrams 111
LecoPlus INIT Circuit & Layout Diagrams 112
Digital Circuit Diagrams 113
Digital Layout Diagrams 121
HDMI Circuit Diagrams 123
HDMI Layout Diagrams 127
8 IC Internal Block Diagrams 129
Analog Board 129
Digital Board 131
HDMI Board 140
9 Exploded view & Service parts list 158
Exploded View of the set 158
Service parts list 159
10 Revision list 160
Copyright 2007 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.

All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Version 1.4
http: / / www. j dwxzl w. com/ ?f romuser=

EN 2 3139 785 32804 1. Technical Specications and Connection Facilities
1. Technical Specications and Connection Facilities
1.1 PCB Locations
1.2 General:
Power supply : 220-240V, ~50 Hz

Power consumption
DVDR3570H : 28 W
DVDR3590H : 35 W
Standby power consumption : < 3.7 W

1.3 RF Tuner (Analogue)
Test equipment: Fluke 54200 TV Signal generator
Test streams: Philips Standard test pattern
1.3.1 System
B/G, I, L/L, D/K
1.3.2 RF - Loop Through:
Frequency range : 43 MHz 860 MHz
Gain (ANT IN ANT OUT)
without amplier : -4dB 2dB
Gain (ANT IN ANT OUT)
with amplier : From 2dB + 3dB until
2dB 2dB
1.3.3 Receiver:
Output of Cinch connector to be used for measurements
(direct output from front end)

Video Performance:
Frequency Response : 0 4dB (0 to 4.4 MHz)

Group Delay : 0 150 n sec
(0 to 4.4 MHz)
Audio Performance:
Audio analogue Mono :
Frequency Response relative to
1 kHz : 0 3dB
(100 Hz to 12 kHz)
S/N unweighted : 40dB (Quasi peak,
22 Hz 22 kHz)
S/N weighted : 45dB (Quasi peak,
CCIR 468)
Harmonic distortion at 1 kHz : 1.5% (FM: 25 kHz)
Harmonic distortion at 1 kHz : 2 %
(AM: m = 54% L/L)
Audio NICAM Stereo/Dual :
Frequency Response relative to
1 kHz : 0 3dB
(40 Hz to 15 kHz)
S/N unweighted : 65dB (Quasi peak,
22 Hz 22 kHz)
S/N weighted : 70dB (Quasi peak,
CCIR 468)
Harmonic distortion at 1 kHz : 0.5% (Headroom:
System I 21.1dB,
all others 16.5dB)
Channel Separation : 45dB
1.3.4 Tuning
Tuning Frequency Range : 45.25 MHz 857 MHz
Antenna Level for 40dB luminance
S/N (video unweighted) at 75 : 40dBV (High End)
60dBV (Low End)
Automatic Search Tuning:
Scanning time auto search without
RF Signal : < 2.5 min.
(Typical 3 minutes)
Stop level (vision carrier) : 40dBV
Maximum tuning error during
operation (drift) : 100 kHz
Maximum tuning error of a recalled
program : 62.5 kHz
Analog Board
HDMI
Board
Front Board (Behind the
Front Cabinet)
HDD
Digital Board
PSU
Board
Basic Engine
Standby Board (Behind
the Front Cabinet)

Tuning Principles:
Automatic system recognition
Manual Selection in Store mode
Storage of frequencies at each random
position number
1.4 Analog Inputs / Outputs
1.4.1 Audio/Video Front Input Connectors
(CAM 1) AUDIO Cinch (L/R):
Input voltage : 2.2Vrms max
Input impedance : > 10k
(CAM1) VIDEO Cinch:
Input voltage : 1Vpp 3dB
Input impedance : 75
1.4.2 Audio/Video Rear Input Connectors
AUDIO IN (AUDIO 1/2) Cinch (L/R):
Input voltage : 2.2Vrms max
Input impedance : > 10k
CVBS IN (VIDEO IN) Cinch:
Input voltage : 1Vpp 3dB
Input impedance : 75
S-VIDEO IN (VIDEO IN) Hosiden:
According to IEC 933-5
Superimposed DC-level on pin 4 (load > 100k)
< 2.4V is detected as 4:3 aspect ratio
> 3.5V is detected as 16:9 aspect ratio
Input voltage Y : 1Vpp 3dB
Input impedance Y : 75
Input voltage C : 300mVpp 3dB
Input impedance C : 75
COMPONENT VIDEO IN Cinch (Y/Pb/Pr):
According to EIO-770-I-A, EIA-770-2

1.4.3 Audio/Video Output Connectors
(AUDIO OUT) AUDIO Cinch (L/R):
Output voltage : 2Vrms max
Output impedance : > 10k
(VIDEO OUT) CVBS OUT Cinch:
Output voltage : 1Vpp 3dB
Output impedance : 75
(VIDEO OUT) S-VIDEO OUT - Hosiden:
According to IEC 933-5
Superimposed DC-level on pin 4 (load > 100k)
< 2.4V is detected as 4:3 aspect ratio
> 3.5V is detected as 16:9 aspect ratio
Output voltage Y : 1Vpp 3dB
Output impedance Y : 75
Output voltage C : 300mVpp 3dB
Output impedance C : 75
COMPONENT VIDEO OUT Cinch (Y/Pb/Pr):
According to EIA-770-1-A, EIA-770-2-A
1.5 Digital Inputs / Outputs
1.5.1 CAM 2 DV IN (IEEE 1394 Digital Video Input)
Implementation Standard according:
IEEE Std 1394-1995
IEC61883 - Part1
IEC61883 - Part 2 SD-DVCR (02-01-1997)
Specication of consumer use digital VCRs using 6.3mm
magnetic tape dec.1994
Mechanical connection according to Annex of IEC 61883-1
1.5.2 (AUDIO OUT) COAXIAL DIGITAL OUT Cinch
LPCM : according IEC 60958
MPEG 1, MPEG 2, AC3 : according IEC 61937
DTS : according IEC 61937 +
addendum
1.5.3 USB
Compatibility : USB 2.0
Type of connector : Series A Connector
1.5.4 HDMI Output
Compatibility : HDMI version 1.1
Type of connector : Type A connector
(19 pins)
1.6 Video Performance
1.6.1 SNR
PAL
RGB CVBS Y/C
55 dB Lumincance: 55 dB
Chroma: 55 dB (AM)
52 dB (PM)
Y: 57 dB
C: 57 dB (AM)
54 dB (PM)
NTSC
Y Pb Pr CVBS Y/C
55 dB Lumincance: 55 dB
Chroma: 54 dB (AM)
54 dB (PM)
Y: 55 dB
C: 54 dB (AM)
54 dB (PM)
1.6.2 Bandwidth
PAL
RGB CVBS Y/C
0.5 to 4 MHz:+1dB/
-2dB
0.5 to 4 MHz:+1dB/
-2dB
Y:4.8MHz-3dB
4.8 MHz:-3dB 4.8 MHz:-3dB C:700 kHz
5.8 MHz:-6dB 5.8 MHz:-6dB
NTSC
YPbPr CVBS Y/C
4.2 MHz:-3dB 4.2 MHz:-3dB Y:4.2MHz-3dB
5.8 MHz:-6dB 5.8 MHz:-6dB C: 700 kHz
With Pscan:
8.4MHz -3dB

1.7 Audio Performance CDDA (PCM)
1.7.1 Cinch Output Rear
Output voltage : 1.8Vrms 2dB
Channel unbalance : < 0.22dB
Crosstalk 1kHz : > 110 dB
Crosstalk 16Hz 20kHz : > 110 dB
Signal to noise ratio (unweighted)
20Hz 20kHz bandwidth limited : > 95dB (mute)
Signal to noise ratio (A-weighted)
RMS 20Hz 20kHz
bandwidth limited : > 112dBA (mute)
Dynamic range 1kHz : > 90dB
Distortion and noise 1kHz : > 85dB
Distortion and noise 16Hz 20kHz : > 78dB
Mute (spin-up, pause, access) : > 78dB

1.8 Dimension and Weight
Set Dimension W x H x D : 435 x 43 x 324 mm
Net Weight : 3.8 kg
1.9 Laser Output Power & Wavelength
1.9.1 DVD
Output power during reading : 1.0mW
Output power during writing : 69mW
Wavelength : 658nm (at 25 C)
1.9.2 CD
Output power : 1.2mW
Wavelength : 783nm (at 25 C)
1.10 Playability
Video Playback
1. Playback Media:
CD-R/CD-RW, DVD+R/+RW,
DVD-R/-RW, DVD-Video, Video
CD/SVCD, DVD+R DL, DVD-R
DL, USB ash drive
x
2. Compression Formats:
MPEG2, MPEG1, DivX 3.11, DivX
4.x, DivX 5.x, DivX 6.0, MPEG4
x
Audio Playback
1. Playback Media:
Audio CD, CD-R/RW, DVD+R DL,
DVD+R/+RW, DVD-R/-RW, MP3-
CD, MP3-DVD, USB ash drive,
WMA-CD
x
2. Compression Format:
Dolby Digital, MP3, MPEG2
Multichannel, PCM, WMA
x
3. MPEG1 bit rates: 64-384 kbps
and VBR
x
Still Picture Playback
1. Playback Media: CD-R/RW,
DVD+R DL, DVD+R/+RW, DVD-
R/-RW, Picture CD, USB Digital
Camera (PTP), USB ash drive
x
2. Picture Compression Format:
JPEG, JPEG digital camera
photos
x
3. Picture enhancement: Slideshow
with MP3 playback, Create
albums, Rotate, Slideshow with
music playback, Zoom
x
1.11 Supported Disc Types and Media Speed for
Recording
Disc Media Speeds
DVD+R 1x - 16x
DVD+RW 2.4x - 8x
DVD-R 1x - 16x
DVD-RW 2.4x - 4x
DVD+R DL 2.4x
1.12 Diversity Matrix
DVDR3570H DVDR3590H
Hard Disk capacity 160 GB 250 GB

EN 5 3139 785 32804 2. Safety Information, General Notes & Lead Free Requirements
2.1 Safety Instructions
2.1.1 General Safety
Safety regulations require that during a repair:
Connect the unit to the mains via an isolation transformer.
Replace safety components, indicated by the symbol ,
only by components identical to the original ones. Any
other component substitution (other than original type)
may increase risk of re or electrical shock hazard.
Safety regulations require that after a repair, you must return
the unit in its original condition. Pay, in particular, attention to
the following points:
Route the wires/cables correctly, and x them with the
mounted cable clamps.
Check the insulation of the mains lead for external
damage.
Check the electrical DC resistance between the mains
plug and the secondary side:
1. Unplug the mains cord, and connect a wire between
the two pins of the mains plug.
2. Set the mains switch to the on position (keep the
mains cord unplugged!).
3. Measure the resistance value between the mains
plug and the front panel, controls, and chassis
bottom.
4. Repair or correct unit when the resistance
measurement is less than 1 M.
5. Verify this, before you return the unit to the customer/
user (ref. UL-standard no. 1492).
6. Switch the unit off, and remove the wire between the
two pins of the mains plug.
2.1.2 Laser Safety
This unit employs a laser. Only qualied service personnel
may remove the cover, or attempt to service this device (due
to possible eye injury).
Laser Device Unit
Type : Semiconductor laser
GaAlAs
Wavelength : 650 nm (DVD)
: 780 nm (VCD/CD)
Output Power : 20 mW
(DVD+RW writing)
: 0.8 mW
(DVD reading)
: 0.3 mW
(VCD/CD reading)
Beam divergence : 60 degree

CLASS 1
LASER PRODUCT
Figure 2-1
Note: Use of controls or adjustments or performance of
procedure other than those specied herein, may result in
hazardous radiation exposure. Avoid direct exposure to beam.
2.2 Warnings
2.2.1 General
All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD, ). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are at the same potential as the mass
of the set by a wristband with resistance. Keep
components and tools at this same potential.
Available ESD protection equipment:
Complete kit ESD3 (small tablemat, wristband,
connection box, extension cable and earth cable)
4822 310 10671.
Wristband tester 4822 344 13999.
Be careful during measurements in the live voltage
section. The primary side of the power supply, including
the heatsink, carries live mains voltage when you
connect the player to the mains (even when the
player is off!). It is possible to touch copper tracks and/
or components in this unshielded primary area, when
you service the player. Service personnel must take
precautions to prevent touching this area or components
in this area. A lightning stroke and a stripe-marked
printing on the printed wiring board, indicate the primary
side of the power supply.
Never replace modules, or components, while the unit is
on.
2.2.2 Laser
The use of optical instruments with this product, will
increase eye hazard.
Only qualied service personnel may remove the cover or
attempt to service this device, due to possible eye injury.
Repair handling should take place as much as possible
with a disc loaded inside the player.
Text below is placed inside the unit, on the laser cover
shield:
Figure 2-2
2. Safety Information, General Notes & Lead Free Requirements
CAUTION VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM
ADVARSEL SYNLIG OG USYNLIG LASERSTRLING VED BNING UNDG UDSTTELSE FOR STRLING
ADVARSEL SYNLIG OG USYNLIG LASERSTRLING NR DEKSEL PNES UNNG EKSPONERING FOR STRLEN
VARNING SYNLIG OCH OSYNLIG LASERSTRLNING NR DENNA DEL R PPNAD BETRAKTA EJ STRLEN
VARO! AVATTAESSA OLET ALTTIINA NKYVLLE JA NKYMTTMLLE LASER STEILYLLE. L KATSO STEESEEN
VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEFFNET NICHT DEM STRAHLAUSSETSEN
DANGER VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID DIRECT EXPOSURE TO BEAM
ATTENTION RAYONNEMENT LASER VISIBLE ET INVISIBLE EN CAS DOUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU

EN 6 3139 785 32804 2. Safety Information, General Notes & Lead Free Requirements
2.3 Lead Free Requirement
Information about Lead-free produced sets
Philips CE is starting production of lead-free sets from
1.1.2005 onwards.
INDENTIFICATION:
Regardless of special logo (not always indicated)
One must treat all sets from 1 Jan 2005 onwards, according
next rules.
Example S/N:

Bottom line of typeplate gives a 14-digit S/N. Digit 5&6 is the year, digit 7&8 is
the week number, so in this case 1991 wk 18
So from 0501 onwards = from 1 Jan 2005 onwards
Important note: In fact also products of year 2004 must be treated in this way as long as you
avoid mixing solder-alloys (leaded/ lead-free). So best to always use SAC305 and the higher
temperatures belong to this.
Due to lead-free technology some rules have to be respected by the
workshop during a repair:
Use only lead-free solder alloy Philips SAC305 with
order code 0622 149 00106. If lead-free solder-pate
is required, please contact the manufacturer of your
solder-equipment. In general use of solder-paste within
workshops should be avoided because paste is not easy
to store and to handle.
Use only adequate solder tools applicable for lead-free
solder alloy. The solder tool must be able
o To reach at least a solder-temperature of 400C,
o To stabilize the adjusted temperature at the solder-
tip
o To exchange solder-tips for different applications.
Adjust your solder tool so that a temperature around
360C 380C is reached and stabilized at the solder
joint. Heating-time of the solder-joint should not exceed
~ 4 sec. Avoid temperatures above 400C otherwise
wear-out of tips will rise drastically and ux-uid will be
destroyed. To avoid wear-out of tips switch off un-used
equipment, or reduce heat.
Mix of lead-free solder alloy / parts with leaded solder
alloy / parts is possible but PHILIPS recommends strongly
to avoid mixed solder alloy types (leaded and lead-free).
If one cannot avoid or does not know whether product is
lead-free, clean carefully the solder-joint from old solder
alloy and re-solder with new solder alloy (SAC305).
Use only original spare-parts listed in the Service-
Manuals. Not listed standard-material (commodities) has
to be purchased at external companies.
Special information for BGA-ICs:
- always use the 12nc-recognizable soldering temperature
prole of the specic BGA (for de-soldering always use
the lead-free temperature prole, in case of doubt)
- lead free BGA-ICs will be delivered in so-called dry-
packaging (sealed pack including a silica gel pack) to
protect the IC against moisture. After opening, dependent
of MSL-level seen on indicator-label in the bag, the
BGA-IC possibly still has to be baked dry. (MSL=Moisture
Sensitivity Level). This will be communicated via AYS-
website.
Do not re-use BGAs at all.
For sets produced before 1.1.2005 (except products of
2004), containing leaded solder-alloy and components,
all needed spare-parts will be available till the end of the
service-period. For repair of such sets nothing changes.
On our website www.atyourservice.ce.Philips.com
you nd more information to:
BGA-de-/soldering (+ baking instructions)
Heating-proles of BGAs and other ICs used in Philips-
sets
You will nd this and more technical information within
the magazine, chapter workshop news.
For additional questions please contact your local repair-helpdesk.

EN 7 3139 785 32804 3. Directions For Use
3. Directions For Use
The following except of the Quick Use Guide serves as an introduction to the set.
The Complete Direction for the Use can be downloaded in different languages from the internet site of Philips Customer care Center:
www.p4c.philips.com
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EN 10 3139 785 32804 4. Mechanical Instructions
4. Mechanical Instructions
Note: The position numbers given here refers to the
Exploded view on chapter 8.
4.1 Dismantling of the DVD Tray cover manually
1) Insert a screwdriver into the slot provided at the bottom
of the set and push in the direction as shown in Figure1 to
unlock before sliding the Tray cover 110 out.
Figure 4-1: Unlock the tray loader
2) Remove the Tray cover 110 as shown in Figure 2.
Figure 4-2: Remove the tray cover
4.2 Dismantling of the Front Panel
1) Remove 7 screws to loosen Top cover 240.
2) Remove 2 screws to loosen the Plate Front Loader 183
and detach the Front Cabinet Assembly P001 as shown
in Figure 3. The Front Panel Service Position is shown in
Figure 4.
Figure 4-3: Unscrew the screws to detach front panel
Figure 4-4: Front Panel Service Position
4.3 Dismantling of the Basic Engine
1) Remove 4 mounting screws as shown in gure 5 to
dismantle the Basic Engine. 1007.
Figure 4-5: Basic Engine mounting screw
1
2
Insulation Sheet
Insulation Sheet

2) Flip the Basic Engine over to remove 4 screws from
the PCB protection plate. Service Position of the Basic
Engine is shown in Figure 6.
Figure 4-6: Basic Engine Service Position
4.4 Dismantling of the PSU Board
1) Remove 3 screws to loosen the PSU Board 1004 as
shown in Figure 7.
Figure 4-7: PSU remove mounting screws
Insulation Sheet
2) Service position for PSU Board is given in Figure 8.
Figure 4-8: PSU Board Service Position
4.5 Dismantling of the HDD
1) Remove 4 screws to loosen the HDD assembly (HDD
1005 and HDD Bracket 186 attached together by the
screws 271, for DVDR3590H there also includes HDD
Damper 191 and HDD Suspension Bracket 192) as
shown in gure 9.
Figure 4-9: Remove mounting screws for HDD
2) Flip over the HDD Assembly to see the mounting screws
271. Remove the screws to dismantle the HDD 1005 from
the HDD assembly.
Notes: Only the special type of screws as described in
Service Parts List must be used for position number 271.
Using improper screws may damage the mounting holes on
the HDD.
.
Insulation Sheet

4.6 Dismantling of HDMI Board
1) Remove 2 screws to loosen the HDMI Board 1006 and
HDMI Shield 190 form the Rear Plate 230. The mounting
screws are shown in gure 10.
Figure 4-10: Remove mounting screws for HDMI Board
2) Remove the HDMI Shield 190 for HDMI Board Service
Position. The HDMI Board Service Position is shown in
gure 11.
Figure 4-11: HDMI Board Service Position.
Insulation
Sheet
4.7 Dismantling of the Digital Board
1) Remove the HDMI Board rst, and remove the HDMI
Bracket 131 by unscrewing one screw.
2) Then remove 4 screws to loosen the Digital Board 1003
as shown in Figure 12.
Figure 4-12: Remove mounting screws for Digital Board

4.8 Dismantling of the Analog Board
1) Remove the HDMI Board 1006 with its Shield 190 and
the HDMI bracket 189 rst. Remove 3 screws that attach
the Analog Board 1001 to the Frame 161. Remove 6
more screws that attach the Analog Board 1001 to the
rear panel 230. Then dismantle the Analog Board. It may
be easier to dismantle the Analog Board if the rear panel
230 is detached rst by removing 3 more screws.
2) Service position for Analogue Board is given in Figure 12.
Figure 4-14: Analogue Board Service Position (Rear Plate
230 detached)
3) Service position for Digital Board is given in Figure 13. (It
may be necessary to remove the Digital Board Bracket
187 and take out the cables beneath it to make it easier to
ip over the digital board. Put the insulation sheets under
the PC Boards. Refer to the set-wiring diagram in chapter
6 and make it sure to have the correct cable connections
among the PC Boards.)
Figure 4-13: Digital Board Service Position
Insulation
Sheet
Insulation
Sheet
Insulation
Sheet

EN 14 3139 785 32804 Firmware Upgrading & Diagnostic Software 5.
5.1 Firmware Upgrading
5.1.1. Preparation to upgrade rmware
1. Unzip the zip-archive le
2. Start the CD Burning software and create a new CD project (data disc) with the following settings:
File system: Joliet
Format: MODE 2: CDROM XA
Recording mode: SINGLE SESSION (TRACK-AT-ONCE), FINALIZED CD
Note: Long le name is necessary for the preparation of the upgrade disc
3. Place the content of the zip-archive into the root directory of the new CD project.
4. Burn the data onto a blank CDR or CD-RW
5.1.2. Procedure to apply the rmware upgrade:
Notes: There are 2 upgrade processes supported: - Normal Upgrade and Forced Download.
For normal upgrading, power up the set, open the tray, insert the upgrade disc, close the tray and follow the on screen
instruction. For forced download upgrading, follow the procedures described below.

1. Hold the <Record> + <Next> buttons down and Power up the set.
2. The tray opens and set will display:
DOWNLOAD >.PUT DISC
3. Insert the prepared Upgrade CDROM and close the tray.
4. The set will display:
INIT DSC > DOWNLOAD >.
The whole process takes less than 10 minutes
Note: Do not press any buttons or interrupt the mains supply during the upgrading process, otherwise the set may
becomes defective.
5. When the upgrade is completed the tray will open automatically and the set will display:
REMOVE
6. Close the tray and the set will display:
DONE
Then the rmware upgrade process is completed successfully.
5.1.3. How to read out the rmware version to conrm set has been upgraded:
Notes: In order to check the rmware version of the set, user version info screen should be accessed. Follow the
procedure below for checking user version info screen.
1. Power up the set
2. Press <OPTIONS> button on the Remote control and go to <Settings> option
3. Then go to <Setup> and choose <Version Info> by pressing OK.
4. The TV connected to the set will display the user version info as shown below for checking software version:
Version Info
Royal Philips
DVDR3570H
Software version: 01.00
Please visit our website
www.philips.com/support
for further software
updates and additional information

Developer name: Royal Philips
Product name (xxxx = model number): DVDRxxxxH (DVDR3570H in the example above)
Ofcial SW release number: Software Version (xx.xx = release): xx.xx (01.00 in the example above)
5. Press <OPTIONS> button to exit.
5. Firmware Upgrading and Useful Firmware Hints, Diagnostic
Software, Alignment and Test Procedures

EN 15 3139 785 32804 5. Firmware Upgrading & Diagnostic Software
5.2. Procedure for checking Development Version Info Screen
Notes: For detail software information such as Slash Version, Drive Software Version, etc of the set,
the development version info screen should be accessed.
1) Power up the set
2) Press <OPTIONS> button on the Remote control and go to <Settings> option
3) Then go to <Setup> and choose <Version Info> by pressing OK.
4) When the user version info screen is appeared, press the blue key on the remote control.
5) The TV connected to the set will display the Development Version Info Screen as shown below:
Version Info
(c)PHILIPS 2006 Version Information:
DI L+06_7/751731 SV 11602
BE 52.07.02.15 ASP 1,18,1,10
C1_7 20070224_1659 pro lecoplusleadV2 <void>
EPG: DPMS:P_DPM
Digital Board Info: (DI: Digital Board, L+06_7: Digital Board name, 75: Hardware ID for EU Non EPG, 1731: SW
BUILD ID for recorder application in the example)
Slash Version (xxxxx = version): SV xxxxx (11602 for /51 in the example above)
Drive SW Version (yy.yy = model, xx.xx = version): BE yy.yy.xx.xx (Model 52.07, Version 02.15 in the example)
ASP Software and VFD Driver Version Number: (1,18: ASP software version number, 1,10: version number of
VFD Driver
Detailed Build Information: (C1_7: Branch Information, 2007: year, 02: month, 24: date, 16: Hour, 59: minute in
the above example)
EPG: DPMS:P_DPM (internal to the recorder application.)
5.3 Procedure for Formatting HDD drive
1) Press and Hold the <Previous> + <Stop> key combination while powering on the mains.
2) The set will start to display FMT KEY, and then it will show FMT HDD while formatting HDD.
3) If the formatting is completed successfully, the set will display FMT DONE. If the formatting is failed, it will show FMT FAIL
Notes: Do not power off the set immediately when the FMT DONE is seen. Wait until the time or - - : - - is displayed before powering
off the set.
5.4. Procedure to Virginize the set
Notes: All the user information will be lost after virginizing the set. Follow the procedure below to virginize the set.
1) Press and hold down the Standby key on the front while connecting to the power outlet.
2) Release the keys when the scrolling messages appear on VFD.
3) Press standby key again and follow the instructions when the set wakes up.
5.5 HDD replacement procedure.
When a defective HDD is replaced by a brand new HDD,
1. Install the new HDD.
2. Upgrade the software (forced download) with the upgrade disc to the latest software (follow the procedures described in 5.1.2)
3. Format the HDD (follow the procedures described in 5.3)
Then the HDD is ready to use. Some of the user information may be lost after HDD Replacement.

Diagnostic Softwa re
D ue to the co mplexity of the DVD rec order, the time to find a
de fect in the rec order can become long. To r educe this ti me ,
the recorder has been equipped wi th D iagn ostic and Serv ice
so ft ware (DS ). Th e DS o ff ers functionali ty t o diagnose the
DV DR hardware and te st s th e fo ll owing:
I nterconnec tions between co mponent s
A cc essibility of com ponents
F unctionality of the audio and video paths
This f unc tionalit y ca n be acces sed via se veral in terf aces :
1. End user/Dealer script interfa ce
2. Comm and Inte rfac e
Fi gu re 5-1
The En d use/Dealer scr ip t ex ecutes all diagnostic nuc lei t ha t
do not ne ed any use r interaction and are meaningful on a
standalone DV D re corder.
Hold k ey <PLAY> pressed
while you plug the recorder
Unplug the power cord
SET O.K.?
YE S
NO
To ex it DEALER SCRIPT, unplug the power cord
During the test, the display will show
the a sequence of nuclei under test
TR 18029_001
120304
The End user/Dealer script interface gives a diagnosis on a
stand alone DVD recorder. During this mode, a number of
hardware tests (nuclei) are automatically executed to check if
the recorder is faulty. The diagnosis is simply a "fail" or "pass"
message. If the message "FAIL" appears on the display, there
is apparently a failure in the recorder. If the message "PASS"
appears, the nuclei in this mode have been executed
successfully. There can be still a failure in the recorder
because the nuclei in this mode do not cover the complete
functionality of the recorder.
Included tests: 1. DS_CHR_DEVTYPEGET_NUC
2. DS_SDRAM_WRITEREADFAST_NUC
3. DS_FLASH_DEVTYPEGET_NUC
4. DS_FLASH_CHECKSUMPROGRAM_NUC
5. DS_VIP_COMMUNICATION_NUC
6. DS_VIP_DEVTYPEGET_NUC
7. DS_DVIO_LINKDEVTYPEGET_NUC
8. DS_DVIO_PHYCOMMUNICATION_NUC
9. DS_DVIO_PHYDEVTYPEGET_NUC
10. DS_BE_COMMUNICATIONECHO_NUC
11. DS_BE_VERSIONGET_NUC
12. DS_SYS_HARDWAREVERSIONGET_NUC
13. DS_SYS_SOFTWAREVERSIONBOOTGET_NUC
14. DS_SYS_SOFTWAREVERSIONDOWNLOADGET_NUC
15. DS_SYS_SOFTWAREVERSIONAPPLGET_NUC
16. DS_SYS_DVIDNUMBERGET_NUC
17. DS_SYS_SLASHVERSIONGET_NUC
18. DS_SYS_SETTINGSDISPLAY_NUC
19. DS_SYS_BUILDINFOGET_NUC
20. DS_ASP_COMM_NUC
21. DS_ASP_VERSION_NUC
22. DS_FRE_COMM_NUC
23. DS_HDD_COMMUNICATION_NUC
24. DS_HDD_VERSION_NUC
25. DS_USB_DEVTYPEGET_NUC
5.6 End User/Dealer Script Interface
5.6.1 Description
5.5.2 Structure
5.6.2 Contents

22 DTTM*
23 USB
5.7 Menu and Command Mode Interface
5.7.1 Nuclei Numeration
Each nucleus has a unique number of four digits. This number
is the input of the command mode.
Figure 5-2
Group number Group name
[ XX YY ]
Nucleus number
Nucleus group number
CL 06532152_012.eps
051200
5.7.3 Command Mode Interface
Se t-Up Physical Interface Component s
Har dware required:
S ervice P C
o ne free CO M po rt on the Serv ic e PC
s pecial c able to c onnect D VD re corder to Ser vice PC
The ser vice PC must have a terminal em ul at ion program (e.g.
Hy perterminal) in stalled and mu st hav e a fr ee C OM port ( e.g.
CO M1 ). A ctiv at e the te rm inal em ulation program and chec k
that the port s ettings for th e free CO M por t are: 19200 bps, 8
data bit s, no pa rity, 1 s top bit a nd no flow c ontro l. T he fr ee C OM
por t mus t be c onnected via a s pecial c able to the RS 232 port
of the DVD recor der. Thi s s pecial ca bl e will also connec t the
test pin, which is available on the connec tor , t o ground (i.e.
ac tivat e test pin).
Code number of PC interface cable : 3122 785 90017
Act ivation of Diagnostic Software
1. Pu ll the ma ins co rd from t he re corder and reconnec t it
a gai n (reboo t) .
2. The next welc ome mes sage wi ll a ppear on t he PC :
Welcome screen D&S program
Fi gu re 5-4
Now , the prom pt 'DS :>' wil l appear . The diagnostic software is
now ready t o re ceive comm ands. The com mands t hat can be
give n are th e num bers of the nuclei. If you see above shown
sc reen, c ontinue with paragraph 'Nuclei Cod es'.
5.7.2 Error Handling
Ea ch nucleus returns an er ror code. This c ode c ontains six
num erals, w hi ch m eans:
Fi gu re 5-3
The nucleus group number s an d nuc leus num bers are the
sa me as above.
[ XX YY ZZ ]
Error code
Nucleus number
Nucleus group numbe r
CL 06532152_013.ep s
05 12 00
1 Codec (e.g. LeCo
+
)
0 Scripts
2 Boot EEPROM*
3 NVRAM (EEPROM of FLASH)*
4 SDRAM (or DDR-RAM)
5 FLASH
6 Video Input Processor
7 DVIO
9 Basic Engine
12 System
15 HDMI
16 Analogue Slave Processor
20 Front End
21 Hard Disk
* Not applicable for DVDR3570H,

3. It is possible that the next messages will appear when
starting the DVD+RW for the first time
Error messages D&S program
Figure 5-5a
Error messages D&S program
Figure 5-5b
In these cases, the boot EEPROM of the Digital Board does not
contain the required string with the hardware information. To
update the Digital Board with the correct string, nucleus 1226
must be executed.
See next section 'Diversity String Input'.
There can also be the next error message.
Figure 5-5c
Enter "Y" to program a safe string. With this automatically
generated string the board will work in principle but it has to be
checked if all board settings were detected correctly.
Diversity String Input
4. Execute nucleus 1226 to enter the string. Please see
chapter 8 for details
Nucleus 1226 execution with string
Figure 5-6
5. To check if the hardware info is filled correctly, you can
execute nucleus 1228.
Nucleus 1228 info example
Figure 5-7
6. Exit the 'Terminal' program.
7. Reboot the DVD recorder to allow the software to start.

Command overview Digital Board
Below you will nd an overview of the nuclei, their numbers,
and their error codes. This overview is preliminary and
subject to modications.
Codec Host Controller (CHR)
Nucleus Name DS_CHR_DevTypeGet
Nucleus Number 100
Description Retrieves the device id, the module ids and revisions of the Codec and returns
them to the stdout port.
Technical - Determine the codec id by means of comparing version ids of the modules.
- Read the module-id register of every module and display it to the user.
Execution Time Less than 1 second.
User Input None
Error Number Description
10000 Getting the information succeeded
10001 Wrong codec id detected
Example
DS:> 100
010000:
Device ID 7300
Codec ID PNX7350
F-BCU (0x0102) 4.0 INTC (0x011d) 3.0
SIF (0xa04b) 2.0
BOOT (0x010a) 3.1 CONFIG (0x013f) 5.0 RESET (0x0123) 5.0
CLOCK (0x013e) 7.0 DEBUG (0x0116) 0.1 UART0 (0x0107) 1.2
UART1 (0x0107) 1.2
I2C0 (0x0105) 0.1 I2C1 (0x0105) 0.1 GPIO (0x013c) 3.1
SYNC (0x013a) 4.0
OSD (0x0136) 1.0 SPU (0xa00e) 1.1 MIXER (0x0137) 3.0
DENC (0x0138) 5.0 CCIR (0x0139) 2.1 VDEC (0x0133) 1.0
PARSER (0xa00d) 0.0 DV (0xa00c) 0.0
IDE0 (0xa009) 1.2 IDE1 (0xa009) 1.2 SGDX (0xa008) 4.0
BYTE (0xa00b) 1.0 OUTPUT (0xa003) 8.0 ACOMP (0xa000) 8.0
VFE (0xa001) 8.0 VCOMP (0xa002) 8.0 SCR (0xa004) 8.0
SIFF (0xa011) 3.0
PSCAN (0xa05d) 0.1
ADEC (0x0134) 1.1 IR (0x0131) 2.0 AOI (0xa08c) 0.0
PIP (0xa04d) 1.0 AVLINK (0x3601) 2.1 USBLINK(0xa08e) 0.0
MSVD (0xa087) 0.0 FEBCU (0xa05e) 1.0 BM (0xa085) 0.0
BMI (0xa084) 0.0 DISP (0xa04d) 1.0
Test OK @

Nucleus Name DS_CHR_TestImageOn
Nucleus Number 101
Description Generates a test-image of a selected video standard on selected video output
on the digital board. When no input is given, the default values will be used (see
user input description below). Make sure to use the proper nuclei to route the
video signal on the VIP to get the video signal to the proper output.
Technical - Validate the user input.
- Initialise the SYNC module.
- Initialise the DISPLAY module.
- Initialise the MIXER module.
- Initialise the DENC module.
- Set the selected video standard.
- Generate the selected test image in memory.
- Start the DISPLAY module.
- Start the MIXER module.
- Start the DENC module according to the selected test image id.
Execution Time 6 seconds.
User Input The user has to decide which test image, video standard and video output must
be used: < Test image id > < Video standard > < Video output >
Test image id:
0 VERTICAL_COLOURBAR (default)
1 HORIZONTAL_COLOURBAR
2 WHITE
3 YELLOW
4 CYAN
5 GREEN
6 MAGENTA
7 RED
8 BLUE
9 BLACK
10 GRAY
11 TEST_IMAGE_FOR_PROGRESSIVE_SCAN
Video standard:
PAL Standard PAL 50 Hz (default)
NTSC Standard NTSC 60 Hz
Video output:
ALL CVBS and YC and RGB signals are enabled (default)
ALL_RGB CVBS and YC and RGB signals are enabled (default)
ALL_YUV CVBS and YC and YUV signals are enabled
CVBS CVBS signal is enabled
YC YC signal are enabled
RGB CVBS, and RGB signals are enabled
YUV YUV signals are enabled
PSCAN Progressive scan is enabled
10100 Generating the test image succeeded.
10101 Invalid input was provided.
10102 The Codec SYNC-module cannot be initialised.
10103 The Codec MIXER-module cannot be initialised.
10104 The Codec VPP-module cannot be initialised.
10105 The Codec DENC-module cannot be initialised.
10106 The digital board hardware information is corrupt
Example
DS:> 101
010100:
Test OK @
DS:> 101 0 pal cvbs
010100:
Test OK @
DS:> 101 4 ntsc yc
010100:
Test OK @

Nucleus Name DS_CHR_TestImageOff
Nucleus Number 102
Description Switches the test-image off.
Technical - Stop the DENC module.
User Input None
10200 Stopping the test image generation succeeded
10201 The Codec DENC-module failed.
Example
DS:> 102
010200:
Test OK @
Nucleus Name DS_CHR_SineOn
Nucleus Number 103
Description Generate an audio sine signal on the audio output of the digital board.
Note: Left channel 6kHz, right channel 12 kHz sine. Make sure to route the
signal first.
When SPDIF is entered as a parameter, the SPDIF path will be activated
correctly to generate a PCM sine wave on the digital audio output.
Technical - De-mute the analogue board
- Set fifo parameters for audio
- Set the volume
- Set the I2S outputs and configuration paths
- Set the decoder mode
- Configure the audio decoder
- Put the AC3 audio in the fifo
- Send prepare command to the audio decoder
- Send play command to the audio decoder
Execution Time Less than 1 second
User Input None or SPDIF
10300 The sine signal was successfully generated
10301 The analogue board could not be de-muted
10302 The audio decoder did not initialise
10303 The dsp2 (DUET) of the audio decoder did not configure
10304 The dsp1 (PALM) of the audio decoder did not configure
10305 There was a delay-error before starting
10306 Wrong input was given to the decoder function
10307 Wrong input was given to the decoder function @@@@@
10308 The audio decoder did not get into the prepared state
Example
DS:> 103
010300:
Test OK @
DS:> 103 spdif
010300:
Test OK @
Nucleus Name DS_CHR_SineOff
Nucleus Number 104
Description Stop generating the audio sine signal
Technical - Reset the audio block of the Codec
User Input None
10400 Switching off the audio sine signal succeeded
10401 Failed to reset the audio decoder
Example
DS:> 104
010400:
Test OK @

Nucleus Name DS_CHR_SineBurst
Nucleus Number 105
Description Generate an audio sine signal on the audio output of the digital board for 4
seconds.
Note: Left channel 6kHz, right channel 12 kHz sine with some known hick-ups
Technical - Call the DS_CHR_SineOn nucleus
- Delay for 4 seconds
- Call the DS_CHR_SineOff nucleus
Execution Time 4 seconds
User Input None
10500 The sine signal burst was successfully generated
10501 The delay did not succeed during the burst
10502 The audio sine could not be generated
Example
DS:> 105
010500:
Test OK @
Nucleus Name DS_CHR_MuteOn
Nucleus Number 106
Description Mute the audio outputs of the digital board
Technical - Send the Mute command to the audio decoder
- Activate the audio mute PIO pin
User Input PIO to just use the PIO pin mute. When muting using this, also de-mute using
this as this works paired.
10600 Muting the audio succeeded
10601 Muting the audio through the PIO-pin failed
Example
DS:> 106
010600:
Test OK @
DS:> 106 PIO
010600:
Test OK @
Nucleus Name DS_CHR_MuteOff
Nucleus Number 107
Description De-mute the audio outputs of the digital board
Technical - Send the DeMute command to the audio decoder
- Deactivate the audio mute PIO pin
Execution Time PIO to just use the PIO pin de-mute. Only de-mute using this when you muted
using the PIO parameter, as this works paired.
User Input None
10700 De-muting the audio succeeded
10701 De-muting the audio through the PIO-pin failed
Example
DS:> 107
010700:
Test OK @
DS:> 107 PIO
010700:
Test OK @

Nucleus Name DS_CHR_MacroVisionOn
Nucleus Number 110
Description Turn on MacroVision.
Technical - Set some registers of the DENC module in the Codec.
User Input None
11000 Turning on MacroVision succeeded
11001 Turning on MacroVision failed
Example
DS:> 110
011000:
Test OK @
Nucleus Name DS_CHR_MacroVisionOff
Nucleus Number 111
Description Turn off MacroVision.
Technical - Set some registers of the DENC module in the Codec.
User Input None
11100 Turning off MacroVision succeeded
11101 Turning off MacroVision failed
Example
DS:> 111
011100:
Test OK @
Nucleus Name DS_CHR_Peek
Nucleus Number 112
Description Peek a value on a specified address
Technical - Check the user input
- Read out the address specified
- Check whether the address to be read is aligned on 4 bytes
User Input The address to peek on
11200 Peeking on the specified address succeeded
11201 Peeking on the specified address failed, wrong user input
11202 Peeking on the specified address failed due to misalignment
Example
DS:> 112 0xa0700000
011200: Value read = 0x000001BD
Test OK @
Nucleus Name DS_CHR_Poke
Nucleus Number 113
Description Poke a value on a specified address
- Change the value on the address specified
- Check whether the address to be modified is aligned on 4 bytes
User Input The address to poke and the value: <address><value>
11300 Poking the specified address succeeded
11301 Poking the specified address failed, wrong user input
11302 Poking the specified address failed due to misalignment
Example
DS:> 113 0xa0700000 0xaabbccdd
011300:
Test OK @

Nucleus Name DS_CHR_INT_PICInterrupts
Nucleus Number 114
Description Test all interrupts of the priority interrupt controller
Technical - Install interrupt handlers
- Generate interrupts
- Test whether all interrupts were received
User Input -
11400 Testing all the PIC interrupts succeeded
11401 Testing all the PIC interrupts failed
Example
DS:> 114
011400:
Test OK @
Nucleus Name DS_CHR_DMA_TestDMA
Nucleus Number 115
Description Test the memory to memory DMA transfer
Technical - Create a block with known data in memory
- Copy this block to the consecutive area using 4 different DMAs
- Check whether all DMAs transferred the data properly
Execution Time Less than 2 seconds.
User Input -
11500 The testing of the DMAs succeeded
11501 The initialisation of the DMAs failed for one or more DMA
11502 One or more DMAs failed the test
Example
DS:> 115
011500:
Test OK @
Nucleus Name DS_CHR_PioGet
Nucleus Number 116
Description Get a value from a PIO pin
Technical - Decode user input
- Read the PIO input register of the codec and return the requested pio line
value
User Input <PIN>
where PIN is the pio pin to get (0..31)
11600 Getting PIO value succeeded
11601 Invalid parameter
Example
DS:> 116 15
011600: Value read = 0x1
Test OK @

Nucleus Name DS_CHR_PioSet
Nucleus Number 117
Description Set a value on a PIO pin. Make sure that the pin is configured as output first
- Update the PIO output register of the codec
User Input <PIN> <VALUE>
where PIN is the pio pin to set (0..31)
and VALUE the value of the pin (0..1)
11700 Setting PIO value succeeded
Example
DS:> 117 15 0
011700:
Test OK @
Nucleus Name DS_CHR_PioConfig
Nucleus Number 118
Description Configure a PIO pin
- Update the PIO configuration register of the codec
User Input <PIN> <DIR>
where PIN is the pio pin to set (0..31)
and DIR the direction of the pin (0=IN 1=OUT)
11800 Setting PIO configuration succeeded
Example
DS:> 118 14 0
011700:
Test OK @

SDRAM (SDRAM OR DDR-RAM)
Nucleus Name DS_SDRAM_WriteRead
Nucleus Number 400
Description Check all data lines, address lines and memory locations of the RAM
Technical - Test the data bus
- Test the address bus
- Test the integrity of the device itself (memory locations)
Execution Time 11 seconds for 32 Mb
23 seconds for 64 Mb
User Input None
40000 The write-read test succeeded
40001 The data bus contains an error
40002 The address bus contains an error
40003 The RAM itself contains an error
Example
DS:> 400
040000:
Test OK @
Nucleus Name DS_SDRAM_WriteReadFast
Nucleus Number 401
Description Check all data lines and address lines of the RAM
Technical - Test the data bus
- Test the address bus
User Input None
40100 The write-read test succeeded
40101 The data bus contains an error
40102 The address bus contains an error
Example
DS:> 401
040100:
Test OK @
Nucleus Name DS_SDRAM_Write
Nucleus Number 402
Description Write to a specific un-cached memory address
Technical - Decode the user input and check its ranges and alignment on 4 bytes
- Write the data to the RAM
User Input 1. The location that must be modified
(RAM starts at address 0xA0000000)
2. The value to put on the selected location
40200 Writing to the RAM succeeded
40201 Writing to the RAM failed; Wrong user input
40202 Address is not dividable by 4
Example
DS:> 402 0xa1000010 0xad112222
040200:
Test OK @

Nucleus Name DS_SDRAM_Read
Nucleus Number 403
Description Read from a specific un-cached memory address
Technical - Decode the user input and check the ranges
- Read from the RAM and return this info to the user
User Input The location from which the data must be read
(RAM starts at address 0xA0000000)
40300 Reading from the RAM succeeded
40301 Reading from the RAM failed; Wrong user input
Example
DS:> 403 0xa1000010
040300: Value read = 0xAD112222
Test OK @
Nucleus Name DS_SDRAM_DmaWriteRead
Nucleus Number 404
Description Write a pattern to the entire RAM using DMA and check the data
Technical - Check if the Stack pointer is not in the write range
- Clear a 64kb block and then fill it with a pattern
- Initialise the DMA controller and write the data to the SDRAM
- Then check if all the data was written correctly (except descriptor tables)
- Repeat the process 4 times with 4 different patterns
User Input None.
40400 Writing to the RAM succeeded
40401 Stack area definition ERROR!
40402 DMA controller could not be initialised.
40403 Not all data was transferred correctly
Example
DS:> 404
040400:
Test OK @

FLASH (FLASH)
Nucleus Name DS_FLASH_DevTypeGet
Nucleus Number 500
Description Get the device (revision) type information of the FLASH ICs. (type,
manufacturer, device ID and size)
Technical - Set the timing for the flash writing
- Write a command sequence to determine device type information
- Return the information to the user
User Input None
50000 Getting the information from the FLASH succeeded
50001 Getting the information from the FLASH failed
Example
DS:> 500
050000: Found FLASH memory:
NOR AMD 29DL640G 8MB,NOR AMD 29DL640G 8MB
Test OK @
Nucleus Name DS_FLASH_Read
Nucleus Number 502
Description Read from a specific memory address in FLASH
Technical - Decode the user input and check the ranges and whether the address is
aligned on 4 bytes
- Read the data and return this to the user
User Input The location from which data must be read
(FLASH starts at address 0xB8000000)
50200 Reading the FLASH succeeded
50201 Reading the FLASH failed; Wrong user input
Example
DS:> 502 0xb8000000
050200: Value read = 0x3C08A000
Test OK @
Nucleus Name DS_FLASH_ChecksumProgram
Nucleus Number 503
Description Check the checksum of the application partitions by recalculating and
comparing partition checksums
Technical - Determine the number of segments
- Find the application in each segment and determine its checksum
- Check whether the checksums stored match the newly calculated
User Input None
50300 The checksum is valid, the test succeeded
50301 The checksum is invalid
Example
DS:> 503
050300:
BootCode checksum is: 0xBABE5B6F, which is correct
Diagnostics checksum is: 0xBABEBAFF, which is correct
Download checksum is: 0xBABEEDBF, which is correct
Application checksum is: 0xBABE8EEC, which is correct
Test OK @

Nucleus Name DS_FLASH_CalculateChecksum
Nucleus Number 504
Description Calculate the checksum over all memory addresses. Used to check entire
FLASH contents
Technical - Run the checksum calculation algorithm on all flash memory addresses
User Input None
50400 Calculating the checksum over all addresses succeeded
Example
DS:> 504
050400: The Checksum = 0xBABE30A4
Test OK @
Nucleus Name DS_FLASH_CalculateChecksumFast
Nucleus Number 505
Description Calculate a checksum over a selected number of address locations
Technical - Run the checksum calculation algorithm on a selected number of flash
memory addresses
User Input None
50500 Calculating the checksum over selected addresses succeeded
Example
DS:> 505
050500: The Checksum = 0xBABEB064
Test OK @
Nucleus Name DS_FLASH_EraseFlfs
Nucleus Number 506
Description Erase the complete Flash File system segment in flash memory. This will erase
all non volatile data including diversity string and DV unique ID number
Technical - Initialise Flash access
- Search in flash for the segment with the FLFS and FLF2 signature
- Ask the user whether he is sure to erase all data
- If available erase the sector containing the FLFS signature
- If available erase the sector containing the FLF2 signature
Important note: This nucleus will erase all data, make sure to reboot after this and
program a diversity string
Execution Time About 1 second per block erased.
User Input None
50600 FLFS successfully erased
50601 User aborted the test
50602 FLFS segment is not available
Examples
DS:> 506
Do you readlly want to erase the entire FLFS ? [Y /N(Default)] :y
Erasing FLFS...
050600: All data has been erased
Test OK @
DS:> 506
Do you readlly want to erase the entire FLFS ? [Y /N(Default)] :n
FLFS not erased.
050601: User abort
Test OK @
DS:> 506
Erasing FLFS...
050602: No FLFS segment found
Error @
Nucleus Name DS_FLASH_EraseFlfs
Nucleus Number 506
Description
Erase the complete Flash File system segment in ash memory. This will erase all non
volatile data including diversity string, DV unique ID number and DivX model ID.
Technical
- Initialise Flash access
- Search in ash for the segment with the FLFS and FLF2 signature
- Ask the user whether he is sure to erase all data
- If available erase the sector containing the FLFS signature
- If available erase the sector containing the FLF2 signature
Important note:
This nucleus will erase all data, make sure to reboot after this and program a
diversity string
Execution Time About 1 second per block erased.
User Input None
50600 FLFS successfully erased
50602 FLFS segment is not available
Examples
DS:> 506
Erasing FLFS...
050600: All data has been erased
Test OK @
DS:> 506
Do you readlly want to erase the entire FLFS ? [Y /N(Default)] :n
FLFS not erased.
050601: User abort
Test OK @
DS:> 506
Erasing FLFS...
050602: No FLFS segment found
Error @
* Beware that when nucleus 506 erases DivX model ID, the DivX VOD registration code of the set will change.
The set will not play back the previously purchased (downloaded) videos from DivX Video On Demand service.
Refer to section 5.11 Setting DivX Model ID for details

VIDEO INPUT PROCESSOR (VIP)
Nucleus Name DS_VIP_DevTypeGet
Nucleus Number 600
Description Get the device (revision) type information of the VIP IC
Technical - Initialise IIC
- Read out the device (revision) type information of the VIP IC
User Input None
60000 Getting the information from the VIP succeeded
60001 The IIC bus initialisation failed
60002 The was an error getting the information from the VIP
60003 Type not according to type stored in HW diversity string
Example
DS:> 600
060000: Found SAA7136
Test OK @
Nucleus Name DS_VIP_Communication
Nucleus Number 601
Description Check the communication between the IIC controller of the Codec and the VIP
IC
Technical - Initialise IIC
- Read data from a location in the VIP
User Input None
60100 Communicating with the VIP succeeded
60101 The IIC bus was not accessible
60102 There was a timeout reading the device
60103 The IIC acknowledge was not received
60104 The communication with the device failed
Example
DS:> 601
060100:
Test OK @

Nucleus Name DS_VIP_SelectInput
Nucleus Number 604
Description Select an input video path to be switched to the analogue output pin (AOUT) of the
VIP
User Input Select an input video path (id) to be switched to the analogue output pin (AOUT1)
of the VIP.
Available channels for input of the SAA7136 and their description:
Id VIP
input
Input source EURO Input source NAFTA
1 AI11 tuner_scart2-cvbs_in reserved
2 AI12 leco-cvbs_in1 rear-y_cvbs_in
3 AI13 front-y_in front-y_in
4 AI21 scart2_c_r_in rear-pr_in
5 AI22 scart1-cvbs_in rear-c_in
6 AI23 front-c_in front-c_in
7 AI31 scart2-g_in rear-y_in (YPbPr)
8 AI32 scart2-cvbs_in front-cvbs_in
9 AI33 scart2-tuner-dttm-cvbs_in tuner-cvbs_in
10 AI41 scart2-b_in rear-pb_in
11 AI42 leco-cvbs_in2 reserved
12 AI43 front-cvbs_in leco-cvbs_in
- Initialise IIC
- Read out the VIP id
- Write the set of registers required for the input specified
60400 Selecting the input of the VIP succeeded
60401 The user provided wrong input
60402 The VIP was not accessible
60403 An unsupported VIP was found
Example
DS:> 604 1
060400:
Test OK @
Nucleus Name DS_VIP_Routing
Nucleus Number 605
Description Perform the routing of the audio and video signals in the set. It sets the audio
and video path according to the user input.
The user inputs the path id of choice, as specified in the table below for EURO
and NAFTA.
User Input <REGION> <PATH_ID>
For details see next tables
- Initialise IIC
- Read out the VIP id
- Write the set of registers required for the input specified
60500 Selecting the input of the VIP succeeded
60502 The VIP was not accessible
60503 An unsupported VIP was found
Example
DS:> 605 euro 00
060500:
Test OK @

Available VIDEO path-lds for NAFTA / APAC routing
NAFTA Path id Description
nafta 00 cvbs, yc, yuv and audio rear out.
nafta 01 cvbs and iis loop through (via itu656_c).
nafta 02 cvbs and iis loop through (via itu656_d).
nafta 03 cvbs and audio front in,
cvbs and audio rear out.
nafta 04 yc and audio rear in,
yc and audio rear out.
nafta 05 yc and audio front in,
yc and audio rear out.
nafta 06 yuv and audio rear out,
yuv and audio rear in.
nafta 07 cvbs, yc, yuv and audio rear out,
tuner in.
nafta 08 spdif rear out,
spdif1 rear in.
nafta 09 spdif rear out,
spdif2 rear in.
nafta 10 cvbs, spdif rear out,
dttm itu656 spdif in..
nafta 11 cvbs and audio front in,
cvbs and audio rear out (via external audio ADC).
nafta 12 cvbs and iis loop through (via itu656_c and external audio
ADC).
nafta 13 yuv and audio rear out(via external audio ADC),
yuv and audio rear in.
Nucleus Name DS_VIP_Reset
Nucleus Number 606
Description Reset the Video input processor
Technical - Toggle the VIP_RESET PIO line of the codec
User Input None
60600 Resetting VIP succeeded
60601 Resetting VIP failed
Example
DS:> 606
060600: Ok
Test OK @

Nucleus Name DS_VIP_FastBlankingCheck
Nucleus Number 607
Description Checks the fast blanking signal on SCART2 in
Technical - Read out the SCART1_P16 GPIO pin of the ASP
User Input None
60700 Value of Fast Blanking Pin is detected
60701 Error Cannot read Fast Blanking Pin
Example
DS:> 607
060700: Fast Blanking is ON
Test OK @
Nucleus Name DS_VIP_WssCheck
Nucleus Number 608
Description Check if the wide screen signal can be set low and high.
Technical - Get the WSS Rear Y/C Out value
User Input None
60800
60801

Example
DS:> 608
060800: WSS is ON
Test OK @
Nucleus Name DS_VIP_DetectVideo
Nucleus Number 609
Description Checks if an active video signal is available on the CVBS input of SCART 1 or
SCART 2.
Technical - Reset the VIP.
- Implement the following video route in the VIP : SCART1 (A32) to
ITU656_C
- Tell user to remove all active video input from SCART1.
- Enable sdtv(hlvln) mask in 0x500(First level interrupt enable) and 0x50d
(SDTV interrupt enable).
- Set GPIO 55 on ASP to input.
- Tell user to connect active video into SCART1.
- Read GPIO 55.
- The line should be LOW if there is active video on SCART1, else LOW.
- Clear the VIP *INTA interrupt.
Execution Time Depending on user input
User Input None
609000 Detecting the Active video succeeded.
609001 Detecting the Active video failed.
609002 This test is not applicable for current HW layout.
609003 Could not retrieve hardware version from ASP.
Example
DS:> 609
Please remove video input from the SCART1 connector.
Press any key when ready ...
Please input video input into the SCART1 connector.
Press any key when ready ...
609000: Active video is ON
Test OK @

DIGITAL VIDEO INPUT OUTPUT CIRCUIT (DVIO)
Nucleus Name DS_DVIO_LinkDevTypeGet
Nucleus Number 700
Description Get the device (revision) type information of the 1394 Link layer IC
Technical - Initialise the PIO pins on the Codec
- Read out the ID register
User Input None
70000 Getting the information from the link layer IC succeeded
70001 Getting the information from the link layer IC failed
70002 Type not according to type stored in HW diversity string
Example
DS:> 700
070000: Device type of the link layer IC: ffc00301
Test OK @
Nucleus Name DS_DVIO_PhyDevTypeGet
Nucleus Number 701
Description Get the device (revision) type information of the 1394 Physical layer IC
Technical - Initialise the PIO pins of the Codec
- Write the PHY-access register in the Link chip to indicate phy read access
- Wait until the link chip has obtained the value from the phy-chip
- Read this out and filter the data to be returned to the user
User Input None
70100 Getting the information from the physical layer IC succeeded
70101 The physical layer IC was not accessible
70102 Getting the information from the physical layer IC failed
70103 Type not according to type stored in HW diversity
Example
DS:> 701
070100: Physical layer IC: VendorID: 0x006037, ProductID: 0x412801
Test OK @
Nucleus Name DS_DVIO_PhyCommunication
Nucleus Number 703
Description Check the accessibility of the 1394 Physical layer IC by writing to and reading
from a specific address
Technical - Initialise the PIO pins of the Codec
- Initialise IIC
- Write the data to be written to the PHY-chip to the link chip first
- Wait until the link chip indicates that the data has been written to the PHY
- Write the PHY-access register in the Link chip to indicate PHY read access
- Wait until the link chip has obtained the value from the PHY-chip
- Test whether the value read back equals the one previously written
User Input None
70300 Communicating with the physical layer IC succeeded
70301 The physical layer IC was not accessible
70302 Communicating with the physical layer IC failed
70303 Result of nucleus not according to HW diversity string
Example
DS:> 703
070300:
Test OK @

Nucleus Name DS_DVIO_Routing
Nucleus Number 704
Description Route a DV stream containing an audio and video signal through the physical
and link layer ICs to the Codec. This test works for both NTSC and PAL.
Technical - Initialise the DMA to transfer 5 frames PAL/NTSC
- Initialise the DV de-multiplexer
- Initialise the 1394 interface and start reception of the DV stream
- Check whether the stream was copied to memory properly by the byte
input interface (port to memory type DMA)
Execution Time 6-10 seconds (6 when OK, 10 when no stream or error)
User Input None
70400 Routing the signals succeeded
70401 The 1394 link chip could not be initialised properly
70402 There was a syntax error in the DV stream
70403 DMA could not copy DV stream to memory. Stream connected?
70404 DMA not working properly
Example
DS:> 704
070400:
Test OK @
Nucleus Name DS_DVIO_DetectNode
Nucleus Number 705
Description Check whether a DV node can be detected by the hardware. This test works for
both NTSC and PAL.
Technical - Initialise the 1394 interface
- Detect whether a node is in range
Execution Time 3 or 5 seconds (3 when OK, 5 when no stream or error)
User Input None
70500 The node was detected OK
70502 Unable to write to 1394 PHY chip
70503 Unable to read from 1394 PHY chip
70504 No node was detected
Example
DS:> 705
070500:
Test OK @
Nucleus Name DS_DVIO_DetectStream
Nucleus Number 706
Description Check whether a DV stream can be detected by the hardware. This test works
for both NTSC and PAL.
Technical - Initialise the 1394 interface
- Start receiving the stream
- Detect whether the stream is OK
Execution Time 3 or 5 seconds (3 when OK, 5 when no stream or error)
User Input None
70600 The stream was detected
70602 No stream detected
Example
DS:> 706
070600:
Test OK @

BASIC ENGINE (BE)
Nucleus Name DS_BE_CommunicationEcho
Nucleus Number 900
Description Check the communication between the digital board and the BE by issuing a
TEST_UNIT_READY ATAPI command
Technical - Send an ATAPI TEST_UNIT_READY command
User Input None
90000 Communicating with the BE over the IDE interface succeeded
90001 There was a time-out while communicating
90002 The Basic Engine returned an unexpected result
90003 The Basic Engine returned an error code
90004 No acknowledge received from BE
90005 Communicating with the Basic Engine failed
90006 Echo check failed, no ready status received
90007 Echo check failed, received wrong pattern
Example
DS:> 900
090000:
Test OK @
Nucleus Name DS_BE_Reset
Nucleus Number 901
Description Reset the basic engine
Technical - Toggle the reset pin of the IDE interface and wait for the BE to become
ready
Execution Time 9 seconds (when disc inside)
User Input None
90100 Resetting the Basic Engine succeeded
90101 Resetting the Basic Engine failed
Example
DS:> 901
090100:
Test OK @
Nucleus Name DS_BE_GetSelftestResult
Nucleus Number 902
Description Return the self-test results through the service port
Technical - Send the ATAPI REPORT_DRIVE_DIAGNOSTICS command
- On error display the specific error codes received from the BE
User Input None
90200 Self test succeeded, no errors
90203 The BE returned an error code
90206 Basic Engine returned no info
90207 Self test failed, errors are echoed
Example
DS:> 902
090200:
Self-test result byte : 00000000
Test OK @

Nucleus Name DS_BE_VersionGet
Nucleus Number 903
Description Get the version of the basic engine and that of the optical unit
Technical - send the ATAPI INQUIRY command
- Send the GET_OPU_VERSION command
- Display the returned version information
User Input None
90300 BE version OK
90306 The BE returned no info
Example
DS:> 903
090300:
BE version = 31.30.24. PHILIPS ,VAD8031
,31302400,REL_8031_313024 2073,
Optical unit version = 00.06.82.19.00
Test OK @
Nucleus Name DS_BE_TrayOut
Nucleus Number 904
Description Open the tray of the basic engine
Technical - Send an ATAPI START_STOP_UNIT command
Execution Time Approximately 2 seconds
User Input None
90400 The command executed successfully
90405 Unable to enter normal mode
Example
DS:> 904
090400:
Test OK @
Nucleus Name DS_BE_TrayIn
Nucleus Number 905
Description Close the tray of the basic engine
Technical - Send an ATAPI START_STOP_UNIT command
Execution Time Approximately 1 - 2 seconds
User Input None
90505 Unable to enter normal mode
Example
DS:> 905
090500:
Test OK @

Nucleus Name DS_BE_WriteReadDvdRw
Nucleus Number 906
Description Write data to and read data from a DVD+RW or DVD-RW disc through the
basic engine for verification of the writing
Technical - Send an ATAPI START_STOP_UNIT command to insert the tray
- Send the READ_TOC command
- Generate a random disc location
- Generate test data to write to the DVD+RW
- Transfer the test data to the disc location using PIO mode ATAPI
WRITE_10
- Transfer the test data from the disc location using PIO mode ATAPI
READ_10
- Compare the two data areas and check whether the areas are equal
User Input None
90601 This nucleus cannot be executed because the Self-Test failed
90602 The BE cannot enter normal operating mode
90603 Unable to send the tray in
90604 Unable to read TOC from disc
90605
Invalid disc is loaded, please insert a DVD+RW or DVD-RW
disc
90606 Writing the test pattern to DVD+RW or DVD-RW failed
90607 Reading back the test pattern from DVD+RW of DVD-RW failed
90608 Compare check failed
90609 Calibrating DVD+RW or DVD-RW failed
Example
DS:> 906
090600: DVD+RW test on sector 0x5dbe0: OK
Test OK @
DS:> 906
090600: DVD-RW test on sector 0x304e0: OK
Test OK @
Nucleus Name DS_BE_WriteReadDvdR
Nucleus Number 907
Description Write data to and read data from a DVD+R or DVD-R disc through the basic
engine for verification of the writing
Technical - Send an ATAPI START_STOP_UNIT command to insert the tray
- Use the OPC area to test if the DVD+R or DVD-R is (still) writable
- Generate test data to write to the DVD+R or DVD-R
- Transfer the test data to the disc location using PIO mode ATAPI
WRITE_10
- Transfer the test data from the disc location using PIO mode ATAPI
READ_10
User Input None
90705 Invalid disc is loaded, please insert a DVD+RW disc
90706 Unable to write, the DVD+R or DVD-R disc is full
90707 No writable DVD+R or DVD-R sector found
90708 Writing the test pattern to DVD failed
90709 Reading back the test pattern from DVD failed
90710 Compare check failed
Example
DS:> 907
090700: DVD+R test on sector 0x36210: OK
Test OK @
DS:> 907
090700: DVD-R test on sector 0x30000: OK
Test OK @

Nucleus Name DS_BE_JitterOptimise
Nucleus Number 912
Description Perform jitter optimisation:
A formatted DVD must be loaded into the engine before executing this nucleus
Technical - Send the START_STOP_UNIT command to insert the tray
- Send the MEASURE_JITTER_BLER_PPN command and display the
average jitter and bler values
User Input None
91200 Optimising jitter succeeded
91203 The Basic Engine returned an error code
91205 Unable to send tray in
91206 Unable to read the disc
91207 No disc is loaded
91208 Unknown disc is loaded
91209 Unable to enter service mode
Example
DS:> 912
091200: Average Jitter, Bler C1, Bler C2: (92,4,254)
Test OK @
Nucleus Name DS_BE_FocusOn
Nucleus Number 913
Description Put the laser of the bit-engine into focus by issuing a TRANSPARENT SEND
and TRANSPARENT_RECEIVE command. This nucleus is not guaranteed to
work on all connected BEs
Technical - Send the transparent BIT engine FOCUS command
Important note: This nucleus uses the transparent bit engine interface of the drive. It is
not guaranteed to work on all drives. Only use this nucleus if you are sure
that the drive supports this interface
User Input None
91300 Focus on succeeded
Example
DS:> 913
091300:
Test OK @

Nucleus Name DS_BE_FocusOff
Nucleus Number 914
Description Turn off putting the laser of the bit-engine into focus by issuing a
TRANSPARENT SEND and TRANSPARENT_RECEIVE command. This
nucleus is not guaranteed to work on all connected BEs
Technical - Send the transparent BIT engine FOCUS command
User Input None
91400 Focus off succeeded
Example
DS:> 914
091400:
Test OK @
Nucleus Name DS_BE_MotorOn
Nucleus Number 915
Description Turn on the turntable motor by issuing a TRANSPARENT SEND and
TRANSPARENT_RECEIVE command. This nucleus is not guaranteed to work
on all connected Bes
Technical - Send the transparent BIT engine TTM command
User Input None
91500 Turn table motor is on
Example
DS:> 915
091500:
Test OK @
Nucleus Name DS_BE_MotorOff
Nucleus Number 916
Description Turn off the turntable motor by issuing a TRANSPARENT SEND and
TRANSPARENT_RECEIVE command. This nucleus is not guaranteed to work
on all connected Bes
Technical - Send the transparent BIT engine TTM command
User Input None
91600 Turn table motor is off
Example
DS:> 916
091600:
Test OK @

Nucleus Name DS_BE_CheckDisc
Nucleus Number 921
Description Check whether there is a disc inside the BE
- Display the Disc type info
- If Disc type is a DVD+R(W), then read ADIP info.
- Display manufacturer and media type.
User Input None
92100 There was a disc inside the set
92101 Unable to load the tray
92102 Error received from BE
Example
DS:> 921
092100:
Disc type: DVD+RW disc
Disc manufacturer id: PHILIPS
Media type id: 010
Test OK @
DS:> 921
090500:
Disc type: None
Test OK @
DS:> 921
092100:
Disc type: DVD+R disc
Disc manufacturer id: RICOHJPN
Media type id: R00
Test OK @
Nucleus Name DS_BE_ReadTocInfo
Nucleus Number 924
Description Read the TOC from the disc. This gives a good indication if the BE works
properly.
- Display the TOC info.
User Input None
92400 A disc is loaded, TOC info if echoed
92401 Unable to load the tray
92402 The BE has not returned TOC info
92403 Error received from BE
Example
DS:> 924
092400: TOC info [hex] = 91 3A 0C
Test OK @
DS:> 924
092403: The BE returned: 0x10 #{no_disc_error} No disc is detected
Error @
DS:> 924
092403: The BE returned: 0x1e #{illegal_medium_error} Engine
unable to handle current disc. Probably illegal medium.
Error @

Nucleus Name DS_BE_RegionCodeSet
Nucleus Number 928
Description Set the region code in the AV3.
Technical - Send the ATAPI SEND_KEY command
Execution Time
User Input Region code
92806 No disc is present, please insert disc
92807 Region code out of range
92808 User input wrong
92809 Region counter expired
92810 This nucleus is not supported by the engine
Example
DS:> 928 1
092800:
Test OK @
Nucleus Name DS_BE_RegionCodeGet
Nucleus Number 929
Description Read the region code from the AV3.
Technical - Send the ATAPI REPORT_KEY command
Execution Time
User Input None
Example
DS:> 929
092900: DVD region 1
Test OK @
Nucleus Name DS_BE_RegionCounterReset
Nucleus Number 930
Description Reset the region counter in the AV3.
Technical - Send a special ATAPI RESET_REGION_COUNTER command
Execution Time
User Input None
Example
DS:> 930
093000:
Test OK @

Nucleus Name DS_BE_AdjustLaserControl
Nucleus Number 931
Description Adjust the DVD-M (with the OPU) with PCBA. (So adjusts the two PCBS to
each other)
Technical - Sending a transparent BIT engine command to align the PCBs to each
other.
User Input None
Example
DS:> 931
093100:
Test OK @
Nucleus Name DS_BE_WriteReadDvdRDualLayer
Nucleus Number 932
Description Write data to and read data from both layers of a DVD+R DL disc through the
basic engine for verification of the writing
Technical - Send the TRAY_IN command
- Use READ_TRACK_INFORMATION to determine the next free writable
address on Layer 0.
- In case of address 0, reserve a track of 0x1FD800 sectors for Layer 0
- Use command SEND_OPC_INFORMATION to calibrate Layer 0
- Generate test data to write to the disc
- Transfer the test data to Layer 0 using PIO mode ATAPI WRITE_12
- Use READ_TRACK_INFORMATION to determine the next free writable
address on Layer 1
- Use command SEND_OPC_INFORMATION to calibrate Layer 1
- Transfer the test data to Layer 1 using PIO mode ATAPI WRITE_12
- Read back the data of Layer 0 using PIO mode ATAPI READ_12
- Compare the original data with the read data and check whether the areas
are equal
- Read back the data of Layer 1 using PIO mode ATAPI READ_12
- Compare the original data with the read data and check whether the areas
are equal
User Input None
93205 Invalid disc is loaded, please insert a DVD+R DL disc
93206 Unable to write, the DVD+R DL disc is full
93207 No writable sector found
93208 Writing the test pattern to Layer 0 failed
93209 Writing the test pattern to Layer 1 failed
93210 Reading back the test pattern from Layer 0 failed
93211 Reading back the test pattern from Layer 1 failed
93212 Compare check for Layer 0 failed
93213 Compare check for Layer 1 failed
Example
DS:> 932
093200: Dual Layer DVD+R test on LBA 0x750 and 0x1fdf60 OK
Test OK @

Nucleus Name DS_SYS_HardwareVersionGet
Nucleus Number 1200
Description Get the hardware version and type of the digital board
Technical - Read the segment header in FLASH and determine hardware version
User Input None
120000 Getting the hardware version and type of the digital board
succeeded
120001 Getting the hardware version and type of the digital board failed
120002 Wrong hardware version read from FLASH
Example
DS:> 1200
120000: Hardware ID = 0x29
Test OK @
Nucleus Name DS_SYS_SoftwareVersionBootGet
Nucleus Number 1201
Description Get the version of the boot software on the digital board
Technical - Read the segment header in FLASH and determine Boot software version
User Input None
120100 Getting the Boot software version succeeded
120101 Getting the Boot software version failed
Example
DS:> 1201
120100: Software Boot Version = 0331
Test OK @
Nucleus Name DS_SYS_SoftwareVersionDownloadGet
Nucleus Number 1202
Description Get the version of the download software on the digital board
Technical - Read the segment header in FLASH and determine Download software
version
User Input None
120200 Getting the Download software version succeeded
120201 Getting the Download software version failed
Example
DS:> 1202
120200: Software Download Version = 0001
Test OK @
Nucleus Name DS_SYS_SoftwareVersionApplGet
Nucleus Number 1203
Description Get the version of the application software on the digital board
Technical - Read the segment header in FLASH and determine Application software
version
User Input None
120300 Getting the Application software version succeeded
120301 Getting the Application software version failed
Example
DS:> 1203
120300: Software Application Version = 0001
Test OK @

Nucleus Name DS_SYS_SoftwareVersionDiagnosticsGet
Nucleus Number 1204
Description Get the version of the diagnostics software on the digital board
Technical - Read the segment header in FLASH and determine Diagnostics software
version
User Input None
120400 Getting the Diagnostics software version succeeded
120401 Getting the Diagnostics software version failed
Example
DS:> 1204
120400: Software Diagnostics Version = 0001
Test OK @
Nucleus Name DS_SYS_DvIdNumberSet
Nucleus Number 1207
Description Set the IEEE 1394 unique ID
Technical - Decode the user input
- Store the id (<b4><b3><b2><b1><b0>) into NVRAM (offset +
<b4><b3><b2><b1><b0>)
- Validate the segment of storage by updating the checksum
User Input The unique ID to be set.
120700 Setting the unique DV ID succeeded
120701 User input is not valid.
120702 Setting the unique DV ID failed.
120703 Write succeeded, but checksum is corrupt.
Example
DS:> 1207 1234567890
120700:
Test OK @
Nucleus Name DS_SYS_DvIdNumberGet
Nucleus Number 1208
Description Get the IEEE1394 unique ID
Technical - Read out the ID from the configuration segment and return this info to the
user
User Input None
120800 Getting the unique DV ID succeeded
120801 Getting the unique DV ID failed
120802 Reading an unexpected section version in NVRAM
Example
DS:> 1208
120800: The DvIdNumber is: 1234567890
Test OK @

Nucleus Name DS_SYS_IicWrite
Nucleus Number 1209
Description Perform an IIC write action on the digital board
Technical - Determine bus ID, slave address, number of bytes to be written and the
byte array of data from the user input
- Initialise IIC
- Write the data to the slave specified through IIC
User Input The user input the number of bytes to write followed by the bytes to write:
<BusID><Slave address to write to><number of bytes to
write><d1><d2><..><dx>
Where the bus id is either 0 (normally used) or 1
120900 Writing the data over IIC succeeded
120902 There was a timeout writing to the device
120905 Got unknown IIC bus error:
120906 Unable to initialise IIC bus
120907 Decoding bus ID unsigned value failed
120908 Decoding slaveAddr unsigned value failed
120909 Decoding nrBytes unsigned value failed
120910 Bus ID out of range
120911 nrBytes out of range
120912 Unable to decode parameters
Example
DS:> 1209 0 0xa0 1 0x6
120900: 1 Bytes written
Test OK @
Nucleus Name DS_SYS_IicRead
Nucleus Number 1210
Description Perform an IIC read action on the digital board
Technical - Determine the bus ID, slave address and number of bytes to read from the
user input
- Initialise IIC
- Read the data form the slave specified
User Input The user inputs the bus number, the address to read them from and the
number of bytes to read:
<BusID><Slave address to read from><Number of bytes to read>
Where the bus id is either 0 (normally used) or 1
121000 Reading the data over IIC succeeded
121002 There was a timeout writing to the device
121005 There was an unknown IIC bus error
121006 IIC bus initialisation failed
121008 Decoding slave address unsigned value failed
121009 Decoding number of bytes unsigned value failed
121011 nrBytes out of range
Example
DS:> 1210 0 0xa0 0x20
Read :
0x0000: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x0008: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x0010: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x0018: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
121000: 0 0xa0 0x20
Test OK @

Nucleus Name DS_SYS_UartWrite
Nucleus Number 1211
Description Perform an UART write action on the digital board on a specified UART
Technical - Decode the user input for the proper port to use
- Write out the bytes through the indicated port
User Input The user inputs the UART to write to, the number of bytes and the bytes to be
written to the UART.
1=UART port 1 : not used
2=UART port 2 : Bit Engine
3=UART port 3 : Analogue board
<UartNr><Number of bytes to write><d1><d2><..><dx>
121100 Writing the bytes to the UART succeeded
121102 Writing to the UART failed
Example
DS:> 1211 2 2 0xd1 0x01
121100:
Test OK @
Nucleus Name DS_SYS_UartRead
Nucleus Number 1212
Description Perform an UART read action on the digital board on a specified UART
Technical - Decode the user input for the port to read from
- Read from the port and return data read to the user
User Input The user inputs the UART to read from.
1=UART port 1 : not used
2=UART port 2 : Bit Engine
<UartNr >
121200 Reading the data from the UART succeeded
121202 Reading the data from the UART failed
Example
DS:> 1212 2
121200: The HEX value that was read is: 0x50 0xD1 0x00
Test OK @

Nucleus Name DS_SYS_VideoLoopThroughStart
Nucleus Number 1213
Description The video signal, which is conform the user input, is routed from the input to the
output. The input is set using the proper nucleus to route the signal on the
board(s). All outputs are enabled.
Note: Before executing this nucleus the user must route the video signal on the
VIP using DS_VIP_Routing
Technical - Decode the videosignal: PAL / NTSC and Y/C, RGB, CVBS,YUV
- Initialise the Video Input Processor and check for valid signal
- Initialise the Video Front End and start capturing frames to memory
- Initialise the SYNC module
- Initialise the Video Post Processing and retrieve frames from memory
- Initialise the mixer
- Initialise the DENC module
- Route the signal to all outputs
Execution Time Less than 1 second, but stays running.
Note: First set the correct video route using
User Input <VideoSignal> <VideoStandard>
1. Video Signal (CVBS,YC,RGB,YUV).
2. VideoStandard (PAL, NTSC).
121300 Video LoopthroughStart succeeded
121301 User input is not valid.
121302 Initialisation of the VIP failed.
121303 Unable to stop the loop through before restarting.
121304 Video Signal on the input is not a valid signal.
121305 Initialisation of the VFE failed.
Example
DS:> 1213 rgb pal
121300:
Test OK @
Nucleus Name DS_SYS_VideoLoopThroughStop
Nucleus Number 1214
Description Stop routing the video input to all the outputs.
Technical - Stop the DENC and the Video Front End
User Input None
121400 VideoLoopthroughStop succeeded
121401 DENC module on Codec failed.
Example
DS:> 1214
121400:
Test OK @

Nucleus Name DS_SYS_VideoLoop
Nucleus Number 1215
Description The Codec generates a video signal with a specific signature and sends it to
the output of the digital board. The user selects which video input path must be
routed on the digital board and a video standard. The Codec encodes the video
signal, checks the signature, and returns a conclusion.
Note: Before executing this nucleus the user must route the video signal on the
VIP using DS_VIP_Routing.
Technical - Evaluate user input.
- Reset the global variables, video memory.
- Fill the video memory with a vertical colourbar.
- Initialise the Codec SYNC-module.
- Initialise the Codec MIXER-module.
- Initialise the Codec VPP-module.
- Initialise the Codec DENC-module.
- Display the original image.
- Initialise the VIP.
- Initialise the Codec VFE-module.
- Try to detect a sync in the VIP input.
- Catch the received image in memory.
- Display the received image.
- Compare the received image with original image.
- Create a conclusion.
User Input <VideoSignal> <VideoStandard>
1. Video Signal (CVBS,YC,RGB,YUV,DTT).
2. VideoStandard (PAL, NTSC).
121500 Videoloop test succeeded.
121501 Wrong user input.
121502 The Codec SYNC-module cannot be initialised.
121503 The Codec MIXER-module cannot be initialised.
121504 The Codec VideoPostProcessor-module cannot be initialised.
121505 The Codec DENC-module cannot be initialised.
121506 The VideoInputProcessor cannot be initialised.
121507 The VideoInputProcessor cannot detect a sync-signal.
121508 The Codec VideoFrontEnd-module cannot be initialised.
121509 The Codec VideoFrontEnd-module cannot capture a video
field.
121510 When selected the RGB video input:
Error in colour red signal and/or
Error in colour green signal and/or
Error in colour blue signal.
When selected one of the other video inputs:
Error in luminance signal (Y) and/or
Error in chrominance signal (U) and/or
Error in chrominance signal (V).
Example
DS:> 1215 cvbs ntsc
121500:
Test OK @
DS:> 1215 cvbs pal
121508: The VideoInputProcessor cannot detect a sync-signal.
Error @
DS:> 1215 yuv ntsc
121511:
Error in luminance signal(Y)
Error in chrominance signal(U)
Error in chrominance signal(V)
Error @

Nucleus Name DS_SYS_AudioLoop
Nucleus Number 1216
Description In this nucleus the Codec generates an audio sine signal with a specific
signature and sends it to the output of the digital board. The Codec encodes
the audio signal to MPEG I layer II and after this the signature of the signal will
be checked.
Note: Before executing this nucleus the user must route the audio signal on
the VIP using DS_VIP_Routing.
Technical - The user needs to route the signal to the audio inputs so the test can
encode the audio to MPEG I layer II
- An audio signal is generated, resulting in a sine of 6kHz on the left and
12kHz on the right channel.
- Then the signal is decoded in memory.
- When both signals are detected correctly in the MPEG, the test succeeded.
User Input InputType:
- I2S (default, when no user input is given)
- SPDIF: This input needs a second parameter:
- OPT (optical, default, when no user input is given)
- COAX
121600 Testing the components on the audio signal path succeeded
121601 The audio encoder did not initialise.
121602 No audio could be generated.
121603 The audio encoder did not encode audio.
121604 The audio could not be decoded.
121605 Frequency on left channel out of range.
121606 Frequency on right channel out of range.
121607 The frequencies on both channels are out of range.
121608 Frequency on left channel out of range. Right channel silent.
121609 Right channel is silent.
121610 Frequency on right channel out of range. Left channel silent.
121611 Left channel is silent.
121612 Both channels are silent.
Example
DS:> 1216
121600:
Test OK @
DS:> 1216 spdif coax
121600:
Test OK @
DS:> 1216 spdif opt
121600:
Test OK @

Nucleus Name DS_SYS_SlashVersionSet
Nucleus Number 1217
Description Set the slash version of the system
Technical - Decode the user input for the slash version to set
- Issue the command to set the slash version to the analogue board
User Input The slash version
121700 Setting the slash version succeeded
121701 Invalid slash version, no slash version is set.
121702 Setting the slash version on the Analogue Board fails.
121703 Invalid input.
121704 The returned error code from the analogue board is unknown:
121705 No DS error code known for analogue board error:
121706 There was no response from the analogue board.
121707 Retrieving the current version failed
121708 Unknown recorder layout type
121709 Validating the section where the version is stored failed
121710 Getting the configuration section from NVRAM failed
121711 Initialisation of IIC or reaching NVRAM failed
Example
DS:> 1217 82
121700:
Test OK @
Nucleus Name DS_SYS_SlashVersionGet
Nucleus Number 1218
Description Get the slash version of the system
Technical - Issue the command to get the slash version to the analogue board
- Return the received information to the user
User Input None
121800 Getting the slash version succeeded
121801 Getting the slash version failed
121802 The IIC write failed
121803 The IIC read failed
121806 Reading the slash version failed
121808 Reading an unexpected section version in NVRAM
Example
DS:> 1218
121800: The slash version is: 82
Test OK @
Nucleus Name DS_SYS_VirginModeOn
Nucleus Number 1220
Description Turn on the virgin mode functionality (e.g. the auto channel search upon start-
up)
Technical - Issue the command to set the bit for the virgin mode to the analogue board
User Input None
122000 Turning on the virgin mode succeeded
122001 Turning on VirginMode on the Analogue Board failed.
122005 Section validation or write failed in NVRAM
122006 Reading the CONFIG section from NVRAM failed
Example
DS:> 1220
122000:
Test OK @

Nucleus Name DS_SYS_VirginModeOff
Nucleus Number 1221
Description Turn off the virgin mode functionality (e.g. the auto channel search upon start-
up)
Technical - Issue the command to reset the bit for the virgin mode to the analogue
board
User Input None
122100 Turning off the virgin mode succeeded
122101 Turning off VirginMode on the Analogue Board failed.
122106 Reading the CONFIG section from NVRAM failed
Example
DS:> 1221
122100:
Test OK @
Nucleus Name DS_SYS_VirginModeGet
Nucleus Number 1222
Description Get the virgin mode functionality status (e.g. the auto channel search upon
start-up)
Technical - Issue the command to reset the bit for the virgin mode to the analogue
board
User Input None
122200 Getting the virgin mode succeeded
122201 Reading the Virgin Mode flag from NVRAM failed
122202 Initialisation of IIC or reaching the NVRAM failed
122203 Reading an unexpected version of the section in NVRAM
Example
DS:> 1222
122200: The Virgin Mode functionality is: ON
Test OK @
Nucleus Name DS_SYS_DisplayFatalOn
Nucleus Number 1223
Description Turn on the display-fatal functionality which displays debug-information on the
display when encountering a fatal error condition from which could not be
recovered automatically
Technical - Issue the command to use the display-fatal functionality to the analogue
board
User Input None
122300 Turning on the display-fatal functionality succeeded
122301 Turning on the display-fatal functionality failed
122306 Reading the section from NVRAM failed
Example
DS:> 1223
122300:
Test OK @

Nucleus Name DS_SYS_DisplayFatalOff
Nucleus Number 1224
Description Turn off the display-fatal functionality which displays debug-information on the
display when encountering a fatal error condition from which could not be
recovered automatically
Technical - Issue the command to stop using the display-fatal functionality to the
analogue board
User Input None
122400 Turning off the display-fatal functionality succeeded
122401 Turning off the display-fatal functionality failed
122402 The returned errorcode from the analogue board is unknown:
122403 No DS errCode known for analogue board error:
122406 Reading the section from NVRAM failed
Example
DS:> 1224
122400:
Test OK @
Nucleus Name DS_SYS_DisplayFatalGet
Nucleus Number 1225
Description Get the display-fatal flag of the recorder
Technical - Issue the command to get the status of the display-fatal functionality to the
analogue board
User Input None
122500 Getting the display-fatal flag succeeded
122501 Getting the display-fatal flag failed
122502 The returned errorcode from the analogue board is unknown:
122503 No DS errCode known for analogue board error:
122505 Reading the display fatal flag failed
122507 Unexpected version read from NVRAM section
122508 Reading the fatal flag from NVRAM failed
Example
DS:> 1225
122500: The Display Fatal functionality is ON
Test OK @
Nucleus Name DS_SYS_SettingsSet
Nucleus Number 1226
Description Programs the digital board settings into the boot EEPROM on the digital board.
Technical - Evaluate user input.
- Set-up IIC-bus.
- Write data to boot EEPROM.
- Update checksum.
Execution Time 1 second
User Input A large hexadecimal value that represents the digital board hardware
information string
122600 The settings were successfully programmed.
122601 User input is invalid.
122602 IIC access failed.
Example
DS:>1226 44424849716040014C45434F2B0000006020070000010200000101008
008000044564452323030312E30303102020000000103000000020100000000000
00000
122600:
Test OK @

Nucleus Name DS_SYS_SettingsDisplay
Nucleus Number 1228
Description Show the settings that are programmed in the BROM on the digital board.
Technical - Set-up IIC-bus.
- Read Digital Board Settings from boot EEPROM.
- Display the settings.
User Input None.
122800 The settings were successfully displayed.
122802 Invalid settings
Example
DS:> 1228
Investigating the system, please wait...
DBHI-string :
44424849716040014C45434F2B0000006020070000010200000101008008000044
56445232303031
2E3030310202000000010300000002010000000000000000
Boardname : LECO+
Hardware ID : 60
Download Table Filename : DVDR2001.001
RAM type : DDRAM
RAM size [MB] : 128
ROM bank 1 type : NOR
ROM bank 1 size [MB] : 8
ROM bank 2 type : none
ROM bank 2 size [MB] : 0
EEPROM I2C-bus0 size [KB] : 0
EEPROM I2C-bus1 size [KB] : 0
Codec id : PNX7350
VIP id : SAA7136
Progressive scan id : codec internal
Dvio physical layer id : PDI1394P25
Dvio link layer id : PDI1394L41
USB id : Internal
Connector S2B : not available
Connector IDE1 : available
Connector IDE2 : available
Connector PCI : not available
Connector AVI : not available
Connector HDMI : not available
Connector DVB-T : not available
Interface analog board : IIC-bus
Audio output : stereo
Audio clock scheme : none
YUV matrix : not available
Bit Engine drive : D 4.3
122800:
Test OK @
Nucleus Name DS_SYS_SettingsGet
Nucleus Number 1229
Description Get the digital board diversity settings string that is programmed in the BROM
on the digital board.
Technical - Set-up IIC-bus.
- Read Digital Board Settings from boot EEPROM.
- Read System Settings from boot EEPROM.
- Display the settings.
User Input None.
122900 The settings were successfully displayed.
122902 The settings are invalid
Example
DS:> 1229
122900:
44424849716040014C45434F2B0000006020070000010200000101008008000044
564452
323030312E3030310202000000010300000002010000000000000000
Test OK @

Nucleus Name DS_SYS_AudioLoopThroughStart
Nucleus Number 1230
Description Description: The audio input is routed from the input to all outputs. The input is
set routing the signal with the proper nucleus. All outputs are enabled.
Technical - Encode the audio to AC3 in memory
- Decode the AC3 in memory to audio on the outputs
Execution Time 1second buffer time and 30 seconds playing.
User Input InputType:
- I2S (default)
- SPDIF (Only for recorders with 5.1 input and DTT module)
InputPort: (Only for recorders with 5.1 input. For DTT modules no parameter
should be filled in, so default is chosen )
- OPT : Optical input path is selected (default)
- COAX : Coax input path is selected
123000 AudioLoopthroughStart succeeded
123001 Resetting the audio decoder failed
123002 Resetting the audio encoder failed
123003 Encoding the audio failed
123004 Decoding the audio failed
Example
DS:> 1230
123000:
Test OK @
Example DTT
DS:> 1230 spdif
123000:
Test OK @
Example 5.1 input
DS:> 1230 spdif coax
123000:
Test OK @
Nucleus Name DS_SYS_AudioLoopThroughStop
Nucleus Number 1231
Description Stop routing the audio input to all the outputs
Technical - Send the Mute command to the audio decoder and reset the audio
decoder
User Input None.
123100 AudioLoopthroughStop succeeded
123101 Resetting the audio decoder failed
123102 Resetting the audio encoder failed
Example
DS:> 1231
123100:
Test OK @

Nucleus Name DS_SYS_SettingsHwIdSet
Nucleus Number 1232
Description This nucleus sets the HW-Id in the HW-diversity string
Technical - Read out the HW-diversity string
- Modify the HW-ID in that string as requested
- Write the modified HW-diversity string to the EEPROM
User Input - <HW-ID> - The hardware ID to set
- No input - The user will be asked for the ID
123200 Setting the hardware ID succeeded
123201 Setting the hardware ID failed
123202 The user aborted setting the hardware ID, no changes made
Example
DS:> 1232
Enter the new HW ID of the digital board (Currently equals 21)
Enter a value between 0 and 99:
> 22
The HW ID will be set to: 22. Is that correct? ([Y/N]):y
123200:
Test OK @
DS:> 1232
Enter the new HW ID of the digital board (Currently equals 22)
Enter a value between 0 and 99:
>
The HW ID will be set to: 0. Is that correct? ([Y/N]):N
123202: Setting the HW ID was aborted by the user.
Error @
DS:> 1232 99
123200:
Test OK @

Nucleus Name DS_SYS_SettingsDoubleCheck
Nucleus Number 1233
Description Double check whether stored HW-string equals actual HW as far
as we can automatically detect this. An automatic and a manual mode is
supported.
Technical - Read out the HW diversity string
- Check whether these settings correspond the actual hardware
- In case of modification: Write back the new HW-diversity settings.
Execution Time 4 seconds in auto mode when everything matches
User Input - manual or MANUAL to enter manual mode
- default is automatic mode where the nucleus stops upon and reports the
first encountered error
123300 Double checking the HW-diversity settings succeeded
123301 Double check failed, a difference in settings was encountered
123302 Reading the HW-diversity settings failed
123303 Writing the modified HW-diversity settings failed
Example
DS:> 1233
123300:
Test OK @
DS:> 1233 manual
123300:
Test OK @
DS:> 1233
123301:
Hardware ID mismatch: in HW-Diversity string:99, actual in FLASH:0
Error @
DS:> 1233 manual
Hardware ID mismatch! in HW-Diversity string:99, actual in FLASH:0
Enter the correct HW ID of the digital board.
> 0
The HW-diversity string has been modified by you. Settings:
Board name: DIAG
Hardware ID: 0
Codec IC: PNX7100_MF3
Video Input Processor IC: SAA7118
Progressive Scan Deinterlacer IC: None
Progressive Scan Denc IC: ADV7196
I-Link physical layer circuit IC: PDI1394P25
I-Link link layer circuit IC: PDI1394P40
Audio clock: Clock scheme 1
Bit engine connector: available
IDE connector 1: available
IDE connector 2: not available
PCI connector: not available
RAM size 32MByte
ROM size (NOR FLASH bank 1) 8MByte
ROM size (NOR FLASH bank 2) Not available
ROM size (NAND FLASH) Not available
Is it OK to program this in
the new HW-diversity string? ([y]es/[n]o):y
Diversity HW-string programmed successfully.
123300:
Test OK @
DS:>

Nucleus Name DS_SYS_SettingsDlTableFilenameSet
Nucleus Number 1234
Description This nucleus sets the Download table filename in the HW-diversity string
Technical - Retrieve the new filename from the user
- Ask the user whether the filename is correct before setting it
- Update the diversity settings to use the newly entered filename
Execution Time Dependent on the user confirmation
User Input - The filename to be set
- No input - No new filename will be set
123400 Setting the new filename succeeded
123401 Unsupported setting of the current HW-diversity settings
123402 Setting the filename was aborted by the user.
Example
DS:> 1234
Enter the new Download Table Filename (Currently equals
DVDR2001.001)
Enter a filename:
>
The Download Table Filename will be set to: DVDR2001.001. Is that
correct? ([Y/N]):
123402: Setting the filename was aborted by the user.
Error @
DS:> 1234
Enter the new Download Table Filename (Currently equals
DVDR2001.001)
Enter a filename:
>DVDR2002.001
The Download Table Filename will be set to: DVDR2002.001. Is that
correct? ([Y/N]):Y
123400:
Test OK @
Nucleus Name DS_SYS_IicWriteRead
Nucleus Number 1235
Description Perform an IIC write-read action on the digital board
Technical - Determine bus ID, slave address, number of bytes to be written and the
byte array of data from the user input
- Initialise IIC
- Write the data to the IIC slave
- Read the data from the IIC slave
User Input The user inputs the Bus ID, Slave Address, number of bytes to read,
number of bytes to write and the bytes to be written
<NucNr><BusId><SlaveAddr><ReadLen><WriteLen><WrByte0...WrByteN>
Max number of bytes to write: 255
Max number of bytes to read: 255
123500 Writing data to and reading data from the IIC slave succeeded
123502 There was a bus timeout reading the device
123506 Unknown IIC bus error received
123511 Number of bytes out of range
Example
DS:> 1235 0 0xa0 0xf 1 0
0x0000: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x0008: 0x00 0x00 0x00 0x00 0x00 0x00 0x00
123500:
Test OK @

Nucleus Name DS_SYS_BuildInfoGet
Nucleus Number 1236
Description Retrieve the software build information of the Diagnostics & Service application
Technical - Show the information that is stored in the DVDR_BuildInfoType structure
User Input None
123600 Retrieving build info succeeded
123601 Retrieving build info failed
Example
DS:> 1236
123600:
Version :1091
Build :20050823_0630
Release :SG1_1
Buildtype :dev
Baseline :SGP29atl#SG1_1_20050609_base
Variant :genlecoplus
Test OK @
Nucleus Name DS_SYS_UartSetup
Nucleus Number 1237
Description Set up a configuration for the selected UART
Technical - Parse user input
- Use MIS_UART_Setup to setup the selected UART with the requested
parameters
User Input The user inputs 6 parameters:
<UartNr><baudrate><flowcontrol><databits><parity><stopbits>
UartNr:
1=UART port 1 : not used (Chrysalis only)
2=UART port 2 : Bit Engine or DTTM (Chrysalis only)
baudrate:
115200,62500,57600,38400,19200,9600,4800,2400,1200
flowcontrol:
0=disabled 1=enabled
databits:
7 or 8
parity:
NO, ODD or EVEN
stopbits:
1 or 2
123700 Setting up the selected UART succeeded
123701 User provided Invalid setup parameters
123702 Setting up the selected UART Failed
123703 Selected UART is not available
Example (Chrysalis)
DS:> 1237 2 38400 0 8 NO 1
123700:
Test OK @
Example (Leco)
DS:> 1237 2 38400 0 8 NO 1
123703: The selected UART is not available
Error @

Nucleus Name DS_SYS_LowPowerStandby
Nucleus Number 1239
Description Send wakeup reason to ASP and set the set to low power standby.
Technical - Set up ASP
- Send wakeup reason to ASP
- Send low power standby command to ASP
Execution Time Vary (Maximum time will depend on the relative timer used)
User Input - wakeup reason - the wakeup reason for the DB to power up
- timer - relative timing for the DB to power up if wakeup reason 1 or 3 is
chosen
123901 Invalid data was given by the user
123902 Failed to communication to ASP
Example
DS:> 1239
Wakeup reason from Low Power Standby
1) timer only
2) local key or RC pressed only
3) any reason
or press 'a' to abort
1
Enter time to wake up from low power standby.
Range 1 - 5 mins:
1
Entering low power standby
Nucleus Name DS_SYS_DivxModelIdSet
Nucleus Number 1240
Description Sets the Divx Model Id in NVRAM.
Technical - Initialize the NVM interface.
- Read the NVRAM CONFIG section into RAM
- Store the Divx model id into the CONFIG section in RAM
- Validate the CONFIG section in RAM
- Write the CONFIG section in RAM back into the non-volatile storage.
Execution Time Less than 2 seconds
User Input - 16-bit word containing the 12-bit Divx model Id.
- For example :
o 0x3031 (means Low Byte : 0x30 and High Byte 0x31)
124001 Validate CONFIG section failed
124002 Cannot read CONFIG section
124003 Invalid user parameters
124004 Error initializing NVRAM interfaces
Example
DS:> 1240 0x3031
124000:
Test OK @
Nucleus Name DS_SYS_DivxModelIdGet
Nucleus Number 1241
Description Retrieves the Divx Model Id from NVRAM.
Technical - Read the CONFIG section from NVRAM
- Check the header information of the CONFIG section to ensure that it is
Version 4
- If Version 4 is detected, proceed to read and display the High Byte and
Low byte of the Divx Model Id.
User Input None.
124101 Section version not Version 4
Example
DS:> 1241
124100: Divx model id high byte = 0x31, low byte = 0x30
Test OK @
Nucleus Name DS_SYS_DivxModelIdSet
Nucleus Number 1240
Description Sets the Divx Model Id in NVRAM.
Technical - Initialize the NVM interface.
- Read the NVRAM CONFIG section into RAM
- Store the Divx model id into the CONFIG section in RAM
- Validate the CONFIG section in RAM
- Write the CONFIG section in RAM back into the non-volatile storage.
User Input - 16-bit word containing the 12-bit Divx model Id.
- For example :
o 0x4BF0 (means Low Byte : 0x4B and High Byte 0xF0)
124001 Validate CONFIG section failed
124003 Invalid user parameters
Example
DS:> 1240 0x4BF0
124000:
Test OK @
Nucleus Name DS_SYS_DivxModelIdGet
Nucleus Number 1241
Description Retrieves the Divx Model Id from NVRAM.
Technical - Read the CONFIG section from NVRAM
- Check the header information of the CONFIG section to ensure that it is Version 4
- If Version 4 is detected, proceed to read and display the High Byte and Low byte of
the Divx Model Id.
User Input None.
124101 Section version not Version 4
Example
DS:> 1241
124100: Divx model id high byte = 0xF0, low byte = 0x4B
Test OK @

HIGH-DEFINITION MULTIMEDIA INTERFACE (HDMI)
Nucleus Name DS_HDMI_DevTypeGet
Nucleus Number 1500
Description Get the device (revision) type information of the HDMI-IC.
Technical - Read out the information through IIC
User Input None
150000 Getting the device type of the nucleus succeeded
150001 Failed to retrieve the hardware diversity string
150002 Failed to initialise the IIC communication
150003 The hardware was not detected although indicated by Diversity
150004 Failed to access HDMI transmitter chip SI9030
Example
DS:> 1500
150000:
Vendor ID : 0x 0 0x 1
Device ID : 0x91 0x42
Device Revision : 0x 0
Test OK @
Nucleus Name DS_HDMI_Communication
Nucleus Number 1501
Description Check the communication between the I2C controller on the Codec and the
HDMI-IC by reading and writing data to one device register. This test detects
faults of the I2C lines or a defected HDMI transmitter IC.
Technical - Read out an accessible register in the HDMI transmitter IC
- Modify this register by writing a known value to it
- Read back and check this value for correctness
User Input None
150100 Communicating with the HDMI tx chip succeeded
150104 An IIC-bus error occurred
150108 There was an IIC error upon the stop-condition
150109 The IIC bus was chosen wrong
150110 The IIC functionality is not running
150111 An unknown error was returned by the IIC read
150112 The data written did not equal the date read
Example
DS:> 1501
150100:
Test OK @

Nucleus Name DS_HDMI_EdidParse
Nucleus Number 1502
Description Return the E-EDID (Enhanced Extended Display Identification Data) contained
in the HDMI / DVI able TV attached to the DVD+RW.
Parse the information retrieved to print the capabilities of the TV in user
understandable format
Technical - Read out the E-EDID through the DDC channel (IIC)
- Parse the information contained in the E-EDID
- Print out the information to the user in understandable format
User Input None
150200 Getting the configuration of the HDMI-IC succeeded
150204 Retrieving the E-EDID failed
Example
DS:> 1502
Checksum OK of EDID block 0.
Checking EDID Structure with 1 extensions:
Checking each Extension for consistency.
E-EDID structure contains no errors.
EDID structure OK.
Vendor Specific Data Block: 03 0c 00 10 00
Attached Display is an HDMI device.
EDID Version 1.3
Total Native DTD Formats = 0
Monitor Features (CEA Byte 3): BasicAudio YCbCr444
YCbCr422
HDMI compatible EDID
Supported video format 1
index:0 Linear PCM 1 channels, 48KHz, 44KHz, 32KHz,
SPK:RLC FLC RC RL FC LFE FL
RRC FRC .. RR .. ... FR
Attached display is HDMI compatible.
Display is YCbCr444 compatible.
Display is YCbCr422 compatible.
150200:
Test OK @

Nucleus Name DS_HDMI_DefaultVideoSet
Nucleus Number 1503
Description Set a default video configuration in the HDMI TX chip (720x480p)
Technical - Write a known configuration for 720x480P in the registers of the HDMI
transmitter chip
User Input <Id> configures the HDMI transmitter to receive an embedded or a separated
sync signal at its input.
Chose embedded sync if signal comes directly from Leco+ (ITU656) or
separated sync if signal comes from Fli2310.
Id:

<id > HDMI Tx input configuration
0 Separated sync input (default)
1 Embedded sync input
150300 Setting the video configuration succeeded
150304 Setting the video configuration failed
Example
DS:> 101 11 ntsc all
010100:
Test OK @
DS:> 1516
151600:
Test OK @
DS:> 1503
150300:
Test OK @
or
DS:> 101 0 ntsc pscan
010100:
Test OK @
DS:> 1503 1
150300:
Test OK @
Nucleus Name DS_HDMI_Reset
Nucleus Number 1504
Description Reset the HDMI transmitter chip by means of a hardware reset and re-initialize
in order to have the HDMI transmitter chip accessible again.
Technical - Pull the reset line connected to the HDMI transmitter low
- Wait a little while
- Enable the HDMI chip again by setting the reset line high
User Input None
150400 Resetting the HDMI tx chip succeeded
150404 Resetting the HDMI tx chip trhrough PIO failed.
150405 Software Reset of the HDMI tx chip failed.
Example
DS:> 1504
150400:
Test OK @

Nucleus Name DS_HDMI_DdcIicWrite
Nucleus Number 1506
Description Perform an IIC write action to a device on the DDC bus
Technical -
User Input <TimeOut> <Slave address> <offset> <nr of bytes> <d1> <.> <dx>
150600 Writing to the device was OK, number of bytes is echoed
150604 Writing the bytes to the device failed
150605 Decoding time-out unsigned value failed
150607 Decoding offset unsigned value failed
150609 Number of bytes out of range. Should be less than 17.
150610 Incorrect number of data bytes entered
150611 Unable to initialise IIC
Example
DS:> 1506 1 0xa0 1 0
150600:
Test OK @
DS:> 1506 1 0xa8 1 0
150604: Writing the bytes to the device failed.
Error @
Nucleus Name DS_HDMI_DdcIicRead
Nucleus Number 1507
Description Perform an IIC read action to a device on the DDC bus
Technical -
User Input <TimeOut> <Slave address> <Offset> <Number of bytes>
150700
150704 Reading from the device on the DDC bus failed
150705 Decoding time-out unsigned value failed
150707 Decoding offset unsigned value failed
Example
DS:> 1507 1 0xa0 0 15
[ 0]:0x0
[ 1]:0xff
[ 2]:0xff
[ 3]:0xff
[ 4]:0xff
[ 5]:0xff
[ 6]:0xff
[ 7]:0x0
[ 8]:0x34
[ 9]:0xa9
[ 10]:0x53
[ 11]:0xc0
[ 12]:0x1a
[ 13]:0x0
[ 14]:0x0
150700:
Test OK @

Nucleus Name DS_HDMI_ExtendedWrite
Nucleus Number 1508
Description Perform an IIC write action on port 0/1 of the HDMI transmitter
Technical -
User Input <Port> <Register> <Data> Where 0 == Port 0 and 1 == Port 1
150800 Byte was written OK
150804 A wrong port number was given by the user
150805 An invalid register was given by the user
150806 Invalid data was given by the user
150807 There was an error writing to the register indicated
Example
DS:> 1508 0 0x10 0x22
150800:
Test OK @
Nucleus Name DS_HDMI_ExtendedRead
Nucleus Number 1509
Description Perform an IIC read action on port 0 or 1 of the HDMI transmitter
Technical -
User Input <Port> <Register> Where 0 == Port0 and 1 == Port 1
150900 Byte was read and echoed OK
150904 A wrong port number was given by the user
150905 An invalid register was given by the user
150906 There was an error reading the register indicated
Example
DS:> 1509 0 0x10
150900: Data read: 0x22
Test OK @
Nucleus Name DS_HDMI_CheckHPDTx
Nucleus Number 1510
Description Check whether Hot-Plugging of the HDMI cable is detected by the SII9030
HDMI transmitter.
Technical -
User Input None
151000 The Hot Plug was detected OK by the HDMI transmitter
151004 Error writing to interrupt register
151005 Error reading interrupt register
151006 Test aborted by user
151007 Unknown action
Example
DS:> 1510
Insert or remove the HDMI cable.(or type 'a' to abort):
151006: Test aborted by user.
Test OK @
DS:> 1510
151000:
Test OK @

Nucleus Name DS_HDMI_CheckHPDChrysalis
Nucleus Number 1511
Description Check whether Hot-Plugging of the HDMI cable is detected by the software.
This tests the interrupt line to the Chrysalis.
Technical -
User Input None
151100 The Hot Plug was detected OK by software. Interrupt line OK.
151104 Error writing to HDMI tx register
151105 User aborted HPD test
151106 Error reading from HDMI tx register
Example
DS:> 1511
151100:
Test OK @
DS:> 1511
151105: User aborted HPD test.
Test OK @
Nucleus Name DS_HDMI_FLI2310_DevTypeGet
Nucleus Number 1512
Description Get the device and revision information of the FLI2310
Technical -
User Input None
151200 Retrieving the device type information succeeded
Example
DS:> 1512
151200:
Chip name : 2300
Chip version : 4
Test OK @
Nucleus Name DS_HDMI_FLI2310_Communication
Nucleus Number 1513
Description Test whether the communication to the FLI2310 can be established
Technical -
User Input None
151300 Something is properly read so the communication is OK
151309 The read data is not the same as the written data
Example
DS:> 1513
151300:
Test OK @

Nucleus Name DS_HDMI_FLI2310_TestImageOn
Nucleus Number 1514
Description Generate a test image using the FLI2310
Technical -
User Input None
151400 Test image is generated successfully
151404 Unable to generate image
151405 Unable to initialise De-inter-lacer
Example
DS:> 1514
151400:
Test OK @
Nucleus Name DS_HDMI_FLI2310_TestImageOff
Nucleus Number 1515
Description Switch of test-image generation by the FLI2310
Technical -
User Input None
151500 Test image is turned off successfully
151504 Unable to initialise De-Inter-lacer
151505 IIC Error during writing DENC
Example
DS:> 1515
151500:
Test OK @
Nucleus Name DS_HDMI_FLI2310_Routing
Nucleus Number 1516
Description Have the FLI2310 pass the video from its input to its output
Technical -
User Input None
151600 Routing path is created successfully
151604 Unable to initialise the Chrysalis.
151605 Unable to access de-inter-lacer
Example
DS:> 1516
151600:
Test OK @

Nucleus Name DS_HDMI_FLI2310_ExtendedWrite
Nucleus Number 1517
Description Write to any register of the FLI2310
Technical -
User Input <Register> <RegLen:1=8bits;2=16bits> <Data>
151700 The IIC write action succeeded
151704 Decoding register unsigned value failed
151705 Decoding register length unsigned value failed
151706 Decoding register data unsigned value failed
151707 Error writing to register
Example
DS:> 1517 0x303 1 0x9a
151700:
Test OK @
Nucleus Name DS_HDMI_FLI2310_ExtendedRead
Nucleus Number 1518
Description Read from any register of the FLI2310
Technical -
User Input <Register> <RegLen:1=8bits;2=16bits>
151800 The IIC read action succeeded
151804 Decoding register unsigned value failed
151805 Decoding register length unsigned value failed
151806 Error reading from the register
Example
DS:> 1518 0x303 1
151800: Data read: 0x009A
Test OK @
Nucleus Name DS_HDMI_FLI2310_1080I
Nucleus Number 1519
Description Set the Faroudja FLI2310 to generate a 1080I image from the video on its
inputs.
Technical -
User Input None
151900 Generating the up-scaled image succeeded
151904 Generating the up-scaled image failed
151905 Unable to configure HDMI Tx.
Example
DS:> 1519
151900:
Test OK @

Nucleus Name DS_HDMI_Audio
Nucleus Number 1528
Description Set the proper audio settings to the HDMI transmitter.
Note: When 1528 spdif is used to set the HDMI transmitter audio settings
correctly and just 103 is entered i.s.o. 103 spdif then clicking audio is heard
because the Chrysalis audio decoder does not use its SPDIF-path explicitly.
Note: Currently there is an issue in the order of the tests:
- Reboot the set.
- First create the video, as audio is passed alongside the video on HDMI
- Create the spdif audio using nucleus 103 spdif
- Create the spdif audio settings in the HDMI transmitter using nucleus
1528 spdif
- The spdif audio will be audible
- Switch off spdif audio using nucleus 104
- Create i2s audio using nucleus 103
- Create the i2s audio settings in the HDMI transmitter using nucleus
1528 or 1528 I2S
- The audio will be audible
- Switch off the audio using nucleus 104
Technical -
User Input SPDIF - Set the HDMI transmitter's audio path to SPDIF
I2S or nothing - Set the HDMI transmitter's audio path to I2S
152800 Creating the proper audio settings succeeded
Example
DS:> 1528 i2s
152800: i2s
Test OK @
DS:> 1528 spdif
152800: spdif
Test OK @

ANALOGUE SLAVE PROCESSOR (ASP)
Nucleus Name DS_ASP_Communication
Nucleus Number 1600
Description This nucleus checks the communication between the IIC controller of the Codec
and the ASP.
Technical - Initialise IIC-bus.
- Read something from ASP.
- Handle the errorcode.
User Input None
160000 Communicating with the ASP succeeded
160005 Got unknown IIC bus error
Example
DS:> 1600
160000:
Test OK @
Nucleus Name DS_ASP_Version
Nucleus Number 1601
Description This nucleus returns the version number of the software running on the ASP or
MCU and if available that of the display driver.
Technical - Read versions from ASP and display it.
User Input None
160100 Retrieving the software versions succeeded
160101 The IIC bus initialisation failed.
160102 The IIC bus failed.
160103 The CRC checksum of the message is wrong.
Example
DS:> 1601
160100:
Software version : 0.9
Display driver version: 0.1
Hardware version : 0x02
Hardware layout : 0x03
Hardware revision : 0x00
Test OK @

Nucleus Name DS_ASP_RealTimeClockSetValues
Nucleus Number 1602
Description This nucleus is used to set the real time clock to the correct values.
Technical - Decode the user input.
- Write RTC value to ASP.
User Input User must give time and date like this:
hh:mm:ss dd/mm/yy
160200 Setting the real time clock succeeded
160201 The ASP initialisation failed.
160203 Wrong user input.
Example
DS:> 1602 03:20:01 22/06/03
160200:
Test OK @
Nucleus Name DS_ASP_RealTimeClockGetValues
Nucleus Number 1603
Description This nucleus is used to retrieve the actual real time from the ASP
Technical - Read RTC value from ASP.
- Decode the RTC value.
User Input None
160300 Retrieving the real time succeeded
160301 The ASP initialisation failed.
160303 The CRC checksum of the message is wrong.
160304 The Real Time Clock has been found invalid or was not found.
Example
DS:> 1603
Time: 03:20:17
Date: 22/06/03 (dd/mm/yy)
160300:
Test OK @
Nucleus Name DS_ASP_NTCGet
Nucleus Number 1606
Description This nucleus reads the value of the NTC-resistor connected to the ASP, which
tells the ambient temperature to the processor.
Technical - Read the ADC input pin of the ASP that is connected to the NTC-resistor.
- Display this value.
User Input None
160600 Getting the NTC-value succeeded
160601 The IIC bus failed
Example
DS:> 1606
160600: Temperature(NTC) ADC input value = 0x94
Test OK @

Nucleus Name DS_ASP_FanSpeedSet
Nucleus Number 1607
Description This nucleus sets the speed of the fan that controls the temperature within the
set.
Technical - Decode user input.
- Set pio-pins FAN_C1 and FAN_C2.
User Input Speed to be set: off, low, medium, high
160700 Setting the new fan speed succeeded
160701 The IIC bus failed
Example
DS:> 1607 low
160700:
Test OK @
Nucleus Name DS_ASP_LightDisplay
Nucleus Number 1608
Description This nucleus lights the entire display.
Technical - Set all segments on in the display buffer.
- Set the grids correct in the display buffer.
- Send the display buffer to the ASP.
User Input None
160800 Lighting the entire display succeeded
160801 IIC-bus communication failed
Example
DS:> 1608
160800:
Test OK @
Nucleus Name DS_ASP_BlinkDisplay
Nucleus Number 1609
Description This nucleus lights the entire display, and lets it blink. Only for ASP
Technical - Set all segments on in the blink buffer.
- Set the grids correct in the blink buffer.
- Send the blink buffer to the ASP.
User Input None or on to start the blinking of the display.
off To stop the blinking of the display.
160900 The test succeeded
Example ASP
DS:> 1609
160900:
Test OK @
DS:> 1609 off
160900:
Test OK @

Nucleus Name DS_ASP_DimmingDisplay
Nucleus Number 1610
Description This nucleus lights the entire display, and dims it.
Technical - Change in a loop the display brightness from maximum to minimum.
User Input ON or OFF
Example
DS:> 1610 ON
161000:
Test OK @
Nucleus Name DS_ASP_ClearDisplay
Nucleus Number 1611
Description This nucleus clears the display and deactivates dimming/blinking functionality
Technical - Make the display buffer empty.
- Make the blink buffer empty.
- Send the display buffer to the ASP.
- Send the blink buffer to the ASP.
User Input None
Example
DS:> 1611
161100:
Test OK @
Nucleus Name DS_ASP_KeyBoard
Nucleus Number 1612
Description This nucleus checks all keys of the keyboard by having the user confirm the
key-code displayed of all keys. If the user presses a or A the test is aborted.
If the user presses o or O the test is indicated as OK.
If the user holds down PLAY for more than a second the test is indicated as
OK, if the user holds down RECORD the test is indicated as failed.
Indicate the number of keys pressed to the user, both in the terminal logging
and on the display.
Technical - Initialise the display.
- Display the key pressed by the user on the display.
- Monitor the service port for an abort and get the next key pressed.
- Update the display and repeat previous steps until user stops / confirms.
- Display the number of keys that were pressed.
Execution Time Depends on the user.
User Input None
161200 Checking all keys succeeded
161202 The user signals a failure of the keyboard
161203 The user aborted the test
Example
DS:> 1612
161200: 3 keys were pressed.
Test OK @

Nucleus Name DS_ASP_RemoteControl
Nucleus Number 1613
Description This nucleus checks the interface to the remote control by having the user
confirm the key-code displayed.
At least one key must be tested.
If the user presses a or A the test is aborted. If the user presses o or O the
test is indicated as OK.
If the user holds down PLAY for more than a second the test is indicated as
OK, if the user holds down RECORD the test is indicated as failed.
Indicate the number of keys pressed to the user, both in the terminal logging
and on the display.
Technical - Initialise the display.
- Display the key pressed by the user on the display.
- Monitor the service port for an abort and get the next key pressed.
- Update the display and repeat previous steps until user stops / confirms.
- Display the number of keys that were pressed.
Execution Time Depends on the user.
User Input None
161302 The user signals a failure of the remote control
161303 The user aborted the test
Example
DS:> 1613
161300: 4 keys were pressed.
Test OK @
Nucleus Name DS_ASP_LEDsOn
Nucleus Number 1614
Description Switches on the display leds.
Technical ASP specific
- Check if the analogue board is a MOBO board, if so:
- Read the ASP pio port.
- Set the RECORD-LED bit on in this port.
- Write the ASP pio port.
- Set the TRAY-LED bit on in this port.
- Set the EPG-LED bit on in this port.
- Else
- Set the RECORD-LED bit on.
- Write the external ASP pio port.
- Set the TRAY-LED bit on.
- Set the EPG-LED bit on.
MCU Specific
- Get the user input and capitalize it and check validity
- Check which lights should be turned on
- Write the command to the MCU
User Input None, Green or Red: Choose which colour of the bi-led should be lit with the
rest (only for OLAL22PREMIER variant)
161400 Switching on the LEDs succeeded
Example
DS:> 1614
161400:
Test OK @

Nucleus Name DS_ASP_LEDsOff
Nucleus Number 1615
Description This nucleus switches off the display leds.
Technical ASP specific
- Check if the analogue board is a MOBO board, if so:
- Set the RECORD-LED bit off in this port.
- Set the TRAY-LED bit off in this port.
- Set the EPG-LED bit off in this port.
- Else
- Set the RECORD-LED bit off.
- Set the TRAY-LED bit off.
- Set the EPG-LED bit off.
MCU Specific
- Write the command to the MCU to turn all display leds off
User Input None
161500 Switching off the LEDs succeeded
Example
DS:> 1615
161500:
Test OK @
Nucleus Name DS_ASP_Reset
Nucleus Number 1616
Description This nucleus resets the ASP.
Technical - Reset the ASP by toggling the reset wire by a GPIO pin of the codec.
- Wait 500ms according to the HSI.
- Read Status from ASP.
- Put ASP in normal mode.
- Configure general ASP PIO.
- Make a ASP pio pin low to read the version.
- Get GPP40 - GPP47 and GPP48 - GPP55.
- Decode hardware version, revision, and layout.
- Configure the ASP clock.
- Configure display, part 1.
- Configure display, part 2.
- Configure blinking.
- Configure external ASP PIO.
- Configure ADC input.
- Configure remote control input.
- Enable power on the AV3.
User Input None
161600 Reset command succeeded
Example
DS:> 1616
161600:
Test OK @

Nucleus Name DS_ASP_Watchdog
Nucleus Number 1618
Description This nucleus configures the watchdog timer of the ASP, and waits till the
watchdog expires. The watchdog time-out is 10 seconds. On expiry of the
watchdog timer, the ASP switching off, and on its power supply, and resets the
main controller.
So, this nucleus will not return an error code when the test succeeded, but the
system will restart again.
Technical - Configure watchdog timer.
- Wait till the watchdog expired.
User Input None
161801 IIC-bus communication failed.
161802 The ASP did not reset the host processor.
Example
DS:> 1618
Waiting till the watchdog expires.
Factory Diagnostics and Service Software
DVD Video Recorder (Sep 10 2004, 08:11:24)
Version :662 Build :20040910_0515
Release :C1_1 Buildtype :no
Baseline :F_C1_195 Variant :verum:dvdrw2_lib
DS:>
Nucleus Name DS_ASP_Reboot
Nucleus Number 1619
Description This command forces a reboot of the main controller. The ASP shutdown the
digital board power supply and then switch it on to force reset.
So, this nucleus will not return an error code when the test succeeded, but the
system will restart again.
Technical - Send command reboot to ASP.
User Input None
161901 IIC-bus communication failed.
161902 The ASP did not reset the host processor.
Example
DS:> 1619
DVD Video Recorder (Sep 10 2004, 08:11:24)
Version :662 Build :20040910_0515
Release :C1_1 Buildtype :no
Baseline :F_C1_195 Variant :verum:dvdrw2_lib
DS:>

Nucleus Name DS_ASP_PioExtended
Nucleus Number 1623
Description This nucleus enables the user to switch all the General Purpose Pins of the
ASP.
Technical - Decode user input.
- Execute the parameter command.
User Input One of the next parameters can be used
GPIO CONFIG <GPP> <DIR> <MODE>"
"GPIO SET <GPP> <VALUE>"
"GPIO GET <GPP>"
"ADC GET <GPP>"
"ADC CONFIG <BYTE0> <BYTE1> <BYTE2>"
(See CONFIG_ADC command parameters)
where <GPP> = 0 .. number of GPP pins
where <DIR> = 0 (input) or 1 (output)
where <MODE> = 0 or 1
0 = input without notification/push-pull output
1 = input with notification/open drain output
where <VALUE> = 0 (low) or 1 (high)
162301 Invalid user input.
Example
DS:> 1623 GPIO SET 45 0
162300:
Test OK @
Nucleus Name DS_ASP_8SC2Check
Nucleus Number 1624
Description Check if the 8SC2 signal (slow blanking) can be set low, medium and high. The
user must connect SCART2 (pin8) to SCART1 (pin8) on the outside of the set.
Works on EURO sets only.
Technical - Set the SCART1_PIN8_OUT pin low
- Measure the value on the ASP 8SC2 input ADC
- Set the SCART1_PIN8_OUT pin to medium level
- Measure the value on the 8SC2 input ADC
- Set the SCART1_PIN8_OUT pin Matrix high
- Measure the value on the ASP 8SC2 input ADC
User Input None
162400 Detecting 8SC2 signal succeeded
162401 Detecting 8SC2 signal failed
162402 This test is not applicable for current HW layout
162403 Could not retrieve hardware version from ASP
Example
DS:> 1624
162400:
Test OK @

FRONTEND (TUNER) (FRE)
Nucleus Name DS_FRE_Communication
Nucleus Number 2000
Description This nucleus checks the communication between the IIC controller of the Codec
and the Front End (Tuner) on the analogue board
Technical - Determine whether anything can be read from the FRE through IIC
User Input None
200000 Communicating with the front end succeeded
200005 Got unknown IIC bus error
Example
DS:> 2000
200000:
Test OK @

Nucleus Name DS_FRE_ChannelSelect
Nucleus Number 2001
Description This nucleus sets the tuner to receive a valid audio and video signal
Technical - Parse the user input to determine all parameters to set
- Pass these parameters to the respective parts using IIC
User Input <Frequency*16> <video standard id> <Tuner>
Tuner frequency: to tune the tuner to e.g. 216 MHz, this parameter must be
3456. (Since 216*16 = 3456. This is to avoid the decimal points to the
parameter list.)
Video Standard ID: The table below shows which video standards are possible
ID Europe Nafta / Apac
0 PAL_BG_S NTSC
1 PAL_BG_M Invalid
2 PAL_I_M Invalid
3 PAL_DK_S Invalid
4 PAL_DK_M Invalid
* Video Standard ID: For TCSM0601PD25F tuner only
ID Europe
0 PAL_BG
1 PA_I
2 PAL_DK
3 SECMA L
4 SECAM L
Tuner: Select the tuner type that you want to tune. This input is not mandatory.
(If no input is detected, tuner will be defined run-time (if recognised).)
* Refer to Video Standard ID table for TCSM0601PD25F tuner
Name Colour system Transmission
standard
Sound modulation
PAL_BG_S PAL BG FM-Stereo
PAL_BG_M PAL BG FM-Mono / NICAM
PAL_I_M PAL I FM-Mono / NICAM
PAL_DK_S PAL DK FM-Stereo
PAL_DK_M PAL DK FM-Mono / NICAM
NTSC_M_S NTSC M FM-Stereo
Tuner Tuner ID Runtime Detected
1 FE1316 (Europe Philips) V
2 FE1319 (Europe Philips) V
3 TMQZ2-403A (Europe ALPS)
4 JS6B2-L121 (Europe Xuguang)
5 TCPK0601 (APAC Samsung)
6 TCMN0682 (NAFTA Samsung) V
7 TCPK0600 (APAC Samsung)
8 TCPD0601 (APAC Samsung)
9 VPC12R_ENG56PPG1F (Panasonic)
10 * TCSM0601PD25F (Europe Samsung)
11 TCSN9082PA26AF (Nafta Samsung)
200100 Setting the tuner channel succeeded
200101 Invalid user input
200102 Getting the version of the set failed
200103 Configuration of the tuner failed
200104 Configuration of the IF module failed
Example
DS:> 2001 3456 0 1
200100:
Test OK @

HARD DISK DRIVE (HDD)
Nucleus Name DS_HDD_Communication
Nucleus Number 2100
Description Check the communication between the digital board and the hard disk drive by
querying the device type of the hard disk drive
Technical - Initialise/start IDE
- Check for an ATA device on the IDE interface
User Input None
210000 Communication with the hard disk drive succeeded
210001 The initialisation of IDE failed
210002 Communication with the hard disk drive failed
Example
DS:> 2100
210000: Found a hard disk drive: MASTER device on IDE interface 1
Test OK @
Nucleus Name DS_HDD_Reset
Nucleus Number 2101
Description Reset the hard disk drive
- Toggle the IDE reset pin of the selected interface
User Input None
Error 210100 Resetting the hard disk drive succeeded
210103 Failed to reset the hard disk drive
Example
DS:> 2101
210100: Resetting IDE interface 1 succeeded
Test OK @
Nucleus Name DS_HDD_VersionGet
Nucleus Number 2102
Description Get the vendor- and product identification and the product revision level of the
hard disk drive
- Send ATA command IDENTIFY DRIVE
- Display the serial, firmware revision and model information
User Input None
Error 210200 Version info successfully
210203 Failed to get version info from the hard disk drive
Example
DS:> 2102
210200: Serial number = F19LP8WE,Firmware rev. = VAM51JJ0 ,Model
nu
mber = Maxtor 2F040L0
Test OK @

Nucleus Name DS_HDD_WriteRead
Nucleus Number 2103
Description Write data to the hard disk, read it back and verify the data read back.
- Generate a random sector number
- Generate test data to write to the disk
- Read the data from the sector using READ_SECTOR(S) and store this in a
temporarily buffer
- Transfer the test data to the disk location using ATA command
WRITE_SECTOR(S)
- Read back the data from the disk location using ATA command
READ_SECTOR(S)
- Write back the data from the temporarily buffer
User Input None
Error 210300 Version info successfully
210303 Unable to retrieve device capabilities from HDD
210304 Writing data to HDD failed
210305 Reading back data from HDD failed
210306 Data read back did not equal written data
Example
DS:> 2103
210300: OK, writing to sector 3f95776
Test OK @
Nucleus Name DS_HDD_CapabilitiesGet
Nucleus Number 2104
Description Get the cylinders, heads and track information of the hard disk drive
- Send ATA command Identify drive information
- Display all required capabilities
User Input None
Error 210400 Capabilities are displayed correctly
210403 Failed to get information from the hard disk drive
Example
DS:> 2104
Number of cylinders 16383
Number of heads 16
Number of sectors per track 63
Capacity in sectors 80293248
Number of current cylinders 16383
Number of current heads 16
Number of current sectors per track 63
Current capacity in sectors 16514064
Number of unformatted bytes per track 0
Number of unformatted bytes per sector 0
210400:
Test OK @

Nucleus Name DS_HDD_Diagnostics
Nucleus Number 2105
Description Shall perform the internal diagnostic tests implemented by the hard disk drive.
- Send the diagnostic (ATA) command to the HDD device
User Input None
210500 The Diagnostic test on the hard disk drive device succeeded
210501 The hard disk drive failed
210501 The diagnostics ATA command failed
Example
DS:> 2105
210500:
Test OK @
Nucleus Name DS_HDD_UploadImage
Nucleus Number 2106
Description Upload raw data from the HDD to a DVD+RW
- Check for an ATAPI DVD+RW drive
- Calibrate the DVD+RW laser
- Repeat until transfer is completed
- Read x MB from HDD source sector into SDRAM
- Write x MB from SDRAM to the destination sector on DVD+RW
- Read sector 0x34000 on DVD containing the transfer table to use
- Update the contents of the table and write it back
Execution Time Depending on the number of sectors to transfer it may take approximately 2 MB
per second.
User Input The user can enter 3 parameters in the next format:
<COMMAND> <HDD sector> <nr of HDD sectors>
<COMMAND> is one of the next strings:
NEW: Create a new transfer image table, <HDD sector> and <nr of
HDD sectors> must be entered.
ADD: Add a section to the current transfer table, <HDD sector> and
<nr of HDD sectors> must be entered
READ: Read the current transfer image table from the DVD. The tray
of the DVD drive is sent out an the user is asked to insert a DVD+RW
VIEW: View the contents of the current transfer table
GO: Copy data from the HDD to the DVD+RW according to the
currently entered transfer table
<HDD sector> = the sector on HDD to start reading from
<HDD sectors> = the number of HDD sectors to transfer
210600 Uploading image succeeded
210603 Communication with the AV3 failed
210604 No DVD+RW is available
210605 Calibrating DVD+RW failed
210607 Error while reading image data from HDD
210608 Error while writing image to DVD+RW
210609 Unable to update the transfer table on the DVD+RW

Example
DS:> 2106
210605: Invalid user input
Error @
DS:> 2106 READ
Please insert a writable DVD+RW
210609: Unable to update transfer table
Error @
DS:> 2106 NEW 0x1 2048
Creating new transfer table
Adding entry 1 to transfer table
Length 1 entries
210605: NEW 0X1 2048
Test OK @
DS:> 2106 VIEW
Length 1 entries
Entry 1:
hddPosition : 0x1
nrHddSectors : 0x800
dvdPosition : 0x34040
nrDvdSectors : 0x200
210605: VIEW
Test OK @
DS:> 2106 ADD 0x2001 20480
Adding entry 2 to transfer table
Length 2 entries
210605: ADD 0X2001 20480
Test OK @
DS:> 2106 GO
Please insert a writable DVD+RW
Executing transfer table 1 of 1, size 1048576 bytes (=1 MB)
Calibrating laser of DVD drive
Start creating image on DVD at 0x34040. Checking ... <OK>
210600: Transfer OK
Test OK @

Nucleus Name DS_HDD_DownloadImage
Nucleus Number 2107
Description Download a raw image from a DVD+RW disc to the hard disc drive. This image
will be written on the hard disc drive.
- Check for an ATAPI DVD+RW drive
- Mount the DVD containing the image to transfer
- Read sector x containing the transfer table to use
- Read the source sector, destination sector and transfer length from the
transfer table
- Repeat until transfer is completed
- Read x MB from DVD source sector into SDRAM
- Write x MB from SDRAM to the destination sector on HDD
Execution Time Assumption based on 4.3GB data 11 movies of 3 minutes.
33 minutes
User Input Actions:
The tray of the DVD drive is sent out and the user is asked to insert a DVD+RW
210700 Downloading image succeeded
210703 Communication with the AV3 failed
210704 No disc is available
210705 Invalid medium is mounted
210706 Unable to read the transfer table from DVD
210707 Error while reading image from DVD
210708 Error while writing image to HDD
Example
DS:> 2107
Please insert the Master DVD <OK>
Executing transfer table 1 of 4
524288 bytes
Dvd Sector 0x50000
Dvd Sector Count 256
Hdd Sector 0x40000
Hdd Sector Count 1024
please wait ..<OK>
10485760 bytes (=10 MB)
Dvd Sector 0x70000
Hdd Sector 0x60000
please wait ..<OK>
524288 bytes
Dvd Sector 0x50000
Hdd Sector 0x40000
please wait ..<OK>
524288 bytes
Dvd Sector 0x50000
Hdd Sector 0x40000
please wait ..<OK>
210700: Transfer OK
Test OK @

Nucleus Name DS_HDD_RandomReadScan
Nucleus Number 2108
Description Perform a short random read scan of x times 1000 commands (x is
selectable between 1 to 20) to test the servo. If anything would
be wrong with the servo or tracking, the result would be too
slow. Recheck the LBA addresses that caused the disc to fail in
order to avoid incorrect failure caused by shock or vibrations
during the measurement.
Technical - Initialise the HDD connection
- Get the user input
- Generate a random sequence of test sectors
- For every sector in the random sequence do
- Read 1000 sectors and measure the time to perform this action
- Update a list of statistics about the measurement
- Display statistical information about the test sequence
- If more than 10% above 160 ms and/or more than 1 request in between
200 & 250ms and/or requests above 250 ms make the result of the test fail.
Execution Time Depending on the user input x times 4 minutes
User Input parameters in the next format:
<nr_cmds><GRAPH>
- Number of commands to send (in multiples of 1000), if no input
is given 1000 commands will be sent
- "GRAPH" optional to print out the measured read scan graph
210801 The initialisation of the HDD failed
210803 Performance failure: more than 10% above 160 ms and/or
more than 1 request in between 200 & 250ms and/or
requests above 250 msec
210804 Read error, unable to read a specified sector from disc
Example
DS:> 2108 1
210800:
Minimum access time = 142 msec
Maximum access time = 159 msec
Average access time = 146 msec
Number of commands below 160 msec = 1000
Number of commands between 160 and 200 msec = 0
Number of commands above 250 = 0
Test OK @

Nucleus Name DS_HDD_LinearSurfaceScan
Nucleus Number 2109
Description Perform a linear surface scan so that most of the disc is covered.
Technical - Initialise the HDD connection
- Get the user input
- Generate a sequence of test sectors according to the user input
- For every sector in the sequence do
- Read the sector and measure the time to perform this action
- Update a list of statistics about the measurement
- Display statistical information about the test sequence
- If more than 1% above 100 ms and/or more than 0.1% above 200 msec
and/or requests above 300 msec make the result of the test fail.
Execution Time Depending on the user input and HDD size
User Input parameters in the next format:
<SECTORS> <STEP> <LOW> <HIGH>
where
- SECTORS: Specifies the number of sectors to read in each access
- STEP: Specifies the step (in sectors) between each access.
- LOW: The start sector address of an explicit range of LBA
addresses to be used for testing. If no value is entered LBA
0 will be used
- HIGH: The end sector address of an explicit range of LBA
addresses to be used for testing. If no value is entered the
maximum LBA will be used.
The user must enter either no parameter or all parameters
If no parameters are entered the next defaults will be used:
1000 sector each access, steps of 1000 sectors and an address
range from 0 to the maximum LBA
210901 The initialisation of the HDD failed
210903 Performance failure: more than 10% above 160 ms and/or
more than 1 request in between 200 & 250ms and/or
requests above 250 msec
210904 Read error, unable to read a specified sector from disc
Example
DS:> 2109 1000 1000 0 100000
210900:
Executed 100 linear seeks of 1000 sectors each
Minimum access time = 141 msec
Maximum access time = 148 msec
Average access time = 141 msec
Number of commands below 160 msec = 100
Number of commands above 250 = 0
Test OK @

Nucleus Name DS_HDD_SpinOff
Nucleus Number 2110
Description Put the HDD in parking position by sending the sleep command so it can be
moved without endangering the mechanical parts
- Send the Sleep (ATA) command to the HDD device
User Input None
211000 The spin off of the hard disk drive device succeeded
211003 The sleep ATA command failed
Note All other HDD nuclei will not work until DS_HDD_Reset is executed
Example
DS:> 2110
211000:
Test OK @
Nucleus Name DS_HDD_SectorRead
Nucleus Number 2111
Description Read 512 bytes from a specified sector on HDD
Technical - Get the user input
- Read the data from the sector using READ_SECTOR(S) and display the
contents
User Input 3 parameters in the next format: <sector> <offset> <length>
where
- sector is the sector to read from
- offset is the byte-offset in the sector buffer (0 .. 256)
- length the length (in bytes) of the data to display (1 .. 256)
211100 Reading from HDD succeeded
211104 The read command failed
Example
DS:> 2111 0x80001 0 128
211100:
0x00 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
Test OK @

Nucleus Name DS_HDD_SetPower
Nucleus Number 2112
Description Set the power of the HDD On or Off
Technical - Get user input
- Set the IDE1_POWER PIO line to the desired value
User Input 1 parameter:
"ON" , enables the power of the HDD
"OFF" , turn off the power of the HDD
211200 Setting the HDD power mode succeeded
211201 Setting the HDD power mode failed
Note All other HDD nuclei will not work until DS_HDD_Reset is executed
Example
DS:> 2112 off
211200:
Test OK @
Nucleus Name DS_HDD_ValidateBootSegmentHeader
Nucleus Number 2113
Description Validates the Boot Segment Header in the HDD.
Technical - Initializes the HDD interface.
- Reads 8 bytes from LBA 0x8001
- Compares these 8 bytes with 0x42,0x4F,0x4F,0x54,0x2D,0x48,0x44,0x4D
- If identical, returns pass. Else Hard Disk Boot Segment Header is corrupt.
User Input None.
211300 Validation of Hard Disk Boot Segment Header passed.
211301 Hard Disk Boot Segment Header corrupt or does not match
expected values.
211302 HDD init failed.
211303 Starting HDD failed.
211304 Reading from HDD failed.
Example
DS:> 2113
211300:
Test OK @

Nucleus Name DS_USB_DevTypeGet
Nucleus Number 2300
Description This nucleus retrieves the device and type information of the USB controller
Technical - Read out the chip-ID and revision register and return the info to the user
Execution Time < 1 sec.
User Input None
230000 Retrieving the device type information succeeded
Example
DS:> 2300
230000: USB Controller chip ID: 0x6123 Revision:0x10.
Test OK @
Nucleus Name DS_USB_Reset
Nucleus Number 2301
Description This nucleus performs a software reset of the controller and tests whether the
functional state of the controller has become USBReset
Technical - Write the command to software reset the controller and read back the
functional status of the controller
User Input None
230100 Resetting the host controller succeeded
230101 Resetting the host controller failed
Example
DS:> 2301
230100:
Test OK @
Nucleus Name DS_USB_CheckDeviceConnect
Nucleus Number 2302
Description This nucleus checks whether a device connect / disconnect can be aught by the
software
Technical - Initialise the host controller and its interrupts
- wait for the port connect status change interrupt
- display the status cause (connect/disconnect) of the interrupt
Execution Time Depending on user actions
User Input None
230200 The device connect was noticed by the hardware correctly
230201 Retrieving the information from the diversity string failed
230202 User aborted HPD test
Example
DS:> 2302
Insert or remove the USB cable (or type 'a' to abort):
230200:
Test OK @
UNIVERSAL SERIAL BUS (USB)

Nucleus Name DS_USB_ CheckDeviceSpeed
Nucleus Number 2303
Description This nucleus checks whether the connected device functions at low / full or high
speed.
Technical - Initialise the host controller and its interrupts
- Find out the total number of ports
- Read out the port status and display it
User Input None
230300 The device connect was noticed by the hardware correctly
230301 Retrieving the information from the diversity string failed
Example
DS:> 2302
230200: Full Speed device on port number: 1
Test OK @

SCRIPT (SCRIPT)
Nucleus Name DS_IH_ScriptHandler
Nucleus Number Script
Description The test requires no user interaction. A number of nuclei will be run before a
message is returned indicating if there is a failure in the DVD Recorder. When a
nucleus failed, the script stops and displays the message "FAIL". Otherwise it
displays "PASS" at the end when all nuclei are executed. During the execution
of a script, a progress indicator is displayed on the display of the DVD
Recorder.
Technical Execute the included nuclei one by one
If a nucleus fails quit and display the failed nucleus on the local display and
service port
Included tests: 1. DS_CHR_DEVTYPEGET_NUC
2. DS_SDRAM_WRITEREADFAST_NUC
3. DS_FLASH_DEVTYPEGET_NUC
4. DS_FLASH_CHECKSUMPROGRAM_NUC
5. DS_VIP_COMMUNICATION_NUC
6. DS_VIP_DEVTYPEGET_NUC
7. DS_DVIO_LINKDEVTYPEGET_NUC
8. DS_DVIO_PHYCOMMUNICATION_NUC
9. DS_DVIO_PHYDEVTYPEGET_NUC
10. DS_BE_COMMUNICATIONECHO_NUC
11. DS_BE_VERSIONGET_NUC
12. DS_SYS_HARDWAREVERSIONGET_NUC
13. DS_SYS_SOFTWAREVERSIONBOOTGET_NUC
14. DS_SYS_SOFTWAREVERSIONDOWNLOADGET_NUC
15. DS_SYS_SOFTWAREVERSIONAPPLGET_NUC
16. DS_SYS_DVIDNUMBERGET_NUC
17. DS_SYS_SLASHVERSIONGET_NUC
18. DS_SYS_SETTINGSDISPLAY_NUC
19. DS_SYS_BUILDINFOGET_NUC
20. DS_ASP_COMM_NUC
21. DS_ASP_VERSION_NUC
22. DS_FRE_COMM_NUC
23. DS_HDD_COMMUNICATION_NUC
24. DS_HDD_VERSION_NUC
DS_USB_DEVTYPEGET_NUC
Note! Invocation by holding down the PLAY button when powering up the
system
Note! The following example is for Lecoplus variant only
Example
DVD Video Recorder (Dec 15 2006, 14:14:54)
Version :1463 Build :20061215_1352
Release :SG1_1 Buildtype :dev
Baseline :SGP29atl#SG1_1_20050609_base Variant :lecoplusleadV1
Executing User/Dealer script.
Busy executing NUC100

Device ID 7300
Codec ID PNX7350
F-BCU (0x0102) 4.0 INTC (0x011d) 3.0 SIF (0xa04b) 2.0
BOOT (0x010a) 3.1 CONFIG (0x013f) 5.0 RESET (0x0123) 5.0
CLOCK (0x013e) 7.0 DEBUG (0x0116) 0.1 UART0 (0x0107) 1.2
UART1 (0x0107) 1.2 I2C0 (0x0105) 0.1 I2C1 (0x0105) 0.1
GPIO (0x013c) 3.1 SYNC (0x013a) 4.0 OSD (0x0136) 1.0
SPU (0xa00e) 1.1 MIXER (0x0137) 3.0 DENC (0x0138) 5.0
CCIR (0x0139) 2.1 VDEC (0x0133) 1.0 PARSER (0xa00d) 0.0
DV (0xa00c) 0.0 IDE0 (0xa009) 1.2 IDE1 (0xa009) 1.2
SGDX (0xa008) 4.0 BYTE (0xa00b) 1.0 OUTPUT (0xa003) 8.0
ACOMP (0xa000) 8.0 VFE (0xa001) 8.0 VCOMP (0xa002) 8.0
SCR (0xa004) 8.0 SIFF (0xa011) 3.0 PSCAN (0xa05d) 0.1
ADEC (0x0134) 1.1 IR (0x0131) 2.0 AOI (0xa08c) 0.0
PIP (0xa04d) 1.0 AVLINK (0xdead) 10.11 USBLINK(0xa08e) 0.0
MSVD (0xa087) 0.0 FEBCU (0xa05e) 1.0 BM (0xa085) 0.0
BMI (0xa084) 0.0 DISP (0xa04d) 1.0
Found FLASH memory:
NOR ST M29DW160ET 2MB
BootCode , in FLASH, checksum is: 0xBABE7E83, which is correct
Diagnostics, in FLASH, checksum is: 0xBABED436, which is correct
Download , in FLASH, checksum is: 0xBABE7C57, which is correct
Application, on HDD , checksum is: 0xBABE5D76, which is correct
Found SAA7136
Be version = 52.07.02.10.PHILIPS ,D5.2, 52070210,5VC0635130300,
Basic Engine returned no OPU info
Hardware ID = 0x66
Software Boot Version = 1463
Software Download Version = 1463
Software Application Version = 1463
The DvIdNumber is: 0000000000
The slash version is = 11602
PASS
DS:>

Alignments & Test Procedures
Restoration of settings in NVM after Digital Board Replacement
In a new Digital Board, the non-volatile memory (NVM), where the factory settings of the set are stored, is an
empty device. If the factory settings such as Slash Version and Hard Diversity String are not initialized properly
after Digital Board replacement, the set can only start up in Diagnostic Software Mode.
For the set to start up and function normally with a new digital board, using the commands in Diagnostic
Software (DS) from the PC via HyperTerminal connection to the set, the following settings should be restored.
Slash information (or slash version)
IEEE Unique number (or DV ID)
Hard Ware Diversity String (or Hardware ID)
DivX Model ID
5.8. Setting Slash Version
The slash version is stored with DS command 1217 followed by the slash version as parameter.
The slash versions used in DVDR3570H and DVDR3590H are as follows:
DVDR3570H/97 & DVDR3590H/97: 13601
DVDR3570H/75 & DVDR3590H/75: 13602
DVDR3590H/93: 13620
Example:
DS:> 1217 13601
121700:
Test OK@
With DS command 1218 the slash version can be displayed
5.9. Setting IEEE Unique Number
1. Note the serial number of the set example:
VN19 0650 100070
- VN = production center (VN.Szekesfehervar).
According to UAW-500: V=22 and N=14 (A = 1, B = 2, C =3, etc)
- 19 = change code (this is not used for this calculation)
- 06 = YEAR
- 50 = Production WEEK
- 100070 = Lot and SERIAL number
2. Calculate the unique number: this number always exists out of 10 hexadecimal numbers
3. First 5 numbers: First we calculate a decimal number according to formula below:
- 35828*YEAR + 676*WEEK + 26*V +N + 8788
- The gures are xed, YEAR, WEEK and production center codes V, N are variables
- Example: 35828*06 + 676*50 + 26*22 + 14 + 8788 = 258142 (decimal)
- Then we translate this decimal number to a hexadecimal number.
- Example: 258142 = 3F05E (hex)
4. Last 5 numbers: The last 5 numbers exist out of the Lot and SERIAL number.
We have to translate the decimal number to the next 5 hexadecimal numbers:
Example: 100070 (decimal) = 186E6 (hex)
5. This IEEE Unique number (10-digit hexadecimal number) is stored with DS command 1207.
Example:
DS:>1207 3F05E186E6
120700:
Test OK@
The set has now its original IEEE unique number.
With DS command 1208 the number can be displayed

5.10. Setting HardwareID
With DS command 1228 (command mode interface) the system settings including the Hardware Diversity
String can be displayed
Note: An error in the Diversity string will render the set not able to boot-up and the Digital board will
be defective.
Via the Diagnostic Software the Diversity String can be stored with the command 1226, followed by the
Diversity String as parameter. That stored Diversity String can be checked with the DS command 1229.
The Diversity String used in DVDR3570H/75/97 and DVDR3590H/75/97/93 is as follow:
44424849E38840014C2B30365F3600006620070000020300000101004002000044564452323030312E303031
0202000000010300010002010000410000000000
Example:
DS:> 1226 44424849E38840014C2B30365F360000662007000002030000010100400200004456445232303031
2E3030310202000000010300010002010000410000000000
122600:
Test OK @
5.11. Checking and Setting DivX Model ID
DivX Model ID is stored in NVM on the Digital Board to generate the DivX VOD (Video On Demand) registration
code. The DivX VOD registration code allows the user to rent or purchase videos from DivX VOD Service at DivX
website and play back them on the set.
If the DivX Model ID is wrongly set, the DivX VOD registration will be wrongly calculated and, as a result, the
playback of the videos downloaded from the DivX website will not be possible.
The DivX Model ID Assigned to all Philips Models is 0x4BF0.
Checking DivX Model ID
The DivX Model ID can be checked with DS Command 1241.
Example:
DS:> 1241
124100: DivX model id high byte = 0xf0, low byte = 0x4b
Test OK @
Setting DivX Model ID
The DivX Model ID can be stored via Diagnostic Software with the DS Command 1240, followed by 0x4BF0 as
a parameter.
Example:
DS:> 1240 0x4BF0
124000:
Test OK @
Note: Returning the set to the user after digital board replacement, inform the user that the device will generate
a new DivX VOD code, the previous purchased titles may not play anymore and they need to re-activate this
device again in the DivX Website under the same user account.

EN 95 3139 785 32804
6. Block Diagrams, Waveforms, Wiring Diagram
Overall Block Diagram
S
C
L_5V
S
D
A
_5V
O
ptical
D
ig
it a
lB
d.
12345678910111213141 5161718
G
N
D
S
C
L_S
S
D
A
_S
G
N
D
W
S
R
O
S
T
B
Y
D
D
_O
N
FA
N
_S
P
E
E
D
FA
N
_S
P
E
E
D
_F
IN
E
REGION_SEL _A_P90_DECON
REGION_SEL_B_P91_DECON
G
N
D
8S
C
1
H
D
_O
N
8S
C
2
IM
U
T
E
LO
O
P
_T
H
R
U
_O
N
Y
U
V
_A
C
T
IV
E
N
1
A
U
D
IO
1
L
2
G
N
D
3
A
U
D
IO
1
R
4
G
N
D
5
A
U
D
IO
2
L
6
G
N
D
7
A
U
D
IO
2
R
8
G
N
D
9
N
/U
10
G
N
D
11
N
/U
1 2
G
N
D
13
LR
1_L
14
G
N
D
15
LR
1_R
16
G
N
D
17
D
_K
IL L
18
D
A
O
U
T
19
G
N
D
20
D
A
IN
C
O
A
X
(n/u)
21
D
A
IN
O
P
T
(n/u)
22
G
N
D
23
S
IF
2 4
G
N
D
1234567891011121314151617181 9202 1222324
D
_U
B
G
N
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D
_Y
G
G
N
D
D
_V
R
G
N
D
D
_C
G
N
D
D
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G
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D
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V
B
S
G
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D
S
C
1
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V
B
S
G
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D
V m
ux_6_out
G
N
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A
_Y
G
G
N
D
A
_U
B
G
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A
_V
R
G
N
D
Vm
ux_5_out
G
N
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D
5
.
2
C
l
o
s
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1
40
H
A
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-
D
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(
1
6
0
G
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)
(
2
5
0
G
B
)
O
O
24
A
U
D
IO
1
L
23
G
N
D
22
A
U
D
IO
1
R
2 1
G
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20
A
U
D
IO
2
L
1 9
G
N
D
18
A
U
D
IO
2
R
17
G
N
D
16
N
/U
15
G
N
D
14
N
/U
13
G
N
D
12
LR
1_
L
11
G
N
D
10
LR
1_
R
9
G
N
D
8
D
_K
ILL
7
D
A
O
U
T
6
G
N
D
5
D
A
IN
C
O
A
X
9(n/u)
4
D
A
IN
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P
T
(n/u)
3
G
N
D
2
S
IF
1
G
N
D
A
L
1
A
R
1
A
na
lo
g
B
d.
C
V
B
S
A
L
A
R
5V
B
U
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U
S
B
M
U
S
B
P
G
N
D
123456
TP
B
n
TP
B
G
N
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TP
A
n
TP
A
G
N
D
1234
12345
G
N
D
+ 5
V
S
T
B
Y
+1
2V
S
T
B
Y
V
N
S
T
B
Y
G
N
D9
A
F
C
R
I_F
C
8
G
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7
A
F
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LI_F
C
6
G
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5C
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B
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F
IN
_F
C
4
G
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3
C
F
IN
_F
C
2
G
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1
Y
F
IN
_F
C
G
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D
N
/U
D
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_S
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G
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D
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T
_O
N
F
B
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T
654321
D
D
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_ C
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123456789101112
3V
3
D
3V
3
D
3V
3
D
3V
3
D
G
N
D
12V
D
G
N
D
G
N
D
5V
D
G
N
D
G
N
D
5 N
D
18171615141 3121110987654321
1
40
1
40
I2S
_IN
I2S
_O
U
T
T
X
D
S
E
R
V
IC
E
R
X
D
N
/U
G
N
D
N
/U
+
5V
1234567 123456
123456
P
H
I
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_U
B
G
N
D
D
_Y
G
G
N
D
D
_V
R
G
N
D
D
_C
G
N
D
D
_Y
G
N
D
D
_C
V
B
S
G
N
D
S
C
1_C
V
B
S
G
N
D
V
m
ux_6_out
G
N
D
A
_Y
G
G
N
D
A
_U
B
G
N
D
A
_ V
R
G
N
D
V
m
ux_5_out
G
N
D
12345678910111213141516171819202 1222324
M
IU
_A[1 :22]
P
IO
3_
M
IU
_D
[0:15]
S
P
D
IF_O
U
T
A
I22
A
I11
A
I33
A
I13
A
I23
A
I43
A
I31
A
I41
A
I21
A
I12
A
I42
G
N
D
S
C
L_S
3V
3
S
D
A
_S
3V
3
G
N
D
W
S
R
O
S
T
B
Y
D
D
_O
N
F
A
N
_A
F
A
N
_B
REGIO
N_SEL_A_P90_DECON
REGIO
N
SEL_B _P91_DECO
N
G
N
D
8S
C
1/A
F
C
H
D
_O
N
8S
C
2/W
S
R
1
IM
U
T
E
LO
O
P
_T
H
R
U
_O
N
Y
U
V
_A
C
T
IV
E
N
G
N
D
N
/U
D
T
T
_S
E
L
G
N
D
D
T
T
_O
N
F
B
O
U
T
1
A
IN
F
R
2
G
IN
D
3
A
F
IN
L
4
G
N
D
5
C
V
B
S
F
IN
6
G
N
D
7
C
F
IN
8
G
N
D
9
Y
F
IN
S
P
D
IF1
_IN
S
D
0
V
IP
_I2S
_O
U
T
I2C
0
n/u
1
G
N
D
2
D
_B
C
LK
3
G
N
D
4
D
_W
C
LK
5
D
_D
A
T
A
0
6
G
N
D
7
D
_M
C
LK
8
G
N
D
1
G
N
D
2
D
_B
C
LK
3
G
N
D
4
D
_W
C
LK
5
D
_D
A
T
A
0
6
G
N
D
7
D
_P
C
M
C
LK
8
G
N
D
A
L
A
R
A
L
2
A
R
2
T
X
D
S
E
R
V
IC
E
R
X
D
N
/U
G
N
D
N
/U
+5
V
1 2 3 4 5 6 7
Set Block Diagram 3139-249-40531-130-a3.pdf 2006-10-10
6. Block Diagrams, Waveforms, Wiring Diagram.

EN 96 3139 785 32804
Wiring Diagram
4
0
-
p
i
n

I
D
E

c
o
n
n
e
c
t
o
r

3
V
3
D

3
V
3
D

3
V
3
D

3
V
3
D

5
V
D

G
N
D

G
N
D

1
7
0
0

1

2

3

4

5

6

7

8

9

1
0

1
1

1
2

5
N
D

G
N
D

G
N
D

1
2
V
D

G
N
D

5

4

3

2

1

G
N
D

I D

+
D

- D

+
5
V

1
3
0
2

6

5

4

3

2

1

G
N
D

T
P
A
0
+

T
P
A
0
-
G
N
D

T
P
B
0
+

T
P
B
0
-
1
3
0
1

4

3

2

1

+
5
V
E

G
N
D

G
N
D

+
1
2
V
E

1
3
0
1

G
N
D

1
4

1

2

3

4

5

6
7

8

9

1
0

1
1

1
2

1
3

G
N
D

V
F
D
_
C
L
K

D
I S
P
_
D
A
T
A

D
I S
P
_
C
L
K

D
I S
P
_
S
T
B
N

S
T
D
B
Y
_
L
E
D
N

R
C

G
N
D

G
N
D

T
E
M
P
_
S
E
N
S
E

K
E
Y
1

K
E
Y
2
3

S
E
L
K
E
Y
2
3

K
E
Y
2

1

1
4

1
3

1
2

1
1

1
0

9

8

7

6

5

4

3

2

G
N
D

N
U

K
E
Y
1

T
E
M
P
_
S
E
N
S
E

G
N
D

R
C

N
U

C
S
N
_
F

G
N
D

S
C
K
_
F

S
D
A
_
F

G
N
D

4
0
K
H
Z

1
1
0
1

1
6
0
3

A
U
D
I O
1
_
L

1

2

1
0

1
5

1
1

1
2

1
3

1
4

1
6

1
7

1
8

1
9

2
0

2
1

2
2

2
3

2
4

3

4

5

6

7

8

9

G
N
D

A
U
D
I O
1
_
R

G
N
D

A
U
D
I O
2
_
L

G
N
D

A
U
D
I O
2
_
R

G
N
D

A
U
D
I O
3
_
L

G
N
D

A
U
D
I O
3
_
R

G
N
D

L
R
1
_
L

G
N
D

L
R
1
_
R

G
N
D

D
_
K
I L
L

D
A
O
U
T

G
N
D

D
A
I N
C
O
A

D
A
I N
O
P
T

G
N
D

S
I F

G
N
D

2
4

1
9

2
3

2
2

2
1

2
0

1
8

1
7

1
6

1
5

1
4

1
3

1
2

1
1

1
0

9

8

7

6

5

4

3

2

1

A
U
D
I O
1
_
L

G
N
D

A
U
D
I O
1
_
R

G
N
D

A
U
D
I O
2
_
L

G
N
D

A
U
D
I O
2
_
R

G
N
D

A
U
D
I O
3
_
L

G
N
D

A
U
D
I O
3
_
R

G
N
D

L
R
1
_
L

G
N
D

L
R
1
_
R

G
N
D

D
_
K
I L
L

D
A
O
U
T

G
N
D

D
A
I N
C
O
A
X

D
A
I N
O
P
T

G
N
D

S
I F

G
N
D

1

2

1
0

1
5

1
1

1
2

1
3

1
4

1
6

1
7

1
8

3

4

5

6

7

8

9

G
N
D

S
C
L
_
S
3
V
3

S
D
A
_
S
3
V
3

G
N
D

S
R
O

S
T
B
Y

D
D
_
O
N

F
A
N
A

F
A
N
B

R
E
G
I O
N
S
E
L
E
C
T
A

R
E
G
I O
N
S
E
L
E
C
T
B

G
N
D

8
S
C
1

A
F
C

H
D
_
O
N

8
S
C
2

S
R
1

I M
U
T
E

L
O
O
P
T
H
R
U
O
N

Y
U
V
A
C
T
I V
E
N

1
8

1
7

1
6

1
5

1
4

1
3

1
2

1
1

1
0

9

8

7

6

5

4

3

2

1

G
N
D

S
C
L
_
S
3
V
3

S
D
A
_
S
3
V
3

G
N
D

S
R
O

S
T
B
Y

D
D
_
O
N

F
A
N
A

F
A
N
B

R
E
G
I O
N
S
E
L
E
C
T
A

R
E
G
I O
N
S
E
L
E
C
T
B

G
N
D

8
S
C
1

A
F
C

H
D
_
O
N

8
S
C
2

R
1

I M
U
T
E

L
O
O
P
T
H
R
U
O
N

Y
U
V
A
C
T
I V
E

3
V
3
D

3
V
3
D

3
V
3
D

3
V
3
D

5
V
D

G
N
D

G
N
D

1

2

3

4

5

6

7

8

9

1
0

1
1

1
2

5
N
D

G
N
D

G
N
D

1
2
V
D

G
N
D

3

2

1

3
V
3
S
T
B
Y

5
V
S
T
B
Y

G
N
D

3

2

1

3
V
3
S
T
B
Y

5
V
S
T
B
Y

G
N
D

1
1
1
5

1
2
0
2

1
2
0
8

1
2
1
0

1
2
0
9

1
3
1
8

1
3
0
4

1
5
0
7

1
5
0
2

1
6
0
0

1
6
0
6

1
7
0
3

3
9

1

4

3

2

1

+
5
V
H

G
N
D

G
N
D

+
1
2
V
H

3
9

1

9

8

7

6

5

4

3

2

1

Y
F
I N
_
F
C

G
N
D

C
F
I N
_
F
C

G
N
D

C
V
B
S
F
I N
_
F
C

G
N
D

A
I N
F
L

G
N
D

A
I N
F
R

1
5
0
1

9

8

7

6

5

4

3

2

1

Y
F
I N
_
F
C

G
N
D

C
F
I N
_
F
C

G
N
D

C
V
B
S
F
I N
_
F
C

G
N
D

A
I N
F
L

G
N
D

A
I N
F
R

1
2
0
3

1

2

3

4

+
5
V
H

G
N
D

G
N
D

+
1
2
V
H

1
3
1
3

4

3

2

1

+
5
V
E

G
N
D

G
N
D

+
1
2
V
E

2
4

2
3

2
2

2
0

1
9

1
8

1
7

1
6

1
5

1
4

1
3

1
2

1
1

1
0

9

8

7

6

5

4

3

2

1

G
N
D

T
U
N
_
C
V
B
S

G
N
D

A
_
V
R

G
N
D

A
_
U
B

G
N
D

A
_
Y
G

G
N
D

Y
/ C
V
B
S
_
T
U
N
/ D
T
T

G
N
D

S
C
1
_
C
V
B
S

G
N
D

D
_
C
V
B
S

G
N
D

D
_
Y

G
N
D

D
_
C

G
N
D

D
_
V
R

G
N
D

D
_
Y
G

G
N
D

D
_
U
B

2
1

D
_
M
C
L
K

G
N
D

D
_
D
A
T
A
0

D
_
W
C
L
K

G
N
D

D
_
B
C
L
K

G
N
D

G
N
D

3

2

1

8

7

6

5

4

1

2

3

4

5

6

G
N
D

F
B
O
U
T

D
T
T
/ W
U

G
N
D

A
U
D
I O
_
M
U
X
2
_
S
E
L
/ D
T
T
_
S
E
L

V
I D
E
O
_
M
U
X
3
_
S
E
L

F
A
N
_
N

F
A
N
_
P

1

2

1
2
1
1

1
9
1
1

2
1

2
2

2
3

2
4

2
5

2
6

2
7

2
8

2
9

3
0

3
1

3
2

3
3

3
4

3
5

3
6

3
7

3
8

3
9

4
0

G
N
D

G
N
D

F
S
C
L
K
1
2
_
O
U
T

G
N
D

G
N
D

G
N
D

+
3
V
3
_
H
D
M
I
+
5
V
_
H
D
M
I
G
N
D

G
N
D

G
N
D

I T
U
_
O
U
T
_
0

G
N
D

I T
U
_
O
U
T
_
C
L
K

G
N
D

S
C
L
0

G
N
D

S
D
A
0

G
N
D

1
3

1
4

1
5

1
6

1
7

1
8

1
9

2
0

1
2

1
1

1
0

9

8

7

6

5

4

3

2

1

I T
U
_
O
U
T
_
1

I T
U
_
O
U
T
_
2

I T
U
_
O
U
T
_
3

I T
U
_
O
U
T
_
4

I T
U
_
O
U
T
_
5

I T
U
_
O
U
T
_
0
6

I T
U
_
O
U
T
_
7

S
C
K
1
2
_
O
U
T

S
D
_
O
U
T

G
N
D

G
N
D

G
N
D

G
N
D

G
N
D

G
N
D

G
N
D

S
P
D
I F
_
O
U
T

W
S
1
2
_
O
U
T

I N
T
_
H
D
M
I
H
D
M
I _
R
S
T
n

P
S
C
A
N
_
R
S
T
n

D
_
M
C
L
K

G
N
D

D
_
D
A
T
A
0

D
_
W
C
L
K

G
N
D

D
_
B
C
L
K

G
N
D

G
N
D

3

2

1

8

7

6

5

4

G
N
D

F
B
O
U
T

D
T
T
/ W
U

G
N
D

A
U
D
I O
_
M
U
X
2
_
S
E
L
/ D
T
T
_
S
E
L

V
I D
E
O
_
M
U
X
3
_
S
E
L

1

2

3

4

5

6

Set Wiring 3139-249-42051-132-a3.pdf 2008-02-20

EN 97 3139 785 32804
Waveforms of Analog Board
F115 Tuner CVBS F117 Tuner SIF F124 CVBS F126 SY
F127 SC F132 Digital Out Black F133 Yout Green F135 Pr out Red
F136 Pb out blue F138 Audio R Out F139 Audio L Out F201 AIO D_BCLK
F202 AIO D_WCLK F203 AIO D_DATA0 F204 AIO D_MCLK

EN 98 3139 785 32804
Waveforms of Digital Board
) 0 0 1 1 ( 1 0 1 F ) 0 0 1 1 ( 2 0 1 F ) 3 0 3 1 ( 3 0 3 F ) 3 0 3 1 ( 4 0 3 F B _ D _ 0 0 5 F U _ D _ 0 0 5 F
G _ _ D _ 1 0 5 F R _ D _ 2 0 5 F V _ D _ 2 0 5 F C _ D _ 3 0 5 F Y _ D _ 4 0 5 F Y _ D _ 1 0 5 F
S B V C _ D _ 5 0 5 F T U O A D _ 1 3 5 F K L C B _ D _ 7 3 5 F K L C W _ D _ 8 3 5 F 0 A T A D _ D _ 9 3 5 F K L C M _ D _ 0 4 5 F
) w e i V p o T 4 0 5 1 ( 0 5 5 F ) w e i V p o T 4 0 5 1 ( 1 5 5 F ) 5 0 6 1 ( 1 5 6 F ) 5 0 6 1 ( 2 5 6 F ) 4 0 6 1 ( 4 5 6 F ) 4 0 6 1 ( 5 5 6 F

EN 99 3139 785 32804
Waveforms of HDMI Board
F111 HDMI P_HSYNC F112 HDMI P_VSYNC

EN 100 3139 785 32804
Test Points Overview for HDMI Board
HDMI Columbus Test Point Overview 3139-243-32736-132-a1.pdf 2007-05-08

EN 101 3139 785 32804
Test Points Overview for Analog Board
716.3 Analog Test Point Overview_8_3139-243-36735-sh132-a1.pdf 2007-05-08

EN 102 3139 785 32804
Test Points Overview for Digital Board
Digital Board Test Points overview_3139-243-36835_132_a4.eps 2007-07-17

EN 103 3139 785 32804
7. Circuit Diagrams and PWB Layouts
Analog: VIO/SPDIF OUT
T
M
T
M
T
M
T
M
GND
V+
EN
F123 H2
F124 A13
F125 B13
F126 C13
F127 C13
F128 C13
F132 F13
F133 F13
F134 F13
F135 F13
F136 G13
F137 H13
F138 I13
F139 I13
F140 H7
F141 H7
F142 H7
F143 H7
F144 H7
F145 H8
F146 H8
F147 H8
F148 H8
F149 H8
F150 H8
F151 H8
F152 H9
F103 B2
F104 C2
F105 C2
F106 D2
F107 D2
F111 D4
F112 E4
F113 E4
F114 E4
F115 G2
F116 G2
F117 G2
F118 H2
R
V_
D
X
*
from COM_0
B
U_
D
F119 H2
F120 H2
F121 H2
F122 H2
5108 G3
5109 G5
5110 H5
5111 H3
5112 H4
6101 B3
6102 B3
6103 B3
6104 B3
6105 C12
6106 D13
6107 C13
6108 D13
Y
GND
7101 B6
7102 D10
7103 E9
7104 F10
7105 G5
7106 H5
F101 A2
F102 A2
3164 G11
3165 G4
3166 G11
3167 G5
3168 G6
4101 A12
4102 C11
4103 C12
4105 F11
4106 G11
4107 G11
4108 D10
5101 B6
D
N
G
*
%
1
to I2C cct H
D
N
G
Vin2
R
V_
A
3119 C6
3120 D9
3121 D10
3123 D10
3129 D10
3132 E9
3133 E10
3155 E11
3156 F10
3157 F11
3158 F12
3159 F12
3160 G11
C
SW1
(AIO_0)
G
Y_
A
Y_
D
3161 G3
3162 G5
3163 G6
2142 H5
2143 I2
2149 I3
2150 I4
3101 A12
3102 A4
3103 B4
3104 B3
3105 B4
3106 C11
3107 C9
3108 C3
3109 D12
1%
1%
D
N
G
D
N
G
D
N
G
D
N
G
Rear CVBS in
3117 C5
3118 C5
2122 D13
2123 D9
2124 D11
2126 E5
2127 E5
2128 E5
2129 F11
2130 F12
2131 F12
2132 G12
2136 G3
2137 G3
2138 H13
GND
*
1%
1%
Vin3
D
N
G
2139 H13
2140 H4
2141 H4
2102 B2
2103 B2
2104 B5
2105 B3
2106 B7
2107 B7
2108 C5
2109 C9
2110 C4
2118 C5
2119 C11
2120 C2
2121 D13
L
C
VIO_DTT
1%
* Not used (Provision only)
D
N
G
LATAM : USE TCSN9082PA26F(H)
SW1
L
To/From LeCO+ Step
1102-C B2
1103 G1
1104 G1
1105-1 B14
1105-2 B13
1105-3 H14
1105-4 F14
1110 D2
1115 I7
2101 B13
*
from COM_0
C_
D
*
7113_NJM2244
%
1
L
to Tuner
13 14
A
B
C
D
E
F
G
H
*
*
*
*
Pr out - Red
to IOA (AIO_0)
*
V05
T
T
D/
N
U
T_
S
B
V
C/
Y
from PS
1 2 3 4 5 6 7 8 9 10 11 12
VOUT
B
U_
A
RE_SY_IN
For DTTM
%1
VIO/SPDIF OUT
A_C
D
N
G
to Tuner
SW2
5 6 7 8 9 10 11 12 13 14
D
N
G
D
N
G
Bead
to I2C cct
Y
*
Audio L out
D
N
G
S
B
V
C_1
C
S
SW2
RE_CVBS_IN
1%
DTT_CVBS
Vin1
%
1
*
G
Y_
D
1 2 3 4
*
Y out - Green
*
M
T
T
D

m
o
r
F
/
o
T
Pb out - Blue
*
Tuner in
Audio R out
*
to IOA (AIO_0)
I
A
B
C
D
E
F
G
H
I
1101 E4
1102-A A2
1102-B C2
CVBSSIN_DTT
from COM_0
Rear YUV in
from COM_1
*
H
Rear YC in
from IOA
GND
CVBS out
Digital out - Black
*
Y/C out
S
B
V
C_
D
S
B
V
C_
N
U
T
OI
V
GND
8
2
1
2
F116
9
1
1
3
0
M
1
p
0
0
1
1
0
1
6
2
1
C-
4
8
3
X
Z
B
K
7
2
2
3
1
3
7
0
1
6
2
1
C-
4
8
3
X
Z
B
F133
F124
7
2
1
2
33V
5V
5V
5V
p
0
0
1
600R
5111
600R
5110
10
SIF_OUT
VIDEO_OUT
13
VT
11
BB+
1
14 15
16 17
NC
3
NC
12
SCL
6
SDA
7
AFT_OUT
8
5
AS
AUDIO_OUT
9
B+
2
F137
TCSM0601PD25F(H)
R
E
N
U
T
1104
F102
GND
75R
3166
75R
3164
9
4
1
2
n
0
1
F122
75R
3157
6
VIN1
1
VIN2
3
VIN3
5
VOUT
7
GND
7101
8
SW1
2
SW2
4
F127
VIDEO SW
3-INPUT
NJM2244M
10
SIF_OUT
VIDEO_OUT
13
VT
11
1u0 2110
14 15
16 17
NC
3
NC
4
12
NC
SCL
6
SDA
7
1103 TCSN9082PA26F(H)
R
E
N
U
T
AFT_OUT
8
AS
5
AUDIO_OUT
9
B+
2
F113
1K0
3156
p
0
0
1
1
0
1
2
9
0
1
2
n
0
0
1
BSN20
7105
4105
F125
R
5
7
5
0
1
3
0
K
1
1
2
1
3
7102
4
0
1
3
R
5
7
5VSTBY
BC857BW
F135
F139
GND
n
0
1
1
4
1
2
p
0
0
1
8
3
1
2
GND
2
0
1
2
p
0
0
1
1105-3
WHITE-T_RED-B
MSP-806V-10 NI
9
10
8
3155
R
0
7
4
F103
3
0
1
6
2118
2
1
C-
4
8
3
X
Z
B
R
5
7
8
0
1
3
1u0
F106
F105
5
0
1
6
V
0
5
2
1
C-
4
8
3
X
Z
B
7
u
4
6
3
1
2
6
2
1
2
p
0
0
1
6
0
1
2
V
3.
6
u
7
4
n
0
0
1
7
0
1
2
F104
GND
2140
22n
3V3STBY
33V
5109
600R
1
5
1
F
n
0
0
1
2
4
1
F
3
4
1
2
2108
1u0
GND
GND
2
3
1
2
p
0
0
1
GND
F121
33V
R
0
0
1
3
3
1
3
3101
75R
MSP-806V-10 NI
YELLOW
1105-2 6
7
8
1
1
3
0
M
1
2K2
3165
F114
F134
1
2
1
2
p
0
0
1
6
4
1
F
4103
5
0
1
2
0
u
1
1
3
1
2
p
0
9
3
3
4
1
F
100n
2119
0
5
1
2
V
0
1
u
0
0
1
5VSTBY
5V
3V3STBY
3V3STBY
7103
BC847BW
3 4 5 6 7 8 9
4102
6
1
7
1
8
1
9
1
2 0
2
1
2
2
2
3
2
4
2
7
C
2-
S
4
2
W
L
H
5
1
1
1
1 0
1
1
1
2
1
3
1
4
1
5
1
n
0
1
4
0
1
2
F112
F126
GND
150R
3102
5VSTBY
GND
R
0
5
1
9
5
1
3
4106
3123
100R
K
0
1
2
6
1
3
F118
0
5
1
F
4
5
8
4
1
F
MSP-806V-10 NI
SDIN
1105-1
1
2
3
75R
3106
u
2
2
2
4
1
2
V
5
2
F123
3107
150R
8
0
1
4
F117
100R
3129
120R
3158
11
14
12
15
13
16
F101
MSP-806V-10 NI
1105-4
GREEN-BLUE-L_BLACK-RED-R
2
3
1
5
4
74LVC1G125GW
7104
5V
p
0
0
1
0
2
1
2
2
5
1
F
GND
100n
2123
2124
100n
GND
GND
600R
5101
7
4
1
F
4101
22u
5112
LHL08
1
2
3
4
5
6
1
4
1
F
1101
LPR6520-P910F
p
0
0
1
2
2
1
2
47K
3103
2130
8n2
F119
1
6
1
3
R
5
7
8
6
1
3
K
7
4
GND
F120
F132
BSN20
7106
7
6
1
3
K
0
1
GND
4
0
1
6
2
1
C-
4
8
3
X
Z
B
3V3STBY
u
0
1
8
0
1
5
3
8
1
0
8
9
1
3
7
3
1
2
n
0
1
5VSTBY
5V
4107
2
3
4
5
6
2
1
C-
4
8
3
X
Z
B
2
0
1
6
1110
HLW6S-2C7
1
2
1
C-
4
8
3
X
Z
B
8
0
1
6
5
4
1
F
GND
K
7
2
10n
2129
0
2
1
3
9
3
1
2
p
0
0
1
6
0
1
6
2
1
C-
4
8
3
X
Z
B
F136
4
4
1
F
F115
F128
F138
0
4
1
F
75R
3160
GND
3109
75R
p
0
0
1
3
0
1
2
3
4
5
9
4
1
F
MSP-801V1-02-01-B NI FE LF
1102-A
1
2
1102-B 7
6
1102-C
GND
8
7
1
1
3
0
M
1
K
7
4
3
6
1
3
F111
F107
V
5
5V
SIF
GND
5V
A_UB
A_YG
A_VR
DAOUT
VO_SY
AFT
RE_SC_IN
VO_Pr
VO_Pb
VO_Y
ARout
ALout
RE_CVBS_IN
RE_SY_IN
V0_CVBS
VO_SC
8SC2
WSRO YUV_ACTIVEN
DTT_SEL
SCL_S3V3
SDA_S3V3
3139-243-36735-130-01-a2.pdf 2007-03-14

EN 104 3139 785 32804
Analog: AIO/DAC/SPDIF IN/OUT
NC
1
GND
NC
IN OUT
GND GND
GND
NC
SDIN
SCLK
GND
VQ
FILT+
AOUTL
AOUTR
DEM
LRCK
MCLK
VA
GND
(nc)
AIO_1
from Tuner SIF
D_MCLK
from COM_0
AUDIO1_R
GND
GND
from PS
F252 C1
F253 D1
F254 I2
F255 H3
F256 I3
F257 I4
GND
(NC)
DAOUT
N
I

T
P
O
COM_0
(NC)
to DAC
AIO/DAC/SPDIF IN/OUT
F235 H13
F236 H13
F237 H13
F238 H13
F239 H13
F240 H13
F241 H13
F242 H13
*
*
*
DD_ON
GND
(NC)
D_KILL
GND
LR1_R
F243 H13
F244 H13
F245 H13
F248 D2
F249 D2
F251 C1
F220 G2
F221 G2
F222 G2
F223 H2
F224 H2
F225 H6
F226 H6
F227 F13
to DAC
FAN_A
DTT/WU
GND
*
*
*
AUDIO3_L
REGION_SEL_B
F228 F13
F229 F13
F230 G13
F231 G13
F232 G13
F233 H13
F234 H13
F208 E2
F209 E2
F210 F2
F211 F2
F212 F2
F213 F2
F214 F2
F215 F2
from Tuner
GND
AIO_0
to ana_tun
STBY
p
e
t
S

+
o
c
e
L

m
o
r
F
/
o
T
LOOP_THRU_ON
GND
GND
GND
(NC)
COM_1
AUDIO1_L
F216 F2
F217 F2
F218 G2
F219 G2
7222-2 I7
7228 H4
7230 A4
F201 B2
F202 B2
F203 B2
F204 C2
F205 D2
AUDIO_MUX2_SEL / DTT_SEL
GND
d
r
a
o
B l
ati
gi
D
ot/
m
o
rf
to PS
SDA_S3V3
REGION_SEL_A
(nc)
DAINCOAX
to ana_tun
YUV_ACTIVEN
F206 D2
F207 E2
7203-2 E9
7204 C11
7205 C12
7207 E11
7209 E12
7211 F7
7212-1 F6
7212-2 F5
D_WCLK
AUDIO2_L
to IOV
from ana_tun
to PS
p
e
t
S

+
o
c
e
L

m
o
r
F
/
o
T
7217 G1
7219 H6
7222-1 I8
4210 F7
5201 C12
5202 C5
5206 E12
6201 C12
6202 D12
6203 E12
6204 E12
GND
6206 E6
6210 A3
6215 E7
7202 B6
7203-1 C9
3280 I3
3281 I4
3282 I2
3283 I3
3284 I4
3290 E6
3291 E6
3292 E7
Rear Audio In
SPDIF in
*
AUDIO3_R
8SC2/WSRI
*
3293 E7
3294 E7
4201 C2
4202 C2
4205 A3
4206 C5
4207 C5
3263 G5
3264 G12
3265 H12
3268 G2
3269 H2
3270 H7
3271 H11
3272 H11
GND
*
GND
to DAC
3273 H3
3275 H7
3276 H4
3277 I7
3278 I8
3279 H3
3238 D9
3239 D9
3240 E8
3241 E8
3242 E8
3243 E10
3244 E11
3245 E7
FAN_B
FBOUT
3246 D3
3247 E10
3248 D3
3249 E10
3250 E11
3251 E3
3252 E3
3253 E8
3254 E9
3255 E9
3256 F6
3257 E2
3258 E2
3259 F2
3260 F2
3261 F5
3262 F7
2271 E9
2280 B3
2281 B3
2282 B4
2283 D4
2284 D4
2285 F3
2286 F3
*
VIDEO_MUX3_SEL
GND
3204 C8
3212 C8
3213 C8
3214 C10
3216 C11
3218 C7
3221 C10
3222 B2
3223 C10
3224 C11
3230 B2
3234 B2
3236 C2
3237 D8
2236 C5
2240 C5
2241 C3
2242 C3
2243 C3
2244 C3
2245 D9
2248 E7
GND
(NC)
D_DATA0
SCL_S3V3
GND
GND
GND
2249 E8
2250 E9
2252 E10
2253 E13
2255 E2
2256 E2
2257 E2
2258 E3
2259 F6
2260 H6
2261 H2
2262 H3
2263 H3
2264 I2
2270 D9
2219 C9
2221 C7
2222 C8
2224 C9
2225 C9
2233 C10
2234 C13
2235 C9
1
N
A
F
ot
FAN_P
to DAC
*
D_BCLK
to PS (1500)
*
*
*
*
Bead
Bead
Audio-R out
Audio-L out
from AIO_1
from AIO_1
from AIO_1
from AIO_1
DAC
7 8 9 10 11 12 13 14
HD_ON
AUD_MUTING
to PS (1500)
8SC1/AFC
1203 I1
1205 D1
1208 E1
1209 F13
1210 G13
1211 H5
1213 C1
2201 B9
2202 B7
2207 B7
2211 C9
2212 C7
C
D
E
F
G
H
I
1202 B1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4 5 6
5VSTBY
AUDIO2_R
DAINOPT
LR1_L
IMUTE
*
WSRO
FAN_N
A
B
C
D
E
F
G
H
I
A
B
22R
3236
100n
2264
4
4
2
2
p
2
2
22R
3234
8
6
2
3
R
7
4
F205
F224
GND
BC327-25
7219
9
K
3
0
7
2
3
F206
F210
9
4
2
3
3244
39R
0
K
1
2
5
2
2
p
0
3
3
p
0
0
1
6
5
2
2
p
2
2
8
5
2
2
p
0
0
1
F227
2
4
2
2
F204
5V
12VSTBY
5VD
F254
F212
V
5
2
u
0
1
0
6
2
2
F253
3252 1%
100R
PDTA124EU
7211
3251
F201
1% 100R
2
K
2
8
7
2
3
1
7
2
3
K
0
1
F243
7207
BC817-25W
7204
0
K
1
0
5
2
3
BC817-25W
F257
F230
4210
0
K
1
4
9
2
3
0
K
1
3
9
2
3
0
K
1
2
9
2
3
0
K
1
1
9
2
3
0
K
1
0
9
2
3
1
V
5
C-
4
8
3
X
Z
B
5
1
2
6
3216
39R
3
2
2
3
0
K
1
3
3
2
2
p
0
3
3
3214
100R
p
0
7
4
3
5
2
2
n
0
1
3
6
2
2
5V
3260
12K
1
6
2
2
n
0
0
1
F216
F245
F241
K
0
0
1
7
4
2
3
600R
5206
F256
22R
3222
1
2
6
4
5
1205
LPR6520-E610F
3
7209
BC817-25W
BC817-25W
7205
5NSTBY
F209
7217
JFJ2000-010111
2
GND
3
OUT
1
VS
5NSTBY
F223
5VD
3248 1%
100R
3
7
2
3
8
K
1
F225
GND
4K7
1
2
5V
3264
F217
1211
B2B-EH-A
F231
K
0
0
1
1
2
2
3
600R
5201
2
7
2
3
K
0
1
3258
12K
F242
5V
12VSTBY
7
7
2
3
3
K
3
F208
3246
100R 1%
3243
100R
4
2
2
3
0
K
1
100R
3281
p
0
0
1
5
5
2
2
4
3
2
2
p
0
7
4
K
2
2
6
5
2
3
F229
5
6
7
8
9
12VSTBY
18
19
2
20
21
22
23
24
3
4
1
10
11
12
13
14
15
16
17
1208
HLW24S-2C7
10K
3284
F239
5V
F236
12VSTBY
3275
560R
1
2
3
4
5
F202
1213
05FMN-BTRK-A
p
0
0
1
7
5
2
2
GND
12K
3257
2
3
4
5
6
7
8
HLW8S-2C7
1202
1
5
4
2
3
K
7
2
K
7
2
8
1
2
3
50V
2248
4u7
4u7
12K
2221
50V
GND GND
3259
F237
470R
3276
180R
3269
5VSTBY
5V
F219
F248
3230
22R
7222-2
PUMH1
5
3
4
7222-1
PUMH1
2
6
1
n
2
2
9
5
2
2
F249
F228
F222
2
6
2
2
V
0
1
0
u
1
600R
5202
3255
12K
2225 100n
16V 47u
2235
2219
5ND
5VD
100n
2211
47u 16V
2
2
2
2
7
n
2
4
2
2
2
p
0
2
8
2201
820p
3204
680R
1
0
2
6
5VD
2
1
C-
4
8
3
X
Z
B
9
4
2
2
7
n
2
5ND
820p
0
5
2
2
p
0
2
8
3253
2245
390R
3242
6K8
F240
F218
F220
F211
F244
12VSTBY
100R
2271
56p
3265
2270
4
0
2
6
2
1
C-
4
8
3
X
Z
B
56p
2
1
C-
4
8
3
X
Z
B
3
0
2
6
2
1
C-
4
8
3
X
Z
B
2
0
2
6
F207
12VD
3237
390R
3213
6K8
3212
6K8
3238
15K
3239
12K
5
6
7
8
4
3
2
1
8
4
LM833D
7203-2
7
0
2
2
LM833D
7203-1
V
5
2
u
0
1
u
0
0
1
0
8
2
2
n
0
1
1
8
2
2
4205
V
0
1
2212
12VD
25V 10u
2
8
2
2
0
u
1
6210
BAS316
3
6
7
8
4 5
1
7230
MC78L05ACD-R2
2
F238
K
0
0
1
2
6
2
3
3
8
2
3
K
0
0
1
2
8
2
3
2
3 1
5
4
R
5
7
74HC1GU04GW
7228
100R
3280
680R
3240
F213
3241
6K8
15K
3254
4206
5
3
4
6206
BAT54A
6
1
7212-2
PUMH1
7212-1
PUMH1
2
6
F226
HLW6S-2C7
1209
1
2
3
4
5
F203
18
2
3
4
5
6
7
8
9
1
10
11
12
13
14
15
16
17
1210
HLW18S-2C7
n
0
0
1
12VD
7
K
4
3
6
2
3
2
0
2
2
1
9
5
7
10
2 6
8
3
4
CS4344
7202
p
2
2
1
4
2
2
F221
3
4
2
2
p
2
2
1203 2
1
MTJ-032-13
9
7
2
3
K
0
0
1
F235
F233
F234
5VSTBY
F215
F251
F252
4201
4202
4207
2284
2n2
2n2
2283
6
8
2
2
2
n
2
2
n
2
5
8
2
2
V
0
1
u
0
0
1
6
3
2
2
0
4
2
2
n
0
0
1
F255
1
6
2
3
7
K
4
F232
5VD
12VSTBY
F214
BKILL
SDIN
SCLK
MCLK
LRCK
ARout
ALout
BKILL
BKILL
IMUTEn
IPFAIL
DAOUT
DAINOPT
DAINOPT
DAINOPT
FAN_B FAN_A
DAOUT
WSRO
SCL_S3V3
SDA_S3V3
REGION_SEL_A_P90_DECON
REGION_SEL_B_P91_DECON
AFT
FAN_A
DD_ON
FBOUTSC1
STBY
DTT_SEL
DTT_ON
LR1_R
LR1_L
SIF
MCLK
SDIN
LRCK
SCLK
YUV_ACTIVEN
LOOP_THRU_ON
IMUTEn
8SC2
HD_ON
FAN_B
3139-243-36735-130-02-a2.pdf 2007-03-14

EN 105 3139 785 32804
Analog: Power Supply (PS)
C
N
C
N A
F
E
R
K
*
*
GND
12VF
5VF
PS_DIG_STBY
#
*
to IOA
GND
12VD
5VSTBY
PS_HDD
PS_BE
F338 A8
F339 B7
GND
5VD SW
to PS_FP
3V3STBY
F323 F13
F324 F13
F325 F13
F326 G13
F327 G13
F328 H13
F329 H13
F330 H13
F331 H13
F332 I13
F333 H2
F334 D7
F335 F8
5ND
12VD to 33V
5VSTBY
#
from COM_0
12VSTBY
F311 D2
F312 D2
F313 E2
F314 F2
F315 F2
F316 F2
F317 B13
F318 B13
F319 B13
F320 D13
F321 D13
F322 D13
GND
*
GND
12VE
For non DTT models
12VD SW
PS_DIG
3V3D
GND
GND
HARD DRIVE
F306 C2
F307 C2
F308 D2
F309 D2
F310 D2
12VSTBY
3V3D
3V3STBY
(NC)
7350 E11
7353 C7
7354 F12
7355 H8
7356 E11
7357 G11
7359 G3
7360 E7
7361 H2
7362 F7
7363 I2
F301 B3
F302 B3
F303 C4
F304 C2
F305 C2
PS_STBY
*
For non DTT models
from COM_0
U
S
P
m
orf
6312 D12
7340 B12
7341 A11
7342 A8
7343 C11
7344-1 B6
7344-2 B7
7346 D12
7347 F8
7348 C11
7349-1 G8
7349-2 G7
U
S
P
m
orf
#
PS_FP
4320 C3
4320 D3
4321 C3
4321 D3
4322 B13
4322 C4
4323 B13
4323 C4
4324 D12
4325 D12
5310 C4
5311 D3
5312 D3
5313 F4
5314 H2
6304 I7
6305 G5
6310 C3
6311 B13
#
0
_
GI
D
S
P
to FV,PROG,DAC,COM
For non DTT models
5NSTBY
For "specific models"
5ND SW
3385 G7
3387 G8
3389 C8
3391 C8
3392 I8
3393 I7
3395 I8
3396 A7
4309 B3
4310 B3
4311 B3
4312 B3
4313 H7
4314 G2
*
#
DTTM
to
OPTICAL DRIVE
to
3332 E8
3333 F8
3334 F7
3341 H2
3342 H2
3343 I1
3344 H3
3345 H3
3346 I3
3347 I3
3348 H4
3349 G3
3350 H6
3375 A8
3377 A7
3378 B8
3382 G8
3V3D
5V_STBY
3V3D SW
to IOV,COM
d
b I
GI
D
ot
Not used (provision only)
from COM_0
from COM_0
from COM_0
GND
5VSTBY
GND
3314 D11
3315 D12
3316 D13
3317 C12
3323 F10
3324 F11
3325 F12
3326 F13
3327 E12
3331 E8
NC
NC
NC
NC
GND
GND
5V SW
to IOA,PROG,DAC
PS_ANA
2350 H5
2351 H5
2352 E7
2353 H3
2354 E8
2355 F7
2360 D11
2361 F10
2370 B10
2371 B12
2372 D10
2373 D12
2374 F10
2375 F12
3301 B13
3302 A12
3303 B11
3304 B11
3308 B12
3313 D11
For non DTT models
GND
5VD
PS_DTT_5VSTBY
M
T
T
D
ot
to
PS_DTTM
*
1318 C5
1319 E14
1320 E14
1321 D1
1322 G13
1323 C2
1325 H13
1326 H14
2337 B13
2338 B11
2339 A13
2340 B7
2341 D13
2342 D2
2343 G8
2345 C13
2346 F13
2347 I8
2349 E13
* *
*
*
*
4 5 6 7 8
GND
9 10 11 12 13 14
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
*
3V3D
GND
to IOV,IOA,DAC_ADC,CU
GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3
*
*
*
*
*
VGNSTBY
IPFAIL
5VE
GND
GND
12VH
5VH
GND
G
H
I
1301 A14
1304 E1
1313 C14
1314 B3
1315 B3
1316 C3
1317 C1
d
b I
GI
D
ot
5VSTBYPS
K
0
1
1
0
3
3
K
0
1
8
0
3
3
10u
5311
F303
5
R
1
4
4
3
3
5310
22u
4323
4322
4320
4321
0
u
1
6
4
3
2
F324
1314
4A T
F316
F313
2
3
1318
B3B-PH-K
1
7363
BC847BW
F323
5VSTBY
5V
5VSTBY
5VSTBY
5V
K
0
1
2
9
3
3
F319
V
0
5 3
4
3
2
n
0
0
1
33V
5NSTBY
5VSTBY
12VD
3V3STBY
SI2306DS
5
1
3
3
7354
K
0
1
3V3SW
6
9
3
3
7
K
4
7344-1
PUMH1
5V
31
2
4
1323
T 4A
2
6
3
7
V
B
D
C
A
1
3
4
L
T
5
16V
2345
100u
6
1
3
3
K
0
1
8
3
3
2
n
0
0
1
2
5
3
2
4311
4
5
6
7
u
0
6
5
B7B-PH-K-K
1325
1
2
3
5
0
3
6
6
1
3
S
A
B
12VD
5ND
3V3SW
7347
SI2306DS
9
8
3
3
F307
K
0
1
2
3
3
3
R
0
0
1
1
2
3
4
5
1
2
3
4
1319
B5B-EH-A
1320
B4B-EH-A
1
6
3
2
n
0
0
1
K
0
1
6
2
3
3
5
2
3
3
K
0
1
4309
6304
BZX384-C6V8
F334
12VD
5NSTBY
3343
F310
10K
BC857BW
7361
T 1A
1316
F302
F312 10u
5VSTBYPS 5VH
5312
SI2306DS
7346
12VSTBYPS 12VH
PDTC124EU
7343
7350
3302
PDTC124EU
10K
K
7
4
3
0
3
3
4
0
3
3
K
7
4
7341
SI2307BDS
F308
F318
12VD
3349
100R
5NSTBY
F329
DCOL 8
GND 4
IS 7
SWC 1
SWE 2
TIMC 3
VCC
6
7359
MC34063AD
REGULATOR
REFERENCE
OSC
IPK
Q
R
S
CIN_NEG 5
3
9
3
3
12VSTBYPS
K
7
4
1301
B4B-EH-A
1
2
3
4
12VSTBY
1
3
3
3
9
K
3
3
3
3
3
K
0
1
12VSTBY
1m0
5313
5VSTBY
F327
16V 100u
2339
F330
7
3
3
2
V
0
1
u
0
0
1
10K
3382
F304
5
4
3
3
5
R
1
1
2
3
4
5
B5P-VH
1317
F335
F301
4310
3V3D
n
0
1
4
5
3
2
0
n
1
PUMH1
7344-2
1
4
3
2
V
0
1
u
0
0
1
0
4
3
2
5NSTBY
STS9NF30L
F315
7360
3
K
3
2
4
3
3
1
2
3
4
5
6
1321
B6B-PH-K
V
0
1
u
0
2
2
2
4
3
2
7
8
3
3
K
7
4
2
6
1
5VSTBY
7349-1
PUMH1
F331
F309
4313
T 4A
1315
F311
F339
F306
5314
33u
3348
47K
5V
7355
5
9
3
3
0
K
1
SI2306DS
4312
p
0
9
3
0
5
3
2
8
7
3
3
3
K
3
7
K
4
7
7
3
3
16V 100u
2349
1
4
3
3
K
2
2
12VD
12VSTBYPS
K
0
1
1
9
3
3
K
0
1
V
6
1
4
3
3
3
3
5
3
2u
0
0
1
4320
4321
4325
4324
4323
4322
n
0
0
1
4
7
3
2
100n
2373
2
7
3
2
n
0
0
1
F325
7342
7357
SI2307BDS
3327
PDTC124EU
10K
K
7
4
3
2
3
3
4
2
3
3
K
7
4
7356
SI2307BDS
1
2
3
4
B4B-EH-A
1313
n
0
0
1
0
6
3
2
5VSTBY
F322
F321
F320
5VSTBYPS 5VE
F317
7340
SI2306DS
12VE
F305
12VSTBYPS
PMEG1020EA
6312
6311
PMEG1020EA
F326
6310
PMEG1020EA
3
4
5
6
7
1322
HLW7S-2C7
1
2
7
8
9
1304
1
10
11
12
2
3
4
5
6
B12P-PH-K
3V3STBY
F338
K
0
1
5
7
3
3
F328
2375
100n
12VSTBY
VGNSTBY
3317
10K 4
1
3
3
K
7
4
K
7
4
3
1
3
3
7348
6
4
3
3
9
K
3
SI2307BDS
5ND
12VSTBY
n
0
0
1
7
4
3
2
B5B-PH-K
1326
1
2
3
4
5
3V3D
5
5
3
2
p
0
0
1
2371
100n
n
0
0
1
0
7
3
2
F332
12VSTBY
5VSTBY
33V
33V
4314
7
4
3
3
F314
9
K
3
1
5
3
2
V
0
5
u
0
0
1
5VD
12VD
3V3STBY
5VD
VGNSTBY
7353
SI2306DS
4K7
3385
5
3
4
F333
PUMH1
7349-2
0
5
3
3
K
0
1
M
T
T
D
_
V
5
5V_DTTM
5V_DTTM
12VD
3V3STBY
DTT_ON
5V_DTTM
DD_ON
HD_ON
DIROUT
STBY
DTT_ON
DTT_ON
IPFAIL
3139-243-36735-130-03-a2.pdf 2007-03-14

EN 106 3139 785 32804
Layout: Analog Top View
716.3 Analog Top View_7_3139-243-36735-sh132-a1.pdf 2007-05-09

EN 107 3139 785 32804
Layout: Analog Bottom View
716.3 Analog Bottom View_8_3139-243-36735-sh132-a1.pdf 2007-05-09

EN 108 3139 785 32804
Front: Display Part (DISP)
T-
LED
K
KS <1:16>
SG
GR <12:5>
SG
16
15
13
12
11
10
9
8
7
6
5
4
3
2
VDD
1
1
2
3
4
VSS
E
E
V
24
23
22
21
20
19
18
17
OSC
CLK
DIN
GR
DOUT
STB
1
2
1
2
3
4
14
GND
I134 F2
I139 F2
SCN_F
POWER
F120 H2
F121 H2
F122 H2
F126 J3
F130 J13
F131 J13
F132 K13
F133 K13
F134 C13
F135 C10
F140 F9
F141 F9
F142 F9
F143 F9
F144 E9
I100 F6
I101 E6
I121 K9
I122 K8
I127 K7
I128 K6
I129 K6
I133 K5
* OPTIONS
7105 E6
7107 F2
7113 F6
7130 C7
7131 C6
7132 C7
7134 D5
F100 D2
F101 D2
F102 D2
F114 G2
F115 G2
F116 H2
F117 H2
F118 G6
F119 H2
6102 F5
6103 C8
6107 F11
6108 F11
6109 F11
6110 F11
6111 F11
STBY_FP
6112 F12
6113 F12
6114 F12
6115 F12
6116 G12
6117 G12
6118 G13
7100 B11
7101 G6
7102 H6
7103 D10
3173 C9
3174 C9
3175 C9
5100 D5
5101 D10
6100 C5
6101 E5
SCL_F
SDA_F
3123 D5
3125 D6
3127 D9
3128 D7
3129 E9
3130 J6
3134 I2
VFD Sketch code is use for MG, for partlist 12NC is 272217100321
VGNSTBY
3137 E6
3142 F6
3147 F13
3148 F13
3149 F13
3150 F14
3151 F14
3152 F14
3169 J3
3170 B13
3171 C13
3172 C13
3106 J9
3107 J7
3108 J6
3110 J5
3112 F2
3113 B7
3114 C6
T
NI
R
P
-
Y
B
T
S
ot
GND
V
E
R
P
+12VSTBY
3115 C8
3116 C7
3117 C6
3118 C8
3119 C8
3121 F2
3122 C5
2152 D10
2153 D10
2154 D8
2156 E8
2157 E8
2159 G10
2160 D10
RECORD
HDD
+5VSTBY
P
O
T
S
E
S
O
L
C
/
N
E
P
O
Y
A
L
P
COMM_FP
40KHZ
3101 G5
3102 H6
3103 J7
3104 J8
D
E
F
G
H
I
J
T
X
E
NC
E
R
2145 C7
2146 C8
2147 C5
2148 C8
2149 C5
2150 D5
2151 D6
5 6 7 8 9 10 11
SEL_KEY2_3
GND
GND
RC
GND
KEY1
KEY2_3
GND
12 13 14 15
A
B
C
10 11 12 13 14 15
1
d
r
a
o
B l
ati
gi
D
ot/
m
o
rf
GND
STDBY_LED
BLUE LED
RED LED
IEEE1394
PS_FP
D
R
A
O
B
A
N
A
m
o
rf
2 3 4
1178 J14
2100 J9
2103 J7
2105 G5
2107 D3
2116 F2
2144 C7
to DIGITAL BOARD
1 2 3 4 5 6 7 8 9
not used
TEMP_SENSE
K
A
B
C
D
E
F
G
H
I
J
K
1100 D2
1101 G2
1102 J3
1165 K9
1166 K5
1167 K7
1168 K5
1169 K8
1170 K6
1177 J12
F119
V
5
2
u
0
1
0
6
1
2
5101
10u
R
5
0
L
1
1
Q
V
E
0
7
1
1
F143
F140
K
0
1
3
5
1
6
2
2
3
2
4
3
1
3
F116
100n
2159
F141
10R
3170
3175 10R
8
2
1I
6103
BZX384-C6V8
7
0
1
2
V
0
5
6
4
1
2
n
7
4
7
u
4
0
1
1
6
F101
6
1
3
S
A
B
10R 3174
10R
3173 9
1
1
3
R
0
7
4
1n0
3
3
1I
2151
12V
8
0
1
3
K
2
8
1
5
1
3
K
7
4
6100
BZX384-C6V8
K
0
1
4
0
1
3
4
4
K
0
1
0
3
1
3
18
19
20
21
22
9
3
1
3
4
0
3
2
1
33
14
34
35
36
37
38
15
16
17
5
23
24
25
26
27
28
29
31
32
6
42
41
40
39
10
11
1
2
3
4
VFD
PT6315
7103
8
7
5
6
1
1
R
5
0
L
1
1
Q
V
E
R
5
0
L
1
1
Q
V
E
+5VSTBY
6
6
1
1
3116
470R
F133
F131
F132
F130
1177
1
2
3
4
5 6
CSS5004-7A01E
n
0
0
1
9
4
1
2
2150
220n
1
2
1
3
R
0
2
2
u
2
2
+5VSTBY
F144
6
1
1
2
1K0
3112
9
2
1I
0
K
1
2
2
1
3
K
7
4
2
0
1
3
7102
PDTC124EU
R
0
2
2
0
1
1
3
7
5
1
2
1
2
1I
6
5
1
2
p
0
0
1
p
0
0
1
6
0
1
3
K
7
4
F122
1
2
9
3
1I
1102
WH02D-1
8
6
1
1
R
5
0
L
1
1
Q
V
E
4K7
3169
6
1
3
S
A
B 7
1
1
68
1
1
6
6
1
3
S
A
B
PDTC124EU
7113
3137
390R
F126
6
1
3
S
A
B
12V
7
0
1
6
R
5
0
L
1
1
Q
V
E
9
6
1
1
VGNSTBY
n
0
0
1
5
0
1
2
22u
2148
22u
50V
82K
50V
2145
3127
470R
3142
n
0
1
3
0
1
2
3129
10K
n
0
0
1
3
5
1
2
I101
1
2
3
4
5
6
B6B-PH-K
1178
K
2
8
9
4
1
3
K
2
8
8
4
1
3
Y
B
T
S
V
5
+
K
2
8
0
5
1
3
7134
BC847BW
6K8
+12VSTBY
+5VSTBY
3123
3118
1
0
1
3
470R
1
2
K
7
4
7101
SI2307BDS
3
F118
R
0
2
2
3
0
1
3
K
2
8
7
4
1
3
K
0
1
5
1
1
3
5
2
1
3
0
K
1
GND
2
OUT
1
VS
3
TSOP4836ZC1
7107
4
4
1
2
n
7
4
F115
F142
K
2
8
2
5
1
3
6
1
3
S
A
B
8
0
1
6
9
0
1
6
6
1
3
S
A
B
I100
5
1
7
P
4
1
3
1
8
P
9
P
2
1
I134
4
1
P
6
5
1
P
6
1
P
5
7
1
P
4
2
P
9
1
3
P
8
1
4
P
7
1
5
P
6
1
6
P
2
3
2
2
F
C
N
1
2
1
P
0
2
0
1
P
1
1
0
1
1
1
P
9
2
1
P
8
3
1
P
7
G
4
6
2
5
2
G
5
G
6
4
2
G
7
3
2
G
8
2
2
1
1
F
12
2
1
F
1
2
F
1
3
HUV-08SS65T
7100
G
1
9
2
8
2
G
2
G
3
7
2
6102
LTL-816TDK3
2
1
1
6
6
1
3
S
A
B
F135
F134
2147
220n
K
0
1
8
2
1
3
10R
3171
3172
n
0
0
1
10R
2
2
1I
2
5
1
2
7
2
1I
BC807-25
7132
3113
330R 4
1
1
3
F100
R
0
3
3
1
2
3
4
5
1100
B5B-PH-K
7105
+12VSTBY
PDTC124EU
+5VSTBY
0
0
1
2
n
0
1
R
5
0
L
1
1
Q
V
E
7
6
1
1
3107
2K2
12V
LTL816KETNN
6101
33R
3117
6
1
3
S
A
B
1
1
1
6
5100
u
0
0
1
p
0
0
1
4
5
1
2
6
1
3
S
A
B
3
1
1
6
4
1
1
6
6
1
3
S
A
B
BC847BW
7131
7130
BC817-25
7
8
9
10
11
12
13
14
2
3
4
5
6
HLW14S-2C7
1101
1
F102
F121
F117
6
1
3
S
A
B
F114
6
1
1
6
6
1
3
S
A
B
5
1
1
6
SDA_F
FP_CONTROL
F120
VGNSTBY
VFD{P(1:17),G(1:8)}
SDA_F
SCL_F
SCN_F
FP_CONTROL
VGNSTBY
VGNSTBY
2
F
F2
SCL_F
+5VSTBY
SCN_F
Front 717.4 Circuit 3139-243-36954-130-01-a2.pdf 2007-03-14

EN 109 3139 785 32804
Front: Front Connector Part (FC)
GND
4201 C2
4202 C2
4203 C2
5201 B2
5202 B2
6205 A2
F200 D8
F201 D8
F202 D8
F205 E8
F206 B2
F207 B2
F208 B2
F209 C1
AR
YFIN_FC
2200 C5
2205 C6
3200 B5
3202 B5
3205 C3
3209 B5
3210 B6
3211 B6
3212 B6
3213 B6
GND
AV_FP
AFCRI_FC
5 6 7 8 9
1 2 3 4 5 6 7 8 9
A
GND
GND
AFCLI_FC
CVBSFIN_FC
CFIN_FC
AL/MONO
CVBS
1 2 3 4
D
R
A
O
B

L
A
T
I
G
I
D

O
T
CINCH
B
C
D
E
A
B
C
D
E
1200-1 B1
1200-2 B1
1200-3 C1
1203 E9
F202
7
6
8
4
3
5
LPV8529-0100F
RED
1200-3
1
2
LPV8529-0100F
WHITE
1200-2
1200-1 YELLOW
LPV8529-0100F
3212
10K
10K
3210
3213
1K8
3
2
1
1K8
3211
8.
6
A
3
F
D
5
0
2
6
AV_GND
AV_GND
AV_GND
AV_GND
2
3
4
5
6
7
8
9
AV_GND
HLW9S-2C7
1203
1
1K0
5201
5202
1K0
3209
n
0
1
5
0
2
2
1R0
5
0
2
3
R
5
7
4203
4201
4202
F206
9
0
2
F
220R
3202 F207
5
0
2
F
F200
F201
n
0
1
0
0
2
2
3200
220R
F208

EN 110 3139 785 32804
Layout: Display / Front Connector (Top View)
Layout: Display / Front Connector (Bottom View)
Front Display Bd Top View 717.3_3139_243_36944_sh130_a1.pdf 2007-05-09
Front Display Bd Bottom View 717.3_3139_243_36944_sh130_a1.pdf 2007-06-01

EN 111 3139 785 32804
Front: Standby (STBY)
F303 B2 F304 B2 F305 B4
R
E
W
O
P
GND
d
r
a
o
B

t
n
o
r
F

m
o
r
f
POWER
2 3 4
1 2 3 4
A
B
C
A
B
C
1301 B2 1302 B4 2302 B3 4301 B3 5301 B3
not used
not used
1
F305
4301
2u2
5301
2
0
3
2
7
n
4
2
1
F303
2
0
3
1
R
5
0
L
1
1
Q
V
E
1301
1
2
F304
GND
WH02D-1
Layout: Standby (STBY) (Top View) Layout: Standby (STBY) (Bottom View)
Front Standby Bot_3139-243-36934-132-a1.pdf 2007-05-10
Front Standby Top_3139-243-36934-132-a1.pdf 2007-05-10

EN 112 3139 785 32804
LecoPlus INIT
F402 B2 F403 C2 F404 C2
1 2 3
1 2 3
A
B
C
A
B
C
1400 B1 F400 B2 F401 B2
F401
F402
F400
F403
F404
2
3
4
5
6
7
1400
S7B-PH-K
1
Layout: LecoPlus INIT (Top View) Layout: LecoPlus INIT (Bottom View)
LECO PLUS INIT Top_3139-243-37094-132-a1.pdf 2007-05-10 LECO PLUS INIT Bot_3139-243-37094-132-a1.pdf 2007-05-10

EN 113 3139 785 32804
Digital: LeCoplus (LECO)
PIO<0:15>
PIO<16:31>
14
15
0
1
2
3
4
5
6
24
23
22
21
20
19
18
17
16
31
30
29
28
27
26
25
7
8
9
10
11
12
13
CSN
ADDR<0:22>
DATA<0:15>
22
0
1
2
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
10
11
12
13
14
15
OEN
WEN
CLK
UB
LB
LBA
BAA
9
8
7
6
5
4
3
2
1
0
RDY
16
17
18
19
20
21 10
9
8
7
6
5
VDD_DLL_CLEAN
4
3
2
0
1
0
ADDR<0:13>
6
5
4
3
2
1
1
DDR_VREF
0
7
8
9
10
11
12
13
CK
CKB
CKE
WE RAS
CAS
1
0
1
2
15
14
13
12
11
DATA<0:15>
DQM
0
1
DQS
BANK
7
ITU<0:7>
WS
SD
VS
0
1
2
SPDIF
FSCLK
SCK
WS
SD0
Y|CVBS
ITU<0:7>
ITU<0:7>
6
5
6
7
RSET
ANA_VREF
0
1
2
0
1
WS
SCK
1
IDUMP
AVDD
C|CVBS
6
7
3
4
5
VAL
CLK
HS
VAL
CLK
0
1
2
3
4
5
0
SD
VAL
CLK
SCK
FSCLKE
SPDIF1
R|V|C
G|Y|Y
B|U
CVBS|Y
VS
HS
0
1
2
3
4
N
C
N
C
6
5
4
3
DMARQ
2
1
0
DMACK
IORDY
DMARQ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
5 1 5 1
14
13
CS
DA
DD<0:15>
CS
DA
DD<0:15>
12
11
10
9
8
7
0
DMACK
IORDY
DIOR
DIOW
1
0
2
1
0
DIOR
DIOW
1
0
1
2
D N G D N G D N G D N G GND
1V2
GND
2V5 3V3
GNDA
SYSCLK
LINKON
LPS
LREQ
0
D<0:7>
BUFFER
IN
OUT
PLL_OUT
FE_CP
XFER_REQ
BE_BUSY
CTL
HOST
31
30
29
28
27
5
4
3
2
1
SDA
SCL
0
1
DM
DP
RPU
RREF
ID
VBUS
VSSA_TERM
VSSA_REF
VDDA_3V3
VDDA_3V3DRIVER
AVDD_CLK
AVSS_CLK
FE_DD<25:31>
BM_IRQ
BMI
XTAL
0
SDA
SCL
1
0
RXD
TXD
1
6
25
7
26
RXD
TXD
TDO
TDI
TMS
TRST
TCK
RESET
SYS_RESET
N
C
N
C
4 5 6 7
NC
*
NC
A
B
C
D
E
F
G
H
I
1100 G4
2100 A4
2101 A4
2102 G5
2103 G4
2104 E6
2105 E6
2106 E6
D
E
F
G
H
I
NC
NC
*
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3
2123 F7
2124 G6
2125 G6
2126 G7
2127 H7
2128 H7
NC
N
C
(HTS)
NC
NC
8 9 10 11 12 13 14
A
B
C
2139 I7
2140 G1
2141 H7
3100-1 B1
3100-2 B1
3100-3 B1
N
C
N
C
NC
N
C
2107 E6
2108 E7
2109 E7
2110 E7
2111 E7
2112 E7
2113 F5
2120 F5
2121 F5
2122 F6
3102-4 B1
3103-1 C1
3103-2 C1
3103-3 C1
3103-4 C1
3104 C1
NC
N
C
N
C
2129 H7
2130 H7
2131 H7
2132 H7
2133 H7
2134 H7
2135 I7
2136 I7
2138 I7
3114-1 B4
3114-2 B4
3114-3 B4
3114-4 B4
3117 C4
3118 H11
N
C
N
C
3100-4 B1
3101-1 B1
3101-2 B1
3101-3 B1
3101-4 B1
3102-1 C1
3102-2 C1
3102-3 B1
3130 H11
3131 H11
3132 G5
3133 D4
3134 H11
3135 E13
NC
N
C
*
NC
from VIP
3105 C1
3106 C1
3107 C1
3108 C1
3109 D1
3110 D1
3111 D2
3112 B4
3113 B4
3146 B4
3147 B4
3148 C4
3149 C4
3150 C4
3151 C4
*
NC
N
C
N
C
3119 C4
3120 C4
3121 C4
3122 E2
3123 E2
3124 E2
3125 E2
3126 F1
3127 F2
3128 G1
3129 H7
4118 D8
5100 E6
5101 F4
5102 F6
5103 F6
5105 G6
N
C
NC
N
C
*
3136 F13
3137 F13
3138-1 G13
3138-2 G13
3138-3 G13
3139-1 H13
3139-2 H13
3139-3 H13
3139-4 G13
3140-1 H13
3140-2 H13
3140-3 H13
3140-4 H13
3144 B4
3145 B4
F105 F7
F106 G7
F107 G8
F108 H7
F109 I8
F110 I8
NC
NC
NC
NC
NC
N
C
4100 E13
4101 F1
4102 F1
4103 F1
4104 F1
4105 D4
4106 D4
4107 D8
4108 E4
4115 D8
4116 D8
4117 D8
F131 G11
F132 G11
F133 G11
F134 G11
F135 G11
F136 G11
N
C
5106 I7
5107 I7
5108 G7
7100-1 A2
7100-2 A8
7100-3 A11
7100-4 C6
7100-5 E2
7100-6 E11
7100-7 I3
7100-8 I11
F101 G4
F102 G4
F103 E7
F104 F5
F142 H11
F143 H11
F144 H11
F146 D8
F147 D8
c100 H5
N
C
N
C
N
C
*
F112 G5
F115 B7
F120 E11
F121 F11
F122 F11
F123 F11
F124 F11
F125 F11
F126 F11
F127 F11
F128 F11
F129 F11
F130 F11
N
C
NC
NC
F137 G11
F138 G11
F139 G11
F140 H11
F141 H11
5105
50R
BLM31
47R 3140-2
3108
5108
60R
33R
F143
AA12
X
P
N
X
W10
Y10
AB10
Y11
Y12
AA10
W11
AA13
Y6
W6
Y9
W8
Y8
W7
Y7
AA7
AB7
AA8
AB8
AA9
AB9
W15
Y15
W14
Y14
AB14
AA14
AB12
AB11
AA6
AB6
W9
AA15
AB16
AB15
W13
Y13
AA11
AA16
AB17
W16
Y16
DDR
PNX7350E/C1
7100-1
AB13
W12
47R 3140-3
33R 3121
1
0
0
n
2
1
0
8
B1
D3
B2
F107
F1
F3
E1
E3
D1
C1
G2
G4
C3
B3
A1
B4
C4
D4
G1
G3
F2
F4
E2
E4
D2
C2
C10
D10
A9
B9
C9
D9
A8
A3
A2
A4
A7
B7
C7
D7
A6
B6
C6
B10
D6
A5
B5
7100-2
PNX7350E/C1
MIU
D11
A10
B8
C8
D8
1
0
0
n
2
1
3
4
F146
A17
C11
F138
W21
W22
F20
F19
C5
R22
B15
T4
R20
U4
E20
AB20
AA20
Y20
D5
AB21
AB22
AA21
AA22
Y21
Y22
R19
R21
E8
W5
Y5
W17
W18
G19
Y19
7100-4
PNX7350E/C1
PIO
F123
3109 33R
F142
3135 1K2
47R 3138-1
3140-4 47R
F104
2
1
3
1
1
0
0
n
1
0
0
n
2
1
2
5
F144
3120 33R
2
1
3
5
1
0
u
2
5
V
4118
2
1
2
2
1
0
u
2
5
V
N21
P21
A21
C22
A22
M20
N20
P20
M22
P22
N22
E21
E22
M21
V19
V20
V21
V22
U19
U20
U21
U22
T22
T21
T19
L22
L21
L20
L19
K22
K21
K20
J22
K19
T20
J20
J19
H22
H21
H20
H19
G22
F21
F22
G21
M19
A20
C21
D21
B21
N19
P19
B22
D20
C20
G20
J21
OUT
AUDIO
ANA_VIDEO
OUT
ITU_OUT
AV
ITU1_IN
ITU0_IN
AUDIO_IN
PNX7350E/C1
7100-6
E19
D22
B20
F137
47R 3139-2
2
K
7
3139-1 47R
3
1
2
2
F115
47R 3140-1
2
1
4
1
1
0
0
n
F130
BLM31
50R
5107
3145 33R
3102-3 33R
4108
F132
3138-3 47R
3102-1 33R
1
0
u 2
1
3
8
47R
2
5
V
3118
H
1
8
V
1
8
V
1
7
3151 33R
U
1
8
U
5
T
1
8
T
5
E
1
6
R
1
8
R
5
E
1
7
E
1
8
F
1
8
G
1
8
PNX7350E/C1
7100-8
E
7
V
1
6
V
1
5
V
8
V
7
V
6
V
5
N
C
1
0
0
n
2
1
2
8
33R 3148
2
1
2
6
4
7
n
3126
1K5
4107
F110
1
0
0
n
2
1
2
0
2
1
2
7
2
2
u
1
6
V
F139
3105 22R
33R 3102-4
3128
10K
BLM18P
60R
5106
4100
33R 3144
F133
F134
4116
12R 3136
F126
47R 3138-2
33R 3114-4
1
0
0
n
2
1
3
9
33R 3117
Y3
AA2
F140
W2
V4
V2
U3
U1
T2
T1
T3
AA1
Y4
AB1
AB2
AB3
Y2
W4
U2
V1
V3
W1
W3
Y1
J2
J3
J1
N4
N3
N2
P2
P1
AB4
AA4
AA3
K1
L3
L1
M2
M4
M1
L2
L4
K2
K4
R3
R4
P4
P3
R1
N1
M3
K3
IDE0

IDE1
PNX7350E/C1
7100-3
3127 12K 1%
c100
F105
BLM31
50R
5100
33R 3103-4
F108
47R 3139-3
4117
F135
4115
3101-1 33R
4103
1
0
0
n
2
1
1
2
F136
F112
XPNX
2
1
1
1
1
0
0
n
1
0
0
n
2
1
3
0
47R 3130
3114-3 33R
3103-3 33R
F131
1
0
0
n
2
1
1
0
1
6
V
2
2
u 2
1
0
4
F128
F129
F127
2
K
7
3
1
2
4
F124
F141
2
1
2
1
1
0
0
n
2
1
2
3
1
0
0
n
3100-2 33R
4102
X
P
N
X
2
5
V
1
0
u 2
1
2
4
4106
F101
33R 3150
F102
3103-2 33R
33R 3100-1
3129
33R
47R 3139-4
F125
F109
100n
F121
2100
33R 3100-3
3100-4 33R
33R 3101-4
2
1
0
5
1
0
0
n
33R 3102-2
33R 3103-1
47R
3134
2103 22p
4
M
0
1
1
0
0
2
1
2
9
1
0
0
n
BLM18P
5101
60R
2
K
7
3
1
2
3
2
1
3
6
1
0
0
n
3114-1 33R
100n
2140
3149 33R
4105
4104
3
1
2
5
2
K
7
F122
F120
22p 2102
4101
33R 3101-2
3
1
1
1
4
K
7
22R 3107
BLM18P
5103
60R
33R 3114-2
1
0
0
R
3132
4K7
3
1
1
9
3137 12R
3133 10K
3104 22R
2101
100n
P
1
1
P
1
0
P
9
V
1
1
V
1
2J9
J1
0
J1
1
M
1
4
N
9
N
1
0
N
1
1
N
1
2
N
1
3
N
1
4
P
1
4
P
1
3
P
1
2
M
1
8
L
1
0
L
1
1
L
1
2
L
1
3
L
1
4
M
9
M
1
0
M
1
1
M
1
2
M
1
3
M
5
J1
2
J1
3
J1
4
K
9
K
1
0
K
1
1
K
1
2
K
1
3
K
1
4
L
9
L
1
8
V
1
3
V
9
V
1
4
E
1
0
E
1
2
K
1
8
L
5
N
5
N
1
8
E
1
1
SUPPLY
PNX7350E/C1
7100-7
E
9
E
1
3
J1
8
K
5
P
5
P
1
8
V
1
0
3131
47R
2
1
0
9
1
0
0
n
F147
60R
5102
BLM18P
AA19
AB5
Y17
E14
D13
C13
D15
C14
B12
A12
AA17
C19
W20
D19
W19
B11
AB18
AB19
AA18
Y18
A19
B19
A15
A16
B16
C16
D12
A11
B13
C15
AA5
H5
A14
E15
D16
B17
C17
D17
A18
B18
C18
D18
G5
D14
B14
R2
J4
J5
H1
H2
H3
H4
UART
JTAG
GENERAL
FRONT END
IEEE1394-PHY
I2C
USB
CTRL
PNX7350E/C1
7100-5
A13
C12
E5
E6
F5
3113 33R
2
1
0
7
1
0
0
n
1
0
0
n
2
1
0
6
1
0
0
n
2
1
3
2
3
1
1
0
F103
4
K
7
2
1
1
32
5
V
1
0
u
3101-3 33R
3106 22R
2
5
V
1
0
u 2
1
3
3
3147 33R
33R 3146
33R 3112
PSCAN_RESETN
PNX_SD0_IN
ITU_OUT_CLK
ITU_OUT_VSYNC
ITU_OUT_HSYNC
SCL_ABT
SDA_ABT
SDA_ABT
PNX_PIO22_EJTAG_PCST1(1)
VIDEO_MUX3_SEL
F106
PNX_ITU_OUT(5)
PNX_ITU_OUT(6)
PNX_ITU_OUT(7)
HDMI_CEC_INTn
PNX_SYS_RESETN
+VDDR
{PNX_ITU1_IN(7:0),ITU1_IN_VALID,ITU1_IN_CLK}
{PNX_ITU0_IN(7:0),ITU0_IN_VS,ITU0_IN_HS,ITU0_IN_VALID,ITU0_IN_CLK}
PNX_PIO5_VIP_IRQN
TUNER_ON
PNX_PIO17_EJTAG_DSU_TPC1 DTT_RESETN
PNX_PIO18_EJTAG_PCST0(0) PNX_PIO8_HD_ON
PNX_PIO8_HD_ON
PNX_PIO16_EJTAG_DSU_CLK
PHY_LKON
PNX_WS0_IN
PNX_SCK0_IN
PNX_FSCLK_IN
1V2A_DDR_DLL
PNX_PIO9_USB_OC
PNX_PIO7_SPDIF2_IN
HTS_IRQN
+3V3
{PNX_ITU_OUT(7:0),ITU_OUT_VALID,ITU_OUT_CLK,ITU_OUT_VSYNC,ITU_OUT_HSYNC}
PNX_ITU_OUT(0)
PNX_ITU_OUT(1)
PNX_ITU_OUT(2)
PNX_ITU_OUT(3)
PNX_ITU_OUT(4)
PNX_G_Y
PNX_R_V
PNX_Y
1V2_CORE PNX_VDDR 3V3_PAD
PNX_SD_OUT
PNX_WS_OUT
PNX_SCK_OUT
PNX_FSCLK_OUT
PNX_SPDIF_OUT
PHY_CLK
3V3_VDAC_VDD1
+3V3
PNX_PIO3_MIU_A23
+3V3
PNX_RESETN
PNX_UART_RXD(0)
PNX_UART_RXD(1)
PNX_TCK
PNX_TDI
PNX_TDO
PNX_TMS
PNX_TRST
PNX_UART_TXD(0)
PNX_UART_TXD(1)
3V3_VDAC_VDD0
3V3_VDAC_VDD1
PNX_B_U
PNX_CVBS
PNX_C
IDE1_DD(13)
IDE1_DD(14)
IDE1_DD(15)
IDE1_DD(2)
IDE1_DD(3)
IDE1_DD(4)
IDE1_DD(5)
IDE1_DD(6)
IDE1_DD(7)
IDE1_DD(8)
IDE1_DD(9)
IDE1_DIOR
IDE1_DIOW
IDE1_DMACK
IDE1_DMARQ
IDE1_IORDY
PNX_PIO24_1394_PD
PNX_PIO25_HDMI_RSTN
PNX_PIO26_1394_RSTN
PNX_PIO27_DD_ON
PNX_PIO28_IDE0_EN
PNX_PIO29_IR_OUT
PNX_PIO30_DKILLN
PNX_PIO31_USB_VBUSON
1V2A_PLL
MIU_A(18)
MIU_A(19)
MIU_A(2)
MIU_A(20)
MIU_A(21)
MIU_A(22)
MIU_A(3)
MIU_A(4)
MIU_A(5)
MIU_A(6)
MIU_A(7)
MIU_A(8)
MIU_A(9)
MIU_CSN(0)
MIU_CSN(1)
MIU_CSN(2)
MIU_CSN(3)
IDE1_CS(0)
IDE1_CS(1)
IDE1_DA(0)
IDE1_DA(1)
IDE1_DA(2)
IDE1_DD(0)
IDE1_DD(1)
IDE1_DD(10)
IDE1_DD(11)
IDE1_DD(12)
PNX_SCL(1)
+3V3
+3V3 +1V2
+1V2 +VDDR
+VDDR
DDR_CK
DDR_CKB
DDR_VREF
MIU_A(0)
MIU_A(1)
MIU_A(10)
MIU_A(11)
MIU_A(12)
MIU_A(13)
MIU_A(14)
MIU_A(15)
MIU_A(16)
MIU_A(17)
PNX_PIO10_HDMI_IRQ
PNX_PIO12_IDE0_IRQ
PNX_PIO14_DTT_CTS_1
+1V2
1V2_CORE
PNX_VDDR
+1V2
1V2A_PLL
+
1
V
2
+3V3
3V3_PAD
+3V3
3V3_VDAC_VDD0
3V3_USB_VDD
DDR_A(12)
PNX_VDDR
+3V3
PNX_SDA(0)
PNX_SCL(0)
PNX_SDA(1)
USB_ID
3V3_USB_VDD
USB_VBUS
3V3_USB_VDD
{PNX_UART_TXD(1:0),PNX_UART_RXD(1:0)}
{PNX_SCL(0),PNX_SDA(0),PNX_SCL(1),PNX_SDA(1)}
{PHY_D(7:0),PHY_CTL(1:0),PHY_LREQ}
{PNX_TCK,PNX_TRST,PNX_TMS,PNX_TDI,PNX_TDO}
PNX_PIO0_IDE1_RSTN
PNX_PIO2_ASP_RST
PNX_PIO6_IDE1_IRQ
PNX_PIO4_ASP_IRQ
DDR_A(10)
DDR_A(11)
DDR_A(8)
DDR_BA(1)
DDR_BA(0)
DDR_CKE
DDR_WE
DDR_CAS
DDR_RAS
DDR_VREF
DDR_VREF
{DDR_DQM(1:0),DDR_DQS(1:0),DDR_RAS,DDR_CAS}
DDR_D(15:0)
DDR_BA(1:0)
DDR_A(13:0)
{DDR_CK,DDR_CKB,DDR_CKE,DDR_WE}
MIU_CSN(3:0)
MIU_A(22:0) MIU_D(15:0)
MIU_OEN
IDE1_DD(15:0)
{IDE1_CS(1:0),IDE1_DIOW,IDE1_DIOR,IDE1_IORDY,IDE1_DMACK,IDE1_DA(2:0),IDE1_DMARQ}
IDE0_DD(15:0)
USB_DM
USB_DP
DDR_D(12)
DDR_D(13)
DDR_D(14)
DDR_D(15)
DDR_DQM(0)
DDR_DQM(1)
DDR_DQS(0)
DDR_DQS(1)
DDR_A(0)
DDR_A(1)
DDR_A(2)
DDR_A(3)
DDR_A(4)
DDR_A(5)
DDR_A(6)
DDR_A(7)
DDR_A(9)
DDR_D(2)
DDR_D(1)
DDR_D(3)
DDR_D(4)
DDR_D(5)
DDR_D(6)
DDR_D(7)
DDR_D(8)
DDR_D(9)
DDR_D(10)
DDR_D(11)
ITU0_IN_CLK
ITU0_IN_VALID
ITU0_IN_VS
PNX_ITU1_IN(0)
PNX_ITU1_IN(1)
PNX_ITU1_IN(2)
PNX_ITU1_IN(3)
PNX_ITU1_IN(4)
PNX_ITU1_IN(5)
PNX_ITU1_IN(6)
PNX_ITU1_IN(7)
ITU1_IN_CLK
ITU1_IN_VALID
PNX_SPDIF1_IN
DDR_D(0)
PHY_D(3)
PHY_D(4)
PHY_D(5)
PHY_D(6)
PHY_D(7)
PHY_LPS
PHY_LREQ
ITU0_IN_HS
PNX_ITU0_IN(0)
PNX_ITU0_IN(1)
PNX_ITU0_IN(2)
PNX_ITU0_IN(3)
PNX_ITU0_IN(4)
PNX_ITU0_IN(5)
PNX_ITU0_IN(6)
PNX_ITU0_IN(7)
IDE0_DD(15)
IDE0_DD(2)
IDE0_DD(3)
IDE0_DD(4)
IDE0_DD(5)
IDE0_DD(6)
IDE0_DD(7)
IDE0_DD(8)
IDE0_DD(9)
IDE0_DIOR
IDE0_DIOW
IDE0_DMACK
IDE0_DMARQ
IDE0_IORDY
PNX_PIO1_BOOT_1
PNX_PIO11_IDE0_RSTN
PNX_PIO13_DTT_RTS_1
PNX_PIO15_VIP_RSTN
PHY_CTL(0)
PHY_CTL(1)
PHY_D(0)
PHY_D(1)
PHY_D(2)
MIU_D(2)
MIU_D(3)
MIU_D(4)
MIU_D(5)
MIU_D(6)
MIU_D(7)
MIU_D(8)
MIU_D(9)
MIU_RDY
MIU_WEN
IDE0_CS(0)
IDE0_CS(1)
IDE0_DA(0)
IDE0_DA(1)
IDE0_DA(2)
IDE0_DD(0)
IDE0_DD(1)
IDE0_DD(10)
IDE0_DD(11)
IDE0_DD(12)
IDE0_DD(13)
IDE0_DD(14)
1V2A_DDR_DLL
MIU_CLK
MIU_D(0)
MIU_D(1)
MIU_D(10)
MIU_D(11)
MIU_D(12)
MIU_D(13)
MIU_D(14)
MIU_D(15)
3139-243-36835_130-01_a2.eps 2007-07-17

EN 114 3139 785 32804
Digital: FLASH+SDRAM (MEM)
21
2
CE
7
6
WE
RP
1
0
BYTE
3
64M-1
5
8
9
10
11
12
13
14
15
A-1
10
4
9
8
7
6
0
0
A
D
5
11
2
1
17
OE
12
13
14
15
VPP/WP_
20
19
18
16
RB
4
3
CKE
BA
VSS
CS
5
12
2
VDD
7
1
0
NC
DM
VREF
3
VSSQ
VDDQ
D
A
DQS
WE
CAS
6
3
6
1
0
1
CK
2
AP
7
9
RAS
10
CK
4
8
11
4
5
0
19
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
VSS
VDD
0
A
D
5
2
4
RB
OE
CE
7
6
WE
3
1
RP
0
BYTE
2M-1 / 1M-1
NC
A-1
8
9
10
11
12
13
14
15
V
C
C
Q
DQ
NC
6
16
17
G
RP
4
V
C
C
3
0
1
5
RY
21
20
11
15
10
2
8
0
12
19
BY
A-1
WP
DQ
13
14
15
VPP
BYTE
WE
E
18
9
8
7
7
22
ADR
VSS
CKE
BA
VSS
CS
5
12
2
VDD
7
1
0
NC
DM
VREF
3
VSSQ
VDDQ
D
A
DQS
WE
CAS
6
3
6
1
0
1
CK
2
AP
7
9
RAS
10
CK
4
8
11
4
5
0
*
NC
NC NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A21
NC
NC
F216 H11
F217 H11
F218 H11
F219 H11
F220 H11
F221 H11
F222 I11
F223 I11
F250 G9
F252 G9
F253 I4
F254 I5
F256 I10
F272 H9
NC
4214 I13
4215 I13
4216 I1
4238 H1
4238 I1
5200 A2
5201 G1
7200 B1
7201 B6
7203 G10
7204 G4
7XXX G7
F200 A3
F201 F1
F202 G1
F203 I1
F204 I1
F205 I1
F206 I1
F207 I1
F208 G12
F209 H12
F210 H12
F211 H12
F212 H12
F213 H12
F214 H12
F215 H12
*
NC
NC
3224 F1
3225 D1
3226 D5
3227 H2
3228 H1
4200 E2
4201 E5
4202 I1
4202 I5
4203 I1
4204 G12
4205 H12
4206 H12
4207 H12
4208 H12
4209 H12
4210 H12
4211 H12
4212 I13
4213 I13
NC
*
2230 D4
2233 F5
2234 F11
2236 I5
3202 D1
3203 C3
3206 D5
3207 C7
3216 H1
3217 H1
3218 H2
3219 H5
3220 H2
3223 E1
2210 A6
2212 B3
2213 B7
2215 B2
2216 B6
2218 B3
2219 B7
2221 B2
2222 B6
2224 B3
2225 B7
2227 D1
2228 D4
2229 D1
NC
NC
NC
6 7 8 9 10 11 12 13
A
B
C
D
E
F
G
H
I
NC NC
NC
NC
NC
NC
8 9 10 11 12 13
1 2 3 4 5
{MIU_D(15:0), MIU_A(22:0), MIU_CLK, MIU_OEN, MIU_WEN, CSN(0), BYTEN}
NC
NC
NC
NC
NC
NC
1 2 3 4 5 6 7
NC
A
B
C
D
E
F
G
H
I
2200 A2
2201 A3
2202 A6
2203 A7
2206 A3
2207 A7
2209 B2
100n
2212
F210
2221
100n
4213
4212
12
3
7
14
2
7
4
6
11
33
35
38
40
42
44
30
32
28
15
7
47
26
29
31
34
36
39
41
43
45
16
9
23
10
13
22
21
20
19
18
8
25
24
6
5
4
3
2
1
48
17
M29DW640D70N
7204
8Mx8/4Mx16
EPROM
100n
2219
100n
2210
4
K
7
3
2
1
8
BLM31
50R
5200
5
8
6
4
21
1
%
1
K
0
3
2
2
3
91
5
5
5
6
1
49
3
4
4
8
6
66
1
2
5
2
14
16
17
20
25
23
11
8
3
3
3
43
53
54
57
60
63
19
50
7
10
13
2
5
8
11
56
59
62
65
51
4
38
39
40
26
27
22
45
44
46
24
47
29
30
28
41
42
31
32
35
36
37
SDRAM
64Mx8
DDR
EDD5108AFTA-5B
7200
F212
F211
F222
F209
F220
3202
1
0
0
n
2
2
3
3
4225
12
3
7
2
7
4
6
11
F205
38
40
42
44
30
32
13
14
10
28
15
26
29
31
34
36
39
41
43
45
33
35
9
23
22
21
20
19
18
8
7
47
25
24
6
5
4
3
2
1
48
17
16
[FLASH]
2Mx8/1Mx16
7206
M29W160ET70N6F
4201
4
K
7
3
2
1
9
2203
100n
4
K
7
3
2
2
8
4216
2200
100u 6.3V
2209
100n
2
2
3
6
1
0
0
n
4227
3203
F256
F214
F208
4215
4214
3
2
2
4
1
K
0
1
%
3207
F206
4203
F207
2206
100n
F253
100n
2222
3
2
2
7
4
K
7
4205
3
2
1
6
4
K
7
1
0
0
n
2
2
2
7
F219
F218
F216
240R 3226
2213
100n
F215
F213
1
0
0
n
2
2
3
0
F204
2
2
2
9
1
0
0
n
2
9
3
3
5
2
13
16
32
34
1
27
28
30
55
56
14
17
4
3
47
49
51
39
41
44
46
48
50
36
38
22
21
20
10
9
53
35
37
40
42
45
54
19
18
11
25
12
15
2
24
23
31
26
8
7
6
5
4
3
7203
M29DW128F70NF
[FLASH]
DRAM
128M
4
K
7
3
2
2
0
50R
BLM31
5201
4200
3225 240R
F201
2218
100n
2225
100n
4238
3206
4204
100n
2215
F202
2216
100n
4211
F252
4210
F223
F250
4202
4208
4207
4206
2201
F221 F272
100n
F200
100n
2224
2234
100n
100n
2207
F217
6.3V 100u
2202
2
2
2
8
1
0
0
n
F254
21
3
2
1
7
4
K
7
5
5
6
1
49
3
4
4
8
6
66
1
2
5
2
5
8
6
4
17
20
25
23
11
8
3
3
391
5
54
57
60
63
19
50
7
10
13
14
16
5
8
11
56
59
62
65
51
4
43
53
40
26
27
22
45
44
46
24
47
2
30
28
41
42
31
32
35
36
37
38
39
SDRAM
64Mx8
DDR
EDD5108AFTA-5B
7201
29
F203
DDR_D(15)
4209
DDR_D(7)
DDR_DQS(0) DDR_DQS(1)
DDR_D(8)
DDR_D(9)
DDR_D(10)
DDR_D(11)
DDR_D(12)
DDR_D(13)
DDR_D(14)
NOR_RSTN
NOR_RSTN
CSN(0)
CSN(1)
NOR_RSTN
RDY
NOR_RSTN
MIU_RDY
{DDR_A(12),DDR_A(13),DDR_D(15:0),DDR_DQS(0),DDR_DQS(1)}
DDR_D(0)
DDR_D(1)
DDR_D(2)
DDR_D(3)
DDR_D(4)
DDR_D(5)
DDR_D(6)
MIU_A(1)
MIU_A(2)
MIU_A(11)
MIU_A(12)
MIU_A(13)
MIU_A(14)
MIU_A(15)
MIU_A(16)
MIU_A(17)
MIU_A(18)
MIU_A(19)
MIU_A(20)
MIU_A(3)
MIU_A(21)
MIU_A(4)
MIU_A(5)
MIU_A(6)
MIU_A(7)
MIU_A(8)
MIU_A(9)
MIU_A(10)
MIU_A(22)
RDY
{MIU_A(22:0),MIU_CLK,MIU_OEN,MIU_WEN,CSN(0),BYTEN,RDY,NOR_RSTN}
3V3_MIU
RDY
MIU_RDY
RDY
MIU_D(2)
MIU_D(1)
MIU_D(0)
MIU_OEN
MIU_WEN
MIU_A(21)
MIU_A(20)
MIU_A(19)
MIU_A(18)
MIU_A(17)
MIU_A(16)
MIU_A(15)
MIU_A(14)
MIU_A(13)
MIU_A(12)
MIU_A(11)
MIU_A(10)
MIU_A(9)
MIU_A(8)
MIU_A(7)
MIU_A(6)
MIU_A(5)
MIU_A(4)
MIU_A(3)
MIU_A(2)
MIU_A(1)
CSN(0)
MIU_OEN
MIU_WEN
BYTEN
PHI_D(7)
PHI_D(6)
PHI_D(5)
PHI_D(4)
PHI_D(3)
PHI_D(2)
PHI_D(1)
PHI_D(0)
{PHI_D(7:0),NOR_RSTN,CSN(3),CSN(1)}
PNX_PIO3_MIU_A23
MIU_A(22)
CSN(0)
BYTEN
3V3_MIU
MIU_D(15)
MIU_D(14)
MIU_D(13)
MIU_D(12)
MIU_D(11)
MIU_D(10)
MIU_D(9)
MIU_D(8)
MIU_D(7)
MIU_D(6)
MIU_D(5)
MIU_D(4)
MIU_D(3)
MIU_D(8)
3V3_MIU
MIU_D(7)
MIU_D(6)
MIU_D(5)
MIU_D(3)
MIU_D(2)
MIU_D(1)
MIU_D(4)
MIU_D(0)
MIU_OEN
MIU_WEN
MIU_A(22)
PHI_RDN
PHI_WRN
PHI_CMD
PHI_RDY
MIU_A(7)
MIU_A(8)
MIU_A(9)
MIU_A(10)
MIU_A(11)
MIU_A(12)
MIU_A(13)
MIU_A(14)
MIU_A(15)
MIU_A(16)
MIU_A(17)
MIU_A(18)
MIU_A(19)
MIU_A(20)
MIU_A(2)
CSN(0)
MIU_OEN
MIU_WEN
BYTEN
MIU_D(0)
MIU_D(10)
MIU_D(2)
MIU_D(4)
MIU_D(5)
MIU_D(6)
BYTEN
MIU_CSN(3)
MIU_CSN(1)
PHI_CSN
MIU_D(1)
MIU_D(11)
MIU_D(12)
MIU_D(13)
MIU_D(14)
MIU_D(15)
MIU_D(3)
MIU_D(7)
MIU_D(9)
MIU_A(1)
MIU_A(3)
MIU_A(4)
MIU_A(5)
MIU_A(6)
DDR_CK
PNX_SYS_RESETN
MIU_CSN(2)
DDR_VREF
DDR_VDD
DDR_VREF
DDR_A(12)
DDR_RAS
DDR_CAS
DDR_CKE
DDR_CK
DDR_CKB
DDR_VDD
DDR_A(12)
DDR_RAS
DDR_CKE
DDR_BA(1)
DDR_BA(0)
{DDR_A(12:0),DDR_A(13),DDR_BA(1:0),DDR_DQM(1:0),DDR_DQS(1:0),DDR_CK,DDR_CKB,DDR_CKE,DDR_WE,DDR_CAS,DDR_RAS}
DDR_CKB
3V3_MIU
3V3_MIU
MIU_CSN(0)
DDR_VREF
DDR_VDD
DDR_VDD
+VDDR
DDR_VDD
+3V3 3V3_MIU
+VDDR
+VDDR +3V3
+3V3
DDR_DQM(1)
MIU_D(9)
DDR_A(0)
DDR_A(1)
DDR_A(10)
DDR_A(11)
DDR_A(2)
DDR_A(3)
DDR_A(4)
DDR_A(5)
DDR_A(6)
DDR_A(7)
DDR_A(8)
DDR_A(9)
DDR_CAS
DDR_WE
DDR_DQM(0)
DDR_VDD
DDR_A(0)
DDR_A(1)
DDR_A(10)
DDR_A(11)
DDR_A(2)
DDR_A(3)
DDR_A(4)
DDR_A(5)
DDR_A(6)
DDR_A(7)
DDR_A(8)
DDR_A(9)
DDR_BA(0)
DDR_BA(1)
DDR_WE
MIU_D(0)
MIU_D(1)
MIU_D(10)
MIU_D(11)
MIU_D(12)
MIU_D(13)
MIU_D(14)
MIU_D(15)
MIU_D(2)
MIU_D(3)
MIU_D(4)
MIU_D(5)
MIU_D(6)
MIU_D(7)
MIU_D(8)
3139-243-36835_130-02_a2.eps 2007-07-17

EN 115 3139 785 32804
Digital: IEEE 1394+USB (DV+USB)
0
1
R
0
1
FILTER
DGND
LKON
D
PC
CTL
P
L
L
V
D
D
G
N
D
_
H
S
AGND
DVDD
P
L
L
G
N
D
AVDD
TPA+
TPA-
TPB+
TPB-
7
6
5
4
3
2
1
0
1
0
LREQ
SYSCLK
RESET
PD
0 S A I B P T
1
C
2
XO
ISO
LPS
TESTM
SE
SM
CPS
XI
1
2
IN
1
2
3
OUT
USBM
from FRONT BOARD
1
to LECO
from LECO
*
#
E
F
G
H
I
A
8 9 10 11 12 13
A
B B
C
D
E
F
G
H
I
1301 D13
1302 H12
1303 C7
2300 B9
2301 B9
2302 B9
2303 B9
2306 C6
2307 C6
2308 C7
2309 E7
2310 E11
2311 E11
2312 D3
2313 G9
2 3 4 5 6 7 8 9 10 11 12 13
1 2 3 4 5 6 7
3304 D6
3305 D6
3306 D7
3307 D7
3308 D6
3309 E6
3310 E7
3311 D9
C
D
GND
ID
*
TPAn
2304 B7
2305 B7
3321 G7
3322 F8
3323 G8
3324 G10
3325 G9
3326 H11
3327 H11
3330 C6
2314 G10
2315 H9
*
(not used)
to LECO
2316 B8
3300 C9
3301 C7
3303 D6
4303 H7
4304 H7
4305 F8
4306 I11
4308 B5
4309 C6
5300 C3
5301 C3
3312 D9
3313 E9
#
GND
from USB Cable
*
3314 E10
3315 E10
3316 D10
3317 D11
3318 D11
3319 D11
3320 E11
F303 C7
F304 C7
F305 D12
F306 D12
F307 D12
F308 D12
F309 D12
F310 D12
3331 D6
3332 B7
to LECO
TPBn
4300 C7
4301 D6
4302 E10
F314 H12
F315 H12
F316 C6
F317 D7
F318 E7
F319 E7
F320 C9
F321 C9
5302 C3
7300 C8
USBP
TPB
7301 F9
F300 C4
F301 C4
F302 C4
to LECO
F324 C9
F325 C9
F326 C9
F327 D9
F328 D9
F329 D9
F330 D9
F311 H12
F312 H12
USB
from VIP
2308, 4300 Not for PDI1394P25BY #
IEEE1394
*
5VBUS
to LECO
F313 H12
*
F322 C9
F323 C9
TPA
*
GND
29
28
27
31
42
43
F331 D9
F332 E9
*
4
1
4
0
33
34
37
23
24
1
22
30
39
4
9
19
13
48
16
17
18 12
8
9
10
11
1
4
4
6
4
7
2
1
4
4
4
5
38
2
5
3
5
20
2
3
15
4
5
6
7
7300
TSB41AB1PHP
1-PORT CABLE
ARBITER
TRANCEIVER
2
6
3
2
3
6
F308
60R
5302
BLM18P
F316
F302
F303
3
3
2
1
1
0
K
4
3
0
6
F325
10K
3315
F320
3327
F307
3325
5K6
XDV
1
2
3
4
5
6
B6B-PH-K
1301 1
%
3
3
1
6
5
6
R
4
K
7
3
3
0
5
F332
3300
22R
3
3
2
4
1
0
K
F317
680R 3313
1
%
3
3
1
7
3
3
1
9
5
6
R
1
%
5
6
R
4304
100n 2303 2305 100n
2300 100n
4305
1
%
5
6
R
3
3
1
8
1
0
V
1
0
0
u 2
3
1
2
680R 3311
2306
10p
F311
3
3
0
3
1
K
0
1
M
0
XDV
3
3
3
0
100n
4308
2301
2
3
1
0
1
u
0
F318
4
5
1302
B5B-PH-K
1
2
3
3314
10K
1
6
V
4
7
u 2
3
1
4
F313
F328
F326
10p
2307
F324
60R
5300
BLM18P
BLM18P
5301
60R
F331
3
3
2
3
1
0
K
4301
100n 2304
3306 5K6 1%
F330
1
0
K
3
3
2
2
2
2
R
3
3
3
2
F306
F329
3
3
0
4
4
K
7
4300
750R 1% 3307
4302
22R
2
3
OC_
5
6
7
8
3308
TPS2051AD
4
EN
G
N
D
1
7301
F305
4303
1303
AT-49 24M576
F314
3312 680R
2
3
1
3
1
0
0
n
F301
3
3
2
0
5
K
1
1
%
XDV
2
3
1
5
1
0
0
n
3
3
1
0
4
K
7
F321
F322
10K
3331
3326
F310
3309
100R
3301 1K0
2
3
1
1
2
2
0
p
F323
F319
MT2
F327
10V
F309
2316
100u
2308 100n
XDV
F315
F300
100n 2302
F304
2
3
0
9
1
0
0
n
F312
USB_ID
3V3A_PHY
USB_DM
4309
3V3D_PHY
3V3D_PHY
+5V
+5V +3V3
+3V3
PHY_XIN
PHY_CLK
USB_VBUS
3V3PLL_PHY
+5V
+5V
+5V
USB_OC
USB_DP
3V3A_PHY
+3V3
3V3PLL_PHY
3V3D_PHY
PNX_PIO24_1394_PD
PNX_PIO31_USB_VBUSON
PNX_PIO9_USB_OC USB_OC
1394_CNA
PHY_D(3)
PNX_PIO26_1394_RSTN
PHY_CTL(1)
{PHY_CTL(1:0),PHY_LREQ,PHY_D(7:0)}
PHY_LKON
3V3D_PHY
PHY_LPS
3V3D_PHY
PHY_CTL(0)
PHY_D(0)
PHY_D(1)
PHY_D(6)
PHY_D(7)
PHY_LREQ
3V3D_PHY
PHY_D(4)
PHY_D(5)
PHY_D(2)
3139-243-36835_130-03_a2.eps 2007-07-17

EN 116 3139 785 32804
Digital: VIDEO+IDE+BOOT PROM+ EJTAG
to VIO conn
PNX_TMS
INT BOOT-FLASH 16 BIT
from LECO
*
F
G
H
I
1400 B8
1401 F8
1402-1 D12
1402-2 D13
1404 G13
2400 D6
2401 I6
2408 G13
2410 A2
2411 A3
2412 A3
2413 B5
PNX_TDO
INT BOOT-FLASH 8 BIT
EJTAG
EJTAG_RSTn
RXD
PIO13
IDE0
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2
L
to VIO conn
to VIO conn
3 4 5 6 7 8 9 10 11 12 13
*
L
A
B
C
D
E
F
G
H
I
A
B
C
D
E
L
GND
H
H
BOOT MODE
to VIO conn
2414 C2
2415 C2
2416 C3
2417 C4
2418 D1
2419 D1
2420 D2
2421 D4
2422 E1
2423 E2
2424 E2
2425 F3
*
from LECO
2426 F1
2427 F2
2428 G3
2429 G1
2430 G2
2431 H3
2432 I1
2433 I1
3401 A11
3402 A12
3403 A6
+5V
PIO1
from LECO
GND
NC
3404 F6
3405 A7
3406 F7
3407 B11
3409 B12
3410 B7
3411 F7
3412-1 B7
3412-2 B7
3412-3 B7
3412-4 B7
from LECO
*
3413-1 G7
3413-2 G7
3413-3 F7
3413-4 G7
3414-1 B7
3414-2 B7
3414-3 B7
3414-4 B7
3415-1 G7
3415-2 G7
3415-3 G7
3415-4 G7
3416-1 C7
3416-2 B7
3416-3 B7
3416-4 B7
3417-1 G7
GND
from LECO
3417-2 G7
3417-3 G7
3417-4 G7
3418-1 C7
3418-2 C7
3418-3 C7
3418-4 C7
3419-1 G7
3419-2 H7
3419-3 G7
3419-4 G7
3420 B1
3421 B3
3422 C4
3423 D1
3424 D2
I2C BOOT
PNX_TCK
H
BOOT MODE
GND
3425 D3
3426 E1
3427 E3
3428 E4
3429 F1
3430 F2
3431 F3
3432 G1
3433 G2
3434 H3
3435 I1
3436 I2
3437 I3
3438 H11
3439 H12
3440 I12
3441 I12
to VIO conn
GND
PNX_TDI
3442 C11
3443-1 D10
3443-2 D10
3443-3 D10
3443-4 D11
3444 A7
3447 F12
3448 G12
3449 C7
3450 H7
3451 D11
3452 C7
3453 H7
3454 C7
3455 H7
3457 C7
3458 H7
3459 I3
3460 D6
3461 H6
3462 B4
3463 D7
3464 H7
PIO0
3465 C4
3466 C3
3467 D7
3468 H7
3469 D4
3470 E3
3471 D7
3472 I7
3473 E4
3474 D6
3475 D7
3476 I6
3477 I7
3478 D7
3479 I7
3480 D7
3481 I7
3482 D7
3483 I7
3484 D7
3485 I7
3486 D7
3487 I8
3488 G11
3494 F2
3495 G3
OPTICAL DRIVE
*
3496 H3
3497 F13
3498 I2
3499 G11
4400 D5
4401 H6
4405 C4
4406 D3
4407 E4
4411 B4
4412 C3
4413 E3
5401 A1
5402 A3
5403 B2
5404 B3
5405 B3
5406 C1
5407 C2
5408 C2
5409 E2
5410 E2
5411 E3
QUARTZ SEL
*
from LECO
5412 F1
5413 G2
5414 I1
7101 G12
7401 B4
7402 D3
7403 E4
7404 F3
7405 G3
7406 I3
7407 H11
F400 B8
F401 B8
F402 B8
F403 B8
F404 B8
F405 B8
*
F406 B8
F407 B8
F408 B8
F409 B8
F410 B8
F411 B8
F412 C8
F413 C8
F414 C8
F415 C8
F416 C8
F417 C8
F418 C8
F419 C8
F420 C8
F421 D8
F422 D8
F423 D8
F424 D8
F425 D8
F426 D8
F427 D8
F428 D8
F429 D8
L
PIO1
*
GND
IDE1
H
SERVICE
to VIO conn
F430 F8
F431 F8
F432 G8
F433 G8
F434 G8
F435 G8
F436 G8
16MHZ
L 4MHZ
F437 G8
F438 G8
F439 G8
F440 G8
F441 G8
F442 G8
F443 G8
F444 G8
F445 G8
F446 H8
F447 H8
F448 H8
F449 H8
F450 H8
F451 H8
F452 H8
F453 I8
F454 I8
F455 I8
F456 I8
HARD DRIVE
#
QUARTZ SEL
H
F457 I8
F458 I8
F459 I8
F460 D11
F461 D11
F462 D11
F463 D11
F464 D11
F465 D11
F466 B10
F467 A10
F469 A2
F470 A3
F471 B3
F472 C2
F473 E3
F474 H13
F475 H13
F476 H13
SERVICE
TXD
I2C FAST BOOT
*
NC
PIO0
F477 H13
F478 H13
F479 D13
F480 F2
F481 G2
F482 I2
F483 G11
F484 H11
*
*
*
*
*
*
*
F459
GND
PNX_TRST
2
4
3
3
2
7
0
p
2
4
2
3
2
7
0
p
F479
100R
3470
22R 3453
4413
4412
4411
100R
3462
F420
33R 3418-4
F415
3413-2 33R
F480
3439
10K
1
0
K
3
4
4
0
1
0
K
1
0
K
3
4
3
8
3
4
0
4
6
K
8
3
4
4
1
3455 22R
3413-4 33R
3
3
0
R
3
4
6
5
3
4
4
4
1
0
K
33R 3417-4
3419-4 33R
2
4
2
4
F452
1
8
0
p
BC847B
7407
7404
BC847B
100n
2425
3
4
3
31
%
7
5
R
3416-3 33R
7402
BC847B
33R 3412-2
F427
3
4
0
3
1
0
K
3417-1 33R
F446
3419-1 33R
1
0
K
3
4
6
1
2413
100n
3423
1% 75R
33R 3412-4
F424
F465
3
4
9
6
3
3
0
R
3466
100R
3
4
6
9
3
3
0
R
F461
3412-3 33R
F444
33R 3414-4
1
6
V
1
0
u 2
4
1
0
2
7
0
p
2
4
1
9
33R 3416-2
3494
100R
F476
8
2
p
2
4
1
4
82R 3449
75R 1%
3420
F457
BC847B
7403
1
0
K
3
4
7
4
4400
F405
2421
100n
7
5
R
1
%
3
4
3
2
2
4
1
8
8
2
p
2
4
2
7
2
7
0
p
F435
F466
F467
5409
1u2
F432
F478
F404 4
K
7
F401
3
4
0
9
F416
3
4
2
5
1
K
0
F474
F449
33R 3471
F438
3415-1 33R
3
3
0
R
3
4
7
3
3481 33R
22R 3454
3414-3 33R
F443
3418-3 33R
2
4
2
9
2
7
0
p
F481
82R 3467
F418
F456
F448
F407
F462
3418-1 33R
75R 75R 1%
3427
1%
3426
F421
F422
F413
F423
1
K
0
3
4
0
5
2
4
0
1
2
2
p
3
4
7
6
1
0
K
33R 3418-2
1
K
0
3
4
4
7
3413-1 33R
4
K
7
3
4
0
1
3414-1 33R
470n
5408
2
7
3
4
4
3
-2
1
0
K
3
4
8
7
5
K
6
33R 3414-2
F463
5413
3
4
3
1
1
K
0
1u5
F451
F460
7406
BC847B
33R 3451
3463 22R
F458
3472 33R
3417-3 33R
33R 3480
33R 3479
3483 33R
2
7
0
p
2
4
3
0
F450
100n
2417
4405
F403
470n
5405
5406
4401
1u2
1
K
0
3
4
3
4
1
K
0
F426
3
4
2
8
1
0
K
3
4
9
9
BC847B
7405
1n5
2408
2428
100n
7101
BC847B
3416-1 33R
F429
F484
F436
33R 3416-4
5
K
6
3
4
8
6
F431
7
5
R
1
%
3
4
3
0
33R
F442
3419-3
F408
F454
F469
F455
2
4
1
2
1
0
0
n
5401
3412-1 33R
4u7
33R 3415-3
F439
3452 22R
F440
3410 33R
3419-2
F437
33R
3485 33R
F409
F410
3415-4 33R
3458
F425
82R
4406
3477
2
4
2
0
1
8
0
p
5K6
5403
4u7
5402
1u2
F414
3475 5K6
3411 33R
2
4
1
5
2
7
0
p
F411
3
4
0
7
4
K
7
3457 82R
5404
F453
1u5
3
3
0
R
3
4
5
9
1%
3424
75R
38
39
4
40
5
6
7
8
9
28
29
3
30
31
32
33
34
35
36
37
18
19
2
20
21
22
23
24
25
26
27
1
10
11
12
13
14
15
16
17
1400
1-440094-2
F428
3
4
4
3
-4
1
0
K
4
5
3
6
1
0
K
3
4
4
3
-3
BC847B
7401
3415-2 33R
F447
2
2
p
2
4
0
0
1u5
3468
5410
82R
33R 3413-3
7
5
R 3
4
2
91
%
100n
2431
5412
1u5
1
K
0
3
4
2
2
2
4
1
11
0
u
1
6
V
F419
5407
1u5
3495
100R
7
8
9
3
4
6
0
1
0
K
33
34
35
36
37
38
39
4
40
5
6
23
24
25
26
27
28
29
3
30
31
32
15
16
17
18
19
2
20
21
22
1401
1
10
11
12
13
14
1-440094-2
4
K
7
3
4
0
2
F430
3497
3448
4K7
F402
100R
F472
F406
F471
1
8
0
p
2
4
1
6
2
7
0
p
2
4
3
2
4407
8
2
p
2
4
2
2
4K7
3488
3464 22R
F477
F412
7
5
R
F483
1
%
3
4
3
6
2
7
0
p
2
4
2
6
F433
2
4
6
8
10
12 11
1402-2
ROW_2
FTSH-106-01-L-DV
1402-1
ROW_1
FTSH-106-01-L-DV
1
3
5
7
9
3421
1% 75R
F473 5411
470n
F400
F417
6
7
33R 3484
B7B-PH-K
1
2
3
4
5
1
8
1404
1
0
K
3
4
4
3
-1
3478 33R
7
5
R 3
4
3
51
%
F441
F445
F464
F470
3450 82R
F482
3482 33R
1u5
5414
3
4
3
7
1
K
0
33R 3417-2
F434
10K
3442
3
4
0
6
1
K
0
F475
100R
3498
5N_BUF
L
E
C
O
_
C
V
B
S
in
PNX_PIO0_IDE1_RSTN
+3V3
LECO_CVBS
D_Y
PNX_PIO24_1394_PD
+3V3
PNX_PIO11_IDE0_RSTN
+3V3
PNX_PIO0_IDE1_RSTN
+3V3
PNX_UART_RXD(0)
JTAG_RSTN
PNX_TCK
PNX_TMS
PNX_TDI
+3V3
5N_BUF
D_UB
5N_BUF
D_YG
5N_BUF
D_VR
5N_BUF
+5V 5NV
5N_BUF
PNX_R_V
5V_BUF
5NV
5NV +5V
+5V +3V3
+3V3
PNX_UART_TXD(0)
+5V
PNX_CVBS
PNX_Y
5V_BUF
PNX_C
5N_BUF
D_C
5V_BUF
5V_BUF
PNX_G_Y
5V_BUF
IDE1_DMARQ
IDE1_DD(8)
IDE1_DD(7)
IDE1_DD(6)
IDE1_DD(9)
IDE1_DD(5)
IDE1_DD(10)
IDE1_DD(4)
IDE1_DD(11)
IDE1_DD(3)
IDE1_DD(12)
IDE1_DD(2)
IDE1_DD(13)
IDE1_DD(1)
IDE1_DD(14)
IDE1_DD(0)
IDE1_DD(15)
IDE1_DD(15:0)
PNX_PIO6_IDE1_IRQ
+3V3
+3V3
+3V3
5V_BUF
5V_BUF
PNX_B_U
IDE1_CS(1)
IDE1_CS(0)
IDE1_DA(2)
IDE1_DA(0)
IDE1_DA(1)
IDE1_DMACK
IDE1_IORDY
IDE1_DIOR
IDE1_DIOW
IDE0_DD(7)
PNX_TRST
PNX_TDO
PNX_PIO1_BOOT_1 PNX_PIO13_DTT_RTS_1
+5V
IDE0_DD(4)
IDE0_DD(11)
IDE0_DD(3)
IDE0_DD(12)
IDE0_DD(2)
IDE0_DD(13)
IDE0_DD(1)
IDE0_DD(14)
IDE0_DD(0)
IDE0_DD(15)
IDE0_DIOW
IDE0_DIOR
IDE0_DMACK
IDE0_DMARQ
IDE0_IORDY
IDE0_DA(1)
IDE0_DA(0)
IDE0_DA(2)
IDE0_CS(0)
IDE0_CS(1)
+3V3
+3V3
IDE0_DD(15:0)
+3V3
PNX_PIO12_IDE0_IRQ
IDE0_DD(8)
IDE0_DD(6)
IDE0_DD(9)
IDE0_DD(5)
IDE0_DD(10)
3139-243-36835_130-04.eps 2007-07-21

EN 117 3139 785 32804
Digital: Audio/Video Decoder (VIP)
EN
EN
V
D
D
A
O
S
C
V
D
D
A
4
V
D
D
A
3
V
D
D
A
2
V
D
D
A
1
V
D
D
A
0
V
D
D
A
4
A
V
D
D
A
3
A
V
D
D
A
2
A
V
D
D
A
1
A
V
D
D
A
D
A
C
2
V
D
D
A
D
A
C
1
V
D
D
A
D
A
C
V
D
D
A
A
D
C
V
D
D
A
C
1
8
2
3
D
1
2
3
D
VSYNC
DAC_BIAS
RES_REF_V
IF_POS
IF_NEG
P
N
IN1_R
IN1_L
IN2_R
IN2_L
IN3_R
IN3_L
AUX1A
AUX1B
AUX2A
AUX2B
AUX3A
AUX3B
VRPOS_ADC
VRNEG_ADC
VREF_DAC
VREF0
VREF_ADC
V
D
D
A
P
L
L
OUT2_L
AI1
AI2
AI3
AI4
AI40
V
S
S
A
3
A
V
S
S
A
2
A
V
S
S
A
1
A
V
S
S
A
4
A
V
S
S
A
0
V
S
S
A
1
V
S
S
A
2
V
S
S
A
3
V
S
S
A
4
V
S
S
A
P
L
L
A
G
N
D
1
A
G
N
D
2
V
S
S
A
A
D
C
V
S
S
A
D
A
C
V
S
S
A
D
A
C
2
NC
3
1
2
3
D
1
2
V
S
S
A
O
S
C
D
1
V_IOUTP
AOUT2
AOUT1
V_IOUTN
OUT1_R
S_IOUTN
S_IOUTP
OUT1_L
V
D
D
A
1
V
8
XTALO
XTALI
XTOUT
OUT2_R
EN
DQ
VS
DVO
DVO_C
I2S_O
IR_IN
CE
SCK
AMCLK
SD_AUX
6
7
CLK
HCTL
RST
PP_SEL
SD
SCK
4
2
3
4
5
6
7
8
9
CLK
LOCK
5
1
0
1
2
3
D_CON
DI_A
DI_A
DI_E
DI_B
DI_B
VIP_D
VIP
I2S_I_1
I2S_I_2
DVO_D
DVO
GPIO 1
0
ODEV
WS
SPDIF_I
HS
CLK
7
6
5
4
3
2
SPDIF_O
IR_OUT
VSSDI
OUT_RST
VSSDMEM VSSDE
TMS
TCK
TRST
SDA_SILENT
SCL_SILENT
SDA
SCL
VDDDMEM E D D D V I D D D V
5
6
0
VS
0
1
1
2
3
4
5
6
7
CLK
DQ
HS
VAL
SOP
0
1
2
3
4
WS
SD
CLK
7
6
5
4
3
2
1
0
2
WS
SD
SCK
1
0
INT_A
IF_AGC
SI_VSYNC
TDI
TDO
7
0
7 8 9 10 11 12 13
from LECO
NC
NC
NC
1V8
*
F
G
13 14
A
B
C
D
E
H
I
A
B
C
D
E
F
G
H
I
1500 B1
1501 E1
NC
1 2 3 4 5 6
1505 I10
1506 B1
1507 I2
2500 A5
2501 A5
2502 A5
2503 A5
14
1 2 3 4 5 6 7 8 9 10 11 12
NC
GND
VIO conn
GND
NC
3V3
NC
NC
GND
NC
2515 A13
2516 A8
2517 A6
2518 A8
2519 A9
2520 A9
2521 A9
GND
*
NC
AUDIO1_R
NC
NC
NC
from ASP
to DV
NC
1502 H1
1503 I1
1504 G8
2530 A13
2531 A13
2532 H9
2533 A6
2534 B7
2535 B5
2536 B5
GND
*
GND
LR2_R
NC
2504 A5
2505 A6
2506 A6
2507 A6
2508 A6
2509 A12
2510 A12
2511 A12
2512 A12
2513 A13
2514 A13
2548 D4
2549 D4
2550 D4
2552 D4
2553 D4
2554 E4
2555 E4
GND
to FRONT BOARD
GND
NC
DAINOPT
#
*
NC
2522 A9
2523 B4
2524 A10
2525 A10
2526 A10
2527 A10
2528 A11
2529 A11
2565 G4
2566 G4
2567 G12
2568 G5
2569 G7
2570 G8
2571 G2
NC
AINFR
NC
3V3
*
GND
D_WCLK
2537 B7
2538 C4
2539 C4
2540 C4
2541 C4
2542 C4
2543 C4
2544 C4
2545 C4
2546 D4
2547 D4
2575 H5
2576 I4
2577 I2
2578 I2
2579 I2
2580 I3
3501 B13
NC
NC
GND
NC
NC
#
#
LR1_L
SIF
2556 E4
2557 E4
2558 E4
2559 E4
2560 E4
2561 E4
2562 E4
2563 E4
2564 F4
3515-3 D13
3515-4 D13
3516-1 D13
3516-2 D13
3516-3 D13
3516-4 D13
3517-1 E13
1V8 3V3
NC
(C_IN_REAR)
NC
NC
GND
GND
A_YG
NC
CVBSFIN
*
*
from LECO
AUDIO2_R
2572 G2
2573 H2
2574 H2
3518-3 E13
3518-4 E13
3519 G7
3523 B4
3524 D4
3525-1 D13
3525-2 D13
D_CVBS
SC2_YCVBS
GND
GND
NC
GND
GND 3502 B13
3505-1 C14
3505-2 C14
3505-3 C14
3505-4 B14
3512 B13
3513 C14
3515-1 D13
3515-2 D13
3545 H9
3546 H3
3547 I3
3548 I3
3549 I3
3550 H4
3551 C8
CFIN
GND
NC
AUDIO1_L
NC
D_C
* Not used (provision only)
NC
DAINCOAX
3V3
NC
AIO_0 conn
GND
3517-2 E13
3517-3 E13
3517-4 E13
3518-1 F13
3518-2 E13
3565 C3
3566 D3
3567 D3
3569 D3
3570 D3
3571 D3
3573 B3
1V8
2K4
NC
D_KILL#
D_UB
3525-3 E13
3525-4 D13
3526 D4
3528 D4
3531 E12
3533 B13
3534 H10
3536 I10
3537 I10
3539 F8
3540 F12
3543 F7
3544 G8
3587 E3
3588 E4
3589 E4
3590 E4
3591 E4
3592 E4
3593 E4
NC
GND
NC
D_YG
YFIN
GND
D_Y
AOUT2
3552 D8
3553 H12
3554 H12
3555 H12
3556 H12
3557 H12
3558 H12
3559 I7
3560 C3
3561 C3
3562 C3
3563 C3
3564 C3
4522 F9
4523 C3
4524 C3
4525 C3
4526 B5
5500 A4
5501 A12
D_MCLK
GND
GND
NC
NC
NC
NC
3574 B4
3575 B4
3576 B4
3577 B4
3578 D3
3579 D4
3580 D4
3581 D4
3582 E3
3583 E3
3584 E3
3585 E3
3586 E3
6502 E3
7500-1 C5
7500-2 B9
7502 H5
7503 I10
7504 I9
7506 I6
GND
*
*
D_DATA0
*
1V8
4501 F8
4502 F8
4503 F8
4504 H8
4505 H6
4507 I6
4512 H9
4513 C13
4514 C13
4515 I10
4517 I10
4519 C3
F508 C2
F509 C2
F510 D2
F511 D2
F512 D2
F513 D2
F517 E2
*
NC
NC
SC1_CVBS / C_IN_REAR#
*
GND
GND
GND
5502 A8
5503 A11
5504 A13
5505 A6
5506 A7
5507 B5
5508 B7
6500 I10
6501 D3
F521 E2
F522 F2
F523 F2
F524 F2
F525 F2
F526 F2
F527 G2
NC
GND
NC
#
NC
GND
AIO_1 conn
VMUX6_OUT
D_BCLK
GND
7507 I6
7508 I8
F500 B2
F501 B2
F502 B2
F503 C2
F504 C2
F505 C2
F506 C2
F507 D2
F532 G2
F533 G2
F534 G2
F535 H2
F536 H2
F537 I2
F538 I2
NC
NC
NC
GND
A_VR
NC
LR1_R
DAINDTT
NC
NC
NC
GND
GND
NC
AUDIO3_L
F518 E2
F519 E2
F520 E2
F552 C2
F553 C14
F554 C13
F555 C13
F556 C13
F557 C13
F558 C2
FOR DTTM04
GND
NC
GND
AUDIO3_R
*
*
GND
D_VR
A_UB
AINFL
NC
NC
NC
3V3
DAOUT
NC
NC
F528 G2
F529 G2
F530 G2
F531 G2
F562 G2
F563 H2
F564 A7
F565 H8
F570 E13
c500 E2
c501 H7
NC
VMUX5_OUT
NC
NC
#
NC
F539 I2
F540 I2
F541 A6
F542 A6
F543 B5
F545 B7
F546 A10
F547 A11
F548 A13
F549 A13
F550 G7
F551 G8
E
u
(YCVBS_IN_REAR)
#
Eu
E
u*
AOUT1
3V3
AUDIO2_L
to VIO conn
NC
GND
GND
NC
LR2_L
NC
NC
F559 C2
F560 D2
F561 F2
3526 3K0
E
u
1%
BAT54 COL
6500
BLM18P
5505
60R
4
7502
74HCT1G125GW
2
3
1
5
3544
22n
1M0
2549
2
5
6
8
4
7
0
n
22n 2548
2
5
0
8
1
0
0
n
2574
10u 16V
8
9
F519
21
22
23
24
3
4
5
6
7
11
12
13
14
15
16
17
18
19
2
20
1502
HLW24S-2C7
1
10
2
4503
DF3A6.8
6502
3
1
2
5
2
9
1
0
0
n
22n
1
0
0
n
2543
T6
T7
L7
2
5
0
6
M
1
E
5
E
6
D
3
R
6
G
5
K
2
C2
E1
E2
D6
C6
B6
K
1
H
4
G
4J3 J6
M
2
L
5
T
1
R
1
N
4
A
6
D
2
C
7
F
5
D
1
R
7
G
6
F6
C4
E3
E4
K
4
H
5
G
3
J2J4 J7M
3
L
4
H7
H10
H11
H12
H13
A7
B7
F7
E7
K6
H15
J1
J8
K7
M5
M6
M8
P1
T5
B2
B8
E10
F2
F3
C5
D5
A5
B5
B4
D4
A2
H14
P2
R2
K5
K3
A4
C3
B3
A3
A1
B1
F4
H1
J5
L3
L2
L1
M4
N2
N3
N1
P3
ANALOG PART
C
1
L
6
F1
G2
G1
H6
H3
H2
DECODER
AUDIO/VIDEO
SAA7136AE/V1/G
7500-1
1
0
0
n
2
5
6
6
1
0
0
n
2
5
3
6
22n 2552
3517-1 47R
74LVC1G125GW
2
3
1
5
4
7507
2
3
4
5
6
F526
1505
HLW6S-2C7
1
12
2
3
4
5
6
7
8
9
1503
1
10
11
5
6
7
8
HLW12S-2C7
1
2
3
4
F501
HLW8S-2C7 1507
F542
F540
F537
2
2
p
2
5
7
9
GNDA
33R 3546
3
5
7
3
4
7
R
3
5
3
7
4
7
K
2
3
1
5
4
74LVC1G125GW
7506
4504
F504
1
0
K
2
7
2
5
2
1
1
0
0
n
3
6
3
5
0
5
-2
1
0
K
3
5
0
5
-3
2547 22n
F556
2550
F530
22n
2
2
p
2
5
7
8
1% 75R
3552
470n 2564
F533
1
0
0
n
2
5
2
8
2
5
1
0
1
0
0
n
F531
4515
3516-4
4
5
2
5
47R
4
K
7
3
5
5
5
2
5
0
4
1
0
0
n
F532
27R 3562
XVIP
1 8
F529
3525-1 47R
F511
F551
6
.3
V
1
0
0
u 2
5
3
5
2
5
3
0
1
0
0
n
22n 2546
F565
3
5
5
3
4
K
7
4522
F549
100n
2575
2
5
1
9
1
0
0
n
4
7
R
3
5
8
0
22n 2544
2554 22n
4
5
2
6
1
0
0
n
2
5
3
7
F521
60R
5501
BLM18P
1
0
0
n
2
5
1
1
3
5
0
1
4
K
7
1
0
0
n
2
5
0
5
c501
27p
2569
F570
F550
BLM18P
5503
60R
2570
27p
F564
F557
F552
7503
BC847BW
BLM18P
F547
5508
60R
22n 2540
60R
5502
BLM18P
60R
5506
BLM18P
F512
47R 3531
2
5
1
2
1
0
0
n
3518-4 47R
3515-1 47R
3
5
3
4
1
0
K
F538
7504
BC847BW
1
0
0
n
2
5
2
2
47R 3550
3525-4 4 5 47R 1% 3528
4
5
2
4
1
K
0
3
5
1
3
4502
1
0
0
n
2
5
1
8
6
.3
V
F518
2
5
6
5
4
7
u
F546
F560
2
5
2
5
1
0
0
n
2
2
0
p
2
5
7
6
16V 10u
2572
3512 22R
F503
1
0
0
n
2
5
3
4
2 7
2553 22n
47R 3525-2
1
0
0
n
2
5
1
3
F534
F513
47R 3518-3
F561
1
0
0
n
2
5
2
6
4
5
1
9
3561 27R
1
0
0
n
2
5
2
0
BLM18P
5500
60R
3515-2 47R
F509
F508
60R
5507
BLM18P
22n 2538
F548
F500
2
5
3
2
1
0
0
n
6501
DF3A6.8
3
1 2
3533 22R
F553
27R
3570
3571
27R
1
0
0
n
2
5
0
1
47R 3518-2
2555 22n
F558
3516-2 47R
2
5
1
6
1
0
u
1
6
V
2560 4u7
33R 3548
33R 3549
22n 2539
3
5
7
7
4
7
R
F520
F543
22n 2541
F535
47R 3516-1
4
K
7
3
5
5
9
4514
2
5
2
7
1
0
0
n
1
0
0
n
2
5
1
7
3515-3 47R
4
K
7
3
5
5
7
H
8
2
5
2
3
1
0
0
n
L
1
6
J1
2
G
1
0 J9
L
1
1
K
1
0
E
1
2
F
1
1
G
7
M
1
2
F
1
0
E
1
5
C
1
5
A
1
4
A
1
2
B
9
R
1
0
N
1
2
T
1
3
R
1
6
M
1
4
C16
B15
B16
A16
A15
C13
A13
D12
N
8
M
9
P
7
N
1
0
J1
1
E
1
3
D
1
0
D
7
N
1
1
C
1
1
B13
D15
D16
B
1
2
C
9
P
1
0
T
1
1
R
1
3
T
1
6
M
1
3
L
1
5
K
1
6
H
1
6
R3
R4
P4
T3
T2
T
8
R
9
G
1
6
E
1
4
C
1
4
B
1
4
D11 B11
A11
D14
T4
P5
N5
R5
L8
B10 C10
D8
C8
E8
E9
F9
A10
D9
G9
A8
N6
N16
L12
M15
M7
N7
C12
E11
M16
G8
F8
A9
N13
P13
L13
P14
R14
T14
R15
T15
P15
P16
N14
H9
G11
N15
L14
M11
P11
R11
P12
R12
T12
J15
J16
G12
G15
F12
F13
F14
F15
F16
E16
D13
L10
T10
M10
K11
K12
K13
K14
K15
J13
J14
P8
R8
K8
K9
L9
N9
P9
T9
G13
G14
J10
DECODER
AUDIO/VIDEO
SAA7136AE/V1/G
7500-2
DIGITAL PART
P6
27R 3567
3
5
5
8
1504
24M576
4
K
7
3551
75R 1%
1
0
0
n
2
5
1
5
27R 3565
47R 3515-4
3569 27R
4507
4505
4
K
7
3
5
4
5
1
0
0
n
2
5
0
7
2
5
0
2
1
0
0
n
2557 22n
2
5
3
3
4
7
u
6
.3
V
4
5
6
7
8
9
HLW9S-2C7
1501
1
2
3
4
7
R
3
5
2
3
F528
4501
47R
2
2
p
2
5
7
7
3517-4
3536
22K
1
0
0
n
2
5
2
4
F517
33R 3547
3
5
7
8
4
7
R
2556 22n
47R 3 6
F563
3525-3
F555
F541
F527
3
5
1
9
1
R
0
27R 3566
2
5
0
9
1
0
u
1
6
V
2542
6
7
8
9
22n
18
19
2
20
21
22
23
24
3
4
5
1
10
11
12
13
14
15
16
17
HLW24S-2C7 1506
4K7 3539
F506
3
5
7
4
F523
4
7
R
1
6
V
1
0
u 2
5
0
0
4
K
7
4
7
R
3
5
0
2
XVIP
3
5
2
4
2558 4u7
3516-3 47R
F545
4517
F554
3
5
7
5
4
7
R
4
7
R
3
5
7
6
3564 27R
F522
F536
1
R
0
3
5
4
3
12K 3586
3591 390R 3585 12K
3
5
7
9
4
7
R
F562
3517-2 47R
3583 12K
390R 3588 12K 3582
47R
4512
3
5
0
5
-4
1
0
K
4
5
3517-3
1
0
0
n
2
5
0
3
47R 3518-1
7508
PDTC124EU
16V 10u
2573
27R
22p
3563
2567
2559 4u7
2
5
8
0
2
2
p
3593 390R 3587 12K
390R 3592
4513
390R 3590 12K 3584
3589 390R
2563 4u7
2562 4u7
4u7 2561
30
4
5
6
7
8
9
22
23
24
25
26
27
28
29
3
13
14
15
16
17
18
19
2
20
21
1500
HLW30S-2C7
1
10
11
12
22n 2551
4509 4508
F524
F507
4
5
2
3
F502
F510
2545 22n
3
5
5
6
4
K
7
F539
2571
10u 16V
2
5
1
4
1
0
0
n
F505
4
K
7
3
5
5
4
1
8
60R
5504
BLM18P
1
0
K
3
5
0
5
-1
3540 47R
c500
1
0
0
n
2
5
3
1
F559
3
5
8
1
4
7
R
3560 27R
AIN1L
AIN2R
AIN2L
AINFR
AINFL
Y_G
F525
PNX_SD_OUT
PNX_FSCLK_OUT
ITU0_IN_VALID
ITU0_IN_VS
ITU0_IN_HS
ITU0_IN_CLK
+3V3_VIP
PNX_SCK_OUT
3V3SW
VDDAADC
SPDIF_SW
AIN1R
VIP_ITU0_IN_CLK
VIP_ITU0_IN(7)
VIP_ITU0_IN(6)
VIP_ITU0_IN(5)
VIP_ITU0_IN(4)
VIP_ITU0_IN(3)
VIP_ITU0_IN(2)
{VIP_ITU0_IN(2:9),VIP_ITU0_IN_CLK,VIP_ITU0_IN_VAL,VIP_ITU0_IN_SOP,VIP_ITU0_IN_LOCK}
{P
N
X
_
IT
U
0
_
IN
(7
:0
),IT
U
0
_
IN
_
V
S
,IT
U
0
_
IN
_
H
S
,IT
U
0
_
IN
_
V
A
L
ID
,IT
U
0
_
IN
_
C
L
K
}
FR_YIN
FR_CIN
PNX_SPDIF1_IN
DAINOPT
PNX_WS_OUT
VDDDMEM O I D D D V I D D D V
VIP_ITU0_IN(9)
VIP_ITU0_IN(8)
VIP_ITU0_IN_SOP
VIP_ITU0_IN_VAL
VIP_ITU0_IN_LOCK
PHI_WRN
PHI_CSN
PHI_D(7)
PHI_D(6)
PHI_D(5)
PHI_D(4)
PHI_D(3)
PHI_D(2)
PHI_D(1)
PHI_D(0)
PHI_CMD
SDA_S3V3
SCL_S3V3
PNX_WS0_IN
PNX_SCK0_IN
PNX_FSCLK_IN
PHI_RDY
PHI_RDN
PNX_WS0_IN
PNX_SCK0_IN
VIP_SD0_OUT
{VIP_SD0_OUT,PNX_WS0_IN,PNX_SCK0_IN,PNX_FSCLK_IN}
VIP_SD0_OUT
PNX_ITU1_IN(0)
PNX_ITU1_IN(1)
PNX_ITU1_IN(2)
PNX_ITU1_IN(3)
PNX_ITU1_IN(4)
PNX_ITU1_IN(5)
PNX_ITU1_IN(6)
PNX_ITU1_IN(7)
ITU1_IN_VALID
ITU1_IN_CLK
+3V3
LECO_CVBSin
PNX_PIO7_SPDIF2_IN
AINFL
FR_YIN
VMUX6_OUT
SC1_CVBS
AINFR
SC2_YCVBS
FR_CIN
Y_G
SC2_YCVBS
VMUX5_OUT
U_B
+3V3
DAINCOAX
+3V3
+5V
VDDDIO
PNX_PIO5_VIP_IRQN
PHY_XIN
PNX_PIO15_VIP_RSTN
PNX_WS_OUT
PNX_SCK_OUT
PNX_SD_OUT
VIF
+3V3_VIP
FR_CVBS
FR_CIN
{REAR_Y_CVBS,REAR_CIN,Y_G,U_B,V_R_C,TUN_CVBS,SC1_CVBS,SC2_YCVBS,VCR_CVBS,FR_YIN,FR_CIN,FR_CVBS,LECO_CVBS}
V_R_C
FR_YIN
VMUX6_OUT
SC1_CVBS
LECO_CVBS
D_UB
AIN1L
AIN2R
AIN2L
FR_CVBS
VDDA3V3
VDDA3V3
PHI_D(7:0)
VDDDIO
P
N
X
_
S
P
D
IF
_
O
U
T
WU
D_Y
D_C
D_VR
D_YG
AOUT2
AOUT1
VMUX5_OUT
V_R_C
U_B
Y_G
SIF
AIN1R
DAINCOAX
DAOUT
PNX_PIO30_DKILLN
DAOUT
DAINOPT
{AIN1L,AIN1R,AIN2L,AIN2R,AINFL,AINFR,LR1_L,LR1_R,LR2_L,LR2_R,PNX_SCK_OUT,PNX_WS_OUT,PNX_SD_OUT,PNX_FSCLK_OUT,PNX_SPDIF_OUT}
LR2_L
LR2_R
AOUT1
VDDA3V3
VDDA1V8
VDDA3V3 VDDA1V8
PNX_PIO15_VIP_RSTN
VIP_RESET_GATE
+3V3_VIP
VDDA3V3
PNX_SCL(1)
{PNX_ITU1_IN(7:0),ITU1_IN_VALID,ITU1_IN_CLK}
PNX_ITU0_IN(7)
PNX_ITU0_IN(6)
PNX_ITU0_IN(5)
PNX_ITU0_IN(4)
PNX_ITU0_IN(3)
PNX_ITU0_IN(2)
PNX_ITU0_IN(1)
PNX_ITU0_IN(0)
+3V3_VIP
AOUT2
LR2_R
LR2_L
LR1_L
LR1_R
VDDAADC
FBIN
PNX_SDA(1)
+1V8
+1V8 +5V
+5V
SIF
+3V3_VIP VDDDIO VDDDI +1V8
+1V8 VDDDMEM
VDDA1V8 +1V8
+3V3_VIP
LR1_L
LR1_R
+3V3_VIP
+3V3_VIP
3139-243-36835_130-05_a2.eps 2007-07-17

EN 118 3139 785 32804
Digital: Microcontroller+Reset ASP+RESET
13
12
11
10
7
INT0
INT1
TC2
DVO
TEST
V
K
K
V
D
D
V
A
R
E
F
14
13
12
11
10
9
8
23
16
21
20
19
18
17
P4<0:7>
AIN
P5<0:3>
PD<0:4>
V3
P6<0:7>
V
P7<0:7>
V
P8<0:7>
V
P9<0:7>
V
SO1
5
6
7
6
5
4
3
2
1
0
15
V
S
S
PDO
2
1
XTAL
P0<0:7>
PPG
PWM
TC4
TC1
SCK0
0
1
2
3
4
5
6
SI1
SCK1
RESET
V
A
S
S
INT3
INT2
INT4
INT5
XTIN
XTOUT
SCL
SDA
22
TC3
P1<0:7>
STOP
P2<0:2>
SI0
SO0
P3<0:2>
AIN
31
30
29
28
27
26
25
24
2
3
4
VCC
GND
NC RESET
F651 C9
to ANALOG BOARD
NC
F652 C9
F653 B8
F654 E9
F655 F9
F656 G8
F667 F9
c600 E8
F629 D2
F630 D2
F632 E2
F633 E2
F634 E2
F635 F2
F636 F2
F637 F2
F638 F2
F639 F2
F640 G2
F641 G2
F642 G2
F643 G2
F644 H2
F645 H2
NC
COMM_1 conn
GND
G_TXD
FAN_A
GND
F646 H2
F647 H2
F648 H2
F650 A8
F607 B2
F608 B2
F609 B2
F610 B2
F611 B2
F612 C2
F613 C2
F614 C2
F615 D2
F616 D2
F621 D2
F622 D2
F623 D2
F624 D2
F625 D2
*
to VIP
*
F626 D2
F627 D2
F628 D2
LOOP_THRU_ON
7601 C5
7602 E6
7603 E7
7604 B9
7606 D13
7607 H7
7608 A5
F601 H9
F602 C2
F603 C8
F604 B2
F605 B2
F606 B2
NC
to ANALOG BOARD
NC
KEY1
SCL_S3V3
IMUTE
NC
GND
NC
GND
4610 E5
4611 E5
4612 E5
4613 E5
4614 B3
4615 B3
4616 F12
4617 E13
5600 A7
6602 I8
6603 A7
6605 C6
7600 B7
NC
GND
GND
/ YC_REAR_ACTIVE
*
#
#
NC
3660 C9
3662 D13
3664 A4
3665 E12
3666 G13
3667 F8
3668 G14
4601 E3
4602 E2
4603 G12
4604 E4
4605 E3
4606 G3
4609 G2
P50_OUT
NC
from LECO
VIDEO_MUX3_SEL
from VIP
to VIP
NC
STBY
RC
3639 G12
3640 G12
3642 H3
3643 H3
3644 G6
3645 G7
3646 C11
3647 C12
3648 E7
3649 D8
3651 H8
3652 C6
3659 C9
FOR P50 and Gemstar EPG
NC
#
NC
*
TEMP_SENSE
GND
*
3623 E8
3624 F13
3625 F12
3626 F12
3628 F4
3629 F5
3630 F5
3631 F8
3632 G4
3633 G8
3634 G8
3635 G8
3636 G7
3637 G8
3638 G11
NC
NC
STDBY_LEDN
*
*
AUDIO_MUX1_SEL_A
3608 F8
3609 C12
3610 C12
3611 C12
3612 C12
3614 F8
3615 E8
3616 E8
3617 F6
3618 F6
3619 F5
3620 B6
3621 F12
3622 F12
GND
AUDIO_MUX3_SEL_C
GND
GND
*
8SC1 / AFC
GND
NC
REGION_SEL_A
2618 C6
2619 C8
3142 G11
3143 F13
3601 B7
3602 B5
3603 D8
3604 B6
3605 D9
3606 D6
3607 D7
Digital Optical in
NC
HD_ON
VFD_CLK
FOME
*
DIROUT
2605 B7
2606 E8
2607 F6
2608 F8
2609 F5
2610 G5
2611 G8
2613 G6
2614 A4
2616 I7
2617 I8
NC
NC
NC
GND
AMUX2_SEL
FBIN
YUV_ACTIVEN / YC_REAR_ACTIVE
NC
C
D
E
F
G
H
I
A
B
C
D
E
DISP_STBN
P50_IN
GND
WSRO
WU
to ANALOG BOARD NC
DISP_DATA
5 6 7 8 9 10 11 12 13 14
A
B
AUDIO_MUX3_SEL_D
REGION_SEL_B
NC
to ASP
from ASP
COMM_0 conn
3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4
*
DD_ON
G_RXD
COMM_2 conn
FBOUT
FAN_B
from ASP
*
NC
F
G
H
I
1600 E2
1601 G1
1602 I2
1603 B2
1604 E9
1605 C8
1606 G2
2601 B9
2602 B10
2603 B10
2604 B9
KEY2_3
*
GND
45
SDA_S3V3
SEL_KEY2_3
GND
NC
1 2
F644
NC
to FRONT BOARD
8SC2/WSRI
GND
NC
NC
DISP_CLK
68K
3635 1
0
n
2
6
1
0
3629
10K
100R
3630
F638
1
5
K
3
6
3
6
1
0
V
1
0
0
u 2
6
0
1
F633
6
6
0
5
7
8
9
B
A
T
5
4
C
O
L
10
11
12
13
14
2
3
4
5
6
1603
HLW14S-2C7-LF
1
3
6
2
0
1
0
K
F640
F639
4617
F601
F609
2
3
4
5
6
7
8
9
HLW14S-2C7
1601
1
10
11
12
13
14
470R
3604 2605
220n
4
6
0
5
3
6
0
1
1
0
K
7606
BC847BW
8
76
77
10
13
3
9
3
8
4
0
7
8
7
9
65
66
67
68
69
70
71
72
73
74
75
55
56
57
58
59
60
61
62
63
64
44
45
46
47
48
49
50
51
52
53
54
31
32
33
34
35
36
37
41
42
43
12
11
23
24
25
26
27
28
29
30
5
6
15
16
17
18
19
20
21
22
14
7604
79
80
1
2
3
4
MC
TMP87CH74F
F648
F608
1
%
1
0
K
3
6
2
8
F637
F625
F645
4
6
0
2
F615
F616
3605
F612
100R
F635
10K
3623
3648 100R
F614
4604
XASP
3644
47K
F643
3
1
4
2
2
2
K
4616
F629
F628
3
2
K
7
6
8
100R
1
6
0
4
3631
1
0
0
n
2
6
0
7
4613
4612
4611
XASP
1
0
0
n
2
6
0
9
2
K
2
3
6
1
9
PDTC124EU
7600
4603
2
K
2
3
6
1
7
BAT760
6603
100R 3634
F604
3660 100R
F626
6
6
0
2
B
A
T
5
4
C
O
L
4
7
0
p
2
6
1
7
F623
2
2
n
2
6
1
6
5
.5
V
2
2
0
m 2
6
0
2
60R
5600
BLM18P
F647
F646
F651
7602
BSN20
7601
PDTC124EU
1K0
3662
c600
3642 100R
XASP
F606
F653
3
6
5
1
4
K
7
F622
F621
F632
F650
3
4
5
6
F603
HLW6S-2C7 1606
1
2
F613
3633 1K0
4614
1% 910R
3664
3
6
0
2
F602
1
0
K
F627
15p
2608
4
K
7
3
6
2
4 F655
F605
F656
3
6
4
5
8
2
K
1
6
0
5
8
M
0
1
0
n
2
6
1
1
4609
6
7
8
9
10K
3649
1
2
3
4
5
1602
HLW9S-2C7
F641
3
6
6
6
4
7
K
4606
4601
2
6
0
3
1
0
0
n
F654
4
7
K
3
6
3
7
3618
100R
F624
F630
4K7 3667
2
22R 3608
3
4
5
1
7608
NCP301LSN
4
K
7
3
6
2
2
3665
1
0
n
2
6
1
9
10K
100R
3615
3
1
4
3
4
K
7
4610
4
K
7
3
6
0
9
4
K
7
3
6
4
6
3
6
4
7
4
K
7
F610
F611
2618
100n
F667
2
6
1
3
1
0
n
GND
3
INP
2
NC
4
OUTP
1
NCP303LSN29
7607
CD
5
15p
2606
3614 22R
1
M
0
3
6
3
2
1
0
0
n
2
6
1
4
470R 3616
F607
3
6
2
1
4
K
7
4
K
7
3
6
2
6
3
6
2
5
4
K
7
3
6
1
2
4
K
7
4
K
7
3
6
1
1
3
6
1
0
4
K
7
F636
F634
F652
100R 3659
2604
100n
4615
10K
3
6
3
9
3652
4
K
7
3
6
3
8
4
K
7
22K 3603
4
5
6
7
8
9
11
12
13
14
15
16
17
18
2
3
1600
HLW18S-2C7
1
10
4
K
7
3
6
6
8
1
0
K
3
6
0
6
7603
BSN20
4
K
7
1
0
K
3
6
0
7
3
6
4
0
100R 3643
AUDIO_MUX3_SEL_D
WSRO
IMUTE
FBOUT
FAN_B
FAN_A
LOOP_THRU_ON
VIDEO_MUX3_SEL
3V3STBY
F642
5VSTBY
HDMI_BE_CTRL VIP_RESET_GATE
AUDIO_MUX6_SEL
AUDIO_MUX5_SEL_B
AUDIO_MUX5_SEL_A
SPDIF_SW
AUDIO_MUX1_SEL_A
AUDIO_MUX2_SEL
YUV_ACTIVEN
AUDIO_MUX3_SEL_C
WU
YUV_ACTIVEN
TUNER_ON
PNX_SDA(0)
PNX_SDA(1)
PNX_SCL(0)
PNX_SCL(1)
PNX_PIO2_ASP_RST
VFD_CLK
PNX_PIO8_HD_ON
REGION_SEL_B
REGION_SEL_A
FBOUT
FBIN
AUDIO_MUX3_SEL_D
AUDIO_MUX1_SEL_A
VIDEO_MUX3_SEL
AUDIO_MUX3_SEL_C
AUDIO_MUX2_SEL
FOME_AFC
PNX_PIO29_IR_OUT
5VSTBY
WU
8SC1
5VSTBY
FAN_B
FAN_A
PNX_PIO27_DD_ON
STDBY
WSRO
SDA_S3V3
SCL_S3V3
LOOP_THRU_ON
IMUTE
8SC2_WSRI
P50_IN
STDBY
P50_OUT
DISP_CSN
5VSTBY
+3V3
+3V3
STDBY_LEDN
P50_OUT
P50_IN
PNX_UART_TXD(1)
PNX_UART_RXD(1)
FOME_AFC
FR_CIN
8SC2_WSRI
DISP_CLK
DISP_DATA
5VSTBY
REGION_SEL_B
REGION_SEL_A
8SC1
5VSTBY 3V3STBY 5VSTBY
PNX_PIO4_ASP_IRQ
RC
KEY1
5VSTBY
HDMI_CEC_INTn
KEY2_3
5VSTBY
TEMP_SENSE
5VSTBY
5VSTBY
5VSTBY
5VSTBY
5VSTBY 3V3STBY
3V3STBY
5VSTBY
DISP_CSN
VFD_CLK
3V3STBY
DISP_DATA
DISP_CLK
STDBY_LEDN
RC
TEMP_SENSE
KEY1
KEY2_3
+3V3
PNX_RESETN
JTAG_RSTN
+3V3
5VSTBY
3139-243-36835_130-06_a2.eps 2007-07-17

EN 119 3139 785 32804
Digital: Power Supply (PS)
GND
OUT IN
ADJ NC
GND
OUT IN
ADJ NC
NC
INH
ADJ
GND
OUT IN
F768 G10
F769 G10
F770 G10
F771 H10
F772 H10
F773 H10
F774 H10
F781 I10
F782 I10
F783 I10
F784 I10
F785 I10
F786 I10
F787 I10
F788 I10
DB_656(7)
+
I2C_DB_SDA
F748 E1
F751 H6
F753 H6
F754 H6
F755 H5
F760 F10
F761 F10 (+1.80V)
F763 F10
F764 F10
F765 G10
F766 G10
F767 G10
&
GND
GND
GND
NC
GND
GND
F732 B13
F733 C13
F734 C13
F736 C13
F737 C13
F738 C13
F739 C13
F780 H10
F741 D13
F742 D13
F743 D13
F744 D1
F747 D1
GND
OPTION ONLY
# APAC
*
NC / GND
GND
*
*
F711 C4
F712 D1
F713 C1
F714 E5
F715 E7
F716 F6
F720 A13
F721 A13
F722 A13
F723 B13
F724 B13
F762 F10
F726 B13
F728 B13
F729 B13
F730 B13
F731 B13
OPTION ONLY
7705 E6
*
*
*
5ND
GND
*
! For CEC HDMI
7706 H4
7707 H5
7710 C8
7711 C7
F700 C1
F701 D1
F702 D1
F703 D1
F740 C13
F705 E1
F706 E1
F707 A4
F709 A6
F710 B5
DB_656(5)
GND
5706 D3
&
& HTS
3V3STBY
5VSTBY
GND
3V3D
*
# For 7570 HDMI only
%
%
from ANALOG BOARD
5VD
F725 B13
*
5707 E2
5708 E4
5725 H8
5727 G8
7700 A5
7701 A4
7702 B4
4731 D13
3V3D
GND
GND
+
I2C_DB_SCL
To/From HDMI
12VD
4733 D12
4734 C11
4735 H5
4736 H5
4737 H5
4738 H5
4739 H6
F704 D1
4741 B2
4742 B1
4743 B2
5700 A3
5701 B3
5702 C3
5704 D3
5705 D2
3775 F13
NC
NC
DB_656(2)
GND
GND
GND
3776 F13
3777 D13
3778 D13
4710 A13
4714 D12
GND
4723 H10
4724 I10
4725 I10
4726 I9
4727 I10
4728 C9
4729 C7
4730 D13
3746 I9
DB_RXD
GND
GND
to ASP
!
3747 I9
3748 I9
3749 I9
3750 H9
3751 H9
3756 G9
3757 G9
3758 G9
3759 I9
3763-1 B8
3763-2 B8
4740 B1
3763-4 D7
3764 C8
3765 A13
3766 A13
3771 D13
3772 D13
3773 E13
3774 F13
3730 D11
+
*
NC
GND
*
DB_IN_HS
3731 D11
3738-1 F10
3738-2 F10
3738-3 F10
3738-4 F10
3739-1 G10
4722 G10
3739-3 F10
3739-4 F10
3740 G10
3741 G10
3742 G10
3743 H9
3744 H9
3745 H10
3714 F7
NC
DB_IN_VS
5V
GND
DB_656(1)
*
DB_RESETN
3715 G4
3716 G5
3717 D11
3720 D8
3721 D7
3763-3 D9
3723-1 C12
3723-2 C12
3723-3 C12
3723-4 C12
3724-1 D11
3724-2 C12
3724-3 D11
3724-4 D11
2720 D12
GND
*
GND
DB_656(4)
3115 H5
3116 H4
3141 B13
3700 A5
3701 A6
3702 A3
3739-2 G10
3704 A5
3705 B3
3706 B3
3707 B5
3708 C5
3709 C5
3712 F6
3713 F6
D
+ URD
+
OPTION ONLY
GND
To/From DTTM
GND
&
DVDR7570
1731 F11
1734 H10
1735 H11
2700 A4
2701 A6
3722 H5
2703 B4
2704 B5
2705 C3
2706 C4
2708 F6
2709 F7
2710 F5
2711 F6
12
+
(+2.5V)
% For ABT HDMI
GND / DB_RESETN
DB_656(6)
DB_656(3)
NC / GND
&
+
&
SCL_5V
13 14
A
B
C
3703 A3
E
F
G
H
I
A
B
C
13
3V3D
DB_CTS
NC
DB_RTS
(+1.20V)
GND
14
1 2
2702 A6
4 5 6 7 8 9 10 11
1728 E14
DB_TXD
&
GND
To/From DTTM
from EJTAG
1 2 3
D
5 6 7 8 9 10 11 12
to V_Buffer
DB_656_CLK
GND
+
+
SDA_5V
3V3D
DB_656(0)
E
F
G
H
3
3738-2
22R
I
1700 C1
1701 C2
1702 D2
1703 D1
1704 H6
1705 H6
1727 D14
4
F705
47R
3749
F725
F766
16 17
4722
13
14
15
2
3
4
5
6
7
8
9
15FMN-BMT-A-TFT
1734
1
10
11
12
4
7
1
4
22R 3774
F780
F762
10K
3756
1
0
K
3
7
1
5
22R
3741
3
7
5
1
1
0
0
K
3724-2 22R
1
2
F704
BSN20
7710
3
BLM18P
5725
60R
3748 47R
4740
F744
F736
F720
3773 22R 1
2
3
4
5
6
HLW6S-2C7
1728
5
6
7
8
9
1735
09FMN-BMT-A-TFT
1
2
3
4
4726
F742
38
39
4
40
5
6
7
8
9
28
29
3
30
31
32
33
34
35
36
37
19
2
20
21
22
23
24
25
26
27
1
10
11
12
13
14
15
16
17
18
40FLT-SM2-TB(LF)(SN)
1727
F730
F714
F768
3
7
1
3
2
7
0
0
4
7
0
n
3700
1K0 1%
F770
3740
22R
1
2
3
4
3758
B4B-PH-K
1704
10K
BLM31
5707
50R
1
R
0
3
7
0
8
2
7
1
06
.3
V
1
0
0
u
4725
3745
47R
MT3
3723-1 22R
F769
3141
4724
22R
3K3
3763-4
12
2
3
4
5
6
7
8
9
13 14
1700
B12B-PH-SM4-TBT(LF)
1
10
11
4737
BLM31
5708
50R
1
K
0
3
7
0
6
3778 22R
BSN20
7711
3
1
2
MT2
22R 3724-3
28
29
3
30
4
5
6
7
8
9
18
19
2
20
21
22
23
24
25
26
27
1
10
11
12
13
14
15
16
17
30FLT-SM2-TB(LF)(SN)
1731
MT1
3K3
3763-1
1
0
0
u
6
.3
V
2
7
0
9
F760
3765 22R
2
7
2
0
1
0
0
p
5
36
2
1
4
7705
NCP565D2TR4G
F710
F739
F754
F753
F722
MT4
4742
3775 22R
2
7
0
2
1
0
0
n
F721
4710
BLM31
5701
50R
F734
F729
22R
3739-2
22R 3723-2
F784
3739-1
22R
F737
5
K
1
1
%
F728
3
7
1
2
7706
BSN20
2
7
0
4
1
0
0
u
6
.3
V
F741
F726
F774
4741
F764
1
0
K
3
7
0
3
F751
F767
F740
2
7
0
62
5
V
1
0
u
22R 3772
50R
5700
BLM31
F747
F738
22R
3743
F781
3714
5K1 1%
3
7
1
6
1
0
K
3763-3
3K3
F716
22R 3724-4
33R
3701
2.0A F
1701
F748
1
K
0 3
7
0
41
%
2
7
1
12
5
V
1
0
u
F731
22R
3738-1
F763
4736
4
7
2
9
4
7
3
9
F700
22R 3777
3
7
2
1
2
2
R
BLM31
5702
50R
3717 10K
22R 3776
F755
4743
F772
6
0
R
5
7
2
7
B
L
M
1
8
P
22R 3723-4
3739-3
22R
F786
BSN20
7707
3744
22R
1
5
K
3
7
0
5
3K3
4
7
3
0
3763-2
F783
F724
F743
50R
5704
BLM31
2
7
0
16
.3
V
4
7
u
F733
4
5
1% 8K2
3709
1
2
3
1705
B5B-PH-K
10K
3722
F761
F703
22R
3738-3
F782
F785
3723-3 22R
1
0
0
u 2
7
0
56
.3
V
BC847B
7701
F713
F712
60R
5705
BLM18P
3
7
6
4
1
K
0
22R
3739-4
2
7
0
3
6
p
8
F771
22R 3115 3116 22R
22R 3766
3742
22R
F765
4727
F711
1
0
0
K
3
7
5
0
F701
36
2
1
4
7702
NCP565D2TR4G
5
3738-4
22R
4734
47R 3746
4K7
3759
3757
10K
1
%
2
K
7 3
7
0
7
F715
F707
60R
BLM18P
5706
F702
4735
F787
F706
22R 3730
3
7
0
2
2
2
K
2
7
0
8
6
p
8
3747 47R
F788
F773
1A F
1702
LD29150PT
7700
5
3
2
1
4
F732
4
7
3
1
4
7
3
8
F723
22R 3724-1
4
7
3
3
10K 3731
22R 3771
2
3
4723
B3B-PH-K
1703
1
4
7
2
8
3
7
2
0
F709
2
2
R
3V3STBY
3V3STBY
+3V3
3V3_DTT1
+3V3_VIP
+3V3
+3V3
+3V3 +3V3
+3V3
PSCAN_RESETN
+3V3
+3V3
ITU_OUT_HSYNC
SCL_ABT
SDA_ABT
ITU_OUT_VSYNC
HTS_IRQN
PNX_SCL(1)
PNX_SDA(1)
+5V
+5V
PNX_PIO25_HDMI_RSTN
HDMI_BE_CTRL
HDMI_CEC_INTn
ITU_OUT_VSYNC
+5V
PNX_SCL(0)
PNX_SDA(0)
PNX_SCL(1)
+3V3
+5V
+3V3
+5V
HDMI_SDA(1)
HDMI_SCL(1)
{HDMI_SCL(1),HDMI_SDA(1)}
HDMI_SDA(1)
HDMI_SCL(1)
PNX_SDA(1)
HDMI_CEC_INTn
PNX_FSCLK_OUT
ITU_OUT_HSYNC
PNX_PIO7_SPDIF2_IN
3V3_DTT
+3V3
PNX_PIO13_DTT_RTS_1
PNX_UART_TXD(1)
PNX_UART_RXD(1)
PNX_PIO14_DTT_CTS_1
PNX_ITU_OUT(0)
PNX_ITU_OUT(7:0)
{HDMI_SCL(1),HDMI_SDA(1),PNX_SCL(1),PNX_SDA(1)}
ITU_OUT_CLK
PNX_SCK_OUT
PNX_SD_OUT
PNX_SPDIF_OUT
PNX_WS_OUT
PNX_PIO10_HDMI_IRQ
PNX_SDA(1)
PNX_SCL(1)
DTT_RESETN
3V3_DTT
3V3_DTT1
PNX_ITU_OUT(7)
PNX_ITU_OUT(6)
PNX_ITU_OUT(5)
PNX_ITU_OUT(4)
PNX_ITU_OUT(3)
PNX_ITU_OUT(2)
PNX_ITU_OUT(1)
5VSTBY
5NV
+1V8
{VIP_ITU0_IN(2:9),VIP_ITU0_IN_CLK,VIP_ITU0_IN_VAL,VIP_ITU0_IN_SOP,VIP_ITU0_IN_LOCK}
VIP_ITU0_IN(2)
VIP_ITU0_IN(3)
VIP_ITU0_IN(4)
VIP_ITU0_IN(5)
VIP_ITU0_IN(6)
VIP_ITU0_IN(7)
VIP_ITU0_IN(8)
VIP_ITU0_IN(9)
VIP_ITU0_IN_CLK
VIP_ITU0_IN_VAL
VIP_ITU0_IN_SOP
VIP_ITU0_IN_LOCK
+1V2
+VDDR
+1V2
+3V3
+12V
+5V
3139-243-36835_130-07_a2.eps 2007-07-17

EN 120 3139 785 32804
Digital: External ADC
EN
EN
G4
0
3
2
VDD
VEE VSS
1
0
3
2
1
4X
0
3
0
1
DATAO
BCK
WS
VSSA VSSD
VDDD
VINR
SFOR
VINL
MSSEL
VREF
VRN
VDDA VRP
SYSCLK
PWON
COM
OUT IN
F830 A6
3805 C2
3806 C2
3807 D1
3808 D2
3809 D2
3810 D4
3811 C4
3812 D5
3813 C5
3814 B6
3815 C6
3816 D6
3817 C8
3818 C8
3819 D8
3820 C6
3823 E8
4802 D9
4803 D6
4804 E7
5801 B9
5802 A3
5803 A4
7800 C3
7801-1 D4
7801-2 C4
7803 A6
7804 C7
7805 E8
7806 E9
7807 C9
A
B
C
D
E
2814 D6
2815 D6
2816 C6
2817 C6
2818 C7
2819 D3
3804 C1
3 4 5 6 7 8 9 10
A
B
C
D
E
F
1 2 3 4 5 6 7 8 9 10
1 2
2800 B1
2801 B1
2802 C1
2803 C1
2804 D1
2805 D1
2806 B3
2807 A7
2808 A3
2809 A4
2810 C4
2811 C4
2812 D5
2813 C5
G
N
D
F
A
3V3SW
1u0
2801
1
0
0
K
3
8
0
7
3819 22R
1
R
0
3
8
1
4
3
8
0
5
1
0
0
K
3812
10K
5NV_MUX
+5V
10K
3813
A
GND
1
0
0
K
3
8
0
4
6
.3
V
2
8
1
6
4
7
u
PDTC124EU
7805
GND
F830
100n
2819
2800
1u0
1
0
0
n
1K0
3810
2
8
1
4
5V_MUX
1u0
2803
BLM18P
5802
60R
BLM18P
5801
60R
4
7
u
6
.3
V6
.3
V
4
7
u 2
8
0
9
2
8
0
8
15
2
11
4
13
3
5NV
10
9
6
1
6
78
12
1
14
5
4
7800
HEF4052B
MDX
7806
74LVC1G125GW
2
3
1
5
2
3
1
5
4
74LVC1G125GW
7807
4
8
0
3
5V_MUX
3V3SW
4804
100n
2818
3817
3V3SW
22R
6.3V 47u
2813
5NV_MUX
P
N
X
_
S
D
0
_
IN
3
8
1
5
4
7
K
47K
3816
G
N
D
1u0
2802
1
3
2
4
5
1
5
1
0
12
11
13
14
7
6
8
1
6
9
7804
UDA1361TS
ADC
24-BIT AUDIO
60R
5803
BLM18P
A A
1
0
0
K
3
8
0
6
1K0
3811
4K7
2806
100n
3823
3
2
1
8
4
7
8
4
7801-1
LM833D
LM833D
7801-2
5
6
2804
1u0
A A
A
4802
6.3V
3
2812
47u
7803
MC78FC33H
1
2
A
5VSTBY
5NV_MUX
1
0
0
n
2
8
1
7
5NV_MUX
5V_MUX
1
0
0
K
3
8
0
9
2810
100n
3
8
0
8
1
0
0
K
3V3SW
5V_MUX
100n
2811
22R 3818
6
.3
V
2
8
1
5
4
7
u
2
8
0
7
3
3
0
u
1
6
V
1u0
2805
3820
22R
VIP_SD0_OUT
AUDIO_MUX6_SEL
AUDIO_MUX6_SEL
+3V3_MUX
AUDIO_MUX5_SEL_B
+3V3_MUX
+3V3_MUX
PNX_WS0_IN
+5V
+3V3
PNX_FSCLK_IN
PNX_SCK0_IN
AUDIO_MUX5_SEL_A
AIN1R
ADC_SD0_OUT
AINFR
AIN1L
AIN2L
AINFL
AIN2R
3139-243-36835_130-08_a3.eps 2007-07-17

EN 121 3139 785 32804
Layout: Digital Top View
Digital Board Top View 3139 243 36835_132_a3.eps 2008-02-21

EN 122 3139 785 32804
Layout: Digital Bottom View
Digital Board bot View 3139 243 36835_132_a3.eps_2008-02-21

EN 123 3139 785 32804
HDMI: FAROUDJA
10
16
17
0
10
15
SDRAM_BA1
SDRAM_BA0
SDRAM_CSN
SDRAM_DQM
SDRAM_CLKOUT
26
25
1
0
SDRAM_WEN
SDRAM_RASN
SDRAM_CASN
24
27
28
29
30
31
SDRAM_DATA
19
20
21
22
23
3
4
5
6
7
8
9
SDRAM_ADDR
SDRAM_CLKIN
18
1
2
9
8
7
6
5
4
3
2
11
12
13
14
EN
14
17
18
19
20
16
15
3
4
5
28
27
26
25
24
23
22
1
VDD
0
2
8
7
6
VDDQ
VSS VSSQ
NC
BA
2k-1
0
A
D
DQM
13
12
11
10
9
8
7
6
5
4
3
2
1
0
9
10
21
0
1
CLK
CKE
CS
WE
CAS
RAS
0
1
2
3
31
30
29
COM
OUT IN
6
7
0
1
2
3
4
5
6
7
0
1
2
3
6
5
4
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
2
1
3
4
5
6
7 7
0
1
2
3
4
5
VSS
8
7
6
5
2
1
1
2
3
4
5
6
8
7
6
10
11
12
13
14
6
1
2
1
R_VDD
R_VSS
5
6
7
VDD
VDDCORE
8
7
8
9
4
3
2
1
9
15
16
17
5
4
3
2
1
2
3
4
5
2
3
4
1
DEV_ADDR0
DEV_ADDR1
CTLOUT
TEST_IN
1
2
3
0
0
3
2
1
SDATA
CLKOUT
0
1
TEST
3
4
6
D1_IN
2
5
4
3
2
1
IN_SEL
TEST_OUT0
TEST_OUT1
SCLK
4
7
6
5
OE
RESET_N
RESERVED
TEST
D
E
F
G
H
I
A
1911 F14
not used
1 2 3 4 5 6 7 8 9 10 11
HDMI
A
B
C
10
B
C
D
E
F
G
H
I
0005 I8
1100 D13
1101 E13
1102 E13
13
12 13 14
1 2 3 4 5 6 7 8 9 14 11 12
2113 F7
SDRAM
2114 F7
2115 F7
2116 F7
2117 H5
2118 H5
2119 H6
2120 H6
2121 H6
2122 H6
2123 H7
2124 H7
2141 F10
2142 H8
2143 H8
2144 H9
2145 H9
2100 B11
2101 B11
2102 B12
2103 B12
2106 F5
2107 F5
2108 F6
2109 F6
2110 F6
2111 F6
2112 F7
3100 D1
not used
not used
not used
3101 D1
3102 A14
3103 D1
3104 A14
3105 A6
3106 C1
2125 H7
2126 H7
2127 H2
2132 F8
2133 F8
2134 F8
2135 F8
2136 F9
2137 F9
2138 F9
2139 F9
2140 F10
3119 C1
CONTROL BUS
3120 B14
3121 B6
3122 D1
3123 B14
3124 B6
3125 D1
2146 H9
2147 H9
2148 H10
2150 I13
2151 I5
2152 I6
2153 I7
2154 H13
2155 E12
2156 E12
2157 E12
2158 F13
3135 F12
DATA BUS
not used
not used
3136 B6
3137 E1
3139 B6
3140 E1
3142 C6
3143 E1
3144 C14
3145 B1
3146 C14
3147 A1
3148-1 G13
3148-2 G13
3148-3 G13
3107 A14
3108 A6
3109 C1
3110 A14
3111 A6
3112 C1
3113 A9
3114 A14
3115 A6
3116 C1
3117 A14
3118 A6
3163 A1
ADDRESS BUS
3164-1 H13
3164-2 G13
3164-3 G13
3164-4 G13
3165 D14
3166 D5
3167 A1
3169 D14
3170 A1
3172 D14
3173 B1
3126 B14
3127 B6
3128 D1
3129 B14
3130 B6
3131 D1
3132-1 C14
3132-2 B14
3132-3 B14
3132-4 B14
3133 B6
3134 E1
3187 G1
3148-4 G13
3149 C14
3150 C5
3151 A1
3153 C14
3154 C6
3155 A1
3157 C14
3158 C5
3159 A1
3161 C14
3162 C6
7100-4 A12
7102 F12
7103 D5
7104 I6
F100 B12
F101 D13
F1017 H1
F102 E13
F103 E13
F104 D12
F105 E14
F106 E12
F108 E12
F109 F6
F110 E12
F1103 I14
3175 D14
3176 B1
3177 B1
3178 B1
3179 B1
3180 B1
3181 C1
3182 C1
3183 F1
3184 F1
3185 H12
3186 G1
F1124 G14
not used
not used
FAROUDJA SDRAM
F1125 G14
F1127 G14
F1128 H14
F1129 G14
F113 H6
F1131 G14
F1133 G14
F1135 G14
F1137 F14
F1139 F14
F114 H2
4101 E13
4103 E13
5100 B12
5101 F5
5102 H5
5104 H8
5105 D13
5106 E13
5107 E13
7100-1 F2
7100-2 A11
7100-3 A8
F1105 I14
F1107 I14
F1109 H14
F111 G4
F1113 H14
F1115 H14
F1117 H14
F1118 H14
F1119 H14
F112 G4
F1121 H14
F1123 G14
3203 I2
3204 I12
3206 H13
3207 G4
3208 G4
3209 H4
3210 H12
3211 A9
F1140 F14
F115 F12
F116 H8
F117 I7
SW01 I9
SW02 I9
SW03 I10
3188 G2
3190 H2
3193 H4
3195 H4
3196 H13
3197 H13
3198 F12
3199 F13
3200 H12
3201 I13
3202 F12
not used
not used
4100 D13
3
5
V
4
u
7 2
1
4
2
F1128
2
1
2
3
1
0
0
n
3137
10R
3210
22R
2
1
2
0
1
0
0
n
4
K
7
3
1
8
3
58
59
110
105
104
83
84
85
53
86
87
54
55
56
57
71
72
73
52
74
75
76
77
78
79
82
111
109
50
51
60
61
64
65
66
67
70
99
98
95
94
93
92
108
107
106
114
FLI2310-LF-BD
SDRAM
7100-3
103
102
91
101
100
3101
10R
5
1
0
0
B
L
M
1
8
P
2
1
0
7
1
0
0
n
1
0
0
n
2
1
3
5
2
1
1
1
1
0
0
n
22R
3199
F115
+3V3
47R
3135
2
3
1
5
4
74LVC1G125GW
7102
1
0
0
n
2
1
1
0
F1125
3102
47R
22R
3148-4
F116
4103
100n
2158
1
0
0
n
2
1
4
1
2
1
1
3
1
0
0
n
1
0
0
n
2
1
3
3
3169
47R
BLM31
5107
3131
10R
10R
3128
1
0
0
n
2
1
3
7
2
1
2
2
1
0
0
n
10R
3162
F1118
1
0
0
n
2
1
1
2
2
1
1
5
1
0
0
n
1
0
0
p
2
1
5
0
2
1
0
9
1
0
0
n
10R
3116
3178
10R
F106
3
1
8
7
4
K
7
2
1
4
4
1
0
0
n
F1140
+5V
F1115
1V8D
3167
F1103
10R
10R
3143
3139
10R
2
1
2
6
1
0
0
n
1
V
8
D
SW01
10R
3180
22R
3164-2
BLM18P
5105
5106
BLM18P
F102
B
L
M
1
8
P
F113
10R
3154
5
1
0
2
F1107
F1113
4K7
3190
3104
47R
3
1
8
6
10R
3155
4
K
7
F105
F1124
2
1
5
2
3100
1
0
0
n
10R
52 78 84
17
3179
10R
81
44 58 72 86 6 12 32 38 46
15 29 43 3 9 35 41 49 55 75
28
59
14
21
30
57
69
70
73
19
1
7
54
56
8
10
11
13
74
76
16
71
37
39
40
42
45
47
48
50
51
53
77
79
80
82
83
85
31
33
34
36
5
64
65
66
22
23
18
67
68
20
2
4
25
26
24
27
60
61
62
63
7103
MT48LC2M32B2P
SDRAM
2M x 32
47R
3172
F109
4101
1V8D
3182
1
0
0
n
2
1
1
6
10R
2
1
3
2
4
u
7
3
5
V
F111
2
1
1
8
1
0
0
n
F1123
2
1
3
6
1
0
0
n
4
7
u 2
1
5
3
2
1
1
9
6
.3
V
F1119
1
0
0
n
10R
3145
10R
3159
10R
3158
F1109
0005
BRACKET
2
1
4
7
1
0
0
n
F1133
+3V3
10R
3122
1
0
0
n
2
1
0
3
3151
10R
3147 10R
3109
10R
10R
3181
3125
3
V
3
D
22R
10R
3206
10R
1
0
0
n
2
1
0
2
F1127
3133
3V3D
F1129
2
1
5
7
1
0
0
n
10R
3119
2
1 3
7104
LF18ABDT
3204
22R
2
1
2
4
1
0
0
n
2
1
3
4
1
0
0
n
3127
10R
3V3D
F
1
0
0
4
K
7
3
1
8
4
1
0
0
n
2
1
0
8
3140
10R
+1V8
2154
100n
1
0
0
n
2
1
5
5
3208 100R
3207 100R
F1105
1R0 3113
3123
47R
3124
10R
F103
10R
3111
3108
10R
1
n
0
2
1
2
7
F1135
10R
3112
3177
10R
22R
3202
22R 3198
3175
47R
F112
47R
3149
47R
3126
47R
3117
47R
3165
2
1
3
9
+3V3
2
1
4
0
1
0
0
n
1
0
0
n
3110
47R
F104
R_VDD
3105
10R
22R
3148-3
F1137
F114
3209
100R
1
0
0
n
+1V8
2
1
0
1
1
0
0
n
2
1
5
6
22R
3148-2
F1131
10R
3106
200mA
1100
3161
47R
22R
3164-4 22R
3148-1
3V3D
F1121
1K5 3132-4
3188
10R
47R
3144
3195 10R
3193
10R
1
0
0
n
2
1
4
5
F117
3103
1
0
0
n
2
1
5
1
10R
10R
3121
3
5
V
2
1
1
7
4
u
7
350mA
1101
3153
47R
SW02
3170
10R
47R
3120
140
141
142
143
144
145
155
21
22
23
24
25
26
27
28
136
137
38
39
40
148
149
150
151
152
153
154
131
132
133
134
135
29
32
33
34
35
11
12
13
14
15
18
19
20
126
127
130
7100-4
FLI2310-LF-BD
VIDEO
10R
3150
2
1
1
4
1
0
0
n
2
1
4
8
1
0
u
+3V3
1
6
V
3132-1 1K5
47R
3157
F1017
41 42
3176
10R
36
37
38
39
4
40
5
6
7
8
9
26
27
28
29
3
30
31
32
33
34
35
17
18
19
2
20
21
22
23
24
25
1911
40FLZ-RSM2-R-TB(LF)(SN)
1
10
11
12
13
14
15
16
4100
47R
3114
3166
10R
2
1
0
0
4
u
7
3
5
V
3173
10R
F110
1
0
0
n
2
1
4
6
2
1
4
3
1
0
0
n
10R
47R
3107
F1139
3130
1
0
0
n
2
1
2
5
3134
10R
3200
22R
F1117
22R
3164-1
22R
3196
F101
47R
+3V3
3129
10R
3142
+12V
F108
22R
3201
3211 1R0
69
81
89
129
139
147
194
198
17
31
37
49
63
36
68
80
96
123
138
197
9
97
113
124
8
30
48
62
88
112
128
146
193
16
177
186
187
184
172
175
178
185
167
169
182
166
163
159
162
157 158
183
168
171
174
P
O
W
E
R
P
L
L
R
E
S
E
R
V
E
D
FLI2310-LF-BD
165
164
160
161
3V3D
7100-2
B
L
M
1
8
P
5
1
0
4
3132-2 1K5
SW03
3136
10R
1
0
0
n
2
1
2
1
22R
3185
3203
3132-3
10R
1K5
1102
1.5A T
2
1
3
8
1
0
0
n
47R
192
3146
188
189
190
115
90
116
117
2
6
207
191
181
180
176
173
179
170
47
45
46
42
43
3
7
206
1
5
208
4
10
41
156
122
196
199
200
201
202
203
204
205
44
FLI2310-LF-BD
MISC
125
195
118
119
120
121
3118
7100-1
10R
3115
10R
5
1
0
1
B
L
M
3
1
5
0
R
2
1
0
63
5
V
4
u
7
22R
3164-3
22R
3197
VO_CLK
3163
10R
SCL0
SCL0
S
C
L
0
S
D
A
0
SDA0
SDRAM_CLK_F
+1V8
R_VDD R_VDD
PSCAN_RSTn
HDMI_RSTn
D_DATA(22)
D_DATA(21)
D_DATA(20)
D_DATA(19)
D_DATA(18)
D_DATA(17)
D_DATA(31:0)
D
_
D
A
T
A
(3
1
:0
)
D_DATA(16)
D_DATA(7)
P_HSYNC
P_VSYNC
P_CLK
SPDIF_OUT
ITU_OUT(6)
ITU_OUT(5)
ITU_OUT(4)
ITU_OUT(3)
ITU_OUT(2)
ITU_OUT(1)
ITU_OUT(0)
ITU_OUT_2(0:7)
P
S
C
A
N
_
R
S
T
n
PSCAN_RSTn
FSCLK12_OUT
SCK12_OUT
SD_OUT
WS12_OUT
DQM_F
WEN_F
VO_CLK_2
ITU_OUT(7)
CbCr(2)
CbCr(3)
C
b
C
r(2
:1
1
)
Y
(2
:1
1
)
CbCr(4)
CbCr(5)
CbCr(6)
CbCr(7)
CbCr(8)
CbCr(9)
CbCr(10)
CbCr(11)
Y(2)
Y(3)
Y(4)
Y(5)
Y(6)
Y(7)
Y(8)
Y(9)
Y(10)
Y(11)
D_DATA(14)
D_DATA(15)
D_DATA(16)
D_DATA(17)
D_DATA(18)
D_DATA(19)
D_DATA(2)
D_DATA(20)
D_DATA(21)
D_DATA(22)
D_DATA(23)
D_DATA(24)
D_DATA(25)
D_DATA(26)
D_DATA(27)
D_DATA(28)
D_DATA(29)
D_DATA(3)
D_DATA(30)
D_DATA(31)
D_DATA(4)
D_DATA(5)
D_DATA(6)
D_DATA(7)
D_DATA(8)
D_DATA(9)
DQM_F
INT_HDMI
ITU_OUT_2(6)
ITU_OUT_2(7)
A_ADDR(0)
A_ADDR(1)
A_ADDR(10)
A_ADDR(2)
A_ADDR(3)
A_ADDR(4)
A_ADDR(5)
A_ADDR(6)
A_ADDR(7)
A_ADDR(8)
A_ADDR(9)
D_DATA(0)
D_DATA(1)
D_DATA(10)
D_DATA(11)
D_DATA(12)
D_DATA(13)
SDRAM_CLK_F
CSN_F
CASN_F
RASN_F
BA0_F
BA1_F
CSN_F
WEN_F
RASN_F
CASN_F
BA0_F
BA1_F
ITU_OUT_2(0)
ITU_OUT_2(1)
ITU_OUT_2(2)
ITU_OUT_2(3)
ITU_OUT_2(4)
ITU_OUT_2(5)
D_DATA(4)
D_DATA(5)
D_DATA(6)
D_DATA(8)
D_DATA(9)
D_DATA(10)
D_DATA(11)
D_DATA(12)
D_DATA(13)
D_DATA(14)
D_DATA(15)
D_DATA(23)
D_DATA(24)
D_DATA(25)
D_DATA(26)
D_DATA(27)
D_DATA(28)
D_DATA(29)
D_DATA(30)
D_DATA(31)
R_VDD
SDA0
A_ADDR(0)
A_ADDR(1)
A_ADDR(2)
A_ADDR(3)
A_ADDR(4)
A_ADDR(5)
A_ADDR(6)
A_ADDR(7)
A_ADDR(8)
A_ADDR(9)
A_ADDR(10)
D_DATA(0)
D_DATA(1)
D_DATA(2)
D_DATA(3)
HDMI Columbus at CR 3139-243-32736-130_1.pdf 2006-02-17

EN 124 3139 785 32804
HDMI: PROG SCAN DAC
COM
OUT IN
RSET1
ALSB
I2C
SDA
6
7
EXT_LF
VAA
SCLK
CLKIN_B
8
9
8
9
8
9
7
0
1
S
C
Y
S_VSYNC
S_HSYNC
COMP2
COMP1
AGND
0
2
1
RSET2
RTC_SCR_TR
VDD VDD_IO
DAC
GND_IO DGND
6
VREF
3
4
5
2
3
4
5
6
7
0
1
2
3
4
5
CLKIN_A
F
E
D
C
B
A
RESET
P_BLANK
P_VSYNC
P_HSYNC
S_BLANK
A
B
C
D
E
F
G
H
I
1920 E13
1921-1 E12
1921-2 G12
2 3 4 5 6 7 8
1921-3 H12
2250 A6
2251 A7
2252 G4
2253 A9
2254 A10
2255 A2
2256 C3
2258 A1
2259 A2
2260 B3
2261 B3
2262 B3
2263 B3
2266 C2
2267 C4
2268 C2
1 2 3 4 5 6 7 8 9 10 11 12 13
1
n
o
t u
s
e
d
2285 D9
2286 D10
2290 F8
9 10 11 12 13
A
B
C
D
E
F
G
H
I
not used
PB
PR
Not used
2269 D2
2270 D4
2271 D4
2272 D4
2273 D2
2274 D4
2275 D6
2276 D11
2277 F11
2278 H11
2280 G2
2281 G2
2282 F5
2284 D8
GND
Y
3269 F8
2291 F9
2292 F10
2296 H8
2297 H9
3255 D8
3256 F8
3257 H8
3258 D8
3259 D6
3260 D5
3261 D5
3262 D6
3263 D5
3264 D5
A
N
A
L
O
G
B
O
A
R
D
n
o
t u
s
e
d
Not used
3284 H5
3285 H5
3286 H5
3287 H9
3288 H11
3265 D9
3266 D11
3267 D10
3268 E10
GND
GND
3270 F9
3271 D9
3272 F11
3273 F10
3274 E6
3275 G2
3276 G6
3277 G6
3278 E6
3279 F10
3280 H8
3281 G5
3282 G5
3283 G5
Not used
n
o
t u
s
e
d
GND
7252-2 H10
7253 D3
F2001 F12
F2002 F12
F2004 F12
F2006 F12
F201 C3
3289 H10
3290 H10
3291 E11
3292 F11
3293 H11
3294 F9
3295 H9
4250 G6
4251 A2
4252 F5
4253 F5
4254 D12
4255 F12
4256 H12
5250 A7
5251 A10
5253 A2
5254 D9
5255 D9
5256 F9
5257 F9
5258 H9
5259 H9
6251 E11
6252 G11
6253 I11
7250 A1
7251 D10
7252-1 F10
2
2
8
4
2
2
p
F202 C3
F203 D3
F204 A9
F205 A12
N
o
t u
s
e
d
N
o
t u
s
e
d
N
o
t u
s
e
d
3n9
2280
2292
100n
2
2
9
7
2
2
p
2u2
5259
F203
1
0
0
n
2
2
5
2
F205
2
2
7
8
2
2
0
u
4
V
1
K
2
3
2
7
1
3
2
6
7
1
K
2
1
0
0
n
2
2
5
8
F204
F2001
3272
75R 1%
1% 2K7
3284
1% 75R
3266
3
2
6
1
1
0
K
1
0
K
3
2
6
0
2
2
7
2
1
0
0
n
10R
3282
2
2
9
1
1
K
2
3
2
5
7
2
2
p
2
2
8
5
2
2
p
3
2
9
4
1
K
2
3278
10R
3
2
7
6
4
K
7
1
0
0
n
2
2
5
3
3
2
5
6
1
K
2
4u7
5258
100n
B
Z
X
3
8
4
-C
4
V
7
6
2
5
1
2274
2
2
9
6
2
2
p
2268
1n0
3
5
V
4
u
7 2
2
5
9
4252
1%
10R
1
%
3283
330R
3
2
9
3
7
5
R
2
2
7
5
5257
2u2
1
n
0
100n
2261
1
0
K
3
2
6
4
F
2
0
1
3
2
6
5
1
K
2
3
2
7
7
4
K
7
4
2
5
4
1
0
K
3
2
6
3
6
7
1920
1
2
3
4
5
PSCAN
07FMN-BMT-A-TFT
2281
1n0
2270
2
2
7
6
2
2
0
u
4
V
820p
2
2
7
7
2
2
0
u
4
V
1% 75R
3288
1
%
7
5
R
3
2
9
2
2
1 3
7250
LF25CDT
4u7
5254
3
2
5
5
1
K
2
2u2
5255
1
6
V
4
7
u 2
2
5
1
2
2
p
2
2
9
0
3274
10R
100n
2286
F
2
0
2
2273
100n
4
2
5
6
F2006
4
2
5
5
F2004
5
2
F2002
7251
AD8091ART
3
4
1
3
2
7
3
1
K
2
2
2
R
3
2
5
9
BLM21
5250
1
K
2
3
2
5
8
2
2
5
0
1
0
0
n
4
2
5
0
B
Z
X
3
8
4
-C
4
V
7
3
2
9
1
7
5
R
1
%
6
2
5
2
B
Z
X
3
8
4
-C
4
V
7
6
2
5
3
5256
4u7
2
2
8
2
1
5
p
3285
10R
7
8
4
1
K
2
3
2
8
0
AD8092AR
7252-2
5
6
1
0
0
n
2
2
5
5
10n
2267
100n
4253
2269
3
2
8
7
1
K
2
1
K
2
3
2
6
9
4
u
7
2
2
5
4
16V 47u
2266
2
2
7
1
1
0
0
n
3275
680R
1
K
2
3
2
9
0
330R
3286
3
2
6
8
1%
1
K
2
2256
10n
2263
100n
4251
100n
2262
1
K
2
3
2
7
0
3
2
7
9
1
K
2
1%
5253
3281
2K7
3
2
6
2
4
7
K
7252-1
AD8092AR
3
2
1
8
4
2260
4V 220u
9
12
13
3
2
8
9
1
K
2
5
6
1
46
2
3
4
5
6
7
8
59
60
61
62
22
21
48
50
49
4
1
1
0
33
47
35
31
51
52
53
54
55
58
38
37
1
1
5
7
34
6
4
19
25
23
24
29
30 32
63
45
36
44
43
42
39
4
0
20
14
15
16
17
18
26
27
28
VIDEO
ADV7320KSTZ
7253
ENCODER
4u7
5251
1
K
2
3
2
9
5
YKC21-3930
YELLOW
1921-1
2
1
YKC21-3930
RED
1921-3
6
5
YKC21-3930
WHITE
1921-2
4
3
VO_CLK
+5V_PS
+5V_PS
ITU_OUT(5)
ITU_OUT(6)
ITU_OUT(7)
P_CLK
+5V_PS
+2V5
+3V3D_VDAC
+5V_PS
+2V5 +2V5 +2V5
+3V3
ITU_OUT(0:7)
ITU_OUT(0)
ITU_OUT(1)
ITU_OUT(2)
ITU_OUT(3)
ITU_OUT(4)
+5V
CbCr(3)
CbCr(5)
CbCr(7)
CbCr(9)
CbCr(11)
+3V3D_VDAC
P_HSYNC
P_VSYNC
CbCr(2:11)
Y(2:11)
P
S
C
A
N
_
R
S
T
n
+3V3D_VDAC
+3V3D_VDAC
+2V5 +2V5
Y(6)
Y(2)
Y(4)
Y(8)
Y(10)
CbCr(2)
CbCr(4)
CbCr(6)
CbCr(8)
CbCr(10)
Y(3)
Y(5)
Y(7)
Y(9)
Y(11)
+3V3
SDA0
SCL0
+2V5
+2V5

EN 125 3139 785 32804
HDMI: HDMI Tx
V VV
V V
IN OUT
ADJ
NC
VOUT INHIBIT
GND
VIN
VCC
GND
VCC2
ACC
SCL
SDA
SCL
SDA
OUT IN
G
N
D
_
H
S
14
15
16
17
18
19
20
21
22
23
HSYNC
VSYNC
DE
SPDIF
MCLK
CVCC18 IOVCC PVCC
AGND CGND IOGND PGND
D
AVCC
8
7
12
13
CSDA
CSCL
CI2CA
RESET
IDCK
0
1
2
3
4
5
6
NC
DSDA
DSCL
INT
HPD
EXT_SWING
TXC+
TXC-
TX0+
TX0-
TX1+
TX1-
TX2+
TX2-
RSVDL
VIA
SCK
WS
SD0
SD1
SD2
SD3
11
10
9
V
VV
not used
BLM18A
I
1300 H12
1930 A13
1931 I5
2300 A1
2301 A2
2302 A3
2303 A3
2306 B5
2307 B5
2308 B6
2309 B6
2310 B3
2311 B3
2312 B3
2314 A5
2315 A5
2316 A6
2317 D13
2318 C1
2319 C1
2320 C2
2321 C2
2322 C2
2323 C3
1 2 3 4 5 6
n
o
t u
sed2304 A3
7 8 9 10 11 12 13
1 2 3 4 5 6 7 8
n
o
t u
sed
9 10 11 12
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
G
H
2324 D6
2325 I4
2326 H11
2327 I11
2328 I12
2330 B1
2333 B11
2334 B9
3300 E10
3301 E10
3302 E10
3303 E10
3304 E10
3305 A2
3306 E10
3307 E10
3308 E10
3309 A2
3310 B2
3313 C6
3314 B9
3315 D6
not used
3316 B9
3317 D5
3318 D6
3319 B10
3320 B11
3322 D13
13
3324 D9
3325 E9
3326 E9
3328 G2
3329 G2
3332 G3
3333 G3
3339 H6
3340 H6
3341 H6
3342 H7
3343 I3
3344 H5
3345 H5
3346 H6
3347 H5
3348 H5
3349 H6
3350 H6
3351 H11
3352 H11
3353 I11
3354 D9
3355 D5
3356 D5
2329 A1
3361 B12
3362 B12
3363 B12
3364 B12
3365 B12
3366 B12
3367 B12
3368 B12
4300 G6
4301 G6
4302 G6
4303 G6
4304 G6
5300 A3
5301 B5
5302 B3
5303 A5
not used
5304 C1
5305 A2
6301 D13
6304 I13
6305 D10
6306 D11
3323 D9
BLM18A
7300 A1
7301 D11
7302 C9
7303 C10
7304 F8
7305 H11
7306 H10
7307 A9
F301 A2
F302 A3
F303 B5
F304 B3
F305 A5
F306 C3
F307 H13
F308 B13
F3101 I6
3357 D12
F3103 I6
F3105 I6
F3107 I6
F3109 I5
F311 A13
F3111 I5
F3113 I5
F312 A13
F313 A13
F314 A13
F315 A13
F316 A13
F317 A13
F318 B13
F319 B13
F320 B13
F321 B13
F322 B13
not used
2
3
2
9
1
0
0
n
10R 3308
BLM21
5303
3303 10R
3
3
1
5
1
R
0
3
3
6
8
6
3
0
5
6
3
0
6
B
A
V
9
9
W
B
A
V
9
9
W
3
3
1
6
1
0
K
1n0
2324
3
3
0
9
1
2
0
R
1
%
F
3
1
0
9
F311
4304
F304
2
0
0
m
A
1
3
0
0
3301 10R
3
3
6
4
F
3
1
0
1
3
3
6
2
F302
1
0
K
3
3
1
4
4
7
K
3
3
2
2
2
3
1
2
1
0
0
n
10R 3302
2
3
0
4
1
0
0
n
4
R
7
3
3
5
1
F
3
1
1
1
2
3
0
61
6
V
4
7
u
1K0
3352
3
3
4
7
2
2
R
2
3
0
7
1
0
0
n
F301
2
3
1
5
1
0
0
n
3
3
3
3
1
0
K
2
3
0
8
1
0
0
n
2
3
0
1
47K
3313
4
7
u
1
6
V
10R 3306
3
3
4
6
3
3
6
3
2
2
R
B
L
M
2
1
5
3
0
5
1
0
0
n
2
3
2
0
F
3
1
1
3
3
3
4
9
2
2
R
5302
2
3
2
6
1
0
0
n
3
3
6
7
1
0
0
n
2
3
2
2
1
0
K
3
3
4
3
2
3
2
1
1
0
0
n
1
0
u
2
3
1
1
1
6
V
3
3
2
3
1
R
0
2
3
0
3
1
0
u
1
0
K
3
3
3
9
1
6
V
2
3
1
41
6
V
4
7
u
7303
BSN20
1
0
K
3
3
4
0
F307
1
u
0
1
0
0
n
2
3
1
9
2
3
2
7
10R 3300
1
0
K
3
3
5
3
F305
B
Z
X
3
8
4
-C
6
V
8
6
3
0
1
5301
BLM21
F
3
1
0
7
5304
BLM21
3
9
0
R
3
3
1
0
3
3
5
0
2
2
R
1
%
5
0
V
2
3
2
8
2
u
2
3357
F306
4K7
2
2
R
3
3
4
4
1
2
3
5
4
74LVC1G08GW
7301
4
K
7
3
3
2
0
1%
3326
470R
5
4
8
1
2 3 6 7
3325
4R7
7305
LE50ABD
2
7300
LM317MDT
1
3
F
3
1
0
5
7302
BSN20
F
3
1
0
3
3354
47K
1
0
K
3
3
2
8
3
3
4
1
1
0
K
100n
2317
90
2
11
F320
94
95
96
97
83
84
85
86
87
88
89
29
33
32
36
35
27
26
82
91
92
93
3
8
42
21
12
10
9
8
7
5
30
1
4
4
7
7
2
1
3
4
8
7
1
6
40
2
2
3
9
2
3
80
20
19
24
8
1
18
1
66
17
52
51
50
49
76
75
70
69
68
67
65
64
63
62
61
58
57
56
55
54
53
77
41
43
44
41
6
4
55
9
7
4
79
78
2
5
3
1
3
7
2
8
3
4
3
1
5
4
6
6
0
7
3
HDMI
TRANSMITTER
7304
SII9030CTU
F318
1
R
0
3
3
2
4
F317
1
%
1
2
0
R
3
3
0
5
F308
4
7
u 2
3
0
0
5300
1
0
0
n
2
3
0
9
1
6
V
F303
4302
3
3
1
7
1
R
0
3 2
6 7
8 1
F321
PCA9512DP
7307
5
4
2
3
2
3
1
0
0
n
4K7
3356
1
0
0
n
2
3
0
2
3
3
1
9
4
K
7
3304 10R
1
0
0
n
2
3
1
0
23
F322
3
4
5
6
7
8
9
2021
22
10
11
12
13
14
15
16
17
18
19
2
DC1R019JDA
1930
1
1
1
1
2
1
32 3 4 5 6 7 8 9
1
9
3
1
13FMN-BMT-A-TFT
1
1
0
3
3
6
1
BC857BW
7306
2
2
R
3
3
4
5
3
3
4
8
2
2
R
2
3
2
5
1
0
p
3
3
4
2
3
9
0
R
3
3
6
6
1
0
K
B
Z
X
3
8
4
-C
6
V
8
6
3
0
4
3
3
2
9
1
u
0
2
3
3
0
1
0
K
3
3
6
5
3
3
3
2
4
K
7
3
3
5
5
F316
F315
F314
F312
F313
10R
2
3
1
6
1
0
0
n
3307
4303
4
7
u
1
6
V
2
3
1
8
4301
4300
3
3
1
8
2
2
R
1
0
0
n
2
3
3
3
2
3
3
4
1
0
0
n
F319
TX0+_1
TX0-_1
TXC+_1
TXC+_1
TX_DDC_SCL
TXC-_1
TX2-_1
TX_DDC_SCL
TX_DDC_SDA
+5V
+5V_HDMI
+5V
TX2+_1
TX2+_1
TXC-_1
TX0+_1
TX0-_1
TX1+_1
TX1-_1
TX2-_1
TX1+_1
TX1-_1
Y
(1
)
Y
(0
)
+5V
+12V
+3V3
+3V3_HDMI_T
+5V
SPDIF_OUT
+3V3_PLL2_T
C
b
C
r(1
)
C
b
C
r(0
)
FSCLK12_OUT
S
C
K
1
2
_
O
U
T
W
S
1
2
_
O
U
T
S
D
_
O
U
T
+3V3_HDMI_T
CbCr(5)
CbCr(7)
CbCr(11)
CbCr(10)
CbCr(9)
CbCr(8)
CbCr(6)
CbCr(4)
+3V3A_HDMI_T
+
3
V
3
A
_
H
D
M
I_
T
+
3
V
3
_
H
D
M
I_
T
+3V3_HDMI_T
+1V8_HDMI_T
+3V3_HDMI_T
+3V3
+3V3
+1V8
H
D
M
I_
R
S
T
n
+
3
V
3
_
P
L
L
1
_
T
+
3
V
3
_
P
L
L
2
_
T
P_VSYNC
S
C
L
0
S
D
A
0
+
3
V
3
_
H
D
M
I_
T
+
1
V
8
_
H
D
M
I_
T
Y(0)
Y(1)
Y(6)
Y(7)
Y(8)
Y(9)
Y(10)
Y(11)
Y(2)
Y(3)
CbCr(0)
CbCr(1)
CbCr(2)
CbCr(3)
Y(4)
Y(5)
HPD
P_HSYNC
P_CLK
INT_HDMI
+3V3_PLL1_T
+3V3_HDMI_T
+5V_HDMI
TX_DDC_SDA
HPD

EN 126 3139 785 32804
HDMI: COLUMBUS
CLKASA
8
0
1
2
3
4
5
6
7
2
5
3
DQM
WE
6
0
1
2
3
4
5
7
2
1
0
3
4
5
15
6
5
4
8
7
14
5
6
8
11
10
WEA
6
VA
7
YA
0
1
2
4
3 8
7
11
12
13
HREF
9
8
CLKASB
7
16
8
WEB
3
2
1
0
6
10
9
4
1
A
DAVA
DI9
UVA
DI
UVB
DO
DO9
YB
DAVB
DQ
RAS
CAS
CLK
COM
VDDC
VSS
VDDS
A0IIC
CLKSEL
656SEL
SCL
AVD
SDA
AVS
F415 F5
4401-1 B2
F410 E1
F411 E1
F412 E1
F413 E1
F414 F5
2409 A8
2411 B7
F407 E2
F408 E2
F409 E1
Not used for DVDR9000H
Jumper
2407 A5
1
4401-2 B2
4401-3 B2
4401-4 B2
4408 C2
4409 D2
4410 D2
4411 E1
4412 E1
4413 E2
4414 F2
5400 A8
5401 B8
5402 D5
7400-1 C7
7400-2 D2
7401 A8
F400 A8
F401 A7
F402 B7
F403 D4
F404 D5
F405 D2
F406 D2
not used
n
o
t u
s
e
d
not used
2408 A5
2410 A7
2412 B7
2413 B7
2414 B7
2415 B6
2416 B6
2417 B6
2418 B6
2419 B5
2420 D5
3400 D6
3401 D4
3402 D4
3403 D1
3404 E1
3405 E5
3406 E5
3607 F2
3608 F2
3609 F2
4400-1 A2
4400-2 A2
4400-3 B2
4400-4 B2
2403 A6
2404 A6
2405 A6
2406 A6
2401 A7
Not used for DVDR7300H
2402 A7
2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
not used
n
o
t u
s
e
d
n
o
t u
s
e
d
A
B
C
D
E
F
2400 A7
3V3_COLUM 3404
4K7
F410
F409
2
4
1
7
1
0
0
n
1
0
0
n
2
4
1
6
2
4
1
5
1
0
0
n
1
0
0
n
2
4
1
4
F401
1
0
0
n
2
4
1
8
3V3_COLUM 1V5_COLUM
3
4
0
1
4
K
7
3402
4K7
4
K
7
3
4
0
0
3V3_COLUM
B1
4400-1
A11
B12
A12
G2
F2
E2
E1
D2
D1
C2
C1
A13
B13 A1
J15
B7
B9
A9
B10
A10
B11
B6
A6
M2
M1
L2
L1
K2
K1
J2
J1
H2
L14
A14
K15
A2
B3
A3
B4
A4
B5
A5
M14
M15
L15
R12
P11
P10
R10
P9
P8
R8
R13
P4
K14
J14
H1 G1
P12
R14
R15
P15
N15
R6
R7
P7
P5
R5
R1
R2
R3
P3
R4
T6TU5XBG
7400-1
P6
2
4
1
1
+3V3
1
6
V
1
0
u
2
4
0
9
1
0
u
1
6
V
F484
3405
100R
3406
100R
4401-4
F411
F412
3V3_COLUM
B
L
M
1
8
P
5
4
0
2
2
4
1
9
1
0
0
n
F415
F402
F414
F400
BLM18P
5400
2420
100n
1V5_COLUM
1
0
K
3
6
0
7
1
0
K
3
6
0
9
3
6
0
8
1
0
K
4412
1
0
0
n
3V3_COLUM
2
4
1
3
1
0
0
n
2
4
0
5
1
0
0
n
2
4
1
2
2
4
0
4
1
0
0
n
2
4
0
3
1
0
0
n
2
4
1
0
2
4
0
2
1
0
0
n
3V3_COLUM
1
6
V
1
0
u
4410
F
4
0
4
4408
F483
F406
F407
3
V
3
_
C
O
L
U
M
F405
F
4
0
3
1
0
0
n
2
4
0
1
2
4
0
0
1
0
0
n
LF15ABDT
7401
2
1 3
5401
BLM18P
+3V3
F408
4413
2
4
0
8
1
0
0
n
4401-1
4400-4
4401-3
4401-2
F481
1V5_COLUM
4409
P
1
4
R
9
R
1
1
C
3
C
5
C
6
C
9
C
1
0
C
1
3
D
1
3
L
3
M
1
3
N
4
N
5
B
1
4
N
7
N
1
0
N
1
2
N
1
3
P
2
L
1
3
M
3
N
3
N
8
N
1
1
B
2
E
3
F
3
F
1
3
J
3
J
1
3
K
1
3
H
1
3
K
3
N
6
N
9
C
4
N
1
4
P
1
3
C
1
2
G
3
G
1
3
E14
F14
A8
F1
H3
C
7
C
8
C
1
1
D
3
E
1
3
D4
N2
G15
B15
A15
D14
C14
C15
D15
F15
E15
A7
G14
N
1
P
1
B
8
H14
H15
F482
CTRL
T6TU5XBG
7400-2
F413
1
0
0
n
2
4
0
7
2
4
0
6
1
0
0
n
4400-3
4400-2
4411
4K7
3403
4
4
1
4
VO_CLK
ITU_OUT_2(7)
ITU_OUT_2(6)
ITU_OUT_2(5)
ITU_OUT_2(4)
ITU_OUT_2(3)
ITU_OUT_2(2)
ITU_OUT_2(1)
ITU_OUT_2(0)
ITU_OUT_2(0:7)
ITU_OUT(7)
ITU_OUT(6)
ITU_OUT(5)
ITU_OUT(4)
ITU_OUT(3)
ITU_OUT(2)
ITU_OUT(1)
ITU_OUT(0)
ITU_OUT(0:7)
VO_CLK_2
ITU_OUT_2(3)
ITU_OUT(4) ITU_OUT_2(4)
VO_CLK VO_CLK_2
ITU_OUT(0:7) ITU_OUT_2(0:7)
PSCAN_RSTn
HDMI_RSTn
ITU_OUT(3)
SCL0
SDA0

EN 127 3139 785 32804
Layout: HDMI Top View
HDMI Columbus at CR Top View_8 3139-243-32736-132-a1.pdf 2007-05-10

EN 128 3139 785 32804
Layout: HDMI Bottom View
HDMI Columbus at CR Bottom View_8 3139-243-32736-132-a1.pdf 2007-05-10

EN 129 3139 785 32804 8. IC Internal Block Diagrams
8.1 Analog Board
IC7202 - CS4344 Digital To Analogue Converter

BLOCK DIAGRAM
PCM
Serial
Interface
Multibit
Modulator
Interpolation
Filter
Internal
Voltage
Reference
Switched
Capacitor
DAC and
Filter
Serial Audio
Input
Right
Output
Left
Output
Switched
Capacitor
DAC and
Filter
De-emphasis
Multibit
Modulator
Interpolation
Filter
3.3 V or 5 V
Figure 8-1
PIN DESCRIPTION AND CONFIGURATION
Pin Name # Pin Description
SDIN 1 Serial Audio Data Input (Input) - Input for twos complement serial audio data.
DEM/SCLK
2 De-Emphasis/External Serial Clock Input (Input) - used for de-emphasis filter control or external serial
clock input.
LRCK
3 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio
data line.
MCLK 4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VQ 5 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
FILT+
6 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling
circuits.
AOUTL
7 Left Channel Analog Output (Output) - The full scale analog output level is specified in the Analog Char-
acteristics specification table.
GND 8 Ground (Input) - ground reference.
VA 9 Analog Power (Input) - Positive power for the analog and digital sections.
AOUTR
10 Right Channel Analog Output (Output) - The full scale analog output level is specified in the Analog
Characteristics specification table.
SDIN AOUTR
DEM/SCLK VA
LRCK GND
MCLK AOUTL
VQ FILT+
1
2
3
4
5 6
7
8
9
10
8. IC Internal Block Diagrams

IC 7101 - NJW2244M - 3-INPUT VIDEO SWITCH WITH 75 DRIVER

BLOCK DIAGRAM
PIN CONFIGURATION
BLOCK DIAGRAM
Pin Connection
INPUT CONTROL SIGNAL-OUTPUT SIGNAL
SW1 SW2 OUTPUT SIGNAL
L L VIN1
H L VIN2
L/H H VIN3
NJM2244D
NJM2244M
NJM2244L
note): Input clamp Voltage is about 2/5 of Supply Voltage
Figure 8-2
PIN DESCRIPTION AND CONFIGURATION
PIN CONFIGURATION
BLOCK DIAGRAM
Pin Connection
L L V
IN
1
H L V
IN
2
L/H H V
IN
3
NJM2244D
NJM2244M
NJM2244L
PIN CONFIGURATION
BLOCK DIAGRAM
Pin Connection
L L V
IN
1
H L V
IN
2
L/H H V
IN
3
NJM2244D
NJM2244M
NJM2244L
Figure 8-3

8.2 Digital Board
IC7300 - TSB41AB1 - IEEE 1394a-2000 ONE-PORT CABLE TRANSCEIVER/ARBITER

BLOCK DIAGRAM
Received Data
Decoder/Retimer
Link
Interface
I/O
Arbitration
and Control
State Machine
Logic
Bias Voltage
and
Current
Generator
Transmit Data
Encoder
Cable Port
Crystal
Oscillator,
PLL System,
and Clock
Generator
TPA+
CPS
TPA
TPB+
TPB
XI
XO
FILTER0
FILTER1
LPS
ISO
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PC0
PC1
PC2
C/LKON
R0
R1
TPBIAS
PD
RESET
CNA output is only available in the 64-pin PAP package

Figure 8-4

PIN CONFIGURATION
14 15
AGND
AV
DD
R1
R0
AGND
TPBIAS
TPA+
TPA
TPB+
TPB
AGND
AV
DD
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
SYSCLK
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PD
17 18 19 20
47 46 45 44 43 48 42 40 39 38 41
21 22 23 24
37
13
PHP PACKAGE
(TOP VIEW)
TSB41AB1
P
L
L
G
N
D
P
L
L
V
F
I
L
T
E
R
1
F
I
L
T
E
R
0
L
R
E
Q
D
G
N
D
D
G
N
D
D
V
T
E
S
T
M
S
E
S
M
C
/
L
K
O
N
P
C
1
P
C
2
I
S
O
C
P
S
D
V
R
E
S
E
T
X
O
X
I
D
G
N
D
L
P
S
P
C
0
D
D
D
V
D
D
D
D
D
D
Figure 8-5

PIN DESCRIPTION
TERMINAL
TYPE I/O DESCRIPTION
NAME PAP NO. PHP NO.
AGND 32, 33, 39,
48, 49, 50
26, 32, 36 Supply Analog circuit ground terminals. These terminals should be tied together to the
low-impedance circuit board ground plane.
AV
DD
30, 31, 42,
51, 52
25, 35 Supply Analog circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 F and 0.001
F. Lower frequency 10 F filtering capacitors are also recommended. These
supply terminals are separated from PLLV
DD
and DV
DD
inside the device to provide
noise isolation. They should be tied at a low-impedance point on the circuit board.
C/LKON 19 15 CMOS I/O Bus manager contender programming input and link-on output. On hardware reset,
this terminal is used to set the default value of the contender status indicated during
self-ID. Programming is done by tying the terminal through a 10-k resistor to a high
(contender) or low (not contender). The resistor allows the link-on output to override
the input. However, it is recommended that this terminal should be programmed
low, and that the contender status be set via the C register bit.
If the TSB41AB1 is used with an LLC that has a dedicated terminal for monitoring
LKON and also setting the contender status, then a 1-k series resistor should be
placed on the LKON line between the PHY and LLC to prevent bus contention.
Following hardware reset, this terminal is the link-on output, which is used to notify
the LLC to power up and become active. The link-on output is a square-wave signal
with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on
output is otherwise driven low, except during hardware reset when it is
high-impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit
cleared) and when:
a) the PHY receives a link-on PHY packet addressed to this node, or
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-time-out interrupt), CPSI
(cable-power-status interrupt), or STOI (state-time-out
interrupt) register bits are 1 and the RPIE (resuming-port
interrupt enable) register bit is also 1.
Once activated, the link-on output continues active until the LLC becomes active
(both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output
when a bus reset occurs unless the link-on output would otherwise be active
because one of the interrupt bits is set (that is, the link-on output is active due solely
to the reception of a link-on PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the link-on
output to be activated if the LLC were inactive, the link-on output is activated when
the LLC subsequently becomes inactive.
CNA 3 N/A CMOS O Cable-not-active output. This terminal is asserted high when there is no incoming
bias voltage.
CPS 24 20 CMOS I Cable power status input. This terminal is normally connected to cable power
through a 400-k resistor. This circuit drives an internal comparator that is used to
detect the presence of cable power. This terminal should be tied directly to DV
DD
supply if application does not require it to be used.
CTL0
CTL1
4
5
2
3
CMOS I/O Control I/Os. These bidirectional signals control communication between the
TSB41AB1 and the LLC. Bus holders are built into these terminals.
D0
D1
D2
D3
D4
D5
D6
D7
6
7
8
9
10
11
12
13
4
5
6
7
8
9
10
11
CMOS I/O Data I/Os. These are bidirectional data signals between the TSB41AB1 and the
LLC. Bus holders are built into these terminals.

TERMINAL
DGND 17, 18, 63,
64
14, 46, 47 Supply Digital circuit ground terminals. These terminals should be tied together to the
DV
DD
25, 26, 61,
62
21, 44, 45 Supply Digital circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 F and
0.001 F. Lower frequency 10 F filtering capacitors are also recommended.
These supply terminals are separated from PLLV
DD
and AV
DD
inside the device to
provide noise isolation. They should be tied at a low-impedance point on the circuit
board.
FILTER0
FILTER1
54
55
38
39
CMOS I/O PLL filter terminals. These terminals are connected to an external capacitor to form
a lag-lead filter required for stable operation of the internal frequency multiplier PLL
running from the crystal oscillator. A 0.1 F 10% capacitor is the only external
component required to complete this filter.
ISO 23 19 CMOS I Link interface isolation control input. This terminal controls the operation of output
differentiation logic on the CTL and D terminals. If an optional Annex J type isolation
barrier is implemented between the TSB41AB1 and LLC, the ISO terminal should
be tied low to enable the differentiation logic. If no isolation barrier is implemented
(direct connection), or TI bus holder isolation is implemented, the ISO terminal
should be tied high to disable the differentiation logic. For additional information
refer to TI application note Galvanic Isolation of the IEEE 1394-1995 Serial Bus,
SLLA011.
LPS 15 13 CMOS I Link power status input. This terminal monitors the active/power status of the link
layer controller and controls the state of the PHY-LLC interface. This terminal
should be connected through a 10-k resistor either to the V
DD
supplying the LLC,
or to a pulsed output which is active when the LLC is powered (see Figure 9). A
pulsed signal should be used when an isolation barrier exists between the LLC and
PHY. (See Figure 10.)
The LPS input is considered inactive if it is sampled low by the PHY for more than
2.6 s (128 SYSCLK cycles), and is considered active otherwise (that is, asserted
steady high or an oscillating signal with a low time less than 2.6 s). The LPS input
must be high for at least 21 ns to guarantee that a high is observed by the PHY.
When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface
into a low-power reset state. In the reset state, the CTL and D outputs are held in
the logic zero state and the LREQ input is ignored; however, the SYSCLK output
remains active. If the LPS input remains low for more than 26 s (1280 SYSCLK
cycles), the PHY-LLC interface is put into a low-power disabled state in which the
SYSCLK output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl
register bit is set to 1, and is considered inactive if either the LPS input is inactive
or the LCtrl register bit is cleared to 0.
LREQ 1 48 CMOS I LLC request input. The LLC uses this input to initiate a service request to the
TSB41AB1. Bus holder is built into this terminal.
PC0
PC1
PC2
20
21
22
16
17
18
CMOS I Power class programming inputs. On hardware reset, these inputs set the default
value of the power class indicated during self-ID. Programming is done by tying
these terminals high or low. Refer to Table 9 for encoding.
PD 14 12 CMOS I Power-down input. A high on this terminal turns off all internal circuitry except the
cable-active monitor circuits, which control the CNA output (64-terminal PAP
package only). Asserting the PD input high also activates an internal pulldown on
the RESET terminal to force a reset of the internal control logic. (PD is provided for
legacy compatibility and is not recommended for power management in place of
IEEE 1394a-2000 suspend/resume LPS and C/LKON features.)

TERMINAL
PLLGND 57, 58 41 Supply PLL circuit ground terminals. These terminals should be tied together to the
PLLV
DD
56 40 Supply PLL circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 F and 0.001
F. Lower frequency 10 F filtering capacitors are also recommended. This supply
terminal is separated from DV
DD
and AV
DD
inside the device to provide noise
isolation. It should be tied at a low-impedance point on the circuit board.
R0
R1
40
41
33
34
Bias Current setting resistor terminals. These terminals are connected through an
external resistor to set the internal operating currents and cable driver output
currents. A resistance of 6.34 k 1.0% is required to meet the IEEE Std
1394-1995 output voltage limits.
RESET 53 37 CMOS I Logic reset input. Asserting this terminal low resets the internal logic. An internal
pullup resistor to V
DD
is provided so only an external delay capacitor is required for
proper power-up operation (see power-up reset in the Application Information
section). The RESET terminal also incorporates an internal pulldown which is
activated when the PD input is asserted high. This input is otherwise a standard
logic input, and may also be driven by an open-drain type driver.
SE 28 23 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal may be tied to GND through a 1-k pulldown resistor or
it may be tied to GND directly.
SM 29 24 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal should be tied to GND.
SYSCLK 2 1 CMOS O System clock output. Provides a 49.152-MHz clock signal, synchronized with data
transfers, to the LLC.
TESTM 27 22 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal should be tied to V
DD
.
TPA+ 37 30 Cable I/O Twisted-pair cable A differential signal terminals. Board traces from the pair of
positive and negative differential signal terminals should be kept matched and as
TPA 36 29 Cable I/O
short as possible to the external load resistors and to the cable connector.
TPB+ 35 28 Cable I/O Twisted-pair cable B differential signal terminals. Board traces from the pair of
TPB 34 27 Cable I/O
short as possible to the external load resistors and to the cable connector.
TPBIAS 38 31 Cable I/O Twisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for
proper operation of the twisted-pair cable drivers and receivers, and for signaling
to the remote nodes that there is an active cable connection.
XI
XO
59
60
42
43
Crystal Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel
resonant fundamental mode crystal. The optimum values for the external shunt
capacitors are dependent on the specifications of the crystal used (see crystal
selection in the Application Information section). When an external clock source is
used, XI should be the input and XO should be left open, and the clock must be
supplied before the device is powered on.

IC7301 TPS2051AD - CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES

BLOCK DIAGRAM
TPS2041A
OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
Active high for TPS205xA series
Current sense
TPS2042A
Thermal
Sense
Driver
Current
Limit
Charge
Pump
UVLO
CS
Driver
Current
Limit
CS
Thermal
Sense
Charge
Pump
Power Switch
GND
EN1
IN
EN2
OC1
OUT1
OUT2
OC2
Active high for TPS205xA series
Current sense
Figure 8-6
PIN CONFIGURATION
1
2
3
4
8
7
6
5
GND
IN
IN
EN
OUT
OUT
OUT
OC
TPS2041A, TPS2051A
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
GND
IN
EN1
EN2
OC1
OUT1
OUT2
OC2
TPS2042A, TPS2052A
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDA
IN1
EN1
EN2
GNDB
IN2
EN3
EN4
OC1
OUT1
OUT2
OC2
OC3
OUT3
OUT4
OC4
TPS2044A, TPS2054A
D PACKAGE
(TOP VIEW)
All enable inputs are active high for the TPS205xA series.
NC No connect
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDA
IN1
EN1
EN2
GNDB
IN2
EN3
NC
OC1
OUT1
OUT2
OC2
OC3
OUT3
NC
NC
TPS2043A, TPS2053A
D PACKAGE
(TOP VIEW)
Figure 8-7

PIN DESCRIPTION
TPS2041A and TPS2051A
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME
TPS2041A TPS2051A
EN 4 I Enable input. Logic low turns on power switch.
EN 4 I Enable input. Logic high turns on power switch.
GND 1 1 I Ground
IN 2, 3 2, 3 I Input voltage
OC 5 5 O Overcurrent. Logic output active low
OUT 6, 7, 8 6, 7, 8 O Power-switch output
TPS2042A and TPS2052A
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME
TPS2042A TPS2052A
EN1 3 I Enable input. Logic low turns on power switch, IN-OUT1.
EN2 4 I Enable input. Logic low turns on power switch, IN-OUT2.
EN1 3 I Enable input. Logic high turns on power switch, IN-OUT1.
EN2 4 I Enable input. Logic high turns on power switch, IN-OUT2.
GND 1 1 I Ground
IN 2 2 I Input voltage
OC1 8 8 O Overcurrent. Logic output active low, for power switch, IN-OUT1
OC2 5 5 O Overcurrent. Logic output active low, for power switch, IN-OUT2
OUT1 7 7 O Power-switch output
OUT2 6 6 O Power-switch output

IC7500 SAA7136AE MULTISTANDARD AUDIO/VIDEO DECODER

BLOCK DIAGRAM
Fig.2 System Block Diagram of SAA7136
SAICO
S-video
Analog Sound Input
Sound Decoder
Analog
16-bit
Stereo ADC
Front End
NF/Audio
Stereo
BUFFER
Analog
Video
ADC Front End
Video
10-Bit
AI31
AI32
AI33
SSIF
CVBS
Sound
Audio
Inputs
Port B
TS data
Digital
Inputs
Data
IR in
Digital Video
Decoder
Comb Filter
Video Scaler
Format
DACs
Stereo
I
2
S
Audio
Output
MUX
I
2
S
Audio
Stereo
VIP Host
DSP
I
2
S
SPDIF
Dual FM/NICAM
BTSC
EIAJ
dBx expander
(***)
Volume control
Bass, Treble and
Balance
SRC
Incredible Sound
I
2
S I
2
S
SPDIF SPDIF
VIP
Analog
Video
ADC Front End
Video
10-Bit
AI40P
AI41
AI42
AI43
Analog
Video
ADC Front End
Video
10-Bit
AI11
AI12
AI13
IF_POS
(*)
Analog
Video
ADC Front End
Video
10-Bit
AI21
AI22
AI23
NAICO
Analog
Control
Input
Video
Unit
Control Unit
Component
Processing
SDTV/HD
Sync.
VBI Slicer
Digital
Low IF
IF
(*)
H-
Scaler
PRE
V-
Scaler
Task A (Video)
Task B
RAW VBI
Scaler Event Handler
EDDI
D
C
I
O
S
T
P
S
C
A
L
E
R
Dig.
Video
Output
Dig. Video IN
DI_A_x
Scaler PLL
Port D
Port C
Video
DAC
ITU
VMI
VIP
Video
I
2
C Slave
TS/PS In
Remote Control
VIP Host Port with
I
2
C Bus
IR out
Remote Control Receiver
Transmitter
PHI
PHI Bus
VIP_Host_Audio
VIP_Host_Audio
Initiator INT_A
IRQ &
Main Control
audio
conversion
TS - Out & Audi - In
Silent
I
2
C Bus
Sound
Audio
Outputs
low IF
SSIF & RGB
(**)
/YP
b
P
r
Video
Inputs
Digital
Programming and Control Ports
M
ADC
X
U
3-Bit
FSW
AV
D-C
FSW
AV/DC
Status bits
A
u
d
i
o

P
r
o
c
e
s
s
i
n
g
V
i
d
e
o

P
r
o
c
e
s
s
i
n
g
P
r
o
g
r
a
m
m
i
n
g

a
n
d

C
o
n
t
r
o
l
P
r
o
c
e
s
s
i
n
g
Programming
AUX Inputs
Port A
Video
Output
Ports
DI_E_x
AI40N
IF_NEG
(*)
I
2
S
Audio
DAC
CVBS
Register Array
I
2
C
read back
PHI
FIFO
Processing
H,V
Soft
Mixer
8-bit/
10-bit
IN1_Left
IN1_Right
IN3_Left
IN3_Right
IN2_Left
IN2_Right
OUT2_Left
OUT2_Right
OUT1_Left
OUT1_Right
DVO_D_X
DVO_C_X
SSIF (*)
CVBS (*)
S_IOUTP
S_IOUTN
V_IOUTP
V_IOUTN
DI_B_x
(DI_A_x)
(DI_B_x)
(*)
only SAA7136E, (**) only SAA7136E/AE/DE,
only SAA7136E/AE/BE (***)
Figure 8-8

PIN CONFIGURATION
Table 1 Pin Conguration (BGA 256 top view)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A AUX3A NC AUX2B AUX1A IN2_Left VDDA(3V3) OUT1_Left IF_AGC I2S_I_1_WS I2S_O_S RST_
OUT_N
VSSD(3V3) VIP_HCT
L
VSSD VIP_D6 VIP_D5
B AUX3B NC AUX2A IN3_Left IN2_Right VRPOS_ADC OUT1_Right NC VSSD SPDIF_I IR_OUT VDDD(3V3) VIP_CLK VDDD(3V3) VIP_D3 VIP_D4
C AGND1 VSYNC AUX1B VREF_ADC IN1_Left VRNEG_ADC VDDA(3V3) I2S_I_2_SD VDDD(3V3) SPDIF_O VDDD(1V8) GPIO_0 VIP_D7 VDDD(3V3) VSSD VIP_D2
D VDDA
(3V3)
VDDA(1V8) VSSA IN3_Right IN1_Right VREF_DAC VDDD(1V8) I2S_I_2_SCK I2S_O_
SD_AUX
VDDD(1V8) IR_IN VIP_RSN DI_E_7 PP_SEL VIP_D0 VIP_D1
E V_IOUTN V_IOUTP S_IOUTN S_IOUTP VSSA VSSA OUT2_Right I2S_I_2_WS I2S_O_
AMCLK
NC GPIO_1 VSSD VDDD(1V8) VDDD(3V3) VSSD DI_E_6
F AI11 IF_NEG IF_POS DAC_
Bias
VDDA(3V3) VREF0 OUT2_Left I2S_I_1_SD I2S_O_SCK VSSD VSSD DI_E_1 DI_E_2 DI_E_3 DI_E_4 DI_E_5
G AI13 AI12 VDDA(3V3) VSSA VSSA VDDA(3V3) VSSD I2S_I_1_SCK I2S_O_WS VSSD DI_B_VS DI_B_DQ DI_A_8 DI_A_9 DI_E_0 VDDD(3V3)
H AI23 AI22 AI21 VSSA VDDA(3V3) AI1D NC VSSD DI_B_HS NC NC NC NC NC NC VDDD(3V3)
J NC VDDA(1V8) VSSA VDDA(3V3) AI2D VSSA VDDA(3V3) NC VSSD DI_A_CLK VDDD(1V8) VSSD DI_B_5 DI_B_6 DI_B_7 DI_B_
CLK
K VSSA VSSA AOUT2 VDDA(3V3) AOUT1 RES_REF_V NC DI_A_2 DI_A_3 VSSD DI_B_0 DI_B_1 DI_B_2 DI_B_3 DI_B_4 VDDD(3V3)
L AI33 AI32 AI31 VDDA(3V3) VSSA AGND2 XTOUT SI_VSYNC DI_A_4 DI_A_
LOCK
VSSD DVO_ODE
V
DVO_DQ DVO_D_C
LK
VDDD(3V3) VSSD
M VSSA VSSA VDDA(3V3) AI3D NC NC D_CON_1 NC VSSD DI_A_VAL DVO_C_0 VSSD VDDD(3V3) VSSD DVO_VS GPIO_2
N AI41 AI40N AI40P VDDA(3V3) SDA INT_A D_CON_2 VSSD DI_A_5 VDDD(1V8) VDDD(1V8) VSSD DVO_C_6 DVO_D_7 DVO_CLK
_C
DVO_HS
P NC AI43 AI42 TDO SCL_SILENT CE VDDD(1V8) DI_A_0 DI_A_6 VDDD(3V3) DVO_C_1 DVO_C_3 DVO_C_7 DVO_D_0 DVO_D_5 DVO_D_6
R VDDA(3V3) AI4D TCK TDI SDA_SILENT VSSA VDDA(1V8) DI_A_1 VDDD(3V3) VSSD DVO_C_2 DVO_C_4 VDDD(3V3) DVO_D_1 DVO_D_3 VSSD
T VSSA TRST_N TMS SCL NC XTALI XTALO VDDD(3V3) DI_A_7 DI_A_SOP VDDD(3V3) DVO_C_5 VSSD DVO_D_2 DVO_D_4 VDDD(3V3)
Analog Processing Pins Digital Processing Pins
Figure 8-9

8.3. HDMI Board
YUV
Progressive
Cinch
*Provision Only
Y
Pb
Pr
Analog
Board
7P
FFC
Con
19P
HDMI
Con
1920
1921
1930
7304
7103
8bit ITU656
27MHz
20bit YCbCr
8bit ITU656
27MHz
8bit ITU656
27MHz
32bit SDRAM
MT48LC2M3282P
Addr Bits
7253
7100 7400
1911
I2C
1
.
0
m
m

1
3
p

F
F
C

C
o
n
0
.
5
m
m

1
0
p

F
F
C

C
o
n
n
e
c
t
o
r
1931
SPDIF
DDC
TDMS
YPbPr
HDMI Tx
SII9030CTU
I2S1
I2S2
I2S3
I2S
SPDIF
I2S
Video DAC
ADV7320
Faroudja
FL2310
Columbus
T6TU5XBG
Level
Shifter
Buffer
Figure 8-10
8.3.1 IC7253 - ADV7320KSTZ - Multi-Format 216 MHz Video Encoder
DE-
INTER-
LEAVE
DE-
INTER-
LEAVE
SHARPNESS &
ADAPTIVE
FILTER
CONTROL
TEST-
PATTERN
Y COLOR
CR COLOR
CB COLOR 4:2:2TO
4:4:4
TEST-
PATTERN
DNR
GAMMA
COLOR-
CONTROL
SYNC
INSER-
TION
UV SSAF RGB
MATRIX
PS 8X
HDTV2X
2XOVER-
SAMPLING
FSC
MODULA--
TION
CGMS
WSS
LUMA &
CHROMA
FILTERS
SD 16X
DAC
DAC
DAC
TIMING
GENERATOR
Y
CR
CB
Y
CB
CR
U
V
HD PIXEL
INPUT
P_HSYNC\
P_VSYNC\
P_BLANK
SD PIXEL
INPUT
CLOCK
CONTROL
& PLL
CLKIN_A
TIMING
GENERATOR
CLKIN_B
S_HSYNC\
S_VSYNC\
S_BLANK
DAC
DAC
DAC
Figure 8-11

PIN DESCRIPTION
Pin Name Input/Output Function
D G N D G Di gi t al Ground
A G N D G Anal og Ground
C L KI N_ A I Pixel Clock Input for HD ( 74.25MHz Only , PS Only ( 27MHz), SD Onl y
( 27MHz ) .
C L KI N_ B I Pixel Clock Input. Requires a 27MHz reference clock for Progressive Sca n
Mode or a 74.25MHz (74.1758MHz) reference clock in HDTV mode. This
Clock is only used in dual Modes.
COMP 1 , 2 O Compensation Pin for DACs. Connect 0.1uF Capacitor from COMP pin to
V
AA
.
DAC A O CVBS/ GREEN/ Y / Y analog output.
DAC B O Chroma/ BLUE/ U / Pb analog output.
DAC C O Luma/ RED/ V / Pr analog output.
DAC D O In SD onlyu mode: CVBS/Green/Y analog outptu, in HD only mode and
si mul t aneous HD/ SD mode: Y/ Green [HD] anal og out put .
DAC E O In SD onlyu mode: Luma/Blue/U analog outptu, in HD only mode and
si mul t aneous HD/ SD mode: Pr/Red analog output.
DAC F O In SD onlyu mode: Chroma/Red/ V analog outptu, in HD only mode and
simultaneous HD/SD mode: Pb/Blue [HD] analog output.
P_HSYNC I Video Horizontal Sync Control Signal for HD in simultaneous Sd/HD
mode and HD mode only.
P_VSYNC I Video Vertical Sync Control Signal for HD in simultaneous SD/HD mode and
HD mode only.
P_BLANK I Video Blanking Control signal for HD in simultaneous SD/HD mode and HD
mode onl y.
S_BLANK I Video Blanking Control Signal for SD only.
S_HSYNC I Video Horizontal Sync Control Signal for SD only.
S_VSYNC I Video Vertical Sync Control Signal for SD only.
Y9 - 0 I SD or Progressive scan/ HDTV input port for Y data.
Input port for interleaved Progressive Scan data. The LSB is set up
on pin Y0. For 8-bit data input LSB is set up on Y2.
C9 - C0 I Pro gressive Scan/ HDTV input port :4:4 input mode this port is used for
the Cb[Blue/U] data. The LSB is set up on pin C0. For 8-bit data input LSB is
set up on C2.
S 9 - S 0 I SD or Progressive Scan/HDTV input port for Cr [Red/V] data in 4:4:4 input
mode. LSB is set up on pin S0. For 8-bit data input LSB is set up on S2.
RESET I This input resets the on-chip timing generator and sets the ADV7310/11
into Default Register setting. Reset is an active low signal.
R
SET1,2
I A 3040 Ohms resistor must be connected from this pin to AGND and is used
to control the amplitudes of the DAC outputs.
S CL k I I2C Port Serial Interface Clock Input .

S D A I / O I2C Port Serial Data Input/Output .
AL S B I / O TTL Address Input. This signal sets up the LSB of the I2C address.
When this pin is tied low the I2C filter is activated which reduces noise on the
I2C i nt erface.
V
DD_IO
P Power supply for digital i/ps and o/ps
V
DD
P Di gi t al power suppl y
V
AA
P Anal og power suppl y
V
REF
I / O Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235V).
E XT _ L F I External Loop filter for the internal PLL.
RTC_SCR_TR I Multifunctional Input: Real Time Control (RTC) input, Timing Reset input,
Subcarrier Reset input.
I
2
C I This Input Pin must be tied High (V
DD_IO
) for t he ADV7310/ADV7311 to interfac e
over the I
2
C port.
GND_ I O

PIN CONFIGURATION
12
13
14
15
17 18
3
4
5
6
7
1
2
10
11
8
9
56 55 54 57 58 59 60
47
53
42
43
44
45
40
41
38
39
19 20
DAC A
C
L
K
I
N
_
B
DACB
AGND
VAA
R
T
C
_
S
C
R
_
T
R
S
D
A
I
2
C
A
L
S
B
S
C
L
K
C
4
C
3
S
4
VDD_IO
Y0
Y1
Y2
Y3
Y4
Y5
Y6
DAC D
C
7
C
5
P
_
H
S
Y
N
C
C
L
K
I
N
_
A
R
SET 2
S
_
H
S
Y
N
C
61 62 63 64
S_BLANK
DAC F
DACC
P
_
B
L
A
N
K
C
9
C
8
G
N
D
_
I
O
EXT_LF
16
21 22 23 24 25 26 27 28
29 30 31 32
37
35
33
34
COMP1
RESET
DAC E
COMP2
VREF
48
S
_
V
S
Y
N
C
C
6
P
_
V
S
Y
N
C
49
50
51
52
S
0
S
1
46
Y7
VDD
Y9
C0
C1
C2
36
S
2
V
D
D
S
9
S
8
S
6
S
7
D
G
N
D
S
5
DGND
Y8
R
SET 1
S
3
PI N 1
I DENTI FI ER
TOP VIEW
(Not to Scale)
ADV7320
KSTZ
Figure 8-12

8.3.2 IC7400 - T6TU5XBG - Columbus 2D/3D Comb lter and spatial / temporal noise reduction system
BLOCK DIAGRAM
Memory Interface
3
D

C
o
m
b
P
A
L

&
N
T
S
C
L
o
c
a
l

R
e
g
r
e
s
s
i
o
n
&
S
W
A
N

3
D
N
o
i
s
e

R
e
d
u
c
t
i
o
n
6
5
6

D
e
c
o
d
e
r
6
5
6

E
n
c
o
d
e
r
IIC Interface
SNERT Interface
BST
Interface
Pattern
Test
Generator
SDA, SCL
SNDA, SNCL, SNRST
A0IIC
YA(8:0)/
Di(9)
UVA(8:0)/Di(8:0)
UVB(8:0)/Do(8:0)
YVB(8:0)/
Do(9)
Noise
Measurement
T
D
I
T
D
O
T
R
S
T
T
C
K
T
M
S
SEL656
M
u
x
M
u
x
M
u
x
SEL656
CLKASA
CLKASB
WEB/DAVB
WEA/DAVA
HREF
VA
DQ(16:1) A(11:0) CONTROL
656
Test
Generator
Figure 8-13

PIN DESCRIPTION
Signal name Pin no. I/O Short description
WEB/DAVB A1 Out Write enable B / Data valid B
UVA0/Di0 A2 In UV input 0 / 656 Data Input 0
SEL656 A7 In Select 656
TST1 A8 In Test input 1.
YA2 A9 In Luminance input 2
VA A13 In Vertical synchronisation
HREF A14 In Horizontal reference signal
SDA A15 I/O IIC Serial Data
YB8 B1 Out Luminance output 8
VSS B2 Ground
UVA1/Di1 B3 In UV input 1 / 656 Data Input 1
YA0/Di9 B7 In Luminance input 0 / 656 Data Input 9
BISTEN B8 In Build In Self Test Enable
YA1 B9 In Luminance input 1
WEA/DAVA B13 In Write Enable input from picnic/656 Data input valid
VSS B14 Ground
SCL B15 In IIC Serial Clock
YB7 C1 Out Luminance output 7
YB6 C2 Out Luminance output 6
VSS C3 Ground
VDDS C4 3.3 V supply voltage
VSS C5 Ground
VSS C6 Ground

VDDC C7 1.5V Core supply voltage
VSS C9 Ground
VSS C10 Ground
VDDS C12 3.3 V supply voltage
VSS C13 Ground
SNDA C14 I/O Snert Data
SNRST C15 In Snert Reset
YB5 D1 Out Luminance output 5
YB4 D2 Out Luminance output 4
VDDC D3 1.5V Core supply voltage
N.C. D4
VSS D13 Ground
SNCL D14 In Snert Clock
TCK D15 In Boundary scan test, Test clock
YB3 E1 Out Luminance output 3
YB2 E2 Out Luminance output 2
VSS E3 Ground
VDDC E13 1.5V Core supply voltage
TMS E14 In Boundary scan test, Test Mode Select
TDO E15 Out Boundary scan test, Test Data Out
TST2 F1 In Test input 2
YB1 F2 Out Luminance output 1
VSS F3 Ground
VSS F13 Ground
TRST F14 In Boundary scan test, Reset
TDI F15 In Boundary scan test, Test Data In
CLKASB G1 Out Clock ASB
YB0/Do9 G2 Out Luminance output 0 / 656 Data output 9
VDDS G3 3.3 V supply voltage
VDDS G13 3.3 V supply voltage
A0IIC G14 In IIC address select
Reset G15 In Resets the 656-outputs and SDRAM Data I/Os to tri-
state and resets the (asynchronous) IIC transceiver. +
defauls. Reset is active low.
CLKASA H1 In Clock ASA
UVB8/Do8 H2 Out UV output 8 / 656 Data output 8
TST3 H3 In Test input 3
VDDC H13 1.5V core supply voltage

CLKEXT H14 In External clock input
CLKSEL H15 In External clock select
UVB7/Do7 J1 Out UV output 7 / 656 Data output 7
UVB6/Do6 J2 Out UV output 6 / 656 Data output 6
VSS J3 Ground
VSS J13 Ground
CLK J14 Out SDRAMClock
WEN J15 Out SDRAM Write Enable Not. Active Low.
UVB5/Do5 K1 Out UV output 5 / 656 Data output 5
UVB4/Do4 K2 Out UV output 4 / 656 Data output 4
VDDC K3 1.5V core supply voltage
VSS K13 Ground
CASN K14 Out SDRAM Column Access Not. Active Low.
RASN K15 Out SDRAM Row Access Not. Active Low.
UVB3/Do3 L1 Out UV output 3 / 656 Data output 3
UVB2/Do2 L2 Out UV output 2 / 656 Data output 2
VSS L3 Ground
VDDS L13 3.3 V supply voltage
DQM L14 Out SDRAM Data mask
DQ16 L15 I/O SDRAM Data bit 16
UVB1/Do1 M1 Out UV output 1 / 656 Data output 1
UVB0/Do0 M2 Out UV output 0 / 656 Data output 0
VDDS M3 3.3 V supply voltage
VSS M13 Ground
DQ14 M14 I/O SDRAM Data bit 14
DQ15 M15 I/O SDRAM Data bit 15
AVD N1 PLL Supply Voltage
N.C. N2
VDDS N3 3.3 V supply voltage
VSS N4 Ground
VSS N5 Ground
VDDC N6 1.5V core supply voltage
VSS N7 Ground
VDDC N9 1.5 V core supply voltage
VSS N10 Ground
VSS N12 Ground
VSS N13 Ground

DQ13 N15 I/O SDRAM Data bit 13
AVS P1 PLL Ground
VSS P2 Ground
A7 P3 Out SDRAM Address bit 7
DQ7 P8 I/O SDRAM Data bit 7
VDDS P13 3.3 V supply voltage
VSS P14 Ground
A4 R1 Out SDRAM Address bit 4
DQ8 R8 I/O SDRAM Data bit 8
VSS R9 Ground
VSS R11 Ground

8.3.3 IC7100 - FLI2310 - Faroudja Digital Video Format Converter
BLOCK DIAGRAM
Figure 9-25: FLI2310 Simplified Internal Block Diagram
Input Processor
with Auto Sync
and auto Adjust
Noise Reducer,
Deinterlacer, Frame
Rate Converter and
SDRAM interface
Port 2
8-bit
656 Input
Port 1
8/16/24-bit
RGB/YCrCb
Input
Clock
Generation
PLLs
2Mx32
SDRAM
(external)
Vertical and
Horizontal
Scalers
Vertical and
Horizontal
Enhancers
Output
Processor
16/20/24-bit
RBG/YCrCb
Digital Outputs
Figure 8-14

PIN CONFIGURATION
Figure 3.1: Pinout Information
1 5 5
1 5 0
1 4 5
1 4 0
1 3 5
1 3 0
1 2 5
1 2 0
1 1 5
1 1 0
1 0 5
1
5
1 0
1 5
2 0
2 5
3 0
3 5
4 0
4 5
5 0
5

5
6

5
6

0
1

0

0
9

5
9

0
8

5
8

0
7

5
7

0
2

0

5
1

9

5
2

0

0
1

6

0
1

6

5
1

7

0
1

7

5
1

8

0
1

8

5
1

9

0
HSYNC1_PORT1
VDD1
B/Cb/D1_0
VSS
IN_CLK1_PORT1
FIELD ID1_PORT1
VSYNC1_PORT1
HSYNC2_PORT1
IN_CLK2_PORT1
FIELD ID2_PORT1
VSYNC2_PORT1
B/Cb/D1_6
B/Cb/D1_5
B/Cb/D1_4
B/Cb/D1_3
B/Cb/D1_2
B/Cb/D1_1
B/Cb/D1_7
VDDcore1
VSScore
R/Cr/Cb Cr_0
R/Cr/Cb Cr_6
R/Cr/Cb Cr_5
R/Cr/Cb Cr_4
R/Cr/Cb Cr_3
R/Cr/Cb Cr_2
R/Cr/Cb Cr_1
R/Cr/Cb Cr_7
VDD2
VSS
G/Y/Y_0
G/Y/Y_1
G/Y/Y_6
G/Y/Y_5
G/Y/Y_4
G/Y/Y_3
G/Y/Y_2
G/Y/Y_7
VDDcore2
VSScore
IN_SEL
TEST
DEV_ADDR1
DEV_ADDR0
SCLK
SDATA
RESET_N
VDD3
VSS
SDRAM DATA(0)
SDRAM DATA(2)
SDRAM DATA(1)
S
D
R
A
M

D
A
T
A
(
3
)
S
D
R
A
M

D
A
T
A
(
1
0
)
S
D
R
A
M

D
A
T
A
(
9
)
S
D
R
A
M

D
A
T
A
(
8
)
S
D
R
A
M

D
A
T
A
(
7
)
S
D
R
A
M

D
A
T
A
(
6
)
S
D
R
A
M

D
A
T
A
(
5
)
S
D
R
A
M

D
A
T
A
(
4
)
S
D
R
A
M

D
A
T
A
(
1
7
)
S
D
R
A
M

D
A
T
A
(
1
6
)
S
D
R
A
M

D
A
T
A
(
1
5
)
S
D
R
A
M

D
A
T
A
(
1
4
)
S
D
R
A
M

D
A
T
A
(
1
2
)
S
D
R
A
M

D
A
T
A
(
1
3
)
S
D
R
A
M

D
A
T
A
(
1
1
)
V
D
D
4
V
S
S
V
D
D
c
o
r
e
3
V
S
S
c
o
r
e
S
D
R
A
M

D
A
T
A
(
2
0
)
S
D
R
A
M

D
A
T
A
(
1
9
)
S
D
R
A
M

D
A
T
A
(
1
8
)
S
D
R
A
M

D
A
T
A
(
3
1
)
S
D
R
A
M

D
A
T
A
(
3
0
)
S
D
R
A
M

D
A
T
A
(
2
9
)
S
D
R
A
M

D
A
T
A
(
2
8
)
S
D
R
A
M

D
A
T
A
(
2
6
)
S
D
R
A
M

D
A
T
A
(
2
7
)
S
D
R
A
M

D
A
T
A
(
2
5
)
S
D
R
A
M

D
A
T
A
(
2
4
)
S
D
R
A
M

D
A
T
A
(
2
3
)
S
D
R
A
M

D
A
T
A
(
2
1
)
S
D
R
A
M

D
A
T
A
(
2
2
)
V
D
D
c
o
r
e
4
V
S
S
c
o
r
e
V
S
S
V
D
D
5
T
E
S
T

I
N
S
D
R
A
M

A
D
D
R
(
1
0
)
S
D
R
A
M

A
D
D
R
(
5
)
S
D
R
A
M

A
D
D
R
(
4
)
S
D
R
A
M

A
D
D
R
(
3
)
S
D
R
A
M

A
D
D
R
(
6
)
S
D
R
A
M

A
D
D
R
(
7
)
S
D
R
A
M

A
D
D
R
(
8
)
S
D
R
A
M

A
D
D
R
(
9
)
V
D
D
c
o
r
e
5
V
S
S
c
o
r
e
S
D
R
A
M

A
D
D
R
(
0
)
S
D
R
A
M

A
D
D
R
(
1
)
S
D
R
A
M

A
D
D
R
(
2
)
S
D
R
A
M

W
E
N
B/U/Pb_OUT_7
VDDcore7
VSScore
R/V/Pr_OUT_7
VDD8
VSS
G/Y/Y_OUT_7
G/Y/Y_OUT_1
G/Y/Y_OUT_2
G/Y/Y_OUT_3
G/Y/Y_OUT_4
G/Y/Y_OUT_5
G/Y/Y_OUT_6
G/Y/Y_OUT_0
R/V/Pr_OUT_0
R/V/Pr_OUT_1
R/V/Pr_OUT_2
R/V/Pr_OUT_3
R/V/Pr_OUT_4
R/V/Pr_OUT_5
R/V/Pr_OUT_6
B/U/Pb_OUT_0
B/U/Pb_OUT_1
B/U/Pb_OUT_2
B/U/Pb_OUT_3
B/U/Pb_OUT_4
B/U/Pb_OUT_5
B/U/Pb_OUT_6
VSS
VDD7
CLKOUT
VSScore
VDDcore6
TEST OUT1
CTLOUT4
CTLOUT0
CTLOUT1
CTLOUT2
CTLOUT3
TEST OUT0
TEST3
SDRAM CLKIN
SDRAM CLKOUT
VSS
VDD6
SDRAM DQM
SDRAM CASN
SDRAM BA1
SDRAM BA0
SDRAM CSN
SDRAM RASN
OE
P
L
L
_
P
V
D
D
P
L
L
_
P
V
S
S
A
V
S
S
_
P
L
L
_
B
E
1
A
V
D
D
_
P
L
L
_
B
E
1
A
V
S
S
_
P
L
L
_
S
D
I
A
V
S
S
_
P
L
L
_
F
E
A
V
S
S
_
P
L
L
_
B
E
2
A
V
D
D
_
P
L
L
_
F
E
A
V
D
D
_
P
L
L
_
S
D
I
A
V
D
D
_
P
L
L
_
B
E
2
D
A
C
_
P
V
S
S
D
A
C
_
V
D
D
D
A
C
_
V
S
S
D
A
C
_
B
_
O
U
T
D
A
C
_
G
_
O
U
T
D
A
C
_
R
_
O
U
T
D
A
C
_
A
V
D
D
B
D
A
C
_
A
V
D
D
R
D
A
C
_
A
V
D
D
G
D
A
C
_
A
V
S
S
B
D
A
C
_
A
V
S
S
R
D
A
C
_
A
V
S
S
G
D
A
C
_
C
O
M
P
D
A
C
_
R
S
E
T
D
A
C
_
V
R
E
F
O
U
T
D
A
C
_
V
R
E
F
I
N
D
A
C
_
A
V
D
D
D
A
C
_
A
V
S
S
D
A
C
_
G
R
_
A
V
S
S
D
A
C
_
G
R
_
A
V
D
D
D
A
C
_
P
V
D
D
T
E
S
T
0
T
E
S
T
1
T
E
S
T
2
X
T
A
L

I
N
X
T
A
L

O
U
T
V
D
D
9
V
S
S
H
S
Y
N
C
_
P
O
R
T
2
I
N
_
C
L
K
_
P
O
R
T
2
F
I
E
L
D

I
D
_
P
O
R
T
2
V
S
Y
N
C
_
P
O
R
T
2
V
S
S
c
o
r
e
V
D
D
c
o
r
e
8
D
1
_
I
N
_
0
D
1
_
I
N
_
7
D
1
_
I
N
_
6
D
1
_
I
N
_
5
D
1
_
I
N
_
4
D
1
_
I
N
_
3
D
1
_
I
N
_
2
D
1
_
I
N
_
1
Package: 208-pin PQFP
Note: The pinout of FLI2310, which does not have the integrated DACs, differs from the FLI230x only in
relation to the DAC related pins. The pin differences between the FLI230x and FLI2310 are detailed in
following pin descriptions.
Figure 8-15

PIN DESCRIPTION
Pin
No Pin Name I/O Type
Voltage
Tolerance Drive
Pull up/
PulldownDescription
1 HSYNC1_PORT1 Input 5v Horizontal sync or reference -CTL1 of Port 1
2 VSYNC1_PORT1 Input 5v Vertical sync or reference -CTL1 of Port 1
3 FIELD ID1_PORT1 Input 5v Odd/Even Field identification -CTL1 of Port 1
4 IN_CLK1_PORT1 Input 5v Data Clock input -CTL1 of Port 1
5 HSYNC2_PORT1 Input 5v Horizontal sync or reference CTL2 of Port 1
6 VSYNC2_PORT1 Input 5v Vertical sync or reference CTL2 of Port 1
7 FIELD ID2_PORT1 Input 5v Odd/Even Field identification CTL2 of Port 1
8 VDD1 Power 3.3 V - Power pin for IO
9 VSS Ground Ground
10 IN_CLK2_PORT1 Input 5v Data Clock input CTL2 of Port 1
11 B/Cb/D1_0 Input 5v Port 1 Digital video input (Blue/Cb/D1)
16 VDDcore1 Power 1.8 V - Power pin for core
17 VSS Ground Ground
21 R/Cr/CrCb_0 Input 5v Port 1 Digital video input (Red/Cr/CrCb)
29 G/Y/Y_0 Input 5v Port 1 Digital video input (Green/Y)
41 IN_SEL Output 5v 8 mA Output to select external video mux
42 TEST Input 5v Connect to Ground
43 DEV_ADDR1 Input 5v Device address setting 1
44 DEV_ADDR0 Input 5v Device address setting 0

Pin
Voltage
Tolerance Drive
Pull up/
PulldownDescription
45 SCLK I/O 5v 8 mA 2-wire serial control bus clock
46 SDATA I/O 5v 8 mA 2-wire serial control bus data
47 RESET_N Input 5v PU Reset
48 VDD3 Power 3.3 V Power pin for IO
50 SDRAM DATA(0) Tristate I/O 5v 4 mA PD SDRAM data bus *
56 SDRAM DATA(6) Tristate I/O 5v 4 mA PD SDRAMdata bus *
80 VDDcore4 Power 1.8 V Power pin for core
90 TEST IN Input 5V Test input-Connect to ground

Pin
Voltage
Tolerance Drive
Pull up/
PulldownDescription
91 SDRAM ADDR(10) Tristate O/P 5v 8 mA SDRAM address bus *
104 SDRAM WEN Tristate O/P 5v 8 mA SDRAM write enable *
105 SDRAM RASN Tristate O/P 5v 8 mA SDRAM row address select *
106 SDRAM CASN Tristate O/P 5v 8 mA SDRAM column address select *
107 SDRAM BA1 Tristate O/P 5v 8 mA SDRAM bank select 1*
108 SDRAM BA0 Tristate O/P 5v 8 mA SDRAM bank select 0*
109 SDRAM CSN Tristate O/P 5v 4 mA SDRAM CS *
110 SDRAM DQM Tristate O/P 5v 8 mA SDRAM DQM *
111 SDRAM CLKOUT Output 5v 12 mA Clock out to SDRAM *
114 SDRAM CLKIN Input 5v Trace delayed SDRAM Clock in
115 TEST3 Input Test input Connect to ground
116 TEST OUT0 Output Test output leave open
117 TEST OUT1 Output Test output leave open
118 CTLOUT0
Tristate O/P
5v 8 mA
Control signal output selectable as HSync1/
CSync/HRef/Monitor coast
119 CTLOUT1
Tristate O/P
5v 8 mA
Control signal output selectable as
VSync1/CRef/VRef/Film Indicator
120 CTLOUT2
Tristate O/P
5v 8 mA
Control signal output selectable as Monitor
coast/HRef/VDD_en / HSync2
121 CTLOUT3
Tristate O/P
5v 8 mA
Control signal output selectable as Film
Indicator/VRef/backlight_en/VSync2
122 CTLOUT4
Tristate O/P
5v 8 mA
Control signal output selectable as CRef/Field
ID/CSync/Monitor coast
125 CLKOUT Tristate O/P 5v 12 mA Output data rate clock
126 B/U/Pb_OUT_0 Tristate O/P 5v 8 mA Digital video output Blue/U/Pb

Pin
Voltage
Tolerance Drive
Pull up/
PulldownDescription
136 R/V/Pr_OUT_0 Tristate O/P 5v 8 mA Digital video output Red/V/Pr
148 G/Y/Y_OUT_0 Tristate O/P 5v 8 mA Digital video output Green/Y
156 OE Input 5v Output data enable for Digital video output
157 PLL_PVDD Power 1.8 V Power pin for PLL pads
158 PLL_PVSS Ground Ground for PLL pads
159 AVSS_PLL_BE1 Ground PLL Ground
160 AVDD_PLL_BE1 Power 1.8 V Power pin for PLL
161 AVDD_PLL_BE2 Power 1.8 V Power pin for PLL
162 AVSS_PLL_BE2 Ground PLL Ground
163 AVSSPLL_SDI Ground PLL Ground
164 AVDDPLL_SDI Power 1.8 V Power pin for PLL
165 AVDDPLL_FE Power 1.8 V Power pin for PLL
166 AVSSPLL_FE Ground PLL Ground
167
168
169
170
171
172
173
174
175
176
177
178
R_VSS Ground Ground
R_VDD1.8 Power 1.8 V
R_VSS Ground Ground
Reserved - Leave open
R_VDD Power 3.3 V
R_VSS Ground Ground
R_VDD Power 3.3 V
R_VSS Ground Ground
R_VDD Power 3.3 V
R_VSS Ground Ground

181
182
183
184
185
186
187
188 TEST0 Input 5v Test pin connect to ground
191 XTAL IN Input External parallel crystal oscillator
192 XTAL OUT Output External parallel crystal oscillator
195 CLK_PORT 2 Input 5v 4 mA Port 2 - Data Clock input
196 D1_IN_0 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input
206 FIELD ID_PORT 2 Input 5v 4 mA Port 2 - Odd/Even Field identification
207 VSYNC_ PORT 2 Input 5v 4 mA Port 2 - Vertical sync or reference
208 HSYNC_PORT 2 Input 5v 4 mA Port 2 - Horizontal sync or reference
Note:1) * - The connection of these pins depends on the type of external SDRAM used. See Appendix 3
2) For 16/20 bit Y and muxed C output modes see Appendix 2 for pin configuration
Pin
Voltage
Tolerance Drive
Pull up/
PulldownDescription
179
180
R_VSS Ground Ground
R_VDD Power 3.3 V
R_VSS Ground Ground
R_VSS Ground Ground
R_VDD Power 3.3 V
R_VDD Power 3.3 V

8.3.4 IC7304 Sil9030CTU-7 HDMI Transmitter
BLOCK DIAGRAM
HDCP
Encryption
Engine
HDCP
Keys
EEPROM
PanelLink
TMDS
Digital
Core
Video Data
Capture /
DE Gen /
656
Logic
Block
I
2
C
Slave
DE
D[23:0]
CSDA
CSCL
HSYNC
VSYNC
IDCK
EXT_SWING
TXC
TX0
TX1
TX2
RESET#
Audio Data
Capture
Logic
Block
SPDIF
MCLK
INT
HPD Receiver Sense + Interrupt Logic
audio data
encrypted
data
SCK
WS
SD[3:0]
DSDA
DSCL
E-DDC
Master
4:2:2 to
4:4:4
CSC XOR
Registers
----------------
Configuration
Logic Block
CI2CA
Figure 8-16

PIN CONFIGURATION
HSYNC
VSYNC
CGND
CVCC18
SPDIF
MCLK
SD3
SD2
SD1
SD0
WS
SCK
IOVCC
IOGND
CGND
CVCC18
A
G
N
D
T
X
C
-
T
X
C
+
A
V
C
C
T
X
0
-
T
X
0
+
A
G
N
D
T
X
1
-
T
X
1
+
A
V
C
C
T
X
2
-
T
X
2
+
A
G
N
D
P
V
C
C
2
P
G
N
D
2
CVCC18
CGND
IOGND
IOVCC
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
CVCC18
CGND
D
1
3
D
1
2
D
1
1
D
1
0
D
9
I
D
C
K
D
8
D
7
D
6
D
5
I
O
V
C
C
I
O
G
N
D
C
G
N
D
C
V
C
C
1
8
D
4
D
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
7
3
7
4
7
5
7
6
N
C
INT
HPD
DSDA
DSCL
17
18
19
20
R
S
V
D
L
P
G
N
D
1
P
V
C
C
1
E
X
T
_
S
W
I
N
G
2
1
2
2
2
3
2
4
CI2CA
RESET#
CSCL
CSDA
41
42
43
44
D
2
D
1
D
0
D
E
7
7
7
8
7
9
8
0

SiI 9030
80-Pin TQFP
) (Top View
Figure 8-17

EN 158 3139 785 32804
Figure 9-1
U
P
D
A
T
E

S
C
R
E
W
S

C
O
U
N
T

&
A
D
D

I
N
D
I
C
A
T
I
O
N

F
O
R

D
V
D
R
3
5
9
X
H

S
P
E
C
I
F
I
C

I
T
E
M
S
1
6
1
1
8
4
2
3
0
2
4
0
1
3
1

(
D
V
D
R
3
5
7
0
/
9
0
H

A
P
/
L
A
T
A
M
,

D
V
D
R
3
5
7
5
/
7
7
/
9
5
/
9
7
H
)

1
8
9
1
8
7
1
8
8
1
0
0
2

(
-
-
1
0
1
2
)
1
0
0
1
1
0
0
8
1
0
0
6

(
D
V
D
R
3
5
7
0
/
9
0
H

A
P
/
L
A
T
A
M
,

D
V
D
R
3
5
7
5
/
7
7
/
9
5
/
9
7
H
)

1
0
0
4
1
0
0
3
1
0
0
5
1
8
0
1
9
0

(
D
V
D
R
3
5
7
0
/
9
0
H

A
P
/
L
A
T
A
M
,

D
V
D
R
3
5
7
5
/
7
7
/
9
5
/
9
7
H
)

1
0
0
7
1
1
0
1
2
7
1
0
1
1
2
1
1
2
5
1
2
4
1
2
6
1
8
1
1
2
3
1
8
2
1
2
8
1
2
9
1
3
0
1
2
2 1
0
0
2

(
-
-
1
0
1
1
)
1
0
0
2

(
-
-
1
0
1
0
)
1
8
3
2
7
0

(
4
X
)
2
5
6

(
2
X
)
2
5
0
2
6
9

(
4
X
)
2
6
7

(
2
X
)
2
7
2

(
4
X
)
2
5
8

(
D
V
D
R
3
5
7
0
/
9
0
H

E
U
)

(
3
X
)

2
8
1

(
D
V
D
R
3
5
7
5
/
7
7
/
9
5
/
9
7
H
&

D
V
D
R
3
5
7
0
H

A
P
/
L
A
T
A
M
)

(
2
X
)
2
7
5
2
5
7

(
4
X
)
1
8
5
2
6
2

(
D
V
D
R
3
5
7
0
/
9
0
H

E
U
)

(
3
X
)
2
6
4

(
D
V
D
R
3
5
7
0
/
9
0
H

A
P
/
L
A
T
A
M
)
2
7
9

(
D
V
D
R
3
5
7
5
/
7
7
/
9
5
/
9
7
H

E
U
)

(
3
X
)
2
6
5
2
5
9
2
6
8

(
4
X
)
2
7
1

(
4
X
)
2
5
1
2
5
4
2
5
3

(
2
X
)
2
5
5
2
5
2

(
4
X
)
2
7
32
6
1

(
D
V
D
R
3
5
7
0
/
9
0
H

E
U
)

(
3
X
)
2
6
3

(
D
V
D
R
3
5
7
0
/
9
0
H

A
P
/
L
A
T
A
M
)

(
7
X
)
2
7
8

(
D
V
D
R
3
5
7
5
/
7
7
/
9
5
/
9
7
H

E
U
)

(
3
X
)
2
7
6

(
4
X
)
2
7
7

(
3
X
)
2
7
4

(
2
X
)
1
9
3
1
9
1

(
D
V
D
R
3
5
9
X
H
)

(
4
X
)
1
9
2

(
D
V
D
R
3
5
9
X
H
)
1
8
6
2
6
0
2
8
2

(
D
V
D
R
3
5
7
0
/
9
0
H

A
P
/
L
A
T
A
M
,

D
V
D
R
3
5
7
5
/
7
7
/
9
5
/
9
7
H
)

0
7
0
4
-
2
4
E
x
p
lo
d
e
d
V
ie
w
3
1
3
9
-2
4
9
-4
0
9
2
1
-1
1
0
-1
-a
2
.p
d
f 2
0
0
7
-0
4
-2
4
P
0
0
2
P
0
0
1
Exploded View of the set
9. Exploded view & Service parts list

EN 159 3139 785 32804 9. Exploded view & Service parts list
DVDR3570H/75/97
0110 313924415631 COVER TRAY
0180 313924126261 SPRING EMC
0181 313924126291 SPRING AV
0185 313911426671 BUSH, AC CORD
0190 313924416811 SHIELD HDMI
0193 313924160931 SPRING ESD DVDR3570H
0230 313924126301 PLATE REAR
0240 313924124232 COVER TOP
0271 252220098475 SCR PAN TORX ST BK #6-32X6
0341 242254901506 REMOTE CONTROL
0345 242207098231 MAINSCORD IEC /97 only
0345 242207098233 MAINSCORD AUS 7A5 1M8 VH BK B
/75 only
0350 242207600718 CBLE CINCH 1M5 CINCH RDYEWH B
0487 242207600885 CBLE IEC-M 1M47 IEC-F BK B
1001 313924851681 ANALOG BOARD
1002 313924852031 FRONT BOARD
1003 313924851712 PCBAS DIGI DVDR3570H AP BOARD
1004 313924713532 PSU BOARD PIE
1005 282206200172 HDD 3.5 160GB WD1600AVBB-63SY
1006 313924889141 PSCAN HDMI BOARD
1007 313924800333 DRIVE D5.2 CLOSED
1008 282203100057 FAN 12VDC 1.2W 2850RPM B
8001 313924102151 CBLE VH 05P/140/05P VH 20ST BK
8002 313911027881 CBLE PH 06P/180/06P PH 26ST BK
8003 313924103801 CBLE EH 04P/140/04P LC-L UL
8004 313924103761 CBLE EH 04P/280/04P LC-L UL
8005 313911028311 CBLE PH 12P/280/12P PH 26ST BK
8006 310330890611 CWAS 03PH/03PH 220 BK AWG26
8007 313924102101 FFC FOIL 24P/220/24P BD 1MMP
8008 313924102511 FFC FOIL 18P/280/18P BD 1MMP
8009 313913103491 FFC FOIL 06P/220/06P BD 1MMP
8011 313924100301 FFC FOIL 24P/140/24P BD 1MMP
8012 313911035501 FFC FOIL 08P/180/08P 1MMP BD
8013 310330890562 CWAS 05PH/05PH 340 5P BK 26S
8014 313924102071 FFC FOIL 09P/340/09P BD 1MMP
8015 313924102181 FFC FOIL 14P/280/14P BD 1MMP
8017 313924102141 CBLE IDE 40P/340/40P IDE UL
8018 313924102651 CBLE IDE 40P/380/40P IDE UL
8019 242207600786 CBLE USB-A 0M3 PH 5P BK B
8026 313924102211 FFC FOIL 40P/140/40P BD 0.5MMP
8030 313911027931 CBLE PH 07P/100/07P PH 26ST BK
P001 314107942981 CAB FRONT ASSY
P002 314107936761 FRAME ASSY
DVDR3590H/75/97
0110 313924416861 COVER TRAY
0180 313924126261 SPRING EMC
0181 313924126291 SPRING AV
0185 313911426671 BUSH, AC CORD
0190 313924416811 SHIELD HDMI
0191 313924409101 HDD DAMPER
0193 313924160931 SPRING ESD DVDR3570H
0230 313924126301 PLATE REAR
0240 313924124232 COVER TOP
0271 252220000027 SCR WAFER PH STZN BU 6/32X12
0345 242207098231 MAINS CORD IEC /97 only
0345 242207098233 MAINSCORD AUS 7A5 1M8 VH BK B
/75 only
0350 242207600718 AV CABLE 1M5
0487 242207600885 RF CONNECTING CABLE
1001 313924851681 ANALOG BOARD
1002 313924852031 FRONT BOARD
1004 313924713532 PSU BOARD PIE
1005 282206200152 HDD 3.5 250GB ST3250820ACE B
1007 313924800333 DRIVE D5.2 CLOSED
1008 282203100057 FAN 12VDC 1.2W
8001 313924102151 CBLE VH 05P/140/05P VH 20ST BK
8002 313911027881 CBLE PH 06P/180/06P PH 26ST BK
8003 313924103801 CBLE EH 04P/140/04P LC-L UL
8004 313924103761 CBLE EH 04P/280/04P LC-L UL
8005 313911028311 CBLE T PH 12P/280/12P PH 26ST BK
8006 310330890611 CWAS 03PH/03PH 220 BK AWG26
8007 313924102101 FFC FOIL 24P/220/24P BD 1MMP
8008 313924102511 FFC FOIL 18P/280/18P BD 1MMP
8009 313913103491 FFC FOIL 06P/220/06P BD 1MMP
8011 313924100301 FFC FOIL 24P/140/24P BD 1MMP
8012 313911035501 FFC FOIL 08P/180/08P 1MMP BD
8013 310330890562 CWAS 05PH/05PH 340 5P BK 26S
8014 313924102071 FFC FOIL 09P/340/09P BD 1MMP
8015 313924102181 FFC FOIL 14P/280/14P BD 1MMP
8017 313924102141 CBLE IDE 40P/340/40P IDE UL
8018 313924102651 CBLE IDE 40P/380/40P IDE UL
8026 313924102211 FFC FOIL 40P/140/40P BD 0.5MMP
8030 313911027931 CBLE PH 07P/100/07P PH 26ST BK
P001 314107942981 FRONT CABINET ASSY
P002 314107936761 FRAME ASSY


EN 160 3139 785 32804 9. Exploded view & Service parts list
DVDR3590H/93
110 313924416861 COVER TRAY
180 313924126261 SPRING EMC
181 313924126291 SPRING AV
185 313911426671 BUSH, AC CORD
190 313924416811 SHIELD HDMI
191 313924409101 HDD DAMPER
193 313924160931 SPRING ESD DVDR3570H
230 313924126301 PLATE REAR
240 313924124232 COVER TOP
271 252220000027 SCR WAFER PH STZN BU 6/32X12
345 242207098232 MAINSCORD CHN 6A 1M8 VH BK B
350 242207600718 AV CABLE 1M5
360 313924527522 UM DVDR3570H/AP ENGLISH
380 313924527482 QSG DVDR3570H/AP ENGLISH
397 313924527462 QSG DVDR3570H/AP SIMP CHINESE
400 996510007956 Warranty Leaet
401 314101616726 LOCAL GUARANTEE CARD
404 314101617877 SERVICE CARD
487 242207600885 RF CONNECTING CABLE
650 313924631501 BOX DISPLAY DVDR3590H/93
670 313911622511 PE BAG 9012540010
1001 313924851681 ANALOG BOARD
1002 313924852031 FRONT BOARD
1004 313924713532 PSU BOARD PIE
1005 282206200152 HDD 3.5 250GB ST3250820ACE B
1007 313924800333 DRIVE D5.2 CLOSED
1008 282203100057 FAN 12VDC 1.2W
8001 313924102151 CBLE VH 05P/140/05P VH 20ST BK
8002 313911027881 CBLE PH 06P/180/06P PH 26ST BK
8003 313924103801 CBLE EH 04P/140/04P LC-L UL
8004 313924103761 CBLE EH 04P/280/04P LC-L UL
8005 313911028311 CBLE T PH 12P/280/12P PH 26ST BK
8006 310330890611 CWAS 03PH/03PH 220 BK AWG26
8007 313924102101 FFC FOIL 24P/220/24P BD 1MMP
8008 313924102511 FFC FOIL 18P/280/18P BD 1MMP
8009 313913103491 FFC FOIL 06P/220/06P BD 1MMP
8011 313924100301 FFC FOIL 24P/140/24P BD 1MMP
8012 313911035501 FFC FOIL 08P/180/08P 1MMP BD
8013 310330890562 CWAS 05PH/05PH 340 5P BK 26S
8014 313924102071 FFC FOIL 09P/340/09P BD 1MMP
8015 313924102181 FFC FOIL 14P/280/14P BD 1MMP
8017 313924102141 CBLE IDE 40P/340/40P IDE UL
8018 313924102651 CBLE IDE 40P/380/40P IDE UL
8026 313924102211 FFC FOIL 40P/140/40P BD 0.5MMP
8030 313911027931 CBLE PH 07P/100/07P PH 26ST BK
P001 314107942981 FRONT CABINET ASSY
P002 314107936761 FRAME ASSY


EN 161 3139 785 32804 10. Revision List
10 REVISION LIST
Version 1.0
* Initial Release
Version 1.1
* Adding information for DVDR3590H/97
* Deleting DVDR3570H/55/96 information
* Update Service Parts List
Version 1.2
* Adding diversity information
* Adding VFD display info while formatting HDD
Version 1.3
Version 1.4

PHILIPS Service Manual

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Published by KC-TE 0718 V&MA Printed in the Netherlands Subject to modication EN 3139 785 32804

Copyright 2007 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.

CNA output is only available in the 64-pin PAP package

Active high for TPS205xA series

Active high for TPS205xA series

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