GOKARAJURANGARAJU INSTITUTE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION & ANSWERS FOR
MICROCONTROLLERS AND ITS APPLICATIONS
BTECH IV-I SEMESTER (ECE A & B)






N SWETHA
Asst. Professor
ECE Dept.
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CHAPTER IV

REAL TIME CONTROL: TIMERS
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Q. Compare the features between programmable and free running timers.
Sol: The 8051 comes equipped with two timers, both of which may be controlled, set, read, and
configured individually. The 8051 timers have three general functions: 1) Keeping time and/or
calculating the amount of time between events, 2) Counting the events themselves, or 3)
Generating baud rates for the serial port. Obviously, one of the primary uses of timers is to
measure time. We will discuss this use of timers first and will subsequently discuss the use of
timers to count events. When a timer is used to measure time it is also called an "interval timer"
since it is measuring the time of the interval between two events.
PROGRAMMABLE TIMERS IN MCUS
A timer is a counter that receives the count pulses at a prefixed regular intervals and
which time outs on each overflow. A timer can also be used as a counter when instead of internal
clock pulses the external inputs for counting are given. At the timeout, an interrupt occurs which
initiates the ISR
Programming features:
a. Timer start & stop:
In 8051: for start TRx=1
for stop TRx=0
In 68HC11/12: start of a timer cannot be programmed since it is a free-
running timer.
b. Input by prescaling the clock pulses: let P be a factor by which input clock pulses divide
before feeding, T be time interval of clock pulse.
In 8051 P.T: not programmable
In 8096 P.T: 2us
In 68HC11/12 P is programmable by PR0 and PR1
c. Loading a count value at the start: If count value=x, overflow event occurs after 2
n
-x. Timer
timeouts after interval (2
n
-x).P.T
In 8051 x can be loaded and programmable
In 68HC11/12 not programmable
d. Count value loading at start and then auto reload: In certain MCUs, x as well as its auto reload
on an overflow interrupt is programmable.
In 8051, 8052 mode2
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e. Overflow events: Overflow sets a flag inorder to indicate this overflow as well as pending
interrupt routine execution. Ex:TF0 in 8051
An Overflow event is usable to initiate an external event using an ISR. For example, a robotic
arm movement. The ISR can update a time span by keeping a memory location.
Drawback of programmable timers:
No accounting for latency period of ISR.
No accounting for Idle interval of the timer.
Hence, not appropriate for real time control.
FREE RUNNING COUNTER
It is a counter which (i) does not have a counter stop and value load programmability feature.
(ii) once it starts it keeps running endlessly even after its overflow.
Therefore, a free running counter keeps a record of the actual time because there is no latency
period and no Idle interval of the timer. Example, it is like a moving needle that shows seconds
in a clock.
Problem: An 8-bit timer is programmed to receive internal pulses at the rate of 4us.
A. what should be value of x preloaded so that it time outs and generates overflow after
100us.
Sol: (2
n
-x).P.T = 100us
(2
8
-x).1.4us = 100us
x = E7H
B. If internal clock pulse inputs are at the rate 1us, what should be pre-scaling factor, P.
Sol: P.T = 4us
P=4
C. write a program for the above using 8051.
Sol: for 12MHZ clock, T=1us
no prescaling factor in 8051
(2
8
-x).1.1us = 100us
x=9CH
MOV TL0, #9CH
MOV TMOD, #20H
SETB TR0
Problem: move a robotic arm for 1024.P.T seconds.
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Sol: initial value: 2
16
-1024
timer1 in mode1
Step1: Start the robot arm by sending an outbit=1 and start timer TR1=1.
Step2: On interrupt from T1 after overflow after 1024.P.T, we can send outbit=0 and
stop bit.
Problem: Move a robot arm for (4x 2
16
+1024 ).P.T. what is the interval for which the arm
is moved if P=8 and internal clock rate is 1us.
Sol: Start the robot arm by sending an outbit=1 and start timer TR1=1.
The ISR should send outbit=0 on fifth time overflow and stop the arm.
Total time interval = (4x 2
16
+1024 ).8.1us
= 2.1s
Problem: A 16-bit free running counter is regularly getting inputs at 1us.
(i) what will be time interval for its successive overflows?
Sol: 2
16
x 1us = 65536us
(ii) how many overflows will occur in one second?
Sol: 1s/ 65536us = 15
(iii) If counter reads 0000H now, what will be its reading after 1s?
Sol: after 15 overflows, the counter reads 0000H
Time for 15 overflows = 15x 65536us
= 0.983040 (still not 1second)

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(iv) If the counter reads F000H now, then what will be its reading after 1second. How many
overflows will now occur in one second?
Sol: when the initial reading is F000H, first overflow will be quicker.
After 15 overflows,
Reading = F000H + 1s - 0.983040
1us
= F000H + 4240H
= 13240H (one overflow plus 3240H)
Therefore, total overflows = 16
Problem: In 8096, the count inputs to the 16-bit timer are at intervals of 2us. It internally
drives after pre scaling by a fixed factor of 8.
(i) What shall be the time elapsed when its count value at an instant t1 is F0A3H from its
last overflow?
Sol: (F0A3H 0000H) x 2us
= 0.985s
(ii) What shall be the time elapsed when its count value at an instant t2 is F1A3H assuming
that t2 is before timer overflow?
Sol: (F1A3H F0A3H) x 2us
= 512us
(iii) What shall be the time elapsed b/w t3 & t2, assuming its count value at t3 is 02A3H &
t3 instant occurs after one overflow.
Sol:
[(FFFFH F1A3H + 1) + (02A3H-0000H)]x 2us
= 8704us
(iv)What shall be the time elapsed b/w t4 & t2, assuming its count value at t4 is 11A3H & t4
instant occurs after four overflows.
Sol:[(FFFFH F1A3H + 1) + 3 x (1+FFFFH) + (11A3H-0000H)]x 2us
= 16384us
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Q. Explain the different types of timer interrupts in microcontrollers.
Sol: A timer counts the equal interval clock pulses from an oscillator circuit. The pulses are used
after suitable fixed or programmable pre-scaling factor. A timer can be used in different modes
and states as shown in fig. (b).

Input Capture interrupt is used for measuring frequencies and time (to capture clock events).
Input capture register along with timer is used to capture the exact instant or time interval
between two instants.


Out compare Interrupt toggles outputs and generates interrupts on each successful comparison.
Free running counter can be used to raise an interrupt when the timer value equals a preset value
in the Out-compare register .
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Real time clock: RTC can also be used as a timer. But interrupts from this timer once enabled
cannot be disabled. The word real time is used because it never stops and cannot be reset. The
interrupts from this timer are the real time clock ticks, which also update time information at
certain memory addresses.

Problem: A 16-bit free running timer with count inputs at intervals of 2us has a Out-
compare register OC1. How will you move a robotic arm for 16s using OC1.
Sol: Step1: assume two ISRs ISR1& ISR2
ISR1
executes on timer overflow.
continuously updates memory location M1 to keep track of no. of
overflows.
starts the arm at initial interrupt.

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ISR2
executes OCI.
stops the robotic arm.
step2: Initial conditions-
Mask timer & OC overflows.
Assume two locations M1 & M2 whose addresses are FFH & 00H.
step3: ISR1-
Start robotic arm.
Disable interrupts.
Read count value(x).
Load OC reg. with value (16s)that has to be compared with timer
overflows to stop the robotic arm.
No. of overflows in 16s = 16s
2
16
x 2us
= 122 = 7AH
if initial count is x,
after 16s,count = x + 16s 122x 2
16
x 2us
2us
= x + 1200H
Increment M1. set M2 = FFH
Enable OC, unmask OCI
Set primary enable bit of interrupt control system (IE.7 of 8051)
step4: ISR2-
If M1 < 122, Enable out comparison.
If M1 = 122, Disable OCI.
Problem: Find the time taken by a weight lifter for lifting the load from start to end. Use
input capture register to capture the count value x and generate an input capture
interrupt(IC). MCU timer is 16-bit with count inputs at intervals of 2us. Assume that an
input port bit gets a edge transition in both instances from an appropriate interfacing
circuit.
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Sol: Step1: assume two ISRs ISR1& ISR2
ISR1
executes on timer overflow.
continuously updates memory location M1 to keep track of no. of
overflows.
ISR2
executes on ICi and captures into ICr.
step2: Initial conditions-
Mask timer overflow & IC interrupts.
Assume three locations M1, M2 & M3.
M1: 8-bit location to store No. of overflows
Set to FF initially
M2, M3: 16-bit locations that stores count values
Reset to 0000H initially
step3: ISR1-
If ICi enabled, M1 = M1+1.
If ICi masked, mask TOVi.
step4: ISR2-
capture x.
If M2 = 0000H, save 16-bit count at M2 & M2+1 locations.
On next ICi, if M2 0000H & M3 = 0000H, save 16-bit count x at
M3 & M3+1 locations.
mask both next ICi and TOVi.
Time interval(T) = (M3-M2) x 2us if no
overflows
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Problem: Suppose, there is a microwave oven to be started by a switching on event and the
oven is to be programmed to run for a prefixed interval of 16s. Give steps for using both IC
and OC interrupts.
Q. what are real time clock interrupts. Give an example.
Sol: In real time operating systems, there are many tasks running concurrently. For every task,
there are three parameters:
Release time (Ri): It is the time at which the task begins.
Periodicity (Pi): It is the time at which the same task again executes.
Execution time (Ei): It is the time for completion of that task.

Therefore, all tasks are provided with their own timers and these timers get their clock from
RTC.
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For example, MC68HC11 has a 13-bit Real time counter.
RTC interrupts will occur at intervals = r x 2
13
x T
Where r : special real time clock case pre-scaling factor. It is programmed by RT0 & RT1 (1,2 4
or 8)
In some MCUs, RTC interrupts initiates an ISR.
ISR performs one of the following:
Increments the memory location M that updates time and enable next RTC
interrupt.
After successive intervals of r x 2
13
x T RTC interrupts are generated.
RTC interrupts are runned at regular intervals by the s/w to initiate and
synchronize the execution of the number of tasks.

Another example, 8096 processor that uses RTC out compare interrupt (RTCOC)
RTCOC ISR:
Read M.
Increment system time at that location.
Update system clock information.
Enable next real time clock out compare interrupt.
A RTC interrupts at r x 2
13
x T and normal OC interrupts at x.T .
Problem: what will be the intervals between successive real time interrupts, in 68HC11
with 8MHz x-tal when p is set 1 and r is programmed as 1,2,4,8. (T=0.5us)
Sol: P=1
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When r=1, interrupt interval = r x 2
13
x T
= 1 x 2
13
x 0.5us
= 4.096ms
When r=2, interrupt interval = 2 x 2
13
x 0.5us
= 8.192ms
When r=4, interrupt interval = 4 x 2
13
x 0.5us
= 16.384ms
When r=8, interrupt interval = 8 x 2
13
x 0.5us
= 32.768ms
Problem: Assume that the ISR for RTC interrupt service uses a memory location M with
initial value of 64 and decrements M on each successive interrupt. When M=0, it calls a
task j? (i)What are the time intervals after which task j is called successively? (r=1)
Sol: Sol: time interval = 1 x 2
13
x 0.5us = 4.096ms
Task j is called after 64 x 4.096ms = 262.144ms
(ii)What should be the M initial value if a stepper motor is to be moved one step after every
20ms?
Sol: M = 20ms = 4.096ms
= 4.88 (one step=5)
Q. Define Software timers. Compare Software timers interrupts with out-compare
interrupts.
Sol: Software timers:
It is used to generate interrupts at any instance.
Count instance is compared with specific timer.
It sets a flag called software interrupt flag.
It initiates the ISR.
It uses a memory location or register to store the count value, similar to OC interrupt.
For example: 80x96, 68HC11 have 4 SWTs.
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Q. Define the following terms.
Interrupt service latency
Interrupt service Intervals
Interrupt Density
Sol: Interrupt service latency: Interrupt latency is the time between the generation of an interrupt
by a device and the servicing of the device which generated the interrupt. For many operating
systems, devices are serviced as soon as the device's interrupt handler is executed. Interrupt
latency may be affected by interrupt controllers, interrupt masking, and the operating system's
(OS) interrupt handling methods. It is denoted by T
lat
.
Latency when no higher priority interrupt is pending:-
T inst. (longest instruction execution period). Ex: DIV
Tenwait during which the interrupt remains disabled and waits for enabling the
interrupt .
Tend - time taken in re-assigning priorities, re-enabling and retrieving the stack.
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Latency when no higher priority interrupt is pending:-
T inst. (longest instruction execution period). Ex: DIV
Tenwait, during which the interrupt remain disabled and waits for enabling the
interrupt. ex: 68HC11 automatically does this. Latency =
Tenwait + Tend where time taken in reassigning priorities,
re- enabling and retrieving the stack)
Tinitial, to disable interrupts and save CPU registers on to stack.
Latency when higher priority interrupt is pending:-
Tinst.
Tinitial
Tend
TH (initializing, execution and ending of pending higher priority ISR)
Worst case latency = Tinst. + Tinitial +Tend + TH
Interrupt service intervals:-
Interrupt service period = Tinitial +Texec + Tend
If T
i
intv
is the interrupt interval between the successive i
th
interrupt events, then time spent in an
interrupt service = T
i
/ T
i
intv

Interrupt density:-
If there are n interrupts,
Interrupt density = T
i i=1,2-----n

T
i
intv


Problem: A service routine is executing an instruction of 3us when the interrupt occurs.
Longest inst. can take 20.5us. The initial terminating actions take 10.25us before switching
to new routine and the initial actions, before execution of the task related inst. starts take
8.25us.
(i) What is the latency if new routine is called instantaneously, when the new routine has
higher priority?
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Sol:



(ii) What is the latency if the present routine has critical region of duration 24us in which it
disables the interrupts and enables on exiting the region and then a new routine is called
instantaneously?
Sol: TL = 21.5us + 24us
= 45.5us
(iii) What is the latency if new routine cannot start instantaneously, but only at the end of
the present routine(60us) as in 68HC11?
Sol: TL = 60us + Tinitial + Tend
= 78.5us
(iii)What is the worst case latency period when there are other three highest, second
highest and third highest interrupts pending, which take 80us,40us & 100us, and if a new
routine cannot start instantaneously but only at the end of present routine(60us) as in
68HC11?
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Sol:
Worst case TL = (0 + 60us + 1us)+(0 + 80us + 1us)+(0 + 40us + 1us)+(0 + 100us + 1us)
= 284us
Problem: Assume that the RTC interrupt occurs repeatedly every 32.768ms, and RTC ISR
executes for 32.768us, the overflow interrupts occur every 500ms and servicing ISRs takes
800us and the serial UART interrupts assuming 10 bits per character, occur at 56kbps and
ISR for sending a character takes 17.8us.
(i)What is the fraction of time spent by the CPU in the interrupt servicing?
(ii)What is the interrupt density?
Sol :(i) for RTC,
Time spent = T
i
/ T
i
intv

= 32.768us/ 32.768ms
= 0.001
for overflow interrupts,
Time spent = 800us / 500ms = 0.0016
For serial UART interrupts,
10 bits per character occur at 56kbps
For one character: 56kbps/10 = 5600
Time spent = 17.8us / 1/5600
= 0.09968
(ii) Interrupt density = T
i
/

T
i
intv


= (1+1.6+99.68) x 10
-3

= 0.1026
Q. How do you set the TH and TL values for Timer0 in mode0 operation?
Sol: In 8051, timer0 consists of two registers TH0 and TL0. The numbers these registers
include represent a lower and a higher byte of one 16-digit binary number.
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There are two SFRs associated with it. One to set the mode (TMOD) and another to start/stop the
timer (TCON).
TMOD Register (Timer Mode) : This register selects mode of the timers T0 and T1. As
illustrated in the following picture, the lower 4 bits (bit0 - bit3) refer to the timer 0, while the
higher 4 bits (bit4 - bit7) refer to the timer 1. There are in total of 4 modes and each of them is
described here in this book.

Bits of this register have the following purpose:
GATEx starts and stops Timerx by means of a signal provided to the pin INTx :
o 1 Timer x operates only if the bit INTx is set
o 0 - Timer x operates regardless of the state of the bit INT 1
C/Tx selects which pulses are to be counted up by the timer/counter x:
o 1 - Timer counts pulses provided to the pin Tx
o 0 - Timer counts pulses from internal oscillator
TxM1,TxM0 These two bits selects the Timer 1 operating mode.
M1 M0 Mode Description
0 0 0 13-bit timer
0 1 1 16-bit timer
1 0 2 8-bit auto-reload
1 1 3 Split mode
Where x denotes 0 0r 1.
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TCON - Timer Control Register: This is also one of the registers whose bits directly control
timer operating. Only 4 of all 8 bits this register has are used for timer control, while others are
used for interrupt control.

TF1 This bit is automatically set with the Timer 1 overflow
TR1 This bit turns the Timer 1 on
o 1 - Timer 1 is turned on
o 0 - Timer 1 is turned off
TF0 This bit is automatically set with the Timer 0 overflow.
TR0 This bit turns the timer 0 on
o 1 - Timer 0 is turned on
o 0 - Timer 0 is turned off
Timer 0 in mode 0 (13-bit timer): When using this mode, the higher byte TH0 and only the first 5
bits of the lower byte TL0 are in use. With each new pulse coming, the state of the lower register
(that one with 5 bits) is changed. After 32 pulses received it becomes full and automatically is
reset, while the higher byte TH0 is incremented by 1. This action will be repeated until registers
count up 8192 pulses. After that, both registers are reset and counting starts from 0.

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Q. How do you set the registers TH and TL when changing the frequency of operation? OR
Describe with examples various modes of the 8051 timers.
Sol: 8051 timers use 1/12 of Xtal frequency, regardless of machine cycle time.
Timer Mode0: When the timer is in 13-bit mode, TLx will count from 0 to 31. When TLx is
incremented from 31, it will "reset" to 0 and increment THx. Thus, effectively, only 13 bits of
the two timer bytes are being used: bits 0-4 of TLx and bits 0-7 of THx. This also means, in
essence, the timer can only contain 8192 values. If you set a 13-bit timer to 0, it will overflow
back to zero 8192 machine cycles later.
For example, with 11.0592MHZ frequency, T = 1.085us. If a delay of 2us is to be generated,
count = 2us / 1.085us = 1.8433
As mode0 is 13-bit, resultant count = 8192 1.8433 = 8190(in decimal) = 1FFE (in hex)
Therefore, 000 11111111 11110
TH TL
TL = FF and TH = 1E respectively.
Program: consider timer0
MOV TMOD, #00H ; TIMER0 mode 0
MOV TL0, #FFH
MOV TH0, #1EH
SETB TR0 ; to start timer
JNB TF0, $ ; wait till timer overflows
CLR TF0
CLR TR0

Timer Mode1: Timer mode "1" is a 16-bit timer. This is a very commonly used mode. It
functions just like 13-bit mode except that all 16 bits are used. TLx is incremented from 0 to 255.
When TLx is incremented from 255, it resets to 0 and causes THx to be incremented by 1. Since
this is a full 16-bit timer, the timer may contain up to 65536 distinct values. If you set a 16-bit
timer to 0, it will overflow back to 0 after 65,536 machine cycles.
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Depending on the oscillator frequency, the value is loaded into registers.
For example, with 11.0592MHZ frequency, T = 1.085us. If a delay of 2us is to be generated,
count = 2us / 1.085us = 1.8433
As mode1 is 16-bit, resultant count = 65536 1.8433 = 65534.1567(in decimal) = FFFE (in
hex)
Therefore, TL = FE and TH = FF respectively.
Program: consider timer0
MOV TMOD, #01H ; TIMER0 mode 1
MOV TL0, #FEH
MOV TH0, #FFH
SETB TR0 ; to start timer
JNB TF0, $ ; wait till timer overflows
CLR TF0
CLR TR0

Timer Mode2: Timer mode "2" is an 8-bit auto-reload mode. What is that, you may ask? Simple.
When a timer is in mode 2, THx holds the "reload value" and TLx is the timer itself. Thus, TLx
starts counting up. When TLx reaches 255 and is subsequently incremented, instead of resetting
to 0 (as in the case of modes 0 and 1), it will be reset to the value stored in THx.
For example, with 11.0592MHZ frequency, T = 1.085us. If a delay of 2us is to be generated,
count = 2us / 1.085us = 1.8433
As mode2 is 8-bit, resultant count = 256 1.8433 = 254.1567(in decimal) = FE (in hex)
Therefore, TH = FE respectively.
Program: consider timer0
MOV TMOD, #02H ; TIMER0 mode 2
MOV TH0, #FEH
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SETB TR0 ; to start timer
JNB TF0, $ ; wait till timer overflows
CLR TF0
CLR TR0
Timer Mode3: Timer mode "3" is a split-timer mode. When Timer 0 is placed in mode 3, it
essentially becomes two separate 8-bit timers. That is to say, Timer 0 is TL0 and Timer 1 is TH0.
Both timers count from 0 to 255 and overflow back to 0. All the bits that are related to Timer 1
will now be tied to TH0. While Timer 0 is in split mode, the real Timer 1 (i.e. TH1 and TL1) can
be put into modes 0, 1 or 2 normally--however, you may not start or stop the real timer 1 since
the bits that do that are now linked to TH0.
TH and TL value calculation is same as mode2.
Q. Write what in the value (in hex) loaded into TH for to program timers
for mode2.
(a) MOV THO, #00H
(b) MOV THO, #12H
(c) MOV THO, #BH.
Sol:
(a) MOV THO, #00H
The numerical value in decimal can be computed by finding its 2s complement.
2s complement of 0 is 0. Thus, the value loaded into TH0 is 0.
(b) MOV THO, #12H
2s complement of 12 = 11101101 + 1
= 11101110 = (238)
10
= EEH
Thus, the value loaded into TH0 is EEH.

(c) MOV THO, #BH.
2s complement of 0B = 11110100 + 1
= (245)
10
= F5H
Thus, the value loaded into TH0 is F5H.

Q. Draw and discuss the formats of TMOD and PSW of 8051 microcontroller.
Sol:
TMOD Register (Timer Mode): This register selects mode of the timers T0 and T1. As
illustrated in the following picture, the lower 4 bits (bit0 - bit3) refer to the timer 0, while the
higher 4 bits (bit4 - bit7) refer to the timer 1. There are in total of 4 modes and each of them is
described here in this book.
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Bits of this register have the following purpose:
GATEx starts and stops Timerx by means of a signal provided to the pin INTx :
o 1 Timer x operates only if the bit INTx is set
o 0 - Timer x operates regardless of the state of the bit INT 1
C/Tx selects which pulses are to be counted up by the timer/counter x:
o 1 - Timer counts pulses provided to the pin Tx
o 0 - Timer counts pulses from internal oscillator
TxM1,TxM0 These two bits selects the Timer 1 operating mode.
M1 M0 Mode Description
0 0 0 13-bit timer
0 1 1 16-bit timer
1 0 2 8-bit auto-reload
1 1 3 Split mode
Where x denotes 0 0r 1.
PSW Register (Program Status Word) : The Program Status Word (PSW) contains several
status bits that reflect the current state of the CPU. This register contains: Carry bit, Auxiliary
Carry, two register bank select bits, Overflow flag, parity bit, and user-definable status flag. The
ALU automatically changes some of registers bits, which is usually used in regulation of the
program performing.

P - Parity bit. If a number in accumulator is even then this bit will be automatically set (1),
otherwise it will be cleared (0). It is mainly used during data transmission and receiving via
serial communication.
- Bit 1. This bit is intended for the future versions of the microcontrollers, so it is not supposed to
be here.
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OV Overflow occurs when the result of arithmetical operation is greater than 255 (deci mal), so
that it can not be stored in one register. In that case, this bit will be set (1). If there is no
overflow, this bit will be cleared (0).
RS0, RS1 - Register bank select bits. These two bits are used to select one of the four register
banks in RAM. By writing zeroes and ones to these bits, a group of registers R0-R7 is stored in
one of four banks in RAM.
RS1 RS2 Space in RAM
0 0 Bank0 00h-07h
0 1 Bank1 08h-0Fh
1 0 Bank2 10h-17h
1 1 Bank3 18h-1Fh
F0 - Flag 0. This is a general-purpose bit available to the user.
AC - Auxiliary Carry Flag is used for BCD operations only.
CY - Carry Flag is the (ninth) auxiliary bit used for all arithmetical operations and shift
instructions.
Q. Assuming XTAL = 11.0592 MHZ, write a program to generate a square wave of
50MHZ frequency on pin P2.3.
Sol: Assume timer0 in mode1 to generate a square wave of 50MHZ frequency with 50% duty
cycle.
Since XTAL = 11.0592MHZ, the counter counts up every 1.085us.
T = 1/50MHZ = 0.02us
with 50% duty cycle, Ton = Toff = 0.01us

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No. of clock cycles = 0.01us / 1.085us = 0.009
Count = 65536 0.009 = 65535.99 = FFFFH
Program:
MOV TMOD, #01H ; TIMER0 mode 1
L1: MOV TL0, #FFH
MOV TH0, #FFH
SETB TR0 ; to start timer
JNB TF0, $ ; wait till timer overflows
CLR TR0
CPL P2.3
CLR TF1
SJMP L1
Q. What value do we need to load into the timers registers if we want to have a time delay
of 5ms. Show the program for timer 0 to create a pulse width of 5ms on P2.3 ( Assume
XTAL = 11.0592MHZ).
Sol: Assume timer0 in mode1 to create a pulse width of 5ms.
Since XTAL = 11.0592MHZ, the counter counts up every 1.085us.

No. of clock cycles = 5ms / 1.085us = 4608
Count = 65536 4608 = 60928 = EE00H
Program:
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MOV TMOD, #01H ; TIMER0 mode 1
CLR P2.3
SETB P2.3
MOV TL0, #EEH
MOV TH0, #00H
SETB TR0 ; to start timer
JNB TF0, $ ; wait till timer overflows
CLR TF0
CLR P2.3
CLR TR0
Q. Write the mode2 programming of timers in 8051 in detail.
Sol: Timer Mode2: Timer mode "2" is an 8-bit auto-reload mode. What is that, you may ask?
Simple. When a timer is in mode 2, THx holds the "reload value" and TLx is the timer itself.
Thus, TLx starts counting up. When TLx reaches 255 and is subsequently incremented, instead
of resetting to 0 (as in the case of modes 0 and 1), it will be reset to the value stored in THx.
For example, with 11.0592MHZ frequency, T = 1.085us. If a delay of 2us is to be generated,
count = 2us / 1.085us = 1.8433
As mode2 is 8-bit, resultant count = 256 1.8433 = 254.1567(in decimal) = FE (in hex)
Therefore, TH = FE respectively.

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Program: consider timer0
MOV TMOD, #02H ; TIMER0 mode 2
MOV TH0, #FEH
SETB TR0 ; to start timer
JNB TF0, $ ; wait till timer overflows
CLR TF0
CLR TR0



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