Lab Lecture 1

Introduction to FPGA Programming

1. Motivation
2. Overview of HW design
3. FPGA design tools
4. Equipment
5. Demo
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! Goals:
! Prepare you to work on FPGA this semester.
! Make sure you have a good foundation.
! Question time! Raise your hand if you DONT
know following:
1. Whats the difference between concurrent and
sequential programming?
2. What ASIC and FPGA means?
3. What is an HDL?
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1. Motivation
2. Overview of HW design
3. FPGA design tools
4. Equipment
5. Demo
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! HW can be designed a many levels
! Transistors
! Logic gates
! Register Transfer Level (RTL)
! Behavioral (algorithm)
! An HDL is used to describe the design.
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Q D
CLK
! HDL (as opposed to imperative lang. (ex: C)).
! Can be used for all levels; different constructs and
styles for different levels.
! At behavioral level resembles C
! Language-level support for simulation
! Big difference between RTL level and C: HW is
intrinsically concurrent.
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! Remember for this example
! Assignment is <=
! Logical and is and
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! Hardware design is inherently concurrent (in
parallel)
! If A = 1, B = 1, D = 0, and E = 0 assigned
! What happens with HDL code below?
! (remember <= is assignment)
C <= A and B
C <= D and E
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! Hardware design is inherently concurrent (in
parallel)
! If A = 1, B = 1, D = 0, and E = 0 assigned
! What happens with HDL code below?
! (remember <= is assignment)
C <= A and B
C <= D and E
! Error because you essential have:
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and
and
A
B
D
E
C
! Main difference between C and an HDL
! C
! All code is sequential unless you explicitly use
something (fork, etc.) to make code parallel/
concurrent
! HDL
! All code is concurrent unless you explicitly use
something to make code sequential (process, etc.)
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! Different integrated circuit (IC)/fabrication models are
available on the market (ASIC, PLD, etc).
! In this course we will use an Field Programmable Gate Array
(FPGA)
! Write code in VHDL (VHSIC Hardware Description Language).
! VHSIC = Very High Speed Integrated Circuits,
! You get registers, small combinatorial networks, interconnection,
RAM, and arithmetic
! You program the device by writing a bitstream to the
configuration SRAM on the FPGA.
! These logic elements are still very low-level; we prefer to
describe our design at a higher level.
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1. Motivation
2. Overview of HW design
3. FPGA design tools
4. Equipment
5. Demo
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! We focus on Xilinx design tools since they have direct support
for their FPGA families.
! Tools are generally pretty good.
! Xilinx ISE is used to synthesize RTL, perform timing analysis,
simulation, generate bitstream and program the FPGA.
! Each function is actually performed by a different program.
! An integrated design environment provides access to all programs
and file editing.
! Main tool we use in this course.
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! What Xilinx allows you to do:
! Write VHDL/RTL code.
! Simulate it.
! Synthesize it (you usually need to guide the synthesizer)
! Review timings.
! Simulate it with timings.
! Download to FPGA and test.
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Q D
CLK
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RTL design
(.vhd/.v)
Synthesis
(xst)
Netlist
(.ngc)
Translation
(ngdbuild)
Translated file
(.ngd)
Mapping (map)
Mapped file
(.ncd)
Place & route
(par)
Routed file
(.ncd)
Bitstream gen.
(bitgen)
Bitstream
(.bit)
Behavioral
Simulation
Timing
Analysis
Constraint file
(.ucf)
1. Motivation
2. Overview of HW design
3. FPGA design tools
4. Equipment
5. Demo
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! Each PC in CS598 lab has all software installed under linux.
! CS598 TAs suggested that you request access to the lab and
computer password if you need to use them.
! We have a lab license for the software, meaning we can install it
on other computers in CS598 lab or any machine in the
department.
! Software runs on unix, but its possible to download and run on a
windows machine.
! We can also provide a development boards for each group.
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! 65 nm Virtex-5 FPGA (latest).
! Lots of connections, including
RS232, video, audio, USB,
ethernet, GPIO, SATA, and always
useful leds and switches.
! Also provides 1xPCI-E lane.
! The bitstream can be loaded on
either a flash memory or a
compact flash card (after suitable
conversion) for automatic
programming on startup.
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! USB programming cable
! Unless you use a compact
flash, you need it to
program the FPGA.
! We will use Compact
Flash Card to program
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1. Motivation
2. Overview of HW design
3. FPGA design tools
4. Equipment
5. Demo
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! FPGA flip flop
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Q D
CLK
RST
1. ISE tutorial using VHDL in lab.
2. Using Xilinx IPs: how to connect ML505 to the PCI-E bus
and perform bus transactions.
! Available at: http://www.xilinx.com/products/boards/ml505/
pcie.htm
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