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Question Paper Code :

Reg. No. :

M.E. DEGREE EXAMINATION, APRIL/MAY 2011

Applied Electronics

Second Semester

AP 9222 COMPUTER ARCHITECTURE AND PARALLEL PROCESSING

(Common to M.E. Computer and Communication, M.E. VLSI Design and
M.E. Embedded System and Technologies)
(Regulation 2009)
Time : Three hours

Maximum : 100 marks

Answer ALL questions

PART A (10 2 = 20 marks)

In parallel computing, what are shared memory-multiprocessors and

distributed-memory multicomputers?

2.

Mention an approach to solve the mismatch problem between software

parallelism and hardware parallelism.

3.

What is grain packing and scheduling in parallel programming that can help
achieve a short schedule for fast program execution?

4.

What scalability metrics affect the scalability of a computer system for a given
application?

5.

List the characteristics of CISC, RISC and Superscalar processors.

6.

How are sequential consistency and weak consistency memory models

characterized?

7.

Distinguish between asynchronous and synchronous pipeline models.

8.

Distinguish between static dataflow and dynamic dataflow computers.

9.

What are macrotasking, microtasking and autotasking levels of multitasking

employed for parallel execution on Cray X-MP or Y-MP multiprocessors?

10.

Differentiate time-sharing and space-sharing operating systems.

1.

(a)

Discuss how the instruction set, compiler technology. CPU

implementation and control, cache and memory hierarchy affects CPU
performance. Justify their effects in terms of program length, clock rate
and effective cycles per instruction (CPI).
(16)

11.

PART B (5 16 = 80 marks)

Or

12.

Compare the PRAM and VLSI models of parallel computers and mention
how these models facilitate the study of asymptotic behavior of
algorithms implementable on parallel computers.
(16)

(a)

Discuss the different network architectures used for interconnecting

multiprocessor or multicomputer systems highlighting their merits and
demerits.
(16)

(b)

Or

A web server application running on a single processor is enhanced

by a 10 processor parallel computer. The parallel processor is
20 times faster than the original processor, but is available only for
40% of the time. What is the overall speedup gained by
incorporating the enhancement?
(6)

(a)

Discuss the three speedup performance models used under different

computing objectives and resource constraints.
(10)

(ii)

13.

(i)

Discuss the design of a memory hierarchy for a computer system

satisfying the three properties of inclusion, coherence and locality with
due consideration to capacity planning and cost optimization.
(16)

(b)

Or

(b)

(i)

Briefly discuss the instruction pipeline design with reference to

instruction processing, data forwarding, hazard avoidance,
scheduling and branch handling.
(10)
A non pipelined processor X has a clock rate of 25 MHz and an
average CPI (Cycles Per Instruction) of 4. Processor Y. an improved
version of X, is designed with a live-stage linear instruction
pipeline. However, due to latch delay and clock skew effects, the
clock rate of Y is only 20 MHz. If a program containing 100
instructions is executed on both processors, what is the speed up of
processor Y compared with that of processor X?
(6)

(a)

(ii)

14.

Discuss briefly the different shared- memory organization techniques

employed in computer system to meet the memory design goal of
matching memory bandwidth to processor bandwidth.
(16)

Or
2

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Compare the four context switching policies employed in different

multithreaded architectures: switch on cache miss, switch on every load,
switch on instruction (cycle by cycle) and switch on block of instructions.

(b)

(ii)
(a)

How can an optimal choice be made among the four policies?

Parallel programming models are specifically designed for

multiprocessors, multicomputers, or vector/SIMD computers. Briefly
discuss these models that exploit parallelism with different execution
paradigms for these computers.
(16)
Or

Discuss the use of spin locks, suspend locks, binary and counting
semaphores, deadlock prevention, avoidance, detection and recovery
schemes and monitors for shared-variable programming to implement
various synchronization methods among concurrent processes.
(16)

(b)

(16)

15.

What are the advantages and shortcomings of each policy?

(i)

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