805 IEEEJOUIRNALOF SOLID-STATECIRCUITS, VOL SC-20, NO 3, JUNE 1985

Special Correspondence
A MicroPower CMOS-Instromentation Amplifier
M. DEGRAUWE, E. VI TTOZ, fvfEMBER, IEEE,
AND I. VERBAUWHEDE
Abstract A CMOS switched capacitor instromentation amplifier is
presented. Offset is reduced by an auto-zero teehnique and effects due to
charge injection are attenuated by a speciaf amplifier configuration. The
circuit which is realized in a 4-pm double poly process has an offset (a) of
370 pV, an rms input referred integrated noise (0.5 ~C/2) of 79 pV, and
consumes only 21 pW (/= = 8 kHz, V~~ = 3 V).
I . INTRODUCTION
For the real i zati on of i ntel l i gent sensors an i nstrumentati on ampl i fi er i s
ver y often r equi r ed i n or der to detect smal l di fferenti al si gnal s i n the
pr esence of a l arge common mode si gn+. Such ampl i fi ers shoul d have
ver y l ow offset and l /~ noi se, l arge CMRR, and especi al l y for bi omedi cal
appl i cati ons consume as l ess as possi bl e current ~d be abl e to oper ate at
a l ow sLl ppl y vol tage.
Fi rst an offset cancel l ati on techni que wi l l be pr esented. Further the
ampl i fi er real i zati on wi l l be di scussed and exper i mental resul ts wi l l be
gi ven.
I I AUTO-ZEROREALI ZATI ONS
Offset cancel l ati on by means of auto-zer o techni ques can be i mpl e-
mented i n di ffer ent ways [1]. Up to now basi cal l y two approaches are
used.
The fi rst method (see Fi g. l (a)) consi sts of stori ng the offset i nfor ma-
ti on at the i nput of the ampl i fi er. I deal l y the stored i nformati on wi l l be
equal to the offset val ue. However due to char ge i njecti on of the swi tch
S1, thi s vr due wi l l be si gni fi cantl y changed resul ti ng i n a degr aded offset
cancel l ati on
A second method (see Fi g. l (b)) [2] consi sts of stori ng the offset
i nformati on at the output of the fi rst ampl i fi er stage. I n practi ce the
stored offset i nformati on wi l l be about 100 ti mes the offset val ue. Ther e-
for e, the char ge i njecti on of the swi tches SI - S2 wi l l not si gni fi cantl y
degr ade the offset cancel l ati on. However the need of a two-stage ampl i fi er
gi ves ri se to potenti af stabi l i ty probl ems, degr aded noi se, and PSRR
per for mances [3].
I n thi s cor r espondence an al ternati ve auto-zer o topol ogy i s pr esented
(Fi g. l (c)) [5], [8].
AMP i s an or di nar y ampl i fi er wi th gaur ,41 (betwqen node 1 and
output) and offset YO~fl . An auxi l i ary i nput (node 2) of r educed sensi ti vi ty
(gtin A ~ ) is ad@d to the m~n ampl i fi er. I t i s contr ol l ed by a compensa-
ti on vol tage V2 stored i n capaci tor C.. The buffer i s added to speed up the
compensati on phase.
The compensati on works as fol l ows. Dur i ng ti me sl ot a, the i nput
si gnal i s sampl ed. I n the same ti me the i nput termi nal s of the mai n
ampl i fi er are short-ci rcui ted. Thi s ampl i fi er wi l l thus mnpl i fy i ts own
offset. However , due to the feedback path thr ough the auxi l i ary i nput, the
output vol tage wi l l be stabdi zed and across the store capaci tor C. ther e
Manuscnpt received October 29, 1984, rmmedDecember20, 1985 Thi> work was
partiaflysupportedby theFends National Sumsepour la Recherche Sclentlflque, PN13
M. Degrauwe and E V]ttoz are with Centre Sumse dElectFOmque et de hkcrotechmque
S A CSEMRecherche& D4veloppement( formerlyCEH) Maladkre 71,2000 Neuchatel
7, Switzerland
1. Verbauwhede was w,th CEH m 19S3 on leave from Kathoheke Umverslte,t Leuven.
Kardinaal Mercierlaan 94, B-3030 HeveFlee, Belgmm.
Flg 1 Auto-zero techmques (a) In formaacm stored at the input (b) In formatm stored
after a f]rst gam stage (c) In formatmn stored at a low sens,twe auxihary input
WIII be a voltage equal to
AI Km
L= ~+A2
(1)
At the begi nni ng of ti me sl ot b, the swi tches 3 are opened and a
char ge i s i njected at node 1. Thi s causes an addi ti onal offset AV1. ne
feedback mechani sm i s however sti l l actwe and the vol tage across C. i s
now gi ven by
A1(VO~~l+ AVI )
V2=
1+A2
(2)
At the end of ti me sl ot b the swi tch l opens and causes char ge
uqecti on (A V2) at the node 2. The vol tage at thi s node i s now gwen by
A(J%+AL) +AV2,
v2=-
1+A2
At the output node appears then a voltage equaf to
VOU,= Al.
(
(Km + AVI) +~v2.+z
1+A2
1
)
(3)
(4)
whi ch cor r esponds to an equi val ent i nput whi ch i s Al ti mes smal l er.
Fi nal l y dur i ng the ti me sl ot c the char ge stored on the capaci tor aC
(sampl e of the i nput si gnal ) i s transferred to the i ntegrati on capaci tor.
The equi val ent offset of the whol e ampl i fi er contai ns thus two resi dual
parts
the sum of the i ni ti al offset and the char ge i njecti on at node 1 whi ch
both are attenuated by a factor (1+ A ~); and
the char ge i njecti on at node 2 whi ch i s attenuated by a factor Al /A2.
The opti mal val ue of the gai n of the anxi l i l ary i nput i s obtai ned by
di fferenti ati on of (4)
(
A = (VO,fl+AV1)A1 12_1
2
AV2
)
(5)
0018-9200/85 /0600-0805$01 .00 01985 I EEE
806 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-20, NO. 3, JUNE 1985
I I
j
P
f+
t- +
1p
+;rl
IN2-
4
Fig. 2. Amplifier with auxiliary input. (a) Two parallel input stages. (b) Degenerated
current mirror.
and resul ts i n a resi dual offset of
Voff = 2.
(
(Voffl + AV, )AV2 2
Al
)
(6)
The choi ce of Al and ,42 has to be so that the ampl i fi er never saturate,
Ther efor e the method wi l l resul t i n a smal l er achi evabl e resi dual offset for
l arger suppl y vol tages. Further, i t can be shown that the offset of the
auxi l i ary ampl i fi er can be negl ected, pr ovi ded i t i s of the same or der of
magni tude as the i nput offset,
From (5) i t i s seen that the opti mum val ue of the auxi l i ary i nput
depends on the i ni ti al offset of the mai n ampl i fi er and on the cl ock
i njecti on on nodes 1 and 2. For smal l val ues of ( VOffl+ AVI ), the gai n A*
shoul d be smal l and for l arge ( Voffl + AVI ), the gai n ,4* shoul d be l arger.
For o~ti mum compensati on, the gai n A2 shoul d thus not be constant.
Recentl y i t has been shown that a quadrati c auxi l i ary i nput resul ts i n a
better offset r educti on [4].
I f a fi xed gai n A ~ is used, thi s gai n shoul d be opti mi zed for the l argest
expected val ues of the i ni ti al offset and of the cl ock feedthr ough.
I I I . CI RCUI TCONFI GURATI ONANDEXPERtMENTAL RESULTS
There are several ways to add an auxi l i ary i nput at a conventi onal
amplifier. A first method consists of using two parallel input stages (Fig.
2(a)). The rati o of the gai n Al ,/A2 wi l l be deter mi ned by the rati o of the
transconductances of the two i nput stages. The bi as current 1P* can
however not be chosen arbi trary smal l . Due to the offset vol tage VO~fl,the
current I I and 12 can devi ate as much as 10 per cent of thei r i deal val ue.
Fig. 3. Realized amplifier,
Fig. 4. Chip photograph
TABLE I
MEASUREMENTRESULTS
Gain (= 4 c/c) 20 dB
tix. clock frequency 8 kffz
(CL = 22 PF)
Offset (at 8 kHz)
{3
(u
370 JIV
Equivalent input noise (O.5 Hz-4 kHz) 79 Hv
No 1If noise was observed above 0,5 Hz
(= under limit of measurement equipwnt)
CMRR =-95 dB
Current consumption 7 PA
PsaR- (at DC) 54 dll
PSRR+ (at DC) 66 dB
Ther efor e, the current I P2 shoul d be at l east 10 per cent of IP1. Large
Al /A2 can thus onl y be achi eved by oper ati ng transi stors M3 Md much
( Ml , - M19). Those tru,si stors who oper ate i n the l i near r egi on can
deeper i n strong i nversi on than transi stors MI - M2. Thi s wi l l however
modul ate the current rati o of two current mi rrors. The buffer stages are
resul t i n a l arge vol tage dr op across Mq &fd whi ch can be unacceptabl e
si mpl e sour ce fol l ower s ( M20 M23).
for l ow-vol tage battery operati on.
The ci rcui t has been real i zed i n a 4-pm doubl e pol y CMOS process. A
An al ternati ve method consi sts of degr adi ng a current mi rror rati o by
chi p photogr aph i s shown i n Fi g. 4. The total chi p area i s 640 pm x 700
i nserti ng transi stors oper ati ng i n the l i near r egi on (Fi g. 2(b)) [6], [7]. I n Pm ( = 045 m )
thi s case the second i nput i s real i zed wi th no addi ti onal current consump-
The most i mportant measurement resul ts are gi ven i n Tabl e I . The
ti on. However , the gai n Al/A ~ wi l l now depend on the suppl y vol tage
standard devi ati on of the offset i s 370 pV. Further r educti on of the offset
whi ch wi l l resul t i n a r educed PSRR. For battery operati on, the speci fi ca-
can be obtai ned by combi ni ng the offset cancel l ati on techni que of Fi g.
ti ons for the PSRR can however be somewhat r el axed.
l (a) and (c).
An SC i nstrumentati on ampl i fi er was devel oped accor di ng to the
Recentl y the pr esented ci rcui t has been r edesi gned i n a 3-pm technol -
pri nci pl es of Fi gs. l (c) and 2(b). The ci rcui t was real i zed i n a di fferenti al
ogy [9]. Measurement resul ts of thi s ci rcui t wi l l be r epor ted ver y soon [10].
way in order to further improve the performances [2].
The ampl i fi er real i zati on i s shown i n Fi g, 3 (sampl i ng and i ntegrati ng
capaci tors are not shown). The mai n ampl i fi er Ml M15 i s a di fferenti al
I V. CONCLUSIONS
transconductance ampl i fi er whose i nput stage has a l ow gai n. The sec- A mi cr opower i nstrumentati on ampl i fi er has been pr esented whi ch has
ondar y i nputs are real i zed by addi ng four transi stors to the mai n ampl i fi er a typi cal offset of 370 pV and consumes onl y 21 pW. The per for mances
IEEEJOURNAL OF SOLID-STATECIRCUITS, VOL. SC-20, NO. 3, JUNE1985
are acl ueved by the use of a new offset cancel l ati on techni que i n whi ch
the effects of char ge r ejecti on are attenuated. For l arger suppl y vol tages
( ~ 10 V) resi dual offsets of l ess than 50 pV are obtai nabl e wi th the
pr esented techni que.
ACKNOWLEDGNtSNT
The authors wi sh to thank Dr. H. Oguey for useful di scussi ons.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
REFERENCES
R. POUJOIS and J. Borel Low-1evel MOS transistor arnphfler using storage tech-
nmues. in ISSCC Drz. Tech Parxrs. 1973. m 152-153.
R C. Yen and P. R t%y, .(A MOS swtchedcapacltor instrumentation a.mphfuer,
IEEE J. Sohd-Stafe Circwrs, vol SC-17, pp 1W81013, Dec 1982
B. J. Hosticka, W Brockherde, and M Wrede, Effects of the architecture on ncnse
perforraamce of CMOS operational amplifiers, in Proc ECCTD, 1983
E. Vittoz, Dynanuc anafog techmques: Advanced Summer Course on Des,gn of
MOS-VLSI Clrcmts for Telecommunicatmns, LAquila, Itafy, June 18-29, 1984.
E. VMoz and H Oguey, SWISS Patent Apphcatmn No. 2179/84, filed on April 5.
1984
H. Oguey, CEH Rep. HO/81, pp. 56-57, Mar. 1981,
A Acovic, Amplificateur h offset compensk, Masters work of the EPFL, Lausanne,
July 1983, (m French)
M. Degrawe, E, V,ttoz, and L Verbamvhede, *A Wcropower CMOS instrument-
ation amplifier, m Proc. ESSCIRC 84 (J?dmburgh, Scotland), September 1984, pp.
31-34.
I Verbauwhede, Design and integration of a low-power CMOS SC-mstrumentatlon
amplifier, M S thesis, K.U Leuven, June 1984 (in Dutch)
P Van Peteghem, I Verbauwhede, and W Sansen, A nmcmpower h@ performance
S.C building block for integrated low level s,gnal prtxessmg, submitted for pubhca-
rion in the J Sohd-Smte Ctrcum
A Design Strategy in CMOS For Microprocessors
and Its Application to the Intel 80C48
M.D. SAHBATOU
Abstract Tlte main purpose in redesigning the 8048 Intel Microcom-
puter irnlCMOS technology is to test our tools efficiency and to evaluate
our design methodology, called CAPRI [1], which researches a good factor
of regrdlarity.
This paper presents a method of implementing microprocessor circuitry
in CMOS which uses an ordered stmctnre of the layout. It allows the
designer to work, with a symbolism, on a grid made of frdysilicon rows and
aluminimn columns. Thus, data buses rors in polysilicon lines which seem to
give a handicap to this method. Nevertheless, calculations show an accept-
able propagation delay time of ~ ns for a 2.5-mm bus (31 ns in the case of
an etluivafent afuminium bus).
I . INTRODUCTION
I n desi gni ng a mi croprocessor, we shoul d l ook for regul ari ty to decr ease
desi gn cost and i ncrease ci rcui t rehabi l i ty. Thi s cri teri on gi ves bi rth to
school s of di ffer ent styl es.
To attai n our goal , we have chosen the styl e of a top-down approach.
From the ori gi naf I ntel 8048 speci fi cati ons, we came down to a defi ni ti on
of a data path archi tecture whi ch depends essenti al l y upon the decom-
posi ti on of the al gori thm of the i nstructi ons.
Then, we consi der ed an i mpl ementati on strategy i n CMOS to dr aw the
ci rcui t l ayout.
I I . ARCHITECTURE OF THE DATA-PATH
To establ i sh the archi tecture, we started fr om the mstrtrcti on set of the
8048 descri bed i n the I ntel users mantraf [2]. Each i nstructi on was
Manuscnpt recewed November 21, 1984, revmed Febmary 5, 1985
The author was with the Computer Arciutecture Group, IMAG TIM 3, 38041, Grenoble
Cedex, France He IS now with the Department Electmmque, U S T.O. B P 1505, Oran el
MNAover, A1gena
807
ABUS
+ ! , , , , I t
F,g 1, Data path archltectwe
FIg 2 Microcomputer floor plan
descri bed by an i nterpretati on al gori thm, wi th respect to the fi ve state
ti mes of each machi ne cycl e and to the extemaJ si gnafs. We have afso
i ntr oduced a two-phase nonover l appi ng cl ock [3]. Each phase (71 or T2)
l asts 200 ns, for a 6-MHz crystal .
On the other hand, the or i gr naf 8048 archi tecture was based on one
si ngl e bus. As suggested i n the CAPRI desi gn methodol ogy, we have
chosen a two-bus structure, wi thout pr echar ge, to afl ow parafl el transfers
dur i ng one phase.
Her e i s an exampl e of the decomposi ti on of the fi rst two states S1 and
S2 whi ch are common to al l i nstructi ons and concer n the i ncrementati on
of the pr ogr am counter
T1 T2
(S1) U1-a:=FCL; f/2: =O; ci n:=0 PCL+-b:==Ul+U2;
OW:==COUT
(S2) Ul~u:=PCH, U2:=O; cin:=OVF PCH+b:==Ul+U2;
wher e c i n and c out are, respecti vel y, the carry i n and the carry out of the
ALU.
From the decomposi ti on of the i nstructi ons, we der i ved the data path
whi ch i s defi ned by an rmthmeti c and l ogi caf bl ock, some regi sters, a few
fl ags and a ci rcui t gener ati ng some constants. The ari thmeti c secti on
contai ns an 8-bi t ALU wi th two i nput l atches (fJl and u2), a swapper, a
shifter, a decimaf adJUSt, a zero test, and bit test circuitry.
The working registers consist of an 8-bit address register (W) for the
RAM, a program counter divided into two parts PCL (8 bits) and PCH
(four most significant bits), an accumulator ( .4), a timer (T), a temporary
register (TEMP), an instruction re$ister ( IR ), and a program status word
sectioned into two parts PSH (four most si gni fi cant bi ts) and PSL
(thr ee bi ts for stack poi nter ). Some fl ags are afso i mpl emented i n the data
path to compl ete the empty spaces (see Fi g. 1).
The data path was bui l t, usi ng a bi t-sl i ce appr oach [4] and the organi za-
ti on of the whol e mi cr ocomputer wi l l be as shown i n Fi g. 2.
I I I . [MPLEMENTATION IN CMOS
The cl assi caf method to i mpl ement a ci rcui t i n NMOS i s to dr aw the
basi c cel l s wi thi n two fi xed rai l s i n al umi ruum. So, wi th a si ngl e metaf
technol ogy both data and power buses r un hori zontal l y i n ahrmmi um, and
commauds r un per pendi cul ar l y i n pol ysi l i con. Thi s l ayer i s mor e resi sti ve
than afttmi rti um, i t i s used to make gri ds of transi stors and eventual l y
i nterconnecti ons wher e rnetaf cannot be used.
As a CMOS desi gn strategy, we adopted the r ever se si tuati on whi ch
consi sts of data buses i n pol ysi l i con hori zontal l i nes, and power buses and
commands i n afumi ni um verti cal l i nes.
Wi th thi s method, we can afso wor k on a gr i d wi th a uni for m pi tch,
defi ned by pol ysi l i con rows and metaf col umns i nstead of ahmi ni um rows
0018 -9200/85/0600-0807 $01.00 @U985 I EEE