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EE 271 Lab 5

Sequential Logic
University of Washington - Department of Electrical Engineering

Lab Objectives
Now that we have mastered combinational logic, it is time to figure out sequential circuits.
In this lab you will go through the tutorial on sequential circuits and download a premade
design to your board. Then, you get to design your own circuit and get it working.
Assigned Task Mapping sequential logic to the FPGA
Read and follow along with the tutorial in chapter C.4 of the book, but use the code shown
below instead of the books code. Note that you should be able to cut and paste from the
modul e si mpl e ( Cl ock, Reset n, w, out ) ;
i nput Cl ock, Reset n, w;
out put out ;
r eg out ;
wi r e [ 1: 0] PS; / / Pr esent St at e
r eg [ 1: 0] NS; / / Next St at e
wi r e r eset ; / / Her e t o be consi st ent wi t h book
par amet er [ 1: 0] A = 2' b00, B = 2' b01, C = 2' b10;

/ / Next St at e l ogi c
al ways @( w or PS)
case ( PS)
A: i f ( w) NS = B;
el se NS = A;
B: i f ( w) NS = C;
el se NS = A;
C: i f ( w) NS = C;
el se NS = A;
def aul t : NS = 2' bxx;

/ / Out put l ogi c
al ways @( PS)
case ( PS)
A: out = 0;
B: out = 0;
C: out = 1;
def aul t : out = 1' bx;

/ / Swi t ch act i ve- l ow r eset t o act i ve- hi gh i nt er nal l y
assi gn r eset = ~Reset n;

/ / St at ehol di ng
D_FF l sb ( PS[ 0] , NS[ 0] , r eset , Cl ock) ;
D_FF msb ( PS[ 1] , NS[ 1] , r eset , Cl ock) ;

endmodul e

modul e D_FF ( q, d, r eset , cl k) ;
out put q;
i nput d, r eset , cl k;
r eg q; / / I ndi cat e t hat q i s st at ehol di ng

al ways @( posedge cl k or posedge r eset )
i f ( r eset )
q = 0; / / On r eset , set t o 0
el se
q = d; / / Ot her wi se out = d
endmodul e

You will not be able to follow the simulation part directly. Your goal is to duplicate the
inputs shown in C.37 in the simulation. You will also have out, D_FF:msb|q and D_FF:lsb|q
instead of z, y~15 and y~14 because the code is different. You will be done after you have
explored the output of Timing Analyzer.
Print out the Verilog and simulation waveforms.
Next, set up the design to run on the FPGA. For this we need to provide a clock to the
circuit, but the clocks on the chip are VERY fast (24MHz to 50MHz, so a clock every 40ns
to 80ns!). For our purposes wed like a slower clock, so we provide a clock divider a
circuit that generates slower clocks from a master clock. Create a new project, add the code
below, and copy in or import the code for the simple FSM (above). Be sure to give the
project the same name as your top-level module (in this case call it clocked_design). The
new code provides a unit clock_divider that provides a large number of clocks in the
code below we select which clock via the whichClock. whichClock =25 yields a clock
with a cycle time of a bit over a second, 24 is twice as fast, 26 is twice as slow, etc.
modul e cl ocked_desi gn ( CLOCK_50, KEY, LEDG, LEDR) ;
i nput CLOCK_50;
i nput [ 3: 0] KEY; / / Tr ue when not pr essed, Fal se when pr essed
out put [ 7: 0] LEDG;
out put [ 0: 0] LEDR;
wi r e [ 31: 0] cl k;
par amet er whi chCl ock = 25;

wi r e r eset n, w, out ;
assi gn r eset n = KEY[ 0] ;
assi gn w = ~KEY[ 1] ;

si mpl e dut ( cl k[ whi chCl ock] , r eset n, w, out ) ;
cl ock_di vi der cdi v ( CLOCK_50, cl k) ;

assi gn LEDG = { cl k[ whi chCl ock] , 3' b0, w, 2' b0, ~r eset n};
assi gn LEDR[ 0] = out ;

endmodul e

/ / di vi ded_cl ocks[ 0] = 25MHz, [ 1] = 12. 5Mhz, . . . [ 23] = 3Hz, [ 24] = 1. 5Hz,
[ 25] = 0. 75Hz, . . .
modul e cl ock_di vi der ( cl ock, di vi ded_cl ocks) ;
i nput cl ock;
out put [ 31: 0] di vi ded_cl ocks;
r eg [ 31: 0] di vi ded_cl ocks;

i ni t i al
di vi ded_cl ocks = 0;

al ways @( posedge cl ock)
di vi ded_cl ocks = di vi ded_cl ocks + 1;
endmodul e
Youll also need the CSV file that sets the pin assignments. This design uses KEY0 for reset
(press to reset the circuit), KEY1 as the w input, LEDG0 shows the reset signal, LEDG3
shows the w signal, LEDG7 shows the clock, and LEDR0 the output of the FSM.
You do not have to demonstrate this circuit working to the TA, but running this test will help
a LOT in getting the design problem working.
Design Problem Hazard lights
Review the Verilog Tutorial on the website through to the end.
The landing lights at Sea-Tac are busted, so we have to come up with a new set. In order to
show pilots the wind direction across the runways we will build special wind indicators to
put at the ends of all runways at Sea-Tac.
Your circuit will be given two inputs (SW[0] and SW[1], which indicates wind direction, and
three lights to display the corresponding sequence of lights:
SW[1] SW[0] Meaning Pattern
0 0 Calm 1 0 1
0 1 0
0 1 Right to Left 0 0 1
0 1 0
1 0 0
1 0 Left to Right 1 0 0
0 1 0
0 0 1
For each situation, the lights should cycle through the given pattern. Thus, if the wind is
calm, the lights will cycle between the outside lights lit, and the center light lit, over and
over. In a calm wind the lights cycle through two patterns, with the outer lights lit, then the
center, then repeating. The right to left and left to right crosswind indicators repeatedly cycle
through three patterns each, which has the light move from right to left or left to right
The switches will never both be true. The switches may be changed at any point during the
current cycling of the lights, and the lights must switch over to the new pattern as soon as
possible (however, it can enter into any point in the other patterns behaviors).
Your design should be in the style of the simple module given above. That is, you can use
if and case statements to implement the next-state logic and the outputs, and must
explicitly instantiate the flip-flops.
Note that the proscribed Verilog format has the outputs depend only on the current state.
This is called a Moore machine. Every sequential circuit in this class must be a Moore
machine, so if your output logic depends directly on the inputs you did it wrong (the inputs
should not appear AT ALL in the output logic section).
You will be graded 100 points on correctness, style, testing, etc. Your bonus goal is
developing the smallest circuit possible. To measure this, perform a compilation of just your
design (without the clock divider), and look at the flow summary page. Your goal is to use
as few logic elements (total logic elements row) as possible.
Assigned Task Schematic of the FSM
When you have done the compilation of just your design (without the clock divider), draw by
hand a schematic of the logic for your FSM. Go to the compilation report >Analysis &
Synthesis >Equations. If this option isnt there, turn on Tools >Options >General >
Processing > "automatically generate equation files during compilation" and rerun the
compile. Print out these equations.
The Equations item lists all of the flipflops and logic functions. # is OR, $ is XOR, and
A & B +C & D is the same as (A & B) +(C & D) just like 1*2 +3 * 4 =(1*2)+(3*4) in
normal math. For the DFFs, they will be in the form
Q =DFFEAS(D, CLOCK, RESET, , , , , , );
Where Q is the output, D the input, CLOCK the clock, and RESET an asynchronous reset.
Lab Demonstration/Turn-In Requirements
A TA needs to "Check You Off" for each of the tasks listed below.
Turn in the Verilog for the simple FSM and the waveform showing the circuit running.
Demonstrate the Runway Lights circuit to your TA.
Turn in the Verilog for the Runway Lights design, the waveform of simulating the
design, and the Flow Summary (produced during compilation) of compiling just your
FSM (without the clock divider circuit).
Turn in the schematic of the Runway Lights circuit that you drew from the Quartus
equations, along with the printout of the equations themselves.
Tell the TA how many hours (estimated) it took to complete this lab, including reading,
planning, design, coding, debugging, testing, etc. Everything related to the lab (in total).