EC2354 VLSI DESIGN

UNIT I
1. Briefly explain the various steps involved in fabrication of CMOS N Well process (8)
2. Derive the relationship between drain current, drain voltage and gate voltage in different regions
of operation of a transistor. (8)
3. Draw and explain the DC and transfer characteristics of a CMOS inverter with necessary
conditions for the different regions of operation. (8)
4. Give a brief note on the different process techniques to enhance the performance of CMOS
transistors (8)
5. Explain the CMOS process enhancements
6. Explain the operation of a NMOS transistor and derive its current equations
UNIT II
1. Explain the static and dynamic power dissipation in CMOS circuits with necessary diagrams and
expressions .(8)
2. Discuss the principle of constant field scaling and constant voltage scaling (8)
3. Explain the different reliability problems related to the design of reliable chips. (10)
4. Explain about Device Characterization in SPICE. (6)
5. Explain the Device and circuit characterization of circuits. (10)
6. Write a program for CMOS inverter transient analysis using SPICE. (6)
7. Explain the different reliability problems related to the design of reliable CMOS chips. (10)
8. Discuss the principle of constant field scaling and also write its effect on device characteristics.
UNIT III
1. Draw and explain the operation of Conventional, pulsed and resetable latches.(8)
2. Write a brief note on sequencing dynamic circuits.(8)
3. Explain the basic principle of operation of dynamic CMOS logic, Domino and dual rail domino
logic families with neat diagrams.(12)
4.Obtain a CMOS logic design realizing the Boolean function Z=

(4)
5. Write the basic principle of low power logic design. (4)
6.Draw and explain the operation of Conventional, pulsed and resettable latches.(8)
7. Write a brief note on sequencing dynamic circuits. (8)
8. Explain the Maximum and minimum delay constraints of a flip-flop.(8)
9. Explain the operation of Synchronizer.(8)
UNIT IV
1. Explain the principles of silicon debug.(8)
2. Describe the scan based approaches to design for testability in detail (8)
3.Explain in detail about Boundary scan architecture (8)
4.Describe the principle of built in self test (8)
UNIT V
1. Explain in detail the Procedural assignment statements in verilog (6)
2. Write the verilog code for 4:1 multiplexer in Dataflow and gate level of modeling. (10)
3.Explain the different timing controls available in verilog (8)
4.Write a switch level modeling verilog HDL program for 2-input NAND gate. (4)
5.Explain the port connection rules. (4)
6.Write a Verilog HDL program for a 2-bit comparator. (8)
7. Explain in detail about conditional and looping statements with example for each (12)