DOC/LP/01/28.02.

02
LESSON PLAN LP AP9212
LP Rev. No: 00
Date: 07/09/12
Page 01 of 06
Sub Code Na!e: AP9212 Adva"#ed D$g$ta% S&'te! De'$g"
("$t : ) *+a"#, : -E.-AE Se!e'te+: )
(N)/ ) SE0(EN/)AL C)RC()/ DES)1N 9
Analysis of clocked synchronous sequential circuits and modelin! "tate diaram# state
ta$le# state ta$le assinment and reduction!Desin of synchronous sequential circuits!
desin of iterati%e circuits!A"& chart and reali'ation usin A"&.
Se''$o"
No.
/o2$#' to be #ove+ed /$!e Ref
/ea#,$"g
-et,od
1. Analysis of clocked sequential circuits! (ntroduction )0m 1 **
2.
Desin of an "equential +arity checker# Analysis of &oore
and &ealy sequential circuit $y sinal tracin and timin
charts
)0m 1 **
3.
&ethod of constructin state ta$le and state ra+hs for
&oore and &ealy machines
)0m 1 **
4.
,eneral &odels for a clocked &ealy and &oore sequential
circuits.
)0m 1 **
5.
Desin of a sequence detector for &ealy and &oore
machines
)0m 1 **
6. -eduction of state ta$le usin state assinment )0m 1 **
7.
Determination of state equi%alence and circuit equi%alence
usin an im+lication ta$le
)0m 1 **
6.
(ncom+letely "+ecified "tate ta$les and deri%ation of fli+!
flo+ in+ut equations
)0m 1 **
9. ,uidelines for state assinments# one hot state assinment )0m 1 **
10. Desin of it.rati%e circuits# Desin of a com+arator )0m 1 **
11.
"tate &achine /"&0 Charts! D.ri%ation and reali'ation of
"& charts
)0m 1 **
DOC/LP/01/28.02.02
LESSON PLAN LP AP9212
LP Rev. No: 00
Date: 07/09/12
Page 02 of 06
Sub Code Na!e: AP9212 Adva"#ed D$g$ta% S&'te! De'$g"
("$t : )) *+a"#, : -E.-AE Se!e'te+: )
(N)/ )) AS7NC8RONO(S SE0(EN/)AL C)RC()/ DES)1N 9
Analysis of asynchronous sequential circuit 1 flo2 ta$le reduction!races!state
assinment!transition ta$le and +ro$lems in transition ta$le! desin of asynchronous
sequential circuit!"tatic# dynamic and essential ha'ards 1 data synchroni'ers 1 mi3ed
o+eratin mode asynchronous circuits 1 desinin %endin machine controller.
Se''$o"
No.
/o2$#' to be #ove+ed /$!e Ref
/ea#,$"g
-et,od
12. Analysis of Asynchronous sequential circuit ! Desin of
4undamental mode sequential circuit ! Primiti%e state
ta$le# state ta$le reduction and state assinment
)0m 1#2 **
15. Desin of Pulse mode sequential circuit! Primiti%e state
ta$le# state ta$le reduction and state assinment
)0m 1#2 **
16. Pro$lems in Asynchronous sequential circuits 1Cycles#
Critical race and 7on! Critical race
)0m 1#2 **
1). 8a'ards! "tatic# Dynamic and 9ssential 8a'ards )0m 1#2 **
1:. Desin of 8a'ard free s2itchin circuits! "tatic 8a'ard
and 9ssential 8a'ard elimination
)0m 1#2 **
1;. Pro$lems on 8a'ard free circuit 1 "tatic and 9ssential
8a'ard
)0m 1#2 **
18. <orkin +rinci+le of Data synchroni'er )0m 1#2 **
1=. Desin of mi3ed o+eratin mode asynchronous circuit )0m 1#2 **
20. Desin of >endin machine controller! Descri+tion/
"+ecification# 4"& desin ste+s# "tate diaram and state
ta$le
)0m 1#2 **
CA? 1 ( ;)m ! !
DOC/LP/01/28.02.02
LESSON PLAN LP AP9212
LP Rev. No: 00
Date: 07/09/12
Page 03 of 06
Sub Code Na!e: AP9212 Adva"#ed D$g$ta% S&'te! De'$g"
("$t : ))) *+a"#, : -E.-AE Se!e'te+: )
(N)/ ))) 9A(L/ D)A1NOS)S AND /ES/A*)L)/7 AL1OR)/8-S 9
4ault ta$le method!+ath sensiti'ation method 1 *oolean difference method!D alorithm
!?olerance techniques 1 ?he com+act alorithm 1 4ault in PLA 1 ?est eneration!D4?
schemes 1 *uilt in self test.

Se''$o"
No.
/o2$#' to be #ove+ed /$!e Ref
/ea#,$"g
-et,od
21. 4ault &odels! "tuck!at fault# *ridin fault# stuck!o+en fault
and ?em+orary faults
)0m 5 **
22. 4ault Dianosis of Diital systems! ?est eneration for
com$inational loic circuits! one dimensional +ath
sensiti'ation
)0m 5 **
25. *oolean Difference method )0m 5 **
26. D!Alorithm! "inular co%er# Pro+aation D!cu$es# Primiti%e
D!cu$e of a fault# D! intersection
)0m 5 **
2).
?olerance techniques! "tatic redundancy# Dynamic redundancy#
and 8y$rid redundancy
)0m 5 **
2:. "elf! +urin redundancy# "ift!out modular redundancy )0m 5 **
2;. 4ault in PLA and totally self!checkin PLA desin )0m 5 **
28. ?est eneration! Controlla$ility and o$ser%a$ility# Desin of
testa$le com$inational loic circuits
)0m 5 **
2=. Desin of testa$le sequential circuits )0m 5 **
50. *uilt in self test! *uilt!in Diital circuit O$ser%er /*(DCO0#
*uilt in test for >L"( chi+s
)0m 5 **
DOC/LP/01/28.02.02
LESSON PLAN LP AP9212
LP Rev. No: 00
Date: 07/09/12
Page 04 of 06
Sub Code Na!e: AP9212 Adva"#ed D$g$ta% S&'te! De'$g"
("$t : ): *+a"#, : -E.-AE Se!e'te+: )
(N)/): S7NC8RONO(S DES)1N (S)N1 PRO1RA--A*LE DE:)CES 9
Prorammin loic de%ice families 1 Desinin a synchronous sequential circuit usin
PLA/PAL 1 -eali'ation of finite state machine usin PLD 1 4P,A 1 @ilin3 4P,A!
@ilin3 6000.
Se''$o"
No.
/o2$#' to be #ove+ed /$!e Ref
/ea#,$"g
-et,od
51. Proramma$le Loic De%ices /PLD0! 7otations for
PLD# Desin methodoloy usin PLDAs
)0m 6 **
52. Desin of sequential PLA de%ices )0m 6 **
55. Desin of sequential PAL de%ices! 6!$it $inary
counter! state ta$le# B!ma+ and PAL diaram
)0m 6 **
56. 8!$it Parallel Cyclic -edundancy Check /C-C0
enerator! *lock diaram and PAL diaram
)0m 6 **
5). 4ield! Proramma$le ,ate Array /4P,A0! PL" 1)1#
PL"105
)0m 6 **
5:. Asynchronous "tate &achine Desin )0m 6 **
5;. "tate &achine Desin! Proram for the loic $locks#
B ma+s# im+lementation of the state ta$le
)0m 6 **
58. @ilin3 4P,A and @ilin3 6000 $lock diaram
e3+lanation
)0m 6 **
CA? (( 180m ! !
DOC/LP/01/28.02.02
LESSON PLAN LP AP9212
LP Rev. No: 00
Date: 07/09/12
Page 05 of 06
Sub Code Na!e: AP9212 Adva"#ed D$g$ta% S&'te! De'$g"
("$t : : *+a"#, : -E.-AE Se!e'te+: )
(N)/ : S7S/E- DES)1N (S)N1 :8DL 9
>8DL o+erators 1 Arrays 1 concurrent and sequential statements 1 +ackaes! Data flo2
1 *eha%ioral 1 structural modelin 1 com+ilation and simulation of >8DL code 1?est
$ench ! -eali'ation of com$inational and sequential circuits usin 8DL 1 -eisters 1
counters 1 sequential machine 1 serial adder 1 &ulti+lier! Di%ider 1 Desin of sim+le
micro+rocessor.
Se''$o"
No.
/o2$#' to be #ove+ed /$!e Ref
/ea#,$"g
-et,od
5=. (ntroduction to >8DL# Arrays and >8DL o+erators )0m )#: **
60.
Concurrent #"equential statements and Packaes!
Declaration# Deferred constants# Packae $ody
)0m )#: **
61.
(ntroduction to 2rite a +roram in Data flo2#
*eha%ioral and structural model
)0m )#: **
62.
Com+ilation and simulation of >8DL code # ?est
$ench! "timulus only# 4ull test $ench# "imulator
s+ecific# 8y$rid and 4ast test $ench
)0m
)#:
**
65.
"tructural >8DL code! 4ull Adder# &ulti+le3er#
Demulti+le3er# 9ncoder and Decoder
)0m )#: **
66.
*eha%ioral and Dataflo2 >8DL code! CB# ?# D fli+!
flo+
)0m )#: **
6).
Desin of "hift reisters 1 "("O# "(PO# P("O and
P(PO usin >8DL
)0m )#: **
6:. Desin of Counters and "erial adder usin >8DL )0m
)#:
**
6;.
Desin of &ulti+lier! *ooth# &odified *ooth and
Di%ider usin >8DL
)0m )#: **
68.
Desin of &icro+rocessor 2ith sim+le arithmetic
o+eration usin >8DL
)0m
)#:
**
CA? ((( ;)m ! !
DOC/LP/01/28.02.02
LESSON PLAN LP AP9212
LP Rev. No: 00
Date: 07/09/12
Page 06 of 06
Sub Code Na!e: AP9212 Adva"#ed D$g$ta% S&'te! De'$g"
*+a"#, : -E.-AE Se!e'te+: )
Cou+'e De%$ve+& P%a":
<eek
1 2 5 6 ) : ; 8 = 10 11 12 15
( (( ( (( ( (( ( (( ( (( ( (( ( (( ( (( ( (( ( (( ( (( ( (( (
Dnits
1 1 1 1 1

2 2

2 2

2 5 5 5

5 5 6 6 6 6 6 ) ) )

) )

CAT I CAT II
CAT III
RE9ERENCES
1 Charles 8.-oth Cr E4undamentals of Loic DesinF ?homson Learnin 2006
2 7ri+endra 7 *is2as ELoic Desin ?heoryF Prentice 8all of (ndia#2001
5 Para B.Lala E4ault ?olerant and 4ault ?esta$le 8ard2are DesinF * "
Pu$lications#2002
6 Para B.Lala EDiital system Desin usin PLDF * " Pu$lications#2005
) Charles 8 -oth Cr.FDiital "ystem Desin usin >8DLF ?homson learnin# 2006
: Doulas L.Perry E>8DL +rorammin $y 93am+leF ?ata &c,ra2.8ill ! 200:
P+e2a+ed b& A22+oved b&
S$g"atu+e
Na!e -.At,a22a" D+.S.1a"e', :a$d&a"at,a"
De'$g"at$o" A''$'ta"t P+ofe''o+/EC 8OD/EC
Date 07.09.2012 07.09.2012