Interfacing RS-232 With Spartan-3E FPGA

FPGA HOW-TO GUIDE
Interfacing RS-232 with

Spartan-3E FPGA

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Contents at a Glance

RS232 (UART) .................................................................. 3
Interfacing UART with Spartan-3E FPGA ........................... 3
Pin Assignment with Spartan-3E FPGA ............................. 4
Schematics to Interface UART with Spartan-3E ................. 4
VHDL code for UART to led using Spartan-3E FPGA ........... 5


RS232 (UART)

The UART (universal asynchronous receiver/transmitter)
is a serial protocol with separate transmits and receives lines,
and can be used for full duplex communication.
Interfacing UART with Spartan-3E FPGA

The Spartan-3E board has a Serial Port, indicated as in
Figure. RS-232 serial communication is performed through a
9-pin SUB-D connector and the FPGA UART module. The
UART is one of the most common ways of exchanging data
between the FPGA and peripheral components. In order to
enable this communication, it is necessary to establish a
connection between RX and TX lines on SUB-D connector and
the same pins on the target FPGA. Since RS-232
communication voltage levels are different than FPGA logic
levels, it is necessary to use a RS-232 Transceiver circuit, such
as MAX3232 as shown in Figure.


Pin Assignment with Spartan-3E FPGA

Schematics to Interface UART with Spartan-3E

UART
DB-9 Connector
SPARTAN3E
FPGA Lines
TXD P146
RXD P147


VHDL code for UART to led using Spartan-3E FPGA
***************************************************************************************
Title : Program for UART to LED Display

***************************************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity uart is
port ( clk : in std_logic;
din : in std_logic;
l1 : out std_logic;
l2 : out std_logic);

end uart;
architecture Behavioral of uart is
type state is (ready,b0);


signal ps : state := ready;
type state1 is (st1,st2);
signal ps1 : state1 := st1;
signal start,stop : std_logic;
signal store : std_logic_vector(7 downto 0) := "10101010";
begin
process(clk)
variable i : integer := 0 ;
begin
if clk'event and clk = '1' then
if ps = ready then
start <= din;
end if;

if start = '0' then
ps <= b0;
elsif start = '1' then
ps <= ready;
end if;
------------------------------------------1
if ps = b0 then
i := i + 1;
if i = 2600 then
start <= din;


end if;
if i = 7800 then
store(0) <= din;
end if;
if i = 13000 then
store(1) <= din;
end if;
if i = 18200 then
store(2) <= din;
end if;
if i = 23400 then
store(3) <= din;
end if;
if i = 28600 then
store(4) <= din;
end if;
if i = 33800 then
store(5) <= din;
end if;
if i = 39000 then
store(6) <= din;
end if;
if i = 44200 then
store(7) <= din;


end if;
if i = 49400 then
stop <= din;
end if;

if i = 54600 then
i := 0 ;
ps <= ready ;
end if;
end if;
end if;
end process;
process(clk,store)
begin
if clk'event and clk = '1' then
if ps1 = st1 then
if store = x"31" then
l1 <= '1' ;
ps1 <= st2 ;
elsif store = x"32" then
l1 <= '0' ;
ps1 <= st2 ;
else
ps1 <= st2 ;


null;
end if;
end if;
if ps1 = st2 then
if store = x"33" then
l2 <= '1' ;
ps1 <= st1 ;
elsif store = x"34" then
l2 <= '0' ;
ps1 <= st1 ;
else
ps1 <= st1 ;
null;
end if;
end if;
end if;
-----------------------------------------------------10
end process;
end Behavioral;


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FPGA HOW-TO GUIDE

Interfacing RS-232 with

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