Sagar Institute of Science, Technology &

Engineering

BHOPAL


DEPARTMENT OF

Electronics & Communication Engineering


COURSE FILE


Programme : Bachelor of Engineering
Semester : IV
Course Code : EC-403
Subject Name : DIGITAL ELECTRONICS


Prepared By



Approved By


CONTENTS

1. SYLLABUS WITH SCHEME
2. LIST OF BOOKS
3. TIME TABLE
4. LECTURE PLAN
5. TUTORIAL SHEET
6. UNIT TEST PAPERS
7. MID SEM PAPERS
8. TACTICAL PLAN
9. QUESTION PAPERS
10. ATTENDANCE SHEET
11. CLASS NOTES WITH TRANSPARANCIES







RAJIV GANDHI PROUDYOGIKI VISHWAVIDYALAYA, BHOPAL
PROGRAMME: Electronics and Communication Engineering
COURSE: EC-403 Digital Electronics
Course Contents

Unit-I
Review of Number systems and Binary codes, Binary arithmetic addition,
subtraction, multiplication and division algorithms. Boolean algebra: theorems and
functions, Simplification of Boolean functions, minimization techniques, Karnaugh's map
method, Quine and McCluskey's method, realization of various binary functions using
AND ,OR ,NOT,XOR logic gates.

Unit-II
Universal gates: NAND, NOR, realization of boolean function using universal gates.
Half and full adder, half and full subtractor, Series and parallel adder, BCD adders,
lookahead carry generator. Decoders, Encoders, multiplexers and de-multiplexers.
Analysis and design of combination circuits, realization of various Boolean functions
using NAND, NOR gates and multiplexers.

Unit-III
Multivibrators: Astable, Monostable and bistable multivibrators, 555 timer chip and its
application in multivibrators. Flip-Flops: R-S, Clocked R-S, T, D, J-K, race around
problem, Master-slave J-K., State and Excitation Tables. Shift registers and counters
:synchronous and asynchronous counters, Binary ripple counter, up-down counter,
Johnson and ring counter. Analysis and Design of Sequential Circuits.


Unit-IV
Semiconductor memories: Organization and construction of RAM, SRAM, DRAM,
RAMBUS ROM, PROM, EPROM, EEPROM, PAL and PLAs etc

Unit-V
Logic families: RTL, DTL, TTL, ECL, IIL, PMOS, NMOS and CMOS logic etc.
Interfacing between TTL and MOS, vice-versa.

References:
1. M. Mano : Digital Logic and Computer Design, Pearson Education
2. W.H. Gothman : Digital Electronics, PHI.
3. Millman and Taub : Pulse, Digital and Switching Waveforms, MGH
4. Salivahanan and Ari Vahagan : Digital Circuits and Design, Vikas Publishing House
5. Leach and Malvino : Digital Principles and Applications, TMH










LIST OF BOOKS




R1. Digital Electronics by J.S. Katre, Tech-max publication.

R2. Digital circuits & systems by salivahanan.

R3. Digital circuits & systems by Shiv Shankar Mishra.

R4. Digital Electronics by Sanjay Sharma.


























SISTec-R

Day Mon Tue Wed Thu Fri Sat
Max.
available
No. of
Periods

Lecture. Topics to be covered
Date

Reference
Proposed Completed
UNIT-I


1-3
Review of Number systems and Binary codes



R1,R2
4
Binary arithmetic addition, subtraction,
multiplication and division algorithms



R1,R2
5
Boolean algebra: theorems and functions,



R1,R2
6
Simplification of Boolean functions



R1 ,R3
7-9
minimization techniques, Karnaugh's map
method


R1 ,R3
10-12
Quine and McCluskey's method



R1,R2
13-14
realization of various binary functions using
AND ,OR
,NOT,XOR logic gates.


R1 ,R3
15 UNIT TEST




LECTURE PLAN
Format No.
Issue
Page No:
Department
Electronics & communication engineering
Session : Jan-June 2013
Name of
Teacher
Semester EVEN (IV)
Subject
Digital Electronics

Sub. Code EC-403
(B) TIME SCHEDULE : Total expected periods:_56_, Extra periods (if required)_____
UNIT-II


16-17
NAND, NOR, realization of boolean function
using universal gates


R1 ,R3
18
Half and full adder, half and full subtractor



R1,R2
19 Series and parallel adder

R1,R2
20 BCD adder

R1 ,R3
21 Look ahead carry generator

R1,R2
22 Decoders, Encoders

R1 ,R3
23-24
multiplexers and de-multiplexers



R1,R2
25-26
Analysis and design of combination circuits



R1,R2
27
Realization of various Boolean functions using
NAND NOR gates


R1 ,R3
28
Realization of various Boolean functions using
Multiplexers


R1 ,R3
29 UNIT TEST


UNIT-III


30-31 Astable, Monostable

R1,R2
32
Bistable multivibrators



R1,R2
33
555 timer chip and its application in
multivibrators


R1 ,R3
34
Flip-Flops: R-S, Clocked R-S



R1 ,R3
35-36
T, D, J-K, race around problem



R1 ,R3
37
Master-slave J-K., State and Excitation Tables



R1 ,R3
38
Shift registers and counters



R1,R2
39
Synchronous counters,



R1,R2
40
Asynchronous counters



R1,R2
41
Binary ripple counter



R1 ,R3
42
Up-down counter



R1 ,R3
43 Analysis and Design of Sequential Circuits

R1,R2
44-45 UNIT TEST


UNIT-IV


46
Organization and construction of RAM



R1 ,R3
47
SRAM, DRAM,RAMBUS



R4
48
ROM, PROM



R1 ,R3
49 EPROM, EEPROM

R4
50
PAL and PLAs etc



R1 ,R3
51 UNIT TEST


UNIT-V


52 RTL, DTL

R4
53
TTL, ECL, IIL



R4
54 PMOS, NMOS and CMOS logic etc

R1,R2
55 Interfacing between TTL and MOS, vice-versa.

R1,R2
56 UNIT TEST








R1. Digital Electronics by J.S. Katre, Tech-max publication.

R2. Digital circuits & systems by salivahanan.

R3. Digital circuits & systems by Shiv Shankar Mishra.

R4. Digital Electronics by Sanjay Sharma.





















ASSINGMENT 1

Q.1 Perform the subtraction with the following binary number by 1s
& 2s complement
a) 11010-1101 b) 100-110000
Q.2 Convert the decimal no 250.5 to base3, base8 &base 16.

ASSINGMENT 2

Q.3 Simplify the following Boolean function to minimum no of literals
a) xy+xy
b) (x+y)(x+y)
c) zx+zxy

Q.4 Obtain the truth table of the following function.
F=xy+xy+yz


ASSINGMENT 3


Q.5 Simplify the Boolean function by K-map


ASSIGNMENT QUESTIONS
Format No.
Issue
Page No:
Department
Electronics & communication engineering
Session : Jan-June 2013
Name of
Teacher
Semester EVEN (IV)
Subject
Digital Electronics

Sub. Code EC-403
(B) TIME SCHEDULE : Total expected periods:__, Extra periods (if required)_____
F=xyz+xyz+xyz+xyz
Q.6 Simplify the Boolean function in
(a) sum of product (b) product of sum
F(A,B,C,D)=(0,1,2,5,8,9,10)

ASSINGMENT 4

Q.7 Simplify the Boolean function by K-map:
F(w,x,y,z)=(1,3,7,11,15)
and the dont care condition
F(w,x,y,z)=(0,2,5)
Q 8. Design a half adder & full adder circuit



ASSINGMENT 5


Q9. Realization of various Boolean functions using NAND, NOR gates.
Q 10 . Explain the BCD adder circuit.

ASSINGMENT 6

Q.11 Design a look ahead carry generator
Q.12 Design a 4 to 16 decoder ckt by using 3 to 8 decoder.

ASSINGMENT 7

Q.13 Implement a full adder circuit with a decoder & two OR gates.
Q.14. Design 16x1 MUX by using.
F(A,B,C,D)=(0,1,3,7)

ASSINGMENT 8

Q. 15. Explain Astable and bistable multivibrators
Q.16. Show the logic diagram of a clocked RS flip-flop with four NAND
Gates

ASSINGMENT 9

Q.17. Design a BCD counter with JK flip-flop.
Q.18. Explain the working of a shift registers


ASSINGMENT 10

Q.19. Show the logic diagram of a clocked D flip-flop with AND &
NOR gates
Q.20 Design a four bit ring counter.

ASSINGMENT 11

Q.21 Explain the working of SISO, SIPO, PISO, and PIPO
Q.22. What is the difference between synchronous and asynchronous counters?.

ASSINGMENT 12

Q.23 Explain semiconductor memories.
Q. 24 Explain construction of RAM, ROM


ASSINGMENT 13

Q.25 Explain PAL and PLAs etc
Q. 26 Explain the organization and construction of RAMBUS, ROM
ASSINGMENT 14

Q.27 Implement a 4 input NAND gate using CMOS logic.
Q.28 Briefly explain RTL, DCTL, DTL, I
2
L logic families.

ASSINGMENT 15

Q.29 Explain Astable multiviubrator. Derive the expression of duty cycle of Astable
multivibrator.
Q.30 Interface TTL to MOS.

ASSINGMENT 16

Q. 31 differentiate between MOS and CMOS on the basis of chareterstic ,advantages and
disadvantages.
Q.32 Write a short note on IIL logic and applications.

ASSINGMENT 17

Q.33 Explain the working of open collector TTL gate. What is Totem Pole.
Q. 34 Draw and explain CMOS NOT, NAND and NOR gates.

ASSINGMENT 18

Q. 35 What is Multivibrator. Explain the working of Bistable Multivibrator
with waveform diagram.
Q. 36 Explain the operation of ECL gate. Also give its merits and demerits

ASSINGMENT 19

Q. 37 Write short notes on the following:
(i) Noise immunity (ii) Fan-out. (iii) Propagation delay (iv) Figure of merit.
Q .38 Explain the advantage of multi-emitter transfer at input of TTL Logic circuit
families.

ASSINGMENT 20

Q. 39 What is meant by PLA? Draw a block diagram and explain its working.
Q. 40 Implement the following Boolean functions with PLA(give only PLA
programming table

(A) F1= (A,B,C)= (0,1,2,4) , (B) F2= (A,B,C)= (0,5,6,7)




























Q.1) Convert the following:-
(i) (444.456)
10
= (?)
8
= (?)
16

(ii) (FE)
16
= (?)
10
= (?)
8

Q.2) Obtain M-N using :- (i) 1s complement and (ii) 2s complement if
(i) M=10110101, N= 00101101,
(ii) M= 00101101, N= 11101011,

Q.3) (a) write the Gray code for:- (i) (16)
8
(ii) (25)
10

(b) Give the BCD and EXCESS-3 code for (32)
10
.

Q.4) (a) State and proof De-Morgans theorem?
(b) Find the complement of the given functions:-
(i) F
1
= xyz + xyz (ii) F
2
= x(yz+ yz)

Q.5) Proof the following using the Boolean Algebra:-
(i) x + yz = (x+y) (x+z) (ii) (A+B) (A+C) (B+C) = (A+B) (A+C)

Q.6) Simplify the function f using K-map where
f(A,B,C,D)= m (1,3,5,8,9,11,15) + d (2,13).

Q. 7 Implement Full Subtractor with Half Subtractor and OR gate.

Q. 8 Design and explain the working of a 4-bit adder with Look ahead carry


QUESTION BANK
Format No.
Issue
Page No:
Department
Electronics & communication engineering
Session : Jan-June 2013
Name of
Teacher
Semester EVEN (IV)
Subject
Digital Electronics

Sub. Code EC-403
(B) TIME SCHEDULE : Total expected periods:__, Extra periods (if required)_____
generator.

Q.9 Explain the working of Serial Adder.

Q.10 Design and explain the working of BCD adder.

Q.11 What do you mean by a decoder? Implement a full adder circuit with the help of
one 3x8 decoder and 2 OR gates.

Q.12 Implement the following Boolean function with the help of a multiplexer
F (A,B,C,D)=(0,1,3,4,8,9,15).

Q .13 What is Multivibrator. Explain the working of Bistable Multivibrator
with waveform diagram.

Q.14 Explain the operation of ECL gate. Also give its merits and demerits.

Q.15. Explain the working of open collector TTL gate. What is Totem Pole.
Q.16. Draw and explain CMOS NOT, NAND and NOR gates

Q. 17 Explain Counter and its classification. Design a counter having the repeated binary
sequence: 0,4,2,1,6. using JK flip-flop.

Q. 18 Explain Counter and its classification. Design a counter having the
repeated binary sequence: 0,4,2,1,6. using JK flip-flop.

Q. 19 Explain construction of RAM, ROM

Q. 20 Explain PAL and PLAs etc

Q .21 Explain the organization and construction of RAMBUS, ROM

Q.22 What is meant by PLA? Draw a block diagram and explain its working.

Q.23 Design a BCD to EX-3 code converter using ROM.

Q. 24 Implement a 4 input NAND gate using CMOS logic.

Q. 25 Briefly explain RTL, DCTL, DTL, I
2
L logic families.

Q .26 Explain Astable multiviubrator. Derive the expression of duty cycle of Astable
multivibrator.


Q.27 Explain Counter and its classification. Design a counter having the
repeated binary sequence: 0,4,2,1,6. using JK flip-flop.

Q.28 What is Counter. Explain the 4-bit Up/ Down ripple counter

Q.29 Write short notes on the following:
(i) Noise immunity (ii) Fan-out. (iii) Propagation delay (iv) Figure of merit

Q.30 Explain the principle of IIL Logic family.









1.To test and study of operation of all logic Gates for various IC's.


2.Implementation of AND, OR, NOT, NOR, X-OR and X-NOR Gates by NAND and
NOR Universal gates.


3. Binary Addition by Half Adder and Full Adder circuit.


4. Binary Subtraction by Half Subtractor and Full Subtractor circuit.


5. Design a BCD to excess-3 code converter.


6.Verification of the Demorgan's Theorem.


7. Study of RS, JK, T & D flip-flops.



LIST OF EXPERIMENTS
Format No.
Issue
Page No:
Department
Electronics & communication engineering
Session : Jan-June 2013
Name of
Teacher
Semester EVEN (IV)
Subject
Digital Electronics

Sub. Code EC-403
(B) TIME SCHEDULE : Total expected periods:__, Extra periods (if required)_____

8. Multiplexer/Demultiplexer based boolean function realization.



9. Study and Application of 555 timer (Astable, Monostable, Schmitt trigger, VCO