RTBT MUX

The figure above shows a 2:1 multiplexer using RTBT.

The figure above shows a 2:1 mux using logic gates. The working of both of them is exactly the same.



Working
The logic gate above represents the second box represents the first AND gate which has the inverter at
the selection input. The clock is the equivalent of the selection line. When the clock is high, the RTBT 2 is
turned on and the input from a is selected. The clock compliment is low and so the RTBT4 is turned off
and the final output from the second box is 0 and final output from the first box is a. These outputs
are sent to the third circuit which is the OR gate built using RTD and HBT. Since the input at HBT2 is a
and input at HBT1 is 0, the HBT1 is turned off and HBT2 is turned on, thus finally, the final output at
out is a.
When the clock is low, the RTBT2 is turned off and the input from b is selected. The clock is low and
hence the clock compliment is high and the RTBT4 is turned on. The final output form the first box is 0
and from the second box is b. These outputs are sent to the third circuit which is the OR gate built
using RTD and HBT. Since the input at HBT1 is b and input and HBT2 is 0, the HBT2 is turned off and
HBT1 is turned on, thus finally, the final output at out is b.






















MOBILE D-Flip flop operation

The above diagram shows a D-flip flop built from MOBILE. MOBILE stands for Monostable BIstable Logic
Element. MOBILE is developed by connecting an RTD with a MODFET in parallel. This structure allows us
to make compact circuits with a flexible design that allows separate optimization of MODFET and RTD.
Working
When the clk is low, there is no bias voltage, hence the output is zero.
When the clk is high, there are two cases: Data is 1 or Data is 0.
Data 1:
When Data is 1, the the MOBILE 1 is switched ON because the clock is high and GATE voltage is 1 and
MOBILE 2 is connected to the ground so the output at MOBILE 2 is 0. Now both these outputs are sent
to the SR flip flop latch. Due to MOBILE 1, the above RTD is turned off. Output of MOBILE2 turns on the
RTD at the bottom. This in total resets the flipflop and and the output at the end of the flipflop is 0, and
the last second FET is turned off as the GATE voltage is 0. Due to this FET being turned off the final FET is
also off, and so the final output is 1 as it is connected to Vdd.
Data 2:
When Data is 0, the the MOBILE 1 is switched OFF because the clock is high but the GATE voltage is 0,
and MOBILE 2 is ON because the GATE voltage is 0, so it is not connected to the ground, hence the
output at MOBILE 2 is 1. Now both these outputs are sent to the SR flip flop latch. Due to MOBILE 1, the
above RTD is turned ON. Output of MOBILE2 turns on the RTD at the bottom and it is connected to the
ground there by making it 0. This in total sets the flipflop and and the output at the end of the flipflop is
1, and the last second FET is turned ON because GATE voltage is applied. Due to this FET being turned
ON the final FET is turned OFF, and so the final output is 0 as it gets connected to the ground.



SRAM cell using RTD


The SRAM cell designed using RTD is in the latch configuration created by two stable voltage levels at
the storage node. The cell sensing capacitance is provided by the RTDs. The latch maintains two stable
low node voltage levels as long as the RTD peak-value current is larger than the cell leakage current.
Operation:
During read operation, the storage node shares charge with the bit line and a clock latching amplifier
which is used to sense this charge and restore data into the cell. When the word line is low that is cell is
not selected, the read output the storage node latches to one of the two stable voltage levels depending
on the previous return bit line level on very short time scales. RTDs action is negligible and the storage
node capacitance dynamically holds the voltage.
For example at bias of 0.45V, two stable voltage levels exist at approximately 0.08 V and 0.36 V.
The characteristics of the SRAM cell depend on the characteristic curves (I-V Curves) of both the RTDs.
The intersection of these curves gives the logic values. V-Lo is the value for LOGIC 0 and V-HI is the value
for logic 1.