A Synchronous PWM Method of Parallel AC-DC

Converters Using Hybrid-PLL Algorithm

Sung-Joon Cho*, Kwang-Hwan Lee*, Man-Kyu Jeong*, Ji-Yoon Yoo**
*Electro-Mechanical Research Institute, Hyundai-Heavy Industries Co. Ltd., **Korea University
E-mail : csj@hhi.co.kr

Abstract-This paper proposed a synchronous PWM method of
parallel AC-DC converters. The parallel AC-DC converters of
traction control system for high speed train require accurate
PLL (Phase-Locked Logic) method and synchronous PWM
algorithm with phase delay control to implement unit power
factor and input current harmonic reduction. The phase delay
control of parallel converters driven by individual controllers is
difficult. The proposed hybrid PLL algorithm detects the input
voltage phase angle more accurately and improves the
performance of phase delay control. The hybrid PLL algorithm
consists of two kinds of method which calculate simultaneously
the phase angle of input voltage. The single-phase AC-DC
converters are connected in parallel through main transformer.
The first PLL algorithm calculates the phase angle of primary
input voltage adopting the digital APF (All-Pass Filter) and it
has robust characteristics against the disturbance of input signal
compared with conventional zero-crossing detection method by
hardware circuit. The estimated phase angle of this algorithm is
used for unit power factor control and instantaneous input
current control. The second PLL algorithm generates the
common reference signal for synchronous PWM by measuring
the amplitude of input voltage at the near zero-crossing point.
This paper describes the implementation of hybrid PLL
algorithm adopting two different kinds of PLL method in detail.
The feasibility of this algorithm is proven by experimental study
on parallel converters (1.25MW4) for high speed train.
I. INTRODUCTION
The AC-DC converter requires accurate phase angle of
input voltage to implement unit power factor control. The
various PLL algorithms have been adopted to detect this
information [1]-[4]. The conventional zero crossing detection
method needs additional hardware circuit and it is dependent
on the disturbance of input voltage due to pantograph
vibration at the high speed train application. Another phase
detection method at d-q synchronous frame should transform
three phase stationary voltages to two phase signals. This
method cannot be applied directly to single-phase PWM
converter because it does not have three phase input voltages.
To solve this problem, the two phase signal generator is
introduced recently and it converts the single phase signal to
virtual two phase signals which one is the same as original
signal and the other has 90 phase delay [5]. Using this two
phase signal generator, it can calculate the phase angle at d-q
synchronous frame even though the system has single phase
input voltage.
The power circuit topology of traction control system for
high speed train is mainly single-phase PWM converters in
parallel to reduce input current harmonics because switching
frequency is limited by high power semiconductor capability.
The single phase PWM converters in parallel perform the
phase delay control according to the number of converters to
eliminate input current harmonics [6]-[9]. If the phase delay
control algorithm is implemented by the same controller, it
can guarantee constant phase delay angle accurately for each
converter. However, if the phase delay control is performed
by individual controllers which have no communication
signals between them, it may cause phase delay error between
converters in parallel due to the absence of reference signal
for synchronous PWM. Therefore, the reference signal is
necessary to adjust appreciate current phase angle in case
individual controllers perform the phase delay control.
This paper introduces synchronous PWM method for phase
delay control of parallel converters and hybrid PLL algorithm
which is robust against input voltage harmonics. This paper
also describes hardware implementation method of hybrid
PLL algorithm in detail. One PLL algorithm with digital BPF
(Band-Pass Filter) and APF (All-Pass Filter) detects phase
angle of input voltage and the other algorithm generates
reference signal for synchronization between different
controllers. The feasibility of this hybrid PLL algorithm is
proven by the experimental study on traction converters
(1.25MW4) for high speed train.

II. PROPOSED HYBRID PLL AND SYNCHRONOUS PWM
METHOD
A. Input Voltage Phase Detection Algorithm
The proposed hybrid PLL method applies two phase
voltage generator with APF and phase controller to detect
input voltage phase angle. The input voltage of high speed
train through pantograph contains higher order harmonic
components due to vibration or operation mode of other train.
When the input voltage is measured, the BPF passing only
fundamental component (i.e. 60Hz) is adopted to eliminate
harmonics effectively. The block diagram of phase detection
algorithm is shown in Fig. 1. The filtered voltage,
60 p
V ,
passed through BPF is used as an input signal of APF. Then it
can generate virtual signal with 90 phase delay as well as
original input signal.
qss
v
s set
T
S
K
K
i
P
+
+
+

dss
v
qse
v
f qse
v
_

dse
v
p
V
60 p
V
con
f dse
v
_

Fig. 1. Block diagram of phase detection algorithm.
978-1-61284-972-0/11/$26.00 2011 IEEE 1161
Two phase voltage generator with APF makes output signal
with same amplitude and 90 phase delay as shown in Fig. 2.
The APF does not influence on the magnitude of output
signal but causes phase delay. The transfer function of APF,
( ) s H , can be expressed as shown in,
( )
c
c
s
s
s H

= , (1)
where
c
represents characteristics frequency. The phase
delay angle of APF, , is determined by

=

c

1
tan 2 . (2)
It is clear that the characteristics frequency of APF should
be the same value as fundamental frequency (i.e. 60Hz) of
input signal to get the output signal with 90 phase delay
The pantograph voltage filtered by BPF is used as an input
signal of two phase voltage generator to eliminate harmonics.
If it is assumed that the input signal of two phase voltage
generator,
60 p
V , is sinusoidal voltage only with fundamental
component, it can be expressed as (3). The APF generates d-
axis voltage signal,
dss
V , that is in phase with input voltage
and q-axis voltage signal,
qss
V , which is 90
o
apart from the
input signal. These two voltages can be expressed as shown in
(4)-(5) where
s
is angular velocity and is the phase angle
of input signal.
( ) ( ) cos cos
60
E t E V
s p
= = (3)
( ) cos E V
dss
= (4)
( ) sin E V
qss
= (5)
The d-axis and q-axis voltages of stationary reference frame
in (4)-(5) can be transformed as shown in (6)-(7) where
dse
V is
d-axis synchronous reference frame voltage,
qse
V is q-axis
synchronous reference frame voltage and

is estimated phase
angle of input signal.

sin

cos
qss dss dse
V V V + = (6)

cos

sin
qss dss qse
V V V + = (7)
If the error between actual phase angle, , and estimated
phase angle,

, is small, synchronous reference frame

voltages in (6)-(7) can be approximated as (8)-(9).
( ) E E V
dse
=

cos (8)
( ) ( )

sin = E E V
qse
(9)
From (8)-(9), d-axis synchronous reference frame voltage,
dse
V , represents the magnitude of input signal and q-axis
synchronous reference frame voltage,
qse
V , represents the
estimated phase error. In case the input voltage of phase
controller contains harmonics, filtered synchronous reference
frame voltages,
dsef
V and
qsef
V , are obtained using LPF(Low-
Pass Filter). The magnitude of input signal is determined by
filtered d-axis synchronous reference frame voltage,
dsef
V , as
shown in (8). The PI controller of Fig. 1 regulates q-axis
synchronous reference frame voltage,
qsef
V as zero to estimate
phase angle of input voltage. It makes the phase error between
estimated angle and actual angle becomes zero. The dynamic
response characteristics of phase controller can be improved
by adding the phase increment of preset fundamental
frequency. Therefore, the estimated phase angle,

, is
calculated from the output of PI controller,
con
, and feed
forward component as shown in,

AD set con
T + =

, (10)
where
set
is preset fundamental angular velocity of input
signal.
This phase controller with appropriate digital filter design
has robust phase detection characteristics regardless of input
signal disturbance and it does not need any additional
hardware circuit.

B. Zero-Crossing Point Detector for Synchronous PWM
The reference signal for synchronous PWM is necessary, if
individual controllers adjust phase delay for each converter
which is connected in parallel. The common information of
converters driven by individual controllers is only pantograph
voltage. Therefore, if the frequency of pantograph voltage is
measured by detecting zero crossing point and change the
PWM period according to this frequency, then synchronous
PWM for parallel converters can be implemented easily.
The detection algorithm for pantograph voltage zero
crossing point is shown as Fig. 3. The proposed algorithm is
performed by each period of pantograph voltage while
synchronous PWM is carried out by fast sampling time,
s
T . If
individual controller, TCU (Traction Control Unit), performs
m times PWM control during one cycle of pantograph voltage
and the same TCU drives the number of l parallel converters,
the sampling time,
s
T , for synchronous PWM can be
expressed as

m l
T
T
PLL
s

=
2
, (11)
dss
V
qss
V
60 p
V
set
f
1
Fig. 2. Block diagram of two phase voltage generator.
prms
V 2
1 s
1
p
V
PLL
T
s
T
m l 2
1
lpf p
V
_
Fig. 3. Block diagram of zero-crossing detector
1162
where
PLL
T is the estimated period of pantograph voltage and
it is determined by zero-crossing detection algorithm for
synchronous PWM.
The zero-crossing point detector measures the amplitude of
input voltage at every estimated period,
PLL
T , and adjusts the
estimated period to make this amplitude become zero by PI
controller. For example, if the measured amplitude of input
voltage is positive, the zero-crossing detection algorithm
decreases the estimated period. It means that the duration of
next measurement becomes shorter than just before period and
it makes for us to detect actual zero-crossing point. If the
measured amplitude of input voltage is negative, the controller
increases the estimated period compared with current value.
This proposed algorithm can estimate the period of input
voltage by adjusting calculation interval time. Therefore, the
calculated sampling time from (11) will vary according to the
change of pantograph voltage frequency. Since this kind of
zero-crossing detection algorithm is easily affected by input
voltage noise, it is possible to insert LPF having very low cut
off frequency when measuring pantograph voltage. Although
the input voltage signal passed through LPF can be attenuated
and delayed, it is an effective signal to detect only the period
of fundamental voltage because LPF eliminates high order
harmonics.

C. Synchronous PWM with Hybrid PLL Algorithm
The voltage command of single converter,
*
c
V , which is
driven by alone can be expressed as shown in,
( )
c c c
V V =

cos
* *
, (12)
where
c
and

represent phase angle of voltage command

and estimated input voltage phase angle, respectively [10].
The phase angle of voltage command can be calculated from
input voltage,
s
V , input current,
s
I , boosting reactor,
s
L , and
input voltage angular velocity,
s
, as,

s
s s s
c
V
I L

1
tan

= . (13)
The phase relationship between input voltage, input current
and converter voltage command can be seen in Fig. 4. The
input current and voltage are in phase to implement unit power
factor and the direction of input current is different whether
the traction control system is operating as powering or braking
mode. When the traction control system is operating as
powering mode, the input source supplies a dissipated power
to traction motors. Since the power should be regenerated
from motors in braking mode, the input current phase is
opposite to the input voltage, as can be seen in Fig. 4.
The parallel converters voltage command and phase delay
angle,
*
_ k c
V and
delay
, can be expressed as shown in,
( ) ( ) ( ) n k k V V
delay c k c k c
..., , 2 , 1 , 1

cos
*
_
*
_
= = , (14)

n
T
T
s
PLL
delay
=
1
2 , (15)
where n represents the total number of converters in parallel
driven by multi-controllers. For example, from (11) and (15),
the phase delay angle is 10 for two converters in parallel with
9 times synchronous PWM during one period of input voltage.
It can be known easily that the phase delay angle is 5 for four
converters in parallel with same switching frequency. In case
single TCU drives four converters in parallel at the same time,
it is possible to interleave input currents using only phase
delay control of converter voltage command even though
individual converter performs asynchronous PWM. However,
the asynchronous parallel operation of converters by multi-
TCUs has difficulty to implement exact phase delay control
due to the quantization error and interrupt priority of digital
controller. Therefore, the proposed algorithm performs
synchronous PWM continuously according to the frequency of
input voltage and it can guarantee accurate phase delay
between converters. The control block diagram of parallel
converters using proposed synchronous PWM with hybrid
PLL is shown in Fig. 5. The main power circuit consists of a
main transformer and four converters in parallel, and two sets
of converter have common DC-link as shown in Fig. 5. Each
TCU can drive two converters simultaneously so two sets of
TCU are necessary to operate four converters and there are no
communication data between TCUs. To implement

s
V
*
c
V
s
I
s s s
I L j
c

s
V
s
I
s s s
I L j
c

*
c
V

Fig. 4. Phase diagram of input voltage, current and converter voltage
command.
1 dc
V
+
-
+
-
+
+ *
1 dc
V 2 /
m
i
*
1 C
V
s
V
*
s
i
p
V
*
1 U
G
*
1 V
G
s
V
Phase
controller
sin

PI
BPF
PI PWM
+
-
+
+
2 s
i
*
2 C
V
s
V
*
s
i
*
2 U
G
*
2 V
G PI PWM
1 s
i
s
L 2 s
i
s
L
1 s
i
1 dc
V
Zero
crossing
detector
m n 2
1 1 s
T
1 PLL
T
TractionControlUnit1
s
V
2 dc
V
+
-
+
-
+
+ *
2 dc
V 2 /
m
i
*
3 C
V
s
V
*
s
i
p
V
*
3 U
G
*
3 V
G
s
V
Phase
controller
sin

PI
BPF
PI PWM
+
-
+
+
4 s
i
*
4 C
V
s
V
*
s
i
*
4 U
G
*
4 V
G PI PWM
3 s
i
s
L
4 s
i
s
L
3 s
i
2 dc
V
Zero
crossing
detector
m n 2
1 2 s
T
2 PLL
T
TractionControlUnit2
s
V
p
V
CNV1
CNV2
CNV3
CNV4
Main
Trnasforme
r
Delay
time
calculate
r
2 d T
1 d
T
Delay
time
calculat
er
3 d
T
4 d
T
Fig. 5. Control block diagram of synchronous PWM converters.
1163
synchronous PWM with hybrid PLL algorithm, the sampling
time,
1 s
T , for CNV1 (converter 1) & CNV2 (converter 2) and
sampling time,
2 s
T , for CNV3 (converter 3) & CNV4
(converter 4), can be determined respectively from (11).
The proposed algorithm adjusts the delay time of interrupt
generation instant with respect to pantograph voltage zero-
crossing point maintaining sampling time
1 s
T and
2 s
T to be
equal, the effect of this method is equivalent to phase delay
control of converter voltage command.
The delay time of interrupt generation,
dk
T , can be
expressed as shown in,
( )
( ) ( ) ( )

=
2 /
2 / 1 mod 1
1
2 2 n
k n
k
n
m n
T
T
PLL
dk
, (16)

( )
( )

=
2
1
mod 1
2
1
2
k
n
k n
m n
T
T
PLL
dk
, (17)
where n and m represent the number of converters in parallel
and the number of PWM control during input voltage one
period, mod represents a function which is calculating
quotient. This phase delay control using (17) can be explained
by the concept of SVM (Space-Vector Modulation) state
information. The state information of four converters with
asynchronous PWM is shown as Fig. 6. This figure is an
example that input voltage and switching frequency are 60Hz
and 540Hz, respectively. Two converters, CNV1 & CNV2, are
driven by one controller, TCU1, and the state information of
two converters has 90 phase difference. Another two
converters, CNV3 & CNV4, are also driven by same
controller, TCU2, and the state information for these
converters is 90 apart from each other. In this case, 90 phase
difference means that the delay time between states is 463s.
Asynchronous PWM method cannot synchronize the zero-
crossing point of input voltage and state information due to the
frequency change of input voltage and quantization error of
digital controller even though PWM control interrupt of
CNV1 coincide with zero-crossing point of input voltage at
the first time. The delay time of interrupt generation,
dk
T ,
cannot be defined by constant value during operation as shown
in Fig. 6. Therefore, the harmonics of converter input currents
does not interleave each other appropriately and it means that
the harmonics of transformer primary current cannot be
eliminated effectively.
The state information of four converters with synchronous
PWM is shown in Fig. 7. The initial PWM control interrupt of
CNV1 is synchronized with reference signal generated from
hybrid PLL to coincide with zero-crossing point of input
voltage. In this example, the delay time of interrupt
generation for CNV2,
2 d
T , is set as 463s by (17). The delay
time of interrupt generation for CNV3 and CNV4,
3 d
T and
4 d
T , are 232s and 695s, respectively.
Since the reference signal for synchronous PWM is
obtained by zero-crossing detector, the phase delay control
can be implemented effectively although the frequency of
input voltage varies or the quantization error of digital
controller has happened. The harmonic reduction effect by
parallel operation with synchronous PWM has improved, as
shown in Fig. 8. The additional harmonic reduction is
possible due to the interleaving input currents between
parallel converters driven by separated TCU.
III. EXPERIMENTAL STUDY
To verify the validity of the proposed technique, an
experimental study was performed on traction control system
for high speed train. The converter specification of traction
control system is described in table 1. The traction control
system for experiment is shown in Fig. 9. The input currents
waveform of 4 converters with asynchronous PWM method is
shown in Figs. 10-11. These waveforms show the CNV1 input
current (I
s1
, 500A/div), CNV2 input current (I
s2
, 500A/div),
CNV3 input current (I
s3
, 500A/div), CNV4 input current (I
s4
,
500A/div), respectively. These waveforms show no-load
characteristics of input currents, and the harmonic components
between CNV1 & CNV2 driven by same controller are 180
apart from each other. However, the phase difference of
harmonics between CNV1 & CNV3 driven by individual
controller cannot be defined a certain value during operation.
The phase difference of harmonics between CNV1 & CNV3
was measured by 64s, as shown in Fig. 11, but it was
different from operating time.
PLL
T
1 s
T
2 s
T
1 d
T
2 d
T
1 s
T
3 d
T
2 s
T 4 d
T

Fig. 6. State information of 4 converters in parallel (Asynchronous PWM).
Pantograph
voltageVp
Phaseangle
CNV1state
CNV2state
CNV3state
CNV4state
PLL
T
1 s
T
s T
d
463
2
=
1 s
T
s T
d
0
1
=
2 s
T
2 s
T
s T
d
232
3
=
s T
d
695
4
=
Fig. 7. State information of 4 converters in parallel (Synchronous PWM).
1164

The input current waveforms of 4 converters with proposed
synchronous PWM method are shown in Figs. 12-13. These
waveforms show no-load characteristics of input currents, and
the harmonic components between CNV1 & CNV2 are 180
apart from each other. Additionally, the phase difference of
harmonics between CNV1 & CNV3 was 90(about 230s)
apart, as shown in Fig. 13. The harmonic components are
eliminated more effectively by interleaving input currents as
shown in Fig. 12. The load test using traction motors and
inertia load was also performed and the result is as shown in
Fig. 14. One traction control system drove inertia load and the
other was no-load condition. The harmonic reduction can be
carried out effectively under load condition as well as no-load.
To verify the validity of the proposed hybrid PLL algorithm,
a train running test was performed on KTX-II (Korean Train
eXpress-II). The KTX-II train set consists of 10 cars (2 power
cars, 8 trailer cars) as shown in Fig. 15. Each power car has 1
main transformer and two traction control systems, so four
converters perform parallel operation control simultaneously.
The waveform in Fig. 16 describes acceleration test result
from standstill to 300km/h. It shows that the proposed
algorithm with hybrid PLL has good characteristics over the
operating speed range.
IV. CONCLUSION
A synchronous PWM method with hybrid PLL algorithm
for parallel converters was proposed in this paper. The hybrid
1 s
T
1
2
s
T 1
3
s
T
1
4
s
T
1 c
V
1 s
i
2 c
V
2 s
i
1 d
T
2 s
T
2
2
s
T
2
3
s
T
2
4
s
T
3 d
T
2 d
T
3 c
V
3 s
i
4 c
V
4 s
i
4 1
~
s s
i i

Fig. 8. Parallel converter operation control with synchronous PWM

Fig. 9. Traction control system for high speed train

Fig. 10. Converter input currents (Asynchronous PWM).

Fig. 11. Converter input currents (Asynchronous PWM).
I
s1
I
s3
I
s2

I
s4
64s
TABLE I
SPECIFICATION OF CONVERTER
Capacity 1250kW2
Input voltage 1400Vac
Input current 928A
Output voltage 2800Vdc
Output current

857A
Power semiconductor
Press pack type IGBT
(5200V/4000A)
Cooling Heat pipe, forced cooling
Switching frequency 540Hz
1165
PLL algorithm estimates instantaneous input voltage phase
angle based on two voltage generator and phase controller at
the synchronous reference frame. The appropriate digital filter
design improves the robust estimation characteristics against
input voltage disturbances. It can also contribute to input
current control characteristics due to exact phase angle
estimation. The proposed algorithm using reference signal of
zero-crossing detector can synchronize PWM of individual
controller. This proposed synchronous PWM method is
effective to reduce primary current harmonics. The phase
delay control of converter voltage command was implemented
by the time delay of interrupt generation. The validity of
proposed algorithm for parallel converters was proven by
experimental study on traction control system (1.25MW2
converters) for high speed train, KTX-II.
The proposed technique is expected to help improve the
reliability of phase angle estimation and harmonics reduction,
since the hybrid PLL algorithm has robust characteristics and
exact converter phase delay control was achieved.
REFERENCES
[1] Y. K. Kim, J. W. Choi and H. G. Kim, The analysis of Characteristics
for digital PLL control, Proc. of Power Electronics Annual
Conference, July 2003, pp. 548-553.
[2] L. N. Amuda, B. J. Cardoso Filho, S. M. Silva, S. R. Silva and A. S. A.
C. Diniz, "Wide bandwidth single and three-phase PLL structures for
grid-tied PV systems," in Proc. 2000 Photovoltaic Specialists
Conference, 2000. Conference Record of the Twenty-Eighth IEEE,
pp.1660-1663.
[3] L. N. Arruda, S. M. Silva and B. J. C. Filho, "PLL structures for utility
connected systems," in Proc. 2001 Industry Applications Conference,
2001. Thirty-Sixth IAS Annual Meeting. Conference Record of the 2001
IEEE, pp. 2655-2660.
[4] M. Saitou and T. Shimizu, "Generalized theory of instantaneous active
and reactive powers in single-phase circuits based on Hilbert
transform," in Proc. 2002 Power Electronics Specialists Conference,
2002. pesc 02. 2002 IEEE 33rd Annual, pp. 1419-1424.
[5] T. Thacker, W. Ruxi, D. Dong, R. Burgos, F. Wang and D. Boroyevich,
"Phase-Locked Loops using State Variable Feedback for Single-Phase
Converter Systems," in Proc. 2009 Applied Power Electronics
Conference and Exposition, 2009. APEC 2009. Twenty-Fourth Annual
IEEE, pp. 864-870.
[6] M. K. Jeong, S. J. Cho, K. J. Lee, G. T. Park, D. S. Kim, A study on
inertia load test of propulsion control system for Korean Train Express,
Proc. of Power Electronics Annual Conference Korean Institute of
Power Electronics, July 2009, pp. 369-371.
[7] S. J. Cho, M. K. Jeong, K. J. Lee, G. T. Park, D. S. Kim, A study on
propulsion control system for Korean Train Express, Proc. of Power
Electronics Annual Conference, Korean Institute of Power Electronics,
July 2010, pp. 295-296.
[8] A. I. Maswood and M. H. Rashid, Input current harmonic reduction in
high power AC/DC rectifier, in Proc. of IECON, 1991, pp.593-599,
1991.
[9] H. J. Jung, B. G. Park and D. S. Hyun, Design of the feed-forward
controller of a single-phase AC/DC PWM converter in parallel for
high-speed train, in Proc. 2009 Industry Applications Society Annual
Meeting, 2009. IAS 2009., pp. 1-6.
[10] H. W. Lee, S. Y. Jang, Y. J. Kim and K. J. Lee, The parallel operation
of single phase PWM rectifier using IGCT, Korean Institute of Power
Electronics Trans. On Power Electronics, Vol. 5, No. 1, pp. 11-18,
2000.


Fig. 12. Converter input currents (Synchronous PWM).

Fig. 13. Converter input currents (Synchronous PWM).

Fig. 14. Converter input currents with inertia load (Synchronous PWM).
Fig. 15. Train set configuration of KTX-II.
Fig. 16. Running test waveform of KTX-II.
Pantograph voltage
(62.5kV/div)
Converter 2 current
(3300A/div)
Converter 1 current
(3330A/div)
DC-link voltage
(3330A/div)
DC-link current
(4000A/div)
Chopper current
(1660A/div)
Tractive effort command
(50kN/div)
Actual tractive effort
(50kN/div)
Inverter RMS current command
(1000A/div)
Actual inverter RMS current
(1000A/div)
U-phase motor current
(3330A/div)
Slip frequency
(2.5Hz/div)
Powering/Braking command
(200%/div)
Speed
(25km/h/div)
230s
I
s1
I
s3
I
s2

I
s4
305sec
300km/h
10sec/div
1166
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