Open-Silicon Confidential Open-Silicon Confidential

Static Timing Analysis

January 05
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Goals for today

Introduction to STA and the basic idea behind

the process.

STA inputs and outputs.

Defining and applying constraints.

Analyze the results of STA.

Saple STA run and reports

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Synchronous Design

In Synchronous Design Cloc" Controls the

Dataflo#$$$

On %&ery Cloc" Tic" data o&es fro one

State to Another

'ogic Delay bet#een t#o state has to be

'ess then cloc" (eriod

Alost all ASICs are Synchronous Designs

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Synchronous Design: Example

Out * +,b+ if -A./01-C.D0 else +,b2

A
B

D
l!
"ut
Add
Add
omp#
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Timing Analysis

'ogic delay bet#een any t#o 4lops

need to be saller then Cloc" (eriod

There are T#o #ays to &erify

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Dynaic Tiing analysis
5
Static Tiing analysis
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Dynamic Timing analysis

Tiing siulation #ith Series of

4unctional &ectors

Siulator #ill ta"e in netlist7 8ate

delays

Chec" if there is any Tiing 9iolations

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Dynamic Timing analysis

;ea"ness of DTA
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It is difficult to generate &ectors #hich
co&er all cobinations of logic
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<e=uires huge C(> and ?eory
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Tie consuing
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Static Timing Analysis

Design is bro"en do#n in sets of tiing

paths

Delay of each path is calculated

Copare path delay to constraints

chec" if they ha&e been et

;hy is it called STA$

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Static timing analysis: Ad$antages

Do not re=uire any &ectors

<uns &ery fast

?ore efficient in C(> and ?eory

usage
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%hat STA chec!s

If design Can #or" at gi&en ?aB 4re=uency

If Design can #or" in different operating

-(9T0 conditions

If Design Satisfies %lectrical constraints

-Trans7 cap7 fanout etc0

Signal Integrity of routing

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Timing &aths

Design is bro"en do#n in sets of signal

paths

%ach path has startpoint and %ndpoint

Startpoint is (riary Input or Cloc"

pins of <egister

%ndpoint is (riary output or D pins of

registers

<egister is a cell #ith setupCDold tie

re=uireent e.g 4lop7 ?eory etc.
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Timing path Types
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Timing path Types cont'

&rimary input to register

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Start (rom )nput &in* Ends at +egister
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Example )n, to ((,
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+e-uires Setting input delay at input
pin relati$e to cloc!
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Timing path Types cont'

+egister to register
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Start from loc! pin of +egister
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Ends at D pin of +egister
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Example: &ath .et/een ((, to ((0
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onstrained .y specification of the
cloc!
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Timing path Types cont'

+egister to output
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Start from loc! pin of +egister
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Ends at "utput &in
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Example: &ath .et/een ((0 to "ut,
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onstrained .y specification "utput
delay on output port
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Timing path Types cont'

)nput to output
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Start from )nput &in
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Ends at "utput &in
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Example: &ath .et/een )n0 to "ut0
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onstrained .y specification "utput
delay on output port and input delay
on input port
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&ath Groups

(aths are grouped according to cloc"s

controlling their endpoints

Set of paths associated #ith a cloc" is

called as path group

All paths #ith no particular cloc" goes

to default path group
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Timing hec!s

Typical Tiing chec"s done are

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Setup and Dold
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<eco&ery and <eo&al
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?iniu pulse #idth
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8litch detection -cloc" gating0
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Setup and 1old

?iniu tie that a data input pin of

a Se=uential cell ust be stable Before
Cloc" Transition.

?iniu tie that a data input pin of

a Se=uential cell ust be stable After
Cloc" Transition.
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+eco$ery and +emo$al

<eco&eryE ?iniu tie

that an asynchronous
control input pin ust be
stable after deserted and
before neBt cloc" edge

<eo&alE ?iniu tie

that an asynchronous
input pin ust be stable
before being deserted and
after the pre&ious cloc"
edge
Reset
Reset
Clock
Clock
Recovery
Removal
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2inimum loc! &ulse %idth

?iniu Aount of tie bet#een t#o

consecuti&e <ise and fall edge of the cloc"
Minimum High
Pulse width
Minimum Low
Pulse width
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Glitch Detection -Cloc" getting chec"0
+
Flip Flop
CLK
En
Clk
Clk
En
FF.Clk
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onstraints

Constraints are Designer,s goals

<estriction put by technology library

also =ualify as constraints

STA easures if these goals are et.

Typical constraints are cloc"7 inputCout

put delays7 design specific tiing
re=uireents
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Types "f onstraints
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Defining cloc!

Defines #hich are the cloc" ports and the

cloc" attributes

createFcloc" Gperiod +2n G#a&efor H2 3I G

nae cl"
;a&efor starts at 2 #ith 32J duty cycle
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Generated3Deri$ed cloc!

Internal cloc" is di&ide by )

createFgeneratedFcloc"
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4irtual cloc!

This path is constrained by a cloc" -cl"0

outside of chip
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loc! Distri.ution
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loc! &arameters

Cloc" s"e#

Cloc" uncertainty

Cloc" insertion delay

Cloc" Kitter

Ideal and propagated cloc"

Do# this paraeters affects

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loc! s!e/
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loc! 5itter
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loc! latency3delay
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)deal and computed loc!

Off chip cloc" effects are fiBed throughout

a. Source latency
b. Litter

On chip routing is estiated for ideal cloc"

a. /udgeted net#or" latency
b. /udgeted s"e#

On chip routing is coputed after CTS

a. Actual insertion delay
b. Actual s"e#
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Setting )nput Delay

Input signal arri&es at 2.3ns after rising

edge of CM

SetFinputFdelay
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Setting "utput Delay

Output signal needs to arri&e tie at O after

By ns

SetFoutputFdelay
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)nput Dri$e strength

Along #ith tiing constraints one needs to

specify design en&ironent

SetFdri&ingFcell
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"utput load

Setting output load

SetFdri&ingFcell
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hec! 6 hec!7 hec!

Chec"Ftiing #ill chec" if e&ery thing

is constrained
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Timing onstraints Tutorial

Deri&e top 'e&el SDC fro 8i&en

Data
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(alse &ath
A false path is a tiing path that cannot
propagate a signal.

A path ay eBist in the circuit but ne&er

be used

A functional path ay eBist but the

tiing is &ery slo# or irrele&ant

A path ay eBist in the circuit but no

cobination of input &ectors ay e&er
eBercise it
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(alse path Example
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(alse path Example:
&aths Bet/een T/o cloc!s
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2ultiycle &ath

A ulticycle path is a tiing path that is not

eBpected to propagate a signal in one cycle.

Norally7 all paths are constrained for

single-cycle tiing.

?ulticycle paths are eBceptions to the

default single-cycle tiing..

?ulticycle paths are defined by coand

setFulticycleFpath.
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2ultiycle &aths
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(unctional 2odes

CopleB Designs can ha&e ultiple Tie

paths that are dependent on the enabled
functional odes

%.g Noral 4unctional ode and Debug

?ode

Case analysis pro&ides a eans of setting

constant paths that you #ant the tool to
ignore during tiing analysis
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"perating onditions

The operating conditions of a design usually

include the process7 &oltage7 and
teperature ranges a design encounters.

Operating conditions are defined in a

technology library in an operatingFconditions
group.

Oou can choose operation condition by

setFoperatingFcondition
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Specify Design data
and libraries
Specify
Interconnect
Specify Clocks
Specify
Input/Output
Delays
Specify
Timing
Exceptions
ASIC
Netlist
ASIC
Liarary
SP!"
#ire Load
Models
$ack%
annotated
STA 2ethodology
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STA 2ethodology
Ceck Timing
!pdate Timing
"enerate
#eports
Constraints
&iolators
Path
'iming
$ottleneck
Re(orts
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Delays

Total Delay * Cell Delay . Interconnect

Delay

Cell Delay depend upon Input

transition and output cap.

Interconnect Delay depends upon

capacitance and resistance

>ser need to pro&ide Interconnect <7 C

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Specify )nterconnect

Standard parasitic %Bchange forat

-S(%40 file
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%Btracted < and C

Standard Delay 4orat -SD40

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Accurate tiing inforation fro Delay
calculation tool

;ireload ?odels
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(re-layout net delay estiates
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&ath Delay

Actual path delay is su of net and

cell delays along tiing the path
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8et Delays

Is the total tie need to charge or

discharge all the parasites of a Net

Net parasites depends up on

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Net 'ength
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Net <outing
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Net 4anout
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"n7hip $ariation

Intra die &ariation and intra #afer process

&ariations.

Teperature and &oltage &ariation on the

die.

Deration of the appropriate path for the

analysis so that additional argin is
obtained.
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S) effects

%ffect of signal propagation on one net7

affecting another adKacent net.

Causes delay push out and glitch in the

&icti net.

(T-SI analysis
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STA /al! through
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Goals for today

Introduction to STA and the basic idea behind

the process.

STA inputs and outputs.

Defining and applying constraints.

Analyze the results of STA.

Saple STA run and reports