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SYLLABUS

EC 2254 LINEAR INTEGRATED CIRCUITS 3 0 0 3


AIM:
To teach the basic concepts in the design of electronic circuits using linear integrated circuits and their
applications in the processing of analog signals.
OB1ECTIVES
To introduce the basic building blocks of linear integrated circuits.
To teach the linear and non-linear applications of operational amplifiers.
To introduce the theory and applications of analog multipliers and PLL.
To teach the theory of ADC and DAC
To introduce the concepts of waveform generation and introduce some special function Cs.
UNIT - I IC FABRICATION AND CIRCUIT CONFIGURATION FOR LINEAR ICS
9
Advantages of Cs over discrete components ! "anufacturing process of monolithic cs ! Construction of
monolithic bipolar transistor ! "onolithic diodes ! ntegrated #esistors ! "onolithic Capacitors !
nductors. Current mirror and current sources$ Current sources as active loads$ %oltage sources$ %oltage
#eferences$ &'T Differential amplifier with active loads$ (eneral operational amplifier stages -and internal
circuit diagrams of C )*+$ DC and AC performance characteristics$ slew rate$ ,pen and closed loop
configurations.
UNIT - II APPLICATIONS OF OPERATIONAL AMPLIFIERS 9
-ign Changer$ -cale Changer$ Phase -hift Circuits$ %oltage .ollower$ %-to- and -to-% converters$ adder$
subtractor$ nstrumentation amplifier$ ntegrator$ Differentiator$ Logarithmic amplifier$ Antilogarithmic
amplifier$ Comparators$ -chmitt trigger$ Precision rectifier$ peak detector$ clipper and clamper$ Low-pass$
high-pass and band-pass &utterworth filters.
UNIT - III ANALOG MULTIPLIER AND PLL 9
Analog "ultiplier using /mitter Coupled Transistor Pair - (ilbert "ultiplier cell - %ariable
transconductance techni0ue$ analog multiplier Cs and their applications$ ,peration of the basic PLL$
Closed loop analysis$ %oltage controlled oscillator$ "onolithic PLL C 121$ application of PLL for A"
detection$ ." detection$ .-3 modulation and demodulation and .re0uency synthesi4ing.
UNIT - IV ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS 8
Analog and Digital Data Conversions$ D5A converter ! specifications - weighted resistor type$ #-6# Ladder
type$ %oltage "ode and Current-"ode R 2 R Ladder types - switches for D5A converters$ high speed
sample-and-hold circuits$ A5D Converters ! specifications - .lash type - -uccessive Appro7imation type -
-ingle -lope type - Dual -lope type - A5D Converter using %oltage-to-Time Conversion - ,ver-sampling
A5D Converters.
UNIT - V WAVEFORM GENERATORS AND SPECIAL FUNCTION ICs 9
-ine-wave generators$ "ultivibrators and Triangular wave generator$ -aw-tooth wave generator$ CL89:8
function generator$ Timer C 111$ C %oltage regulators - Three terminal fi7ed and ad;ustable voltage
regulators - C )6: general purpose regulator - "onolithic switching regulator$ -witched capacitor filter C
".+9$ .re0uency to %oltage and %oltage to .re0uency converters$ Audio Power amplifier$ %ideo
Amplifier$ solation Amplifier$ ,pto-couplers and fibre optic C.
TOTAL : 45 PERIODS
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TEXT BOOKS:
+. -ergio .ranco$ Design with operational amplifiers and analog integrated circuits$ :
rd
/dition$ Tata
"c(raw-<ill$ 699).
6. D.#oy Choudhry$ -hail 'ain$ Linear ntegrated Circuits$ =ew Age nternational Pvt. Ltd.$ 6999.
REFERENCES:
+. &.-.-onde$ -ystem design using ntegrated Circuits $ =ew Age Pub$ 6nd /dition$ 699+
6. (ray and "eyer$ Analysis and Design of Analog ntegrated Circuits$ >iley nternational$ 6991.
:. #amakant A.(ayakwad$ ,P-A"P and Linear Cs$ Prentice <all 5 Pearson /ducation$ *
th
/dition$
699+.
*. '."ichael 'acob$ Applications and Design with Analog ntegrated Circuits$ Prentice <all of ndia$
+??2.
1. >illiam D.-tanley$ ,perational Amplifiers with Linear ntegrated Circuits$ Pearson /ducation$
699*.
2. 3 Lal 3ishore$ ,perational Amplifier and Linear ntegrated Circuits$ Pearson /ducation$ 6992.
). -.-alivahanan @ %.-. 3anchana &haskaran$ Linear ntegrated Circuits$ T"<$ 6998.
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UNIT -I
IC FABRICATION AND CIRCUIT CONFIGURATION FOR LINEAR ICs
Integrated Circuits :
An integrated circuit ACB is a miniature$ low cost electronic circuit consisting of active and
passive components fabricated together on a single crystal of silicon. The active components are
transistors and diodes and passive components are resistors and capacitors.
Advantages of integrated circuits:
"iniaturi4ation and hence increased e0uipment density.
Cost reduction due to batch processing.
ncreased system reliability due to the elimination of soldered ;oints.
mproved functional performance.
"atched devices.
ncreased operating speeds.
#eduction in power consumption
Classification :
ntegrated circuits can be classified into analog$ digital and mi7ed signal Aboth analog and digital
on the same chipB. &ased upon above re0uirement two different C technology namely "onolithic
Technology and <ybrid Technology have been developed. n monolithic C $all circuit
components $both active and passive elements and their interconnections are manufactured into or
on top of a single chip of silicon. n hybrid circuits$ separate component parts are attached to a
ceramic substrate and interconnected by means of either metalli4ation pattern or wire bounds.
Digital integrated circuits can contain anything from one to millions of logic gates$ flip-flops$
multiple7ers$ and other circuits in a few s0uare millimeters. The small si4e of these circuits allows
high speed$ low power dissipation$ and reduced manufacturing cost compared with board-level
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integration. These digital Cs$ typically microprocessors$ D-Ps$ and micro controllers work using
binary mathematics to process ConeC and C4eroC signals.
Analog Cs$ such as sensors$ power management circuits$ and operational amplifiers$ work by
processing continuous signals. They perform functions like amplification$ active filtering$
demodulation$ mi7ing$ etc. Analog Cs ease the burden on circuit designers by having e7pertly
designed analog circuits available instead of designing a difficult analog circuit from scratch.
Cs can also combine analog and digital circuits on a single chip to create functions such as A5D
converters and D5A converters. -uch circuits offer smaller si4e and lower cost$ but must carefully
account for signal interference
Classification of ICs:
ntegrated Circuits
"onolithic Circuits <ybrid Circuits
&ipolar Dnipolar
p-n ;unction Dielectric ",-./T './T
solation solation
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Generations
SSI, MSI and LSI
The first integrated circuits contained only a few transistors. Called C-mall--cale ntegrationC
A--B$ digital circuits containing transistors numbering in the tens provided a few logic gates for
e7ample$ while early linear Cs such as the Plessey -L69+ or the Philips TAA:69 had as few as
two transistors. The term Large -cale ntegration was first used by &" scientist #olf Landauer
when describing the theoretical concept$ from there came the terms for --$ "-$ %L-$ and DL-.
They began to appear in consumer products at the turn of the decade$ a typical application being
." inter-carrier sound processing in television receivers.
The ne7t step in the development of integrated circuits$ taken in the late +?29s$ introduced devices
which contained hundreds of transistors on each chip$ called C"edium--cale ntegrationC A"-B.
They were attractive economically because while they cost little more to produce than -- devices$
they allowed more comple7 systems to be produced using smaller circuit boards$ less assembly
work Abecause of fewer separate componentsB$ and a number of other advantages.
VLSI
The final step in the development process$ starting in the +?89s and continuing through the present$
was Cvery large-scale integrationC A%L-B. The development started with hundreds of thousands of
transistors in the early +?89s$ and continues beyond several billion transistors as of 699).
n +?82 the first one megabit #A" chips were introduced$ which contained more than one million
transistors. "icroprocessor chips passed the million transistor mark in +?8? and the billion
transistor mark in 6991
ULSI, WSI, SOC and 3D-IC
To reflect further growth of the comple7ity$ the term DL- that stands for CDltra-Large -cale
ntegrationC was proposed for chips of comple7ity of more than + million transistors.
>afer-scale integration A>-B is a system of building very-large integrated circuits that uses an
entire silicon wafer to produce a single Csuper-chipC. Through a combination of large si4e and
reduced packaging$ >- could lead to dramatically reduced costs for some systems$ notably
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massively parallel supercomputers. The name is taken from the term %ery-Large--cale ntegration$
the current state of the art when >- was being developed.
-ystem-on-a-Chip A-oC or -,CB is an integrated circuit in which all the components needed for a
computer or other system are included on a single chip. The design of such a device can be
comple7 and costly$ and building disparate components on a single piece of silicon may
compromise the efficiency of some elements.
<owever$ these drawbacks are offset by lower manufacturing and assembly costs and by a greatly
reduced power budgetE because signals among the components are kept on-die$ much less power is
re0uire. Three Dimensional ntegrated Circuit A:D-CB has two or more layers of active electronic
components that are integrated both vertically and hori4ontally into a single circuit.
Communication between layers uses on-die signaling$ so power consumption is much lower than
in e0uivalent separate circuits. 'udicious use of short vertical wires can substantially reduce overall
wire length for faster operation.
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Construction of a Monolithic Bipolar Transistor:
The fabrication of a monolithic transistor includes the following steps.
+. /pita7ial growth
6. ,7idation
:. Photolithography
*. solation diffusion
1. &ase diffusion
2. /mitter diffusion
). Contact mask
8. Aluminium metalli4ation
?. Passivation
The letters P and = in the figures refer to type of doping$ and a minus A-B or plus AFB with P and =
indicates lighter or heavier doping respectively.
1. Epitaxial growth:
The first step in transistor fabrication is creation of the collector region. >e normally
re0uire a low resistivity path for the collector current. This is due to the fact that$ the collector
contact is normally taken at the top$ thus increasing the collector series resistance and the %
C/A-atB
of
the device.
The higher collector resistance is reduced by a process called buried layer as shown in figure. n
this arrangement$ a heavily doped G=H region is sandwiched between the =-type epita7ial layer and
P ! type substrate. This buried =
F
layer provides a low resistance path in the active collector
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region to the collector contact C. n effect$ the buried layer provides a low resistance shunt path for
the flow of current.
.or fabricating an =P= transistor$ we begin with a P-type silicon substrate having a
resistivity of typically +I-cm$ corresponding to an acceptor ion concentration of +.* J +9
+1
atoms5cm
:
. An o7ide mask with the necessary pattern for buried layer diffusion is prepared. This is
followed by masking and etching the o7ide in the buried layer mask.
The =-type buried layer is now diffused into the substrate. A slow-diffusing material such
as arsenic or antimony us used$ so that the buried layer will stay-put during subse0uent diffusions.
The ;unction depth is typically a few microns$ with sheet resistivity of around 69I per s0uare.
Then$ an epita7ial layer of lightly doped =-silicon is grown on the P-type substrate by
placing the wafer in the furnace at +699
9
C and introducing a gas containing phosphorus Adonor
impurityB. The resulting structure is shown in figure.
The subse0uent diffusions are done in this epita7ial layer. All active and passive
components are formed on the thin =-layer epita7ial layer grown over the P-type substrate.
,btaining an epita7ial layer of the proper thickness and doping with high crystal 0uality is perhaps
the most formidable challenge in bipolar device processing.
2. Oxidation:
As shown in figure$ a thin layer of silicon dio7ide A-i,
6
B is grown over the =-type layer by
e7posing the silicon wafer to an o7ygen atmosphere at about +999
9
C.

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3. Photolithography:
The prime use of photolithography in C manufacturing is to selectively etch or remove the
-i,
6
layer. As shown in figure$ the surface of the o7ide is first covered with a thin uniform layer of
photosensitive emulsion APhoto resistB. The mask$ a black and white negative of the re0uied
pattern$ is placed over the structure. >hen e7posed to ultraviolet light$ the photo resist under the
transparent region of the mask becomes poly-meri4ed. The mask is then removed and the wafer is
treated chemically that removes the une7posed portions of the photoresist film. The polymeri4ed
region is cured so that it becomes resistant to corrosion. Then the chip is dipped in an etching
solution of hydrofluoric acid which removes the o7ide layer not protected by the polymeri4ed
photoresist. This creates openings in the -i,
6
layer through which P-type or =-type impurities can
be diffused using the isolation diffusion process as shown in figure. After diffusion of impurities$
the polymeri4ed photoresist is removed with sulphuric acid and by a mechanical abrasion process.
4. Isolation Diffusion:
The integrated circuit contains many devices. -ince a number of devices are to be
fabricated on the same C chip$ it becomes necessary to provide good isolation between various
components and their interconnections.
The most important techni0ues for isolation areE
+. P= ;unction solation
6. Dielectric solation
n P= ;unction isolation techni0ue$ the P
F
type impurities are selectively diffused into the =-type
epita7ial layer so that it touches the P-type substrate at the bottom. This method generated =-type
isolation regions surrounded by P-type moats. f the P-substrate is held at the most negative
potential$ the diodes will become reverse-biased$ thus providing isolation between these islands.
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The individual components are fabricated inside these islands. This method is very economical$
and is the most commonly used isolation method for general purpose integrated circuits.
n dielectric isolation method$ a layer of solid dielectric such as silicon dio7ide or ruby surrounds
each component and this dielectric provides isolation. The isolation is both physical and electrical.
This method is very e7pensive due to additional processing steps needed and this is mostly used
for fabricating CHs re0uired for special application in military and aerospace.
The P= ;unction isolation diffusion method is shown in figure. The process take place in a furnace
using boron source. The diffusion depth must be atleast e0ual to the epita7ial thickness in order to
obtain complete isolation. Poor isolation results in device failures as all transistors might get
shorted together. The =-type island shown in figure forms the collector region of the =P=
transistor. The heavily doped P-type regions marked P
F
are the isolation regions for the active and
passive components that will be formed in the various =-type islands of the epita7ial layer.
5 Base diffusion:
.ormation of the base is a critical step in the construction of a bipolar transistor. The base must be
aligned$ so that$ during diffusion$ it does not come into contact with either the isolation region or
the buried layer. .re0uently$ the base diffusion step is also used in parallel to fabricate diffused
resistors for the circuit. The value of these resistors depends on the diffusion conditions and the
width of the opening made during etching. The base width influences the transistor parameters
very strongly. Therefore$ the base ;unction depth and resistivity must be tightly controlled. The
base sheet resistivity should be fairly high A699- 199I per s0uareB so that the base does not in;ect
carriers into the emitter. .or =P= transistor$ the base is diffused in a furnace using a boron source.
The diffusion process is done in two steps$ pre deposition of dopants at ?99
9
C

and driving them in
at about +699
9
C. The drive-in is done in an o7idi4ing ambience$ so that o7ide is grown over the
base region for subse0uent fabrication steps. .igure shows that P-type base region of the transistor
diffused in the =-type island Acollector regionB using photolithography and isolation diffusion
processes.
6. Emitter Diffusion:
/mitter Diffusion is the final step in the fabrication of the transistor. The emitter opening must lie
wholly within the base. /mitter masking not only opens windows for the emitter$ but also for the
contact point$ which provides a low resistivity ohmic contact path for the emitter terminal.
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The emitter diffusion is normally a heavy =-type diffusion$ producing low-resistivity layer
that can in;ect charge easily into the base. A Phosphorus source is commonly used so that the
diffusion time id shortened and the previous layers do not diffuse further. The emitter is diffused
into the base$ so that the emitter ;unction depth very closely approaches the base ;unction depth.
The active base is then a P-region between these two ;unctions which can be made very narrow by
ad;usting the emitter diffusion time. %arious diffusion and drive in cycles can be used to fabricate
the emitter. The #esistivity of the emitter is usually not too critical.
The =-type emitter region of the transistor diffused into the P-type base region is shown below.
<owever$ this is not needed to fabricate a resistor where the resistivity of the P-type base
region itself will serve the purpose. n this way$ an =P= transistor and a resistor are fabricated
simultaneously.
7. Contact Mask:
After the fabrication of emitter$ windows are etched into the =-type regions where contacts are
to be made for collector and emitter terminals. <eavily concentrated phosphorus =
F
dopant is
diffused into these regions simultaneously.
The reasons for the use of heavy =
F
diffusion is e7plained as followsE Aluminium$ being a
good conductor used for interconnection$ is a P-type of impurity when used with silicon.
Therefore$ it can produce an unwanted diode or rectifying contact with the lightly doped =-
material. ntroducing a high concentration of =
F
dopant caused the -i lattice at the surface semi-
metallic. Thus the =
F
layer makes a very good ohmic contact with the Aluminium layer. This is
done by the o7idation$ photolithography and isolation diffusion processes.
8. Metallization:
The C chip is now complete with the active and passive devices$ and the metal leads are to
be formed for making connections with the terminals of the devices. Aluminium is deposited over
the entire wafer by vacuum deposition. The thickness for single layer metal is +K m. "etalli4ation
is carried out by evaporating aluminium over the entire surface and then selectively etching away
aluminium to leave behind the desired interconnection and bonding pads as shown in figure.
"etalli4ation is done for making interconnection between the various components
fabricated in an C and providing bonding pads around the circumference of the C chip for later
connection of wires
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.
9. Passivation/ Assembly and Packaging:
"etalli4ation is followed by passivation$ in which an insulating and protective layer is
deposited over the whole device. This protects it against mechanical and chemical damage during
subse0uent processing steps. Doped or undoped silicon o7ide or silicon nitride$ or some
combination of them$ are usually chosen for passivation of layers. The layer is deposited by
chemical vapour deposition AC%DB techni0ue at a temperature low enough not to harm the
metalli4ation.
Transistor Fabrication:
P=P TransistorE
The integrated P=P transistors are fabricated in one of the following three structures.
+. -ubstrate or %ertical P=P
6. Lateral or hori4ontal P=P and
:. Triple diffused P=P
-ubstrate or %ertical P=PE
The P-substrate of the C is used as the collector$ the =-epita7ial layer is used as the base
and the ne7t P-diffusion is used as the emitter region of the P=P transistor. The structure of a
vertical monolithic P=P transistor L
+
is shown in figure. The base region of an =P= transistor
structure is formed in parallel with the emitter region of the P=P transistor.
The method of fabrication has the disadvantage of having its collector held at a fi7ed
negative potential. This is due to the fact that the P-substrate of the C is always held at a negative
potential normally for providing good isolation between the circuit components and the substrate.
Triple diffused P=PE
This type of P=P transistor is formed by including an additional diffusion process over the
standard =P= transistor processing steps. This is called a triple diffusion process$ because it
involves an additional diffusion of P-region in the second =-diffusion region of a =P= transistor.
The structure of the triple diffused monolithic P=P transistor L
6
is also shown in the below figure.
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This has the limitations of re0uiring additional fabrication steps and sophisticated fabrication
assemblies.
Lateral or Horizontal PNP:
This is the most commonly used form of integrated P=P transistor fabrication method. This
has the advantage that it can be fabricated simultaneously with the processing steps of an =P=
transistor and therefore it re0uires as the base of the P=P transistor. During the P-type base
diffusion process of =P= transistor$ two parallel P-regions are formed which make the emitter and
collector regions of the hori4ontal P=P transistor.
Comparison of monolithic =P= and P=P transistorE
=ormally$ the =P= transistor is preferred in monolithic circuits due to the following reasonsE
+. The vertical P=P transistor must have his collector held at a fi7ed negative voltage.
6. The lateral P=P transistor has very wide base region and has the limitation due to the lateral
diffusion of P-type impurities into the =-type base region. This makes the photographic mask
making$ alignment and etching processes very difficult. This reduces the current gain of lateral
P=P transistors as low as +.1 to :9 as against 19 to :99 for a monolithic =P= transistor.
:. The collector region is formed prior to the formation of base and emitter diffusion. During the
later diffusion steps$ the collector impurities diffuse on either side of the defined collector ;unction.
-ince the =-type impurities have smaller diffusion constant compared to P-type impurities the =-
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type collector performs better than the P-type collector. This makes the =P= transistor preferable
for monolithic fabrication due to the easier process control.
Transistor with multiple emittersE The applications such as transistor- transistor logic ATTLB
re0uire multiple emitters. The below figure shows the circuit sectional view of three =-emitter
regions diffused in three places inside the P-type base. This arrangement saves the chip area and
enhances the component density of the C.
Schottky Barrier Diode:
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The metal contacts are re0uired to be ohmic and no P= ;unctions to be formed between the
metal and silicon layers. The =
F
diffusion region serves the purpose of generating ohmic contacts.
,n the other hand$ if aluminium is deposited directly on the =-type silicon$ then a metal
semiconductor diode can be said to be formed. -uch a metal semiconductor diode ;unction e7hibits
the same type of %- Characteristics as that of an ordinary P= ;unction.
The cross sectional view and symbol of a -chottky barrier diode as shown in figure.
Contact + shown in figure is a -chottky barrier and the contact 6 is an ohmic contact. The contact
potential between the semiconductor and the metal generated a barrier for the flow of conducting
electrons from semiconductor to metal. >hen the ;unction is forward biased this barrier is lowered
and the electron flow is allowed from semiconductor to metal$ where the electrons are in large
0uantities.
The minority carriers carry the conduction current in the -chottky diode whereas in the P=
;unction diode$ minority carriers carry the conduction current and it incurs an appreciable time
delay from ,= state to ,.. state. This is due to the fact that the minority carriers stored in the
;unction have to be totally removed. This characteristic puts the -chottky barrier diode at an
advantage since it e7hibits negligible time to flow the electron from =-type silicon into aluminum
almost right at the contact surface$ where they mi7 with the free electrons. The other advantage of
this diode is that it has less forward voltage Aappro7imately 9.*%B. Thus it can be used for
clamping and detection in high fre0uency applications and microwave integrated circuits.
Schottky transistor:
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The cross-sectional view of a transistor employing a -chottky barrier diode clamped
between its base and collector regions is shown in figure. The e0uivalent circuit and the symbolic
representation of the -chottky transistor are shown in figure. The -chottky diode is formed by
allowing aluminium metalli4ation for the base lead which makes contact with the =-type collector
region also as shown in figure.
>hen the base current is increased to saturate the transistor$ the voltage at the collector C
reduces and this makes the diode Ds conduct. The base to collector voltage reduces to 9.*%$ which
is less the cut-in-voltage of a silicon base-collector ;unction. Therefore$ the transistor does not get
saturated.
Monolithic diodes:
The diode used in integrated circuits are made using transistor structures in one of the five possible
connections. The three most popular structures are shown in figure. The diode is obtained from a
transistor structure using one of the following structures.
+. The emitter-base diode$ with collector short circuited to the base.
6. The emitter-base diode with the collector open and
:. The collector !base diode$ with the emitter open-circuited.
The choice of the diode structure depends on the performance and application desired. Collector-
base diodes have higher collector-base arrays breaking rating$ and they are suitable for common-
cathode diode arrays diffused within a single isolation island. The emitter-base diffusion is very
popular for the fabrication of diodes$ provided the reverse-voltage re0uirement of the circuit does
not e7ceed the lower base-emitter breakdown voltage.
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Integrated Resistors:
A resistor in a monolithic integrated circuit is obtained by utili4ing the bulk resistivity of
the diffused volume of semiconductor region. The commonly used methods for fabricating
integrated resistors are +. Diffused 6. epita7ial :. Pinched and *. Thin film techni0ues.
Diffused Resistor:
The diffused resistor is formed in any one of the isolated regions of epita7ial layer during
base or emitter diffusion processes. This type of resistor fabrication is very economical as it runs in
parallel to the bipolar transistor fabrication. The =-type emitter diffusion and P-type base diffusion
are commonly used to reali4e the monolithic resistor.
The diffused resistor has a severe limitation in that$ only small valued resistors can be
fabricated. The surface geometry such as the length$ width and the diffused impurity profile
determine the resistance value. The commonly used parameter for defining this resistance is called
the sheet resistance. t is defined as the resistance in ohms5s0uare offered by the diffused area.
n the monolithic resistor$ the resistance value is e7pressed by
# M #
s
+5w where #M resistance offered Ain ohmsB
#
s
M sheet resistance of the particular fabrication process involved Ain ohms5s0uareB
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l M length of the diffused area and
w M width of the diffused area.
The sheet resistance of the base and emitter diffusion in 699I5-0uare and 6.6I5s0uare
respectively. .or e7ample$ an emitter-diffused strip of 6mil wide and 69 mil long will offer a
resistance of 66I. .or higher values of resistance$ the diffusion region can be formed in a 4ig-4ag
fashion resulting in larger effective length. The poly silicon layer can also be used for resistor
reali4ation.
Epitaxial Resistor:
The =-epita7ial layer can be used for reali4ing large resistance values. The figure shows the cross-
sectional view of the epita7ial resistor formed in the epita7ial layer between the two =
F
aluminium
metal contacts.
Pinched resistor:
The sheet resistance offered by the diffusion regions can be increased by narrowing down
its cross-sectional area. This type of resistance is normally achieved in the base region. .igure
shows a pinched base diffused resistor. t can offer resistance of the order of mega ohms in a
comparatively smaller area. n the structure shown$ no current can flow in the =-type material
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since the diode reali4ed at contact 6 is biased in reversed direction. ,nly very small reverse
saturation current can flow in conduction path for the current has been reduced or pinched.
Therefore$ the resistance between the contact + and 6 increases as the width narrows down and
hence it acts as a pinched resistor.
Thin film resistor:
The thin film deposition techni0ue can also be used for the fabrication of monolithic
resistors. A very thin metallic film of thickness less than +Km is deposited on the silicon dio7ide
layer by vapour deposition techni0ues. =ormally$ =ichrome A=iCrB is used for this process.
Desired geometry is achieved using masked etching processes to obtain suitable value of resistors.
,hmic contacts are made using aluminium metalli4ation as discussed in earlier sections.
The cross-sectional view of a thin film resistor as shown in figure. -heet resistances of *9
to *99I5 s0uare can be easily obtained in this method and thus 69kI to 19kI values are very
practical.
The advantages of thin film resistors are as followsE
+. They have smaller parasitic components which makes their high fre0uency behaviour
good.
6. The thin film resistor values can be very minutely controlled using laser trimming.
:. They have low temperature coefficient of resistance and this makes them more stable.
The thin film resistor can be obtained by the use of tantalum deposited over silicon dio7ide layer.
The main disadvantage of thin film resistor is that its fabrication re0uires additional processing
steps.
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Monolithic Capacitors:
"onolithic capacitors are not fre0uently used in integrated circuits since they are limited in the
range of values obtained and their performance. There are$ however$ two types available$ the
;unction capacitor is a reverse biased P= ;unction formed by the collector-base or emitter-base
diffusion of the transistor. The capacitance is proportional to the area of the ;unction and inversely
proportional to the depletion thickness.
C N A$ where a is the area of the ;unction and
C N T $ where t is the thickness of the depletion layer.
The capacitance value thus obtainable can be around +.6n.5mm
6
.
The thin film or metal o7ide silicon capacitor uses a thin layer of silicon dio7ide as the
dielectric. ,ne plate is the connecting metal and the other is a heavily doped layer of silicon$ which
is formed during the emitter diffusion. This capacitor has a lower leakage current and is non-
directional$ since emitter plate can be biased positively. The capacitance value of this method can
be varied between 9.: and 9.8n.5mm
6
.
Inductors:
=o satisfactory integrated inductors e7ist. f high L inductors with inductance of values
larger than 1K< are re0uired$ they are usually supplied by a wound inductor which is connected
e7ternally to the chip. Therefore$ the use of inductors is normally avoided when integrated circuits
are used.
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CURRENT MIRROR AND CURRENT SOURCES:
Constant current source(Current Mirror):
A constant current source makes use of the fact that for a transistor in the active mode of
operation$ the collector current is relatively independent of the collector voltage. n the basic
circuit shown in fig +

Transistors L
+
@L
6
are matched as the circuit is fabricated using C technology. &ase and
emitter of L
+
@L
6
are tied together and thus have the same %
&/
. .n addition$ transistor L+ is
connected as a diode by shorting it s collector to base. The input current
ref
flows through the
diode connected transistor L+ and thus establishes a voltage across L
+
.
This voltage in turn appears between the base and emitter of L
6
.-ince L
6
is identical to
L
+
$ the emitter current of L
6
will be e0ual to emitter current of L
+
which is appro7imately e0ual to

ref

As long as L6 is maintained in the active region $its collector current
C6M

o
will be
appro7imately e0ual to
ref .
-ince the output current o is a reflection or mirror of the reference current
ref
$ the circuit is
often referred to as a current mirror.
Analysis:
The collector current
C+
and
C6
for the transistor L+ and L6 can be appro7imately
e7pressed as
I
C1 t

F
I
ES
e
V
BE+
V
T
ffffffffffff
---------(1)
I
C2t

F
I
ES
e
V
BE6
V
T
fffffffffffff
------------(2)
.rom e0uation A+B@A6B
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I
C6
I
C+
fffffffff
= e
V
BE6
@V
BE+
V
T
fffffffffffffffffffffffffffffffffffffffffffffffff
-----------------(3)
-ince %
&/+
M%
&/6
we obtain

C6
M
C+
M
C
M
,
Also since both the transistors are identical $

+
=
6
=

3CL at the collector of L
+
gives

ref
M
C+
F
&+
F
&6

= I
C+
+
I
C+

+
ffffffff
+
I
C6

6
ffffffff
= I
C
+ +
6

ffff
f g

----------A*B
solving /0 A*B.

C
may be e7pressed as

I
C
=

+ 6
ffffffffffffffff
I
ref
------------A1B
>here
ref
from fig can be seen to be

I
ref
=V
CC
@
V
BE
R
+
ffffffffffff
OO
V
CC
R
+
ffffffffffff
Aas %
&/
M9.)% is smallB
.rom /0.1 for
PP+,

+ 6
ffffffffffffffff
is almost unity and the output current
9
is e0ual to the reference
current$
ref
which for a given #
+
is constant. Typically
o
varies by about :Q for 19 R

R699.
t is possible to obtain current transfer ratio other than unity simple by controlling the area
of the emitter-base ;unction A/&'B of the transistor L
6 .
.or e7ample$ if the area of /&' of L
6
is *
times that of L+$then

,
M*
I
ref
The output resistance of the current source is the output resistance$r
9
of L6$
#
9
M
96
M
V
A
I
O
fffffffff
OM
V
A
I
ref
ffffffffff
S%
A
is the /arly voltageT
The circuit however operates as a constant current source as long as L
6
remains in the active
region.
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Widlar current source:
>idlar current source which is particularly suitable for low value of currents. The circuit
differs from the basic current mirror only in the resistance #
/
that is included in the emitter lead of
L
6
.
t can be seen that due to #
/
the base-emitter voltage %
&/6
is les than %
&/+
and conse0uently
current o is smaller than
C+
The ratio of collector currents
C+
@
C6
using
I
C6
I
C+
fffffffff
= e
V
BE6
@V
BE+
V
T
fffffffffffffffffffffffffffffffffffffffffffffffff
------------(1)
Taking natural logarithm of both sides$ we get
V
BE1
-V
BE2
V
T

ln
I
C+
I
C6
ffffffff
h
j
i
k
-------(2)
>riting 3%L for the emitter base loop
%
&/+
M%
&/6
FA
&6
F
C6
B#
/
----------------A:B
or %
&/+
-%
&/6
MA+5

F+B
C6
#
/
-----------A*B
.rom e0n A6B@A*B we obtain

+

ffff
+ +
f g
I
c6
R
E
=V
T
ln
I
C+
I
C6
ffffffff
--------------(5)
Or

R
E
=
V
T
+ +
+

ffff
d e
I
C6
ffffffffffffffffffffffffffffffffff
ln
I
C+
I
C6
ffffffff
--------------(6)
A relation between
C+
and the reference current
ref
is obtained by writing 3CL at the
collector point of L
+

ref
M
C+
F
&+
F
&6
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I
C+
+ +
+

ffff
f g
+
I
C6

ffffffff
----------------(7)
(Assuming

6
=
+
=
for identical transistorsB
n the >idlar current source
C6
UU
C+
$therefore the term
I
C6

ffffffff
may be neglected in A)B
Thus
I
ref
t
I
C+
+ +
+

ffff
f g


C+
M

+ +
ffffffffffffffff
I
ref

>here
I
ref
=
V
cc
@V
BE
R
+
ffffffffffffffffffffffffffffff

.or

PP+
I
C+
t
I
ref
Wilson current source:
The >ilson current source shown in fig
t provides an output current
o
$ which is very nearly e0ual to %
ref
and also e7hibits a very
high output resistance.
Analysis:
-ince %
&/+
M%
&/6

C+
M
C6
and
&+
M
&6
M
&
At nodeHbH

/:
M6
&
F
C6
M
6

ffff
+ +
f g
I
C6
-----------A+B

/:
is e0ual to

/:
M
C:
F
&:
M
C:
+ +
+

ffff
f g
-----------A6B
.rom /0n A+B@A6B we obtain
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I
C:
+ +
+

ffff
f g
= I
C6
+ +
6

ffff
f g


I
C:
= I
o
=
+ 6
+ +
ffffffffffffffff
f g
I
C6

-ince
C+
M
C6
I
o
=
+ 6
+ +
ffffffffffffffff
f g
I
C+
At node GaH

I
ref
= I
C+
+ I
B:
=
+ +
+ 6
ffffffffffffffff
I
o
+
I
o

ffffff
=

6
+ 6 + 6

6
+ 6
ffffffffffffffffffffffffffffffffffff
I
o

or

I
o
=

6
+ 6

6
+ 6 + 6
ffffffffffffffffffffffffffffffffffff
I
ref

where

I
ref
=
V
CC
@6V
BE
R
+
ffffffffffffffffffffffffffffffffffff

The difference

I
O
@I
ref
=
6

6
+ 6 + 6
ffffffffffffffffffffffffffffffffffff
I
ref is e7tremely small error for modest
values of


The output resistance of a >ilson current mirror is substantially greater
t

r
o
6
ffffff
d e

than simple current mirror or >idlar current mirror.
Current sources as Active loads:
The current source can be used as an active load in both analog and digital CHs. The active
load reali4ed using current source in place of the passive load Ai.e. a resistorB in the collector arm
of differential amplifier makes it possible to achieve high voltage gain without re0uiring large
power supply voltage. The active load so achieved is basically r
9
of a P=P transistor.
Voltage Sources:
A voltage source is a circuit that produces an output voltage %
9
$ which is independent of
the load driven by the voltage source$ or the output current supplied to the load. The voltage source
is the circuit dual of the constant current source.
A number of C applications re0uire a voltage reference point with very low ac impedance
and a stable dc voltage that is not affected by power supply and temperature variations. There are
two methods which can be used to produce a voltage source$ namely$
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+. using the impedance transforming properties of the transistor$ which in turn determines the
current gain of the transistor and
6. using an amplifier with negative feedback.
Voltage source circuit using Impedance transformation:
The voltage source circuit using the impedance transforming property of the transistor is
shown in figure. The source voltage %
s
drives the base of the transistor through a series resistance
#
-
and the output is taken across the emitter. .rom the circuit$ the output ac resistance looking into
emitter is given by

dV
9
dI
9
fffffffffffff
= R
9
=
R
S
+ +
ffffffffffffffff
+ r
eb
with values as high as +99 for, R
S
is transfored to a value of
R
S
+ +
ffffffffffffffff
A
t is to be noted that$ e0n is applicable only for small changes in the output current. The
load regulation parameter indicates the changes in %
9
resulting from large changes in output
current
9
$ #eduction in %
9
occurs as
9
goes from no-load current to full-load current and this
factor determines the output impedance of the voltage sources.
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Emitter follower or Common Collector Type Voltage sourc e:
The figure shows an emitter follower or common collector type voltage source. This voltage
source is suitable for the differential gain stage used in op-amps. This circuit has the advantages of
+. Producing low ac impedance and
6. resulting in effective decoupling of ad;acent gain stages.
The low output impedance of the common-collector stage simulates a low impedance voltage
source with an output voltage level of %
9
represented by

V
9
=V
cc
R
6
R
+
+ R
6
ffffffffffffffffffffff
h
j
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The diode D
+
is used for offsetting the effect of dc value %
&/
$ across the /-& ;unction of the
transistor$ and for compensating the temperature dependence of %
&/
drop of L
+.
The load V
L
shown
in dotted line represents the circuit biased by the current through L
+.
The impedance #
9
looking into the emitter of L
+
derived from the hybrid W model is given by

R
9
=
V
T
I
+
fffffffff
+
R
+
R
6
R
+
+ R
6
b c
ffffffffffffffffffffffffffffffffff

Voltage Source suing Temperature compensated Avalanche Diode:
The voltage source using common collector stage has the limitations of its vulnerability for
changes in bias voltage %
=
and the output voltage %
9
with respect to changes in supply voltage
%cc. This is overcome in the voltage source circuit using the breakdown voltage of the base-
emitter ;unction shown below.
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The emitter ! follower stage of common ! collector is eliminated in this circuit$ since the
impedance seen looking into the bias terminal = is very low. The current source
+
is normally
simulated by a resistor connected between %cc and node n. Then$ the output voltage level %
9
at
node = is given by
%
9
M %
&
F%
&/
>here %
&
is the breakdown voltage of diode D
&
and %
&/
is the diode drop across D
+.
The
breakdown diode D
&
is normally reali4ed using the base-emitter ;unction of the transistor. The
diode D
+
provides partial compensation for the positive temperature coefficient effect of %
&.
n a
monolithic C structure$ D
&
and D
+
can be conveniently reali4ed as a single transistor with two
individual emitters as shown in figure.

Temperature Compensated avalanche diode Voltage source using
breakdown voltage of the
base- emitter junction
The structure consists of composite connection of two transistors which are diode-
connected back-to back. -ince the transistors have their base to collector terminals common$ they
can be designed as a single transistor with two emitters.
The output resistance #
9
looking into the output terminal in figure is given by
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R
9
= R
B
+
V
T
I
+
fffffffff
>here #
&
and %
T
5
+
are the ac resistances of the base !emitter resistance of diode
D
&
and D
+
respectively. Typically #
&
is in the range of *9I to +99I$ and %
9
in the range of 2.1% to
?%.
Voltage Source using V
BE
as a reference:
The output stage of op-amp re0uires stabili4ed bias voltage source$ which can be obtained using a
forward-biased diode connected transistor.
The forward voltage drop for such a connection is appro7imately 9.)%$ and it changes slightly with
current. >hen a voltage level greater than 9.)%$ is needed$ several diodes can be connected in
series$ which can offer integral multiples of 9.)%. Alternatively$ the figure shows a multiplier
circuit$ which can offer voltage levels$ that need not be integral multiplied of 9.)%. The drop
across #
6
e0uals %
&/
drop of L
+.
Considering negligible base current for L
+
$ current through #
6
is
the same as that flowing through #
+
. Therefore$ the output voltage %
9
can be e7pressed as

V
9
= I
6
R
+
+ R
6
b c
=
V
BE
R
6
ffffffffffff
R
+
+ R
6
b c
=V
BE
R
+
R
6
fffffff
+ +
h
j
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V
BE
multiplier Circuit
<ence$ the voltage %
9
can be any multiple of %
&/
by properly selecting the resistors #
+
and
#
6
. Due to the shunt feedback provided by #
+$
the transistor current
+
automatically ad;usts itself$
towards maintaining
6
and %
9
relatively independent of the changes in supply voltage.
The ac output resistance of the circuit #
9
is given by$
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R
9
=
dV
9
dI
o
fffffffffffff
t
R
+
+ R
6
+ + g

R
6
fffffffffffffffffffffffffffff
when g

R
6
PP +, we have R
9
=
R
+
+ R
6
R
6
ffffffffffffffffffffff
A
+
g

ffffffff


!sing this e"n we have,
V
9
V
BE
ffffffffffff
=
R
+
+ R
6
R
6
ffffffffffffffffffffff
Therefore,
R
9
=
V
9
V
BE
ffffffffffff
+
g

ffffffff
=
V
9
V
BE
ffffffffffff
V
+
I
C
fffffff

Voltage References:
The circuit that is primarily designed for providing a constant voltage independent of
changes in temperature is called a voltage reference. The most important characteristic of a voltage
reference is the temperature coefficient of the output reference voltage TC
#
$ and it is e7pressed as
TC
R
=
dV
R
dT
fffffffffff
The desirable properties of a voltage reference areE
+. #eference voltage must be independent of any temperature change.
6. #eference voltage must have good power supply re;ection which is as independent of the
supply voltage as possible and
:. output voltage must be as independent of the loading of output current as possible$ or in
other words$ the circuit should have low output impedance.
The voltage reference circuit is used to bias the voltage source circuit$ and the combination can
be called as the voltage regulator. The basic design strategy is producing a 4ero TC
#
at a given
temperature$ and thereby achieving good thermal ability. Temperature stability of the order of
+99ppm5
9
C is typically e7pected.
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Voltage Reference circuit using temperature compensation scheme:
The voltage reference circuit using basic temperature compensation scheme is shown
below. This design utili4es the close thermal coupling achievable among the monolithic
components and this techni0ue compensates the known thermal drifts by introducing an opposing
and compensating drift source of e0ual magnitude.
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A constant current is supplied to the avalanche diode D
&
and it provides a bias voltage of
%
&
to the base of L
+.
The temperature dependence of the %
&/
drop across L
+
and those across D
+
and
D
6
results in respective temperature coefficients. <ence$ with the use of resistors #
+
and #
6
with
tapping across them at point = compensates for the temperature drifts in the base-emitter loop of
L
+
. This results in generating a voltage reference %
#
with normally 4ero temperature coefficient.
Applying 3CL at node =$ we get

V
B
@V
BE #
+
b c
@V
BE $
+
b c
@V
R
R
+
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
=
V
R
@V
BE $
6
b c
R
6
fffffffffffffffffffffffffffffff

Assuming matched transistors$

V
BE #
+
b c
= V
BE $
+
b c
=V
BE $
6
b c
=V
BE

Then /0 can be e7pressed as

V
B
@6V
BE
@V
R
R
+
ffffffffffffffffffffffffffffffffffffffff
=
V
R
@V
BE
R
6
fffffffffffffffffffffff

Therefore$ the voltage level %
#
is given by

V
R
=
R
6
V
B
+V
BE
R
+
@6R
6
b c
R
+
+ R
6
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
Differentiating %
&
and %
&/
in e0A6B partially with respect to temperature$ we get
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9 =
R
6
R
+
+ R
6
ffffffffffffffffff
V
B
T
fffffffffff
+
R
+
@6R
6
R
+
+ R
6
ffffffffffffffffffffff
F G
V
BE
T
fffffffffffff

That is$

6R
+
@R
+
R
6
fffffffffffffffffffff
=
V
B
T
ffffffffffffff
V
BE
T
ffffffffffffffff
ffffffffffff
@@@:
` a

Therefore$ it can be inferred that e0A:B is to be satisfied for obtaining 4ero temperature coefficient.
Voltage Reference circuit using Avalanche Diode Reference:
A voltage reference can be implemented using the brerakdown phenomenon condition of a
heavily doped P= ;unction. The 4ener breakdown is the main mechanism for ;unctions$ which
breakdown at a voltage of 1% or less. .or integrated transistors $ the base-emitter breakdown
voltage falls in the range of 2 to 8%. Therefore$ the breakdown in the ;unctions of the integrated
transistor is primarily due to avalanche multiplication. The avalanche breakdown voltage %
&
of a
transistor incurs a positive temperature coefficient$ typically in the range of 6m%5
9
C to 1m%5
9
C.
.igure depicts a current reference circuit using avalanche diode reference. The base bias for
transistor L
+
is provided through register #
+
and it also provides the dc current needed to bias D
&$
D
+
and D
6
.
The voltage at the base of L
+
is e0ual to the 4ener voltage %
&
added with two diode drops
due to D
+
and D
6
. The voltage across #
6
is e0ual to the voltage at the base of L
+
less the sum of the
base ! emitter voltages of L
+
and L
6
.
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<ence$ the voltage across #
6
is appro7imately e0ual to that across D
&
M %
&
. -ince L
6
and L
:
act as a current mirror circuit$ current
9
e0uals the current through #
6
.
Therefore$
I
9
=
V
B
R
6
fffffff

t shows that$ the output current
9
has low temperature coefficient$ if the temperature
coefficient of #
6
is low$ such as that produced by a diffused resistor in C fabrication.
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The 4ero temperature coefficient for output current can be achieved$ if diodes are added in
series with #
6
$ so that they can compensate for the temperature variation of #
6
and %
& .
The
temperature compensated avalanche diode reference source circuit is shown in figure.
The transistor L
*
and L
1
form an active load current mirror circuit. The base voltage of L
+
is
the voltage %
&
across 4ener D
&
.
Then$ %
&
M A%
&/
J nB F%
&/
across L
+
F %
&/
across L
6
F drop across #
6
.<ere$ n is the number of
diodes.
t can be e7pressed as V
B
= n + 6
` a
V
BE
+ I
9
B R
6

Differentiating for %
& $

9
$ #
6
and %
&/
partially$ with respect to temperature T$ we get
V
B
T
fffffffffff
= n + 6
` aV
BE
T
fffffffffffff
+ R
6
I
9
T
fffffffff
+ I
9
R
6
T
ffffffffff
Dividing throughout by
9
#
6
$ we get
+
I
9
R
6
fffffffffffff
V
B
T
fffffffffff
=
n + 6
I
9
R
6
fffffffffffff
V
BE
T
fffffffffffff
+
+
I
9
fffff
I
9
T
fffffffff
+
+
R
X
ffffffff
R
6
T
ffffffffff

Therefore$ 4ero temperature coefficient of
9
can be obtained$ if the following condition is satisfied$
That is$
+
I
9
fffff
I
9
T
fffffffff
= 9 =
+
R
6
I
9
fffffffffffff
V
B
T
fffffffffff
n + 6
` aV
BE
T
fffffffffffff
F G
@
+
R
6
fffffff
R
6
T
ffffffffff
Differential amplifier: The function of a differential amplifier is to amplify the difference
between two signals. The need for differential amplifier arises in many physical measurements
where response from dc to many "<4 of fre0uency is re0uired. This forms the basic input stage of
an integrated amplifier.
The basic differential amplifier has the following important properties of
+. /7cellent stability
6. <igh versatility and
:. <igh immunity to interference signals
The differential amplifier as a building block of the op-amp has the advantages of
+. Lower cost
6. easier fabrication as C component and
:. closely matched components.
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The above figure shows the basic block diagram of a differential amplifier$ with two input
terminals and one output terminal. The output signal of the differential amplifier is proportional to
the difference between the two input signals.
That is %
9
M A
dm
A%
+
! %
6
B
f %
+
M %
6
$ then the output voltage is 4ero. A non-4ero output voltage %
9
is obtained when %
+
and
%
6
are not e0ual. The difference mode input voltage is defined as %
m
M

%
+
! %
6
and the common
mode input voltage is defined as
V
c
=
V
+
+V
6
6
ffffffffffffffffff
These e0uation show that if %
+
M %
6
$ then the differential mode input signal is 4ero and common
mode input signal is %
cm
M %
+
M%
6
.
Differential Amplifier with Active load:
Differential amplifier are designed with active loads to increase the differential mode
voltage gain.
The open circuit voltage gain of an op-amp is needed to be as large as possible. This is achieved by
cascading the gain stages which increase the phase shift and the amplifier also becomes vulnerable
to oscillations. The gain can be increased by using large values of collector resistance. .or such a
circuit$ the voltage gain is given by
A
d
=@g

R
C
=
I
C
R
C
V
T
ffffffffffffff

To increase the gain the
C
#
C
product must be made very large. <owever$ there are limitations in
C fabrication such as$
+. a large value of resistance needs a large chip area.
6. for large #
C$
the 0uiescent drop across the resistor increase and a large power supply will be
re0uired to maintain a given operating current.
:. Large monolithic resistor introduces large parasitic capacitances which limits the fre0uency
response of the amplifier.
Amplifier
with gain
A
dm
%
+
%
6
%
9
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*. for linear operation of the differential pair$ the devices should not be allowed to enter into
saturation. This limits the ma7 input voltage that can be applied to the bases of transistors
L
+
and L
6
the base-collector ;unction must be allowed to become forward-biased by more
than 9.1 %. The large value of load resistance produces a large dc voltage drop A
//
5 6B#
C$
so that the collector voltage will be %
C
M %cc -A
//
5 6B#
C
and it will be substantially less
than the supply voltage %cc. This will reduce the input voltage range of the differential
amplifier. Due to the reasons cited above$ an active load is preferred in the differential
amplifier configurations.
B1T Differential Amplifier using active loads:
A simple active load circuit for a differential amplifier is the current mirror active load as
shown in figure. The active load comprises of transistors L
:
and L
*
with the transistor L
:
connected
as a diode with its base and collector shorted. The circuit is shown to drive a load #
L.
>hen an ac
input voltage is applied to the differential amplifier$ the various currents of the circuit are given by
I
C*
= I
C:
= I
C+
=
g

V
id
6
ffffffffffffffff
. >here
I
C*
= I
C:
due to current mirror action. <ere$
C6
is given by
I
C6
=@
g

V
id
6
ffffffffffffffff
. >e know that the load current
L
entering the ne7t stage is
I
%
= I
C6
@I
C*
.Therefore$ I
%
=@
g

V
id
6
ffffffffffffffff
@
g

V
id
6
ffffffffffffffff
=@g

V
id
. Then$ the output voltage from the differential
amplifier is given by V
9
=@I
%
R
%
=@@g

V
id
b c
R
%
= g

R
%
V
id
. The ac voltage gain of
the circuit is given by
A
V
=
V
9
V
id
ffffffff
=
g

R
%
V
id
V
id
ffffffffffffffffffffffff
= g

R
%
.The differential amplifier can amplify
the differential input signals and it provides single-ended output with a ground reference since the
load #
L
is connected to only one output terminal. This is made possible by the use of the current
mirror active load.The output resistance #
9
of the circuit is that offered by the parallel combination
of transistors L
6
A=P=B and L
*
AP=PB. t is given by #
r
M r
96
YY r
9*
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Analysis of B1T differential amplifier with active load:
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Assuing
V
id
6
ffffffff
=9 for transistor #
+
and #
6
and =1 , then the bias current I
EE
is divided e"uall& between #
+
and #
6
and
hence, I
C+
=I
C6
=I
EE
6
ffffffffff
AThe current I
C+
su''lied b&#
:
is
irrored as I
C*
at the out'ut of transitor #
*
A
therefore, I
C:
=I
C*
=I
EE
and the dc current in the collector of #
*
is e(actl&
the current needed to satisf&#
6
A
whenis ver& large andV
EC*
=V
EC:
=V
BE
, the current irror ratio becoes e(actl&
unit&AThen , the differential a'lifier is co'letl& balanced , and the out'ut voltage
isV
9
=V
CC
@V
BE
#@'ointsE The collector currents of all the transitors are e"ual A
that is, I
C+
=I
C6
=I
C:
=I
C*
=
I
EE
6
ffffffff
A
The Collector @eitter voltages of #
+
and #
6
are given b&

V
CE+
=V
CE6
=V
C
@V
E
= V
CC
@V
EB
b c
@@V
EB
b c
=V
CC
The collector eitter voltages of #
:
and #
*
are given b&,
V
CE:
=V
CE*
=V
EB
The in'ut offset voltagesV
OS
of the differential a'lifier arises fro the isatches
in the in'ut devices #
+
, #
6
and load drives #
:
, #
*
and fro the base current of the
%oad devices A
an a''ro(iaate e('ression forV
OS
is given b&
V
OS
=V
T
I
S)
I
S)
ffffffffffff
@
I
S*
I
S*
fffffffffffff
+
6

ffff
f g
where re'resents the gain of )*) transistor and it is assued that
I
S)
= I
S:
@I
S*
I
S)
=
I
S:
+ I
S*
6
ffffffffffffffffffff
I
S*
= I
S+
@I
S6
and
I
S*
=
I
S+
+ I
S6
6
ffffffffffffffffffff
assuing a worst case value of F *Q for
I
s
I
s
fffffffff
andof 69,

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V
OS
=V
T
9.9* +9.9* +9.+
` a
=62B+9
@:
B 9.+8 =*.28VA
E"n shows that, the offset is higher than that of a resistive loaded differential a'lifier A
This can be reduced b& the use of eitter resistors
for #
:
and #
*
, and a transitor #
1
in the current irror
load as shown in figure A

CMRR of the differential amplifier using active load:
The differential amplifier using active load provides high voltage gain to the differential
input signal and a single ! ended output that is referenced to the ground is obtained. The
differential amplifier which provides conversion for a differential signal to a single ended signal is
necessary in differential input signal ended output amplifiers. The op-amp is one such circuit. The
changes in the common-mode signal of the bias current source. This induces a change in
C6
and an
identical change in
C+.
The change in
C+
will then produce a change in the P=P load devices$ and
thereby a change in
C*$
which is the collector current L
*$
The current
C*
is in such a direction as to
cancel the change in
C6.
As a result of this$ any common mode input does not cause a change in
output.
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The voltage gain of the differential amplifier is independent of the 0uiescent current
//.
This makes it possible to use very small value of
//
as low as 69Ka$ while still maintaining a large
voltage gain. -mall value of
//
is preferred$ since it results in a small value of bias current and a
large value for the input resistance. A limitation in choosing a small
//
is$ however$ the fact that$ it
will result in a poor fre0uency response of the amplifier.
>hen a small value of bias current is re0uired$ the best approach is to use a './T or
",-./T differential amplifier that is operated at comparatively higher values of
//.
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Differential Mode signal analysis:
The ac analysis of the differential amplifier can be made using the circuit model as shown
below. The differential input transistor pair produces e0ual and opposite currents whose amplitude
us given by g
m6
%
id
56 at the collector of L
+
and L
6
. The collector current i
c+
is fed by the transistor
L
:
and it is mirrored at the output of L
*
. Therefore$ the total current i
9
flowing through the load
resistor #
L
is given by

i
9
=6
g
6
V
id
6
ffffffffffffffffff
=g
6
V
id
Then the out'ut voltage is
V
9
=i
9
R
%
= g
6
R
%
b c
V
id
and the differential ode gain A
dd
of the differential a'lifier is given b&
A
dd
=
v
9
V
d
ffffffffff
=g
6
R
%

This current mirror provides a single ended output which has a voltage e0ual to the
ma7imum gain of the common emitter amplifier.
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The power of the current mirror can be increased by including additional common collector stages
at the o5p of the differential input stage. A bipolar differential amplifier structure with additional
stages is shown in figure. The resistance at the output of the differential stage is now given by the
parallel combination of transistors L
6
and L
*
and the input resistance is offered by L
1.
Then$ the
e0uivalent resistance is e7pressed by #
e0
M r
o6
YY r
9*
YY r
i1
M r
i1
. The gain of the differential stage then
becomes
A
d
= g
6
R
e"
= g
6
r
i1
=
91
I
C6
I
C1
fffffff
.
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Bipolar differential amplifier with common mode input signals:
The common mode input signal induces a common mode current i
ic
in each of the differential
transistor pair L
+
and L
6
. The common current i
ic
is given by

i
ic
=
g
6
+ + 6g
6
R
EE
fffffffffffffffffffffffffffffff
V
ic
V
ic
6 R
EE
ffffffffffffff

The current flow through the transistor L
+
is supplied by the reference current of transistor L
:.
This
current is replicated or mirrored in the transistor L
*
and it produces e7actly the same current
needed at the collector of L
6.
Therefore$ the output current and hence the output voltage and
common mode conversion gain A
cd
are all 4ero.
<owever$ for an actual amplifier$ the common mode gain is determined by small imbalances
generated in the bipolar transistor fabrication and the overall asymmetry in the amplifier. ,ne of
the main factors is due to the current gain defect on the active load$ and it can be minimi4ed
through the use of buffered current mirror using the transistor L
1
as shown in figure.
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General Operational Amplifier:
An operational amplifier generally consists of three stages$ anmely$+. a differential
amplifier 6. additional amplifier stages to provide the re0uired voltage gain and dc level shifting :.
an emitter-follower or source follower output stage to provide current gain and low output
resistance.
A low-fre0uency or dc gain of appro7imately +9
*
is desired for a general purpose op-amp
and hence$ the use of active load is preferred in the internal circuitry of op-amp. The output voltage
is re0uired to be at ground$ when the differential input voltages is 4ero$ and this necessitates the
use of dual polarity supply voltage. -ince the output resistance of op-amp is re0uired to be low$ a
complementary push-pull emitter ! follower or source follower output stage is employed.
"oreover$ as the input bias currents are to be very small of the order of picoamperes$ an ./T input
stage is normally preferred. The figure shows a general op-amp circuit using './T input devices.
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Input stage:
The input differential amplifier stage uses p-channel './Ts "
+
and "
6.
t employs a three-transistor
active load formed by L
:
$ L
*
$ and L
1
. the bias current for the stage is provided by a two-transistor
current source using P=P transistors L
2
and L
).
#esistor #
+
increases the output resistance seen
looking into the collector of L
*
as indicated by #
9*.
This is necessary to provide bias current
stability against the transistor parameter variations. #esistor #
6
establishes a definite bias current
through L
1
. A single ended output is taken out at the collector of L
*
.
",-./THs are used in place of './Ts with additional devices in the circuit to prevent any damage
for the gate o7ide due to electrostatic discharges.
Gain stage:
The second stage or the gain stage uses Darlington transistor pair formed by L
8
and L
?
as shown in
figure. The transistor L
8
is connected as an emitter follower$ providing large input resistance.
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Therefore$ it minimi4es the loading effect on the input differential amplifier stage. The transistor
L
?
provides an additional gain and L
+9
acts as an active load for this stage. The current mirror
formed by L
)
and L
+9
establishes the bias current for L
?
. The %
&/
drop across L
?
and drop across #
1
constitute the voltage drop across #
*
$ and this voltage sets the current through L
8
. t can be set to a
small value$ such that the base current of L
8
also is very less.
Output stage:
The final stage of the op-amp is a class A& complementary push-pull output stage. L
++
is an emitter
follower$ providing a large input resistance for minimi4ing the loading effects on the gain stage.
&ias current for L
++
is provided by the current mirror formed by L
)
and L
+6$
through L
+:
and L
+*
for
minimi4ing the cross over distortion. Transistors can also be used in place of the two diodes.
The overall voltage gain A
%
of the op-amp is the product of voltage gain of each stage as given by
A
%
M YA
d
Y YA
6
YYA
:
Y
>here A
d
is the gain of the differential amplifier stage$ A
6
is the gain of the second gain stage and
A
:
is the gain of the output stage.
IC 741 Bipolar operational amplifier:
The C )*+ produced since +?22 by several manufactures is a widely used general purpose
operational amplifier. .igure shows that e0uivalent circuit of the )*+ op-amp$ divided into various
individual stages. The op-amp circuit consists of three stages.
+. the input differential amplifier
6. The gain stage
:. the output stage.
A bias circuit is used to establish the bias current for whole of the circuit in the C. The op-amp is
supplied with positive and negative supply voltages of value Z +1%$ and the supply voltages as low
as Z1% can also be used.
Bias Circuit:
The reference bias current
#/.
for the )*+ circuit is established by the bias circuit consisting of two
diodes-connected transistors L
++
and L
+6
and resistor #
1.
The widlar current source formed by L
++ $
L
+9
and #
*
provide bias current for the differential amplifier stage at the collector of L
+9.
Transistors
L
8
and L
?
form another current mirror providing bias current for the differential amplifier. The
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reference bias current
#/.
also provides mirrored and proportional current at the collector of the
double !collector lateral P=P transistor L
+:.
The transistor L
+:
and L
+6
thus form a two-output
current mirror with L
+:A
providing bias current for output stage and L
+:&
providing bias current for
L
+).
The transistor L
+8
and L
+?
provide dc bias for the output stage. .ormed by L
+*
and L
69
and they
establish two %
&/
drops of potential difference between the bases of L
+*
and L
+8
.
Input stage:
The input differential amplifier stage consists of transistors L
+
through L
)
with biasing provided by
L
8
through L
+6.
The transistor L
+
and L
6
form emitter ! followers contributing to high differential
input resistance$ and whose output currents are inputs to the common base amplifier using L
:
and
L
*
which offers a large voltage gain.
The transistors L1$ L2 and L) along with resistors #
+$
#
6
and #
:
from the active load for input
stage. The single-ended output is available at the collector of L
2.
the two null terminals in the input
stage facilitate the null ad;ustment. The lateral P=P transistors L
:
and L
*
provide additional
protection against voltage breakdown conditions. The emitter-base ;unction L
:
and L
*
have higher
emitter-base breakdown voltages of about 19%. Therefore$ placing P=P transistors in series with
=P= transistors provide protection against accidental shorting of supply to the input terminals.
Gain Stage:
The -econd or the gain stage consists of transistors L
+2
and L
+)$
with L
+2
acting as an emitter !
follower for achieving high input resistance. The transistor L
+)
operates in common emitter
configuration with its collector voltage applied as input to the output stage. Level shifting is done
for this signal at this stage.
nternal compensation through "iller compensation techni0ue is achieved using the feedback
capacitor C
+
connected between the output and input terminals of the gain stage.
Output stage:
The output stage is a class A& circuit consisting of complementary emitter follower transistor pair
L
+*
and L
69
. <ence$ they provide an effective loss output resistance and current gain.
The output of the gain stage is connected at the base of L
66
$ which is connected as an emitter !
follower providing a very high input resistance$ and it offers no appreciable loading effect on the
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gain stage. t is biased by transistor L
+:A
which also drives L
+8
and L
+?$
that are used for establishing
a 0uiescent bias current in the output transistors L
+*
and L
69.
Ideal op-amp characteristics:
+. nfinite voltage gain A.
6. nfinite input resistance #
i
$ so that almost any signal source can drive it and there is no
loading of the proceeding stage.
:. Vero output resistance #
o
$ so that the output can drive an infinite number of other devices.
*. Vero output voltage$ when input voltage is 4ero.
1. nfinite bandwidth$ so that any fre0uency signals from o to [ <V can be amplified with out
attenuation.
2. nfinite common mode re;ection ratio$ so that the output common mode noise voltage is
4ero.
). nfinite slew rate$ so that output voltage changes occur simultaneously with input voltage
changes.
AC Characteristics:
.or small signal sinusoidal AACB application one has to know the ac characteristics
such as fre0uency response and slew-rate.
Frequency Response:
The variation in operating fre0uency will cause variations in gain magnitude and its
phase angle. The manner in which the gain of the op-amp responds to different fre0uencies is
called the fre0uency response. ,p-amp should have an infinite bandwidth &w M[ Ai.eB if its open
loop gain in ?9d& with dc signal its gain should remain the same ?9 d& through audio and onto
high radio fre0uency. The op-amp gain decreases Aroll-offB at higher fre0uency what reasons to
decrease gain after a certain fre0uency reached. There must be a capacitive component in the
e0uivalent circuit of the op-amp. .or an op-amp with only one break AcornerB fre0uency all the
capacitors effects can be represented by a single capacitor C. &elow fig is a modified variation of
the low fre0uency model with capacitor C at the o5p.
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There is one pole due to #
9
C and one -69d&5decade. The open loop voltage gain of an op-amp
with only one corner fre0uency is obtained from above fig.

V
9
=
@+,
C
R
9
@+,
C
ffffffffffffffffffffffff
A
O%
Vd @@@@62
` a
or A =
V
9
Vd
fffffff
=
A
O%
+ + 6+ + R
9
C
b c
or A =
A
O%
+ + +
f
f
+
ffffffff
f g
fffffffffffffffffffffffffffffff
@@@@@6)
` a
where f
+
=
+
6R
9
C
fffffffffffffffffffffff
@@@68
` a
fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

f+ is the corner fre0uency or the upper : d& fre0uency of the op-amp. The magnitude and phase
angle of the open loop volt gain are fu of fre0uency can be written as$

A
L
L
M
M
=
A
O%
+ +
f
f
+
fffffff
f g
6
v
u
u
u
t
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww
ffffffffffffffffffffffffffffff
@@@@@@@6?
` a
=@tan
@+
f
f
+
ffffff
h
j
i
k

The magnitude and phase angle characteristics from e0n A6?B and A:9B
+. .or fre0uency fUU f
+
the magnitude of the gain is 69 log A
,L
in d&.
6. At fre0uency f M f
+
the gain in : d& down from the dc value of A
,L
in d&. This fre0uency f
+
is called corner fre0uency.
:. .or fPP f
+
the fain roll-off at the rate off -69d&5decade or -2d&5decade.

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.rom the phase characteristics that the phase angle is 4ero at fre0uency f M9.
At the corner fre0uency f
+
the phase angle is -*1
9
Alagging and a infinite fre0uency the phase angle
is -?9
9
. t shows that a ma7imum of ?9
9
phase change can occur in an op-amp with a single
capacitor C. Vero fre0uency is taken as te decade below the corner fre0uency and infinite
fre0uency is one decade above the corner fre0uency. The voltage transfer in a --domain can be
written as

A =
A
O%
+ + +
f
f
+
fffffff
f g
fffffffffffffffffffffffff
=
A
O%
+ + +
w
w
+
fffffff
d e
fffffffffffffffffffffff
A =
A
O%
@w
+
+w + w+
fffffffffffffffffffff
=
A
O%
A-
+
S +-
+
ffffffffffffffffffff

The transfer f
9
of as op-amp with : break fre0uency can be assumed as$
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A =
A
O%
+ + +
f
f
+
fffffff
f g
+ + +
f
f
6
ffffffff
f g
+ + +
f
f
:
ffffffff
f g
fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
9U f
+
U f
6
U f
:
@@@@:+
` a
A =
A
O%
w
+
w
6
w
:
s + w
+
` a
s + w
6
` a
s + w
:
` a
fffffffffffffffffffffffffffffffffffffffffffffffffffffffff
@@@:6
` a
with 9Uw
+
Uw
6
Uw
:
Circuit Stability:
A circuit or a group of circuit connected together as a system is said to be stable$ if its
o5p reaches a fi7ed value in a finite time. AorB A system is said to be unstable$ if its o5p increases
with time instead of achieving a fi7ed value. n fact the o5p of an unstable sys keeps on increasing
until the system break down. The unstable system are impractical and need be made stable. The
criterian gn for stability is used when the system is to be tested practically. n theoretically$ always
used to test system for stability $ e7E &ode plots.
&ode plots are compared of magnitude %s .re0uency and phase angle %s fre0uency. Any system
whose stability is to be determined can represented by the block diagram.
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The block between the output and input is referred to as forward block and the block between the
output signal and f5b signal is referred to as feedback block. The content of each block is referred
\Transfer fre0uencyH .rom fig we represented it by A
,L
AfB which is given by
A
,L
AfB M %
9
5%in if %
f
M 9. -----A+B
where A
,L
AfB M open loop volt gain. The closed loop gain A
f
is given by
A
.
M %
9
5%in
A
.
M A
,L
5 A+FAA
,L
B A&B ----A6B
& M gain of feedback circuit.
& is a constant if the feedback circuit uses only resistive components. ,nce the magnitude %s
fre0uency and phase angle %s fre0uency plots are drawn$ system stability may be determined as
follows
1. Method:1:
Determine the phase angle when the magnitude of AA
,L
B A&B is 9d& AorB +. f phase angle is P .-
+89
9
$ the system is stable. <owever$ the some systems the magnitude may never be 9$ in that cases
method 6$ must be used.
2. Method 2:
Determine the phase angle when the magnitude of AA
,L
B A&B is 9d& AorB +. f phase angle is P .-
+89
9
$ f the magnitude is !ve decibels then the system is stable. <owever$ the some systems the
phase angle of a system may reach -+89
9
$ under such conditions method + must be used to
determine the system stability.
Slew Rate:
Another important fre0uency related parameter of an op-amp is the slew rate. A-lew rate is the
ma7imum rate of change of output voltage with respect to time. -pecified in %5KsB.
Reason for Slew rate:
There is usually a capacitor within 9$ outside an op-amp oscillation. t is this capacitor which
prevents the o5p voltage from fast changing input. The rate at which the volt across the capacitor
increases is given by
d%c5dt M 5C --------A+B
-P "a7imum amount furnished by the op-amp to capacitor C. ,p-amp should have the either a
higher current or small compensating capacitors.
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.or )*+ C$ the ma7imum internal capacitor charging current is limited to about +1KA. -o the slew
rate of )*+ C is
-# M d%c5dt Yma7 M ma75C .
.or a sine wave input$ the effect of slew rate can be calculated as consider volt follower -P The
input is large amp$ high fre0uency sine wave .
f %s M %m -inwt then output %
9
M %m sinwt . The rate of change of output is given by
d%
9
5dt M %m w coswt.
The ma7 rate of change of output across when coswt M+
Ai.eB -# M d%
9
5dt Yma7 M w%m.
-# M 6]f%m %5s M 6]f%m v5ms.
Thus the ma7imum fre0uency fma7 at which we can obtain an undistorted output volt of peak
value %m is given by
fma7 A<4B M -lew rate52.68 J %m .
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called the full power response. t is ma7imum fre0uency of a large amplitude sine wave with
which op-amp can have without distortion.
DC Characteristics of op-amp:
Current is taken from the source into the op-amp inputs respond differently to current and
voltage due to mismatch in transistor.
DC output voltages are$
+. nput bias current
6. nput offset current
:. nput offset voltage
*. Thermal drift
Input bias current:
The op-ampHs input is differential amplifier$ which may be made of &'T or ./T.
n an ideal op-amp$ we assumed that no current is drawn from the input terminals.
The base currents entering into the inverting and non-inverting terminals A
&
-
@
&
F
respectivelyB.
/ven though both the transistors are identical$
&
-
and
&
F
are not e7actly e0ual due to
internal imbalance between the two inputs.
"anufacturers specify the input bias current
&


-o$
I
B
=
I
B
+
+ I
B
@
6
fffffffffffffffffffffff
Q +
` a

f input voltage %
i
M 9%. The output %oltage %
o
should also be A%
o
M 9B

&
M 199nA
>e find that the output voltage is offset by$
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V
o
= I
B
@
b c
R
f
Q 6
` a

,p-amp with a +" feedback resistor
%
o
M 1999nA ^ +" M 199m%
The output is driven to 199m% with 4ero input$ because of the bias currents.
n application where the signal levels are measured in m%$ this is totally unacceptable. This can be
compensated. >here a compensation resistor #
comp
has been added between the non-inverting input
terminal and ground as shown in the figure below.
Current
&
F
flowing through the compensating resistor #
comp
$ then by 3%L we get$
-%
+
F9F%
6
-%
o
M 9 AorB
%
o
M %
6
! %
+
__PA:B
&y selecting proper value of #
comp
$ %
6
can be cancelled with %
+
and the %
o
M 9. The value of #
comp
is derived a
%
+
M
&
F
#
comp
AorB

&
F
M %
+
5#
comp
__PA*B
The node GaH is at voltage A-%
+
B. &ecause the voltage at the non-inverting input terminal is A-%
+
B.
-o with %
i
M 9 we get$

+
M %
+
5#
+
__PA1B

6
M %
6
5#
f
__PA2B
.or compensation$ %
o
should e0ual to 4ero A%
o
M 9$ %
i
M 9B. i.e. from e0uation A:B %
6
M %
+
. -o that$

6
M %
+
5#
f
__PA)B
3CL at node GaH gives$

&
-
M
6
F
+
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I
B
@
=
V
+
R
f
ffffffff
+
V
+
R
+
ffffffff


I
B
@
=V
+
R
+
+ R
f
b c
R
+
R
f
ffffffffffffffffffffffffffffff
Q 8
` a

Assume
&
-
M
&
F
and using e0uation A*B @ A8B we get

V
+
R
+
+ R
f
b c
R
+
R
f
ffffffffffffffffffffffffffffff
=
V
+
R
co'
ffffffffffffff


R
co'
=
R
+
R
f
R
+
+ R
f
fffffffffffffffffffffff

#
comp
M #
+
YY #
f
___PA?B
i.e. to compensate for bias current$ the compensating resistor$ #
comp
should be e0ual to the parallel
combination of resistor #
+
and #
f
.
Input offset current:
&ias current compensation will work if both bias currents
&
F
and
&
-
are e0ual.
-ince the input transistor cannot be made identical. There will always be some small
difference between
&
F
and
&
-
. This difference is called the offset current
Y
os
Y M
&
F
-
&
-
__PA+9B
,ffset current
os
for &'T op-amp is 699nA and for ./T op-amp is +9pA. /ven with bias current
compensation$ offset current will produce an output voltage when %
i
M 9.
%
+
M
&
F
#
comp
__PA++B
And
+
M %
+
5#
+
__PA+6B
3CL at node GaH gives$

6
M A
&
_

+
B
I
6
=I
B
@
@ I
B
+
R
co'
R
+
ffffffffffffff
h
j
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k
Q +:
` a

Again
%
9
M
6
#
f
! %
+
%
o
M
6
#
f
-
&
F
#
comp
V
o
= I
B
@
@I
B
+
R
co'
R
+
ffffffffffffff
H
J
I
K
R
f
@I
B
+
R
co'
Q +*
` a

-ubstitute e0uation A?B and after algebraic manipulation $
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V
o
= R
f
I
B
@
@I
B
+
R
co'
R
+
ffffffffffffff
H
J
I
K
@I
B
+
R
co'

V
o
= R
fI
B
@
@I
B
+
R
co'
R
+
ffffffffffffff
R
f
@I
B
+
R
co'

V
o
=R
f
I
B
@
@I
B
+
R
co'
R
f
R
+
ffffffff
+ +
H
J
I
K

V
o
= R
f
I
B
@
@I
B
+
R
co'
R
f
+ R
+
R
+
fffffffffffffffffffffff
H
J
I
K


V
o
=R
f
I
B
@
@I
B
+
R
+
R
f
R
+
fffffffffffffffff

V
o
= R
f
I
B
@
@I
B
+
R
f

V
o
=R
f
I
B
@
@I
B
+
B C
Q +1
` a

V
o
=R
f
I
os
Q +2
` a

-o even with bias current compensation and with feedback resistor of +"$ a &'T op-amp has an
output offset voltage
%
o
M +" ` ^ 699nA
%
o
M 699m% with %
i
M 9
/0uation A+2B the offset current can be minimi4ed by keeping feedback resistance small.
Dnfortunately to obtain high input impedance$ #
+
must be kept large.
#
+
large$ the feedback resistor #
f
must also be high. -o as to obtain reasonable gain.
The T-feedback network is a good solution. This will allow large feedback resistance$ while
keeping the resistance to ground low Ain dotted lineB.
The T-network provides a feedback signal as if the network were a single feedback resistor.
&y T to a conversion$

R
f
=
R
t
6
+ 6R
t
R
s
R
s
fffffffffffffffffffffffffffffffffff
Q +)
` a

To design T- network first pick #
t
UU#
f
56 __PA+8B
Then calculate R
s
=
R
t
6
R
f
6R
t
ffffffffffffffffffff
Q +?
` a

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Input offset voltage:
nspite of the use of the above compensating techni0ues$ it is found that the output voltage
may still not be 4ero with 4ero input voltage S%
o
b 9 with %
i
M 9T. This is due to unavoidable
imbalances inside the op-amp and one may have to apply a small voltage at the input terminal to
make output A%
o
B M 9.
This voltage is called input offset voltage %
os
. This is the voltage re0uired to be applied at
the input for making output voltage to 4ero A%
o
M 9B.
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Let us determine the %
os
on the output of inverting and non-inverting amplifier. f %
i
M 9 A.ig AbB
and AcBB become the same as in figure AdB. The voltage %
6
at the negative input terminal is given by
V
6
=
R
+
R
+
+ R
f
fffffffffffffffffffffff
h
j
i
k
V
o
Q 69
` a
AorB
V
o
=
R
+
+ R
f
R
+
fffffffffffffffffffffff
h
j
i
k
V
6
= + +
R
f
R
+
ffffffff
h
j
i
k
V
6
Q 6+
` a

-ince$ V
os
= V
i
@V
6
L
L
L
M
M
M@ V
i
=9
V
os
= 9 @V
6
L
L
L
M
M
M=V
6
Q 66
` a
or
` a

V
o
= + +
R
f
R
+
ffffffff
h
j
i
k
V
os
Q 6:
` a

Thus$ the output offset voltage of an op-amp in closed loop is given by e0uation A6:B.
Total output offset voltage:
The total output offset voltage %
,T
could be either more or less than the offset voltage
produced at the output due to input bias current A
&
B or input offset voltage aloneA%
os
B.
This is because
&
and %
os
could be either positive or negative with respect to ground.
Therefore the ma7imum offset voltage at the output of an inverting and non-inverting amplifier
Afigure b$ cB without any compensation techni0ue used is given by many op-amp provide offset
compensation pins to nullify the offset voltage.
+93 potentiometer is placed across offset null pins +@1. The wipes connected to the
negative supply at pin *.
The position of the wipes is ad;usted to nullify the offset voltage.
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>hen the given AbelowB op-amps does not have these offset null pins$ e7ternal balancing
techni0ues are used.
V
OT
= + +
R
f
R
+
ffffffff
H
J
I
K
V
os
+ R
f
I
B
Q 6*
` a

>ith #
comp
$ the total output offset voltage
V
OT
= + +
R
f
R
+
ffffffff
H
J
I
K
V
os
+ R
f
I
os
Q 61
` a

Balancing circuit:
Inverting amplifier:
Non-inverting amplifier:
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Thermal drift:
&ias current$ offset current$ and offset voltage change with temperature.
A circuit carefully nulled at 61cC may not remain. -o when the temperature rises to :1cC.
This is called drift.
,ffset current drift is e7pressed in nA5cC.
These indicate the change in offset for each degree Celsius change in temperature.
Open loop op-amp Configuration:
The term open-loop indicates that no feedback in any form is fed to the input from the output.
>hen connected in open ! loop$ the op-amp functions as a very high gain amplifier. There are
three open ! loop configurations of op-amp namely$
+. differential amplifier
6. nverting amplifier
:. =on-inverting amplifier
The above classification is made based on the number of inputs used and the terminal to which
the input is applied. The op-amp amplifies both ac and dc input signals. Thus$ the input signals can
be either ac or dc voltage.
Open loop Differential Amplifier:
n this configuration$ the inputs are applied to both the inverting and the non-inverting
input terminals of the op-amp and it amplifies the difference between the two input voltages.
.igure shows the open-loop differential amplifier configuration.
The input voltages are represented by %
i+
and %
i6.
The source resistance #
i+
and #
i6
are
negligibly small in comparison with the very high input resistance offered by the op-amp$ and thus
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the voltage drop across these source resistances is assumed to be 4ero. The output voltage %
9
is
given by
%
9
M AA%
i+
! %
i6
B
where A is the large signal voltage gain. Thus the output voltage is e0ual to the voltage gain A
times the difference between the two input voltages. This is the reason why this configuration is
called a differential amplifier. n open ! loop configurations$ the large signal voltage gain A is also
called open-loop gain A.
Inverting amplifier:
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n this configuration the input signal is applied to the inverting input terminal of the op-
amp and the non-inverting input terminal is connected to the ground. .igure shows the circuit of an
open ! loop inverting amplifier.
The output voltage is +89
9
out of phase with respect to the input and hence$ the output voltage %
9
is
given by$
%
9
M -A%
i
Thus$ in an inverting amplifier$ the input signal is amplified by the open-loop gain A and in phase
! shifted by +89
9
.
Non-inverting Amplifier:
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.igure shows the open ! loop non- inverting amplifier. The input signal is applied to the
non-inverting input terminal of the op-amp and the inverting input terminal is connected to the
ground.
The input signal is amplified by the open ! loop gain A and the output is in-phase with input
signal.
%
9
M A%
i

n all the above open-loop configurations$ only very small values of input voltages can be applied.
/ven for voltages levels slightly greater than 4ero$ the output is driven into saturation$ which is
observed from the ideal transfer characteristics of op-amp shown in figure. Thus$ when operated in
the open-loop configuration$ the output of the op-amp is either in negative or positive saturation$ or
switches between positive and negative saturation levels. This prevents the use of open ! loop
configuration of op-amps in linear applications.
Limitations of Open loop Op amp configuration:
.irstly$ in the open ! loop configurations$ clipping of the output waveform can occur when the
output voltage e7ceeds the saturation level of op-amp. This is due to the very high open ! loop
gain of the op-amp. This feature actually makes it possible to amplify very low fre0uency signal of
the order of microvolt or even less$ and the amplification can be achieved accurately without any
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distortion. <owever$ signals of such magnitudes are susceptible to noise and the amplification for
those application is almost impossible to obtain in the laboratory.
-econdly$ the open ! loop gain of the op ! amp is not a constant and it varies with changing
temperature and variations in power supply. Also$ the bandwidth of most of the open- loop op
amps is negligibly small. This makes the open ! loop configuration of op-amp unsuitable for ac
applications. The open ! loop bandwidth of the widely used )*+ C is appro7imately 1<4. &ut in
almost all ac applications$ the bandwidth re0uirement is much larger than this.
.or the reason stated$ the open ! loop op-amp is generally not used in linear applications.
<owever$ the open ! loop op amp configurations find use in certain non ! linear applications such
as comparators$ s0uare wave generators and astable multivibrators.
Closed loop op-amp configuration:
The op-amp can be effectively utili4ed in linear applications by providing a feedback from
the output to the input$ either directly or through another network. f the signal feedback is out- of-
phase by +89
9
with respect to the input$ then the feedback is referred to as negative feedback or
degenerative feedback. Conversely$ if the feedback signal is in phase with that at the input$ then
the feedback is referred to as positive feedback or regenerative feedback.
An op ! amp that uses feedback is called a closed ! loop amplifier. The most commonly used
closed ! loop amplifier configurations are +. nverting amplifier A%oltage shunt amplifierB 6. =on-
nverting amplifier A%oltage ! series AmplifierB
Inverting Amplifier:
The inverting amplifier is shown in figure and its alternate circuit arrangement is shown in
figure$ with the circuit redrawn in a different way to illustrate how the voltage shunt feedback is
achieved. The input signal drives the inverting input of the op ! amp through resistor #
+
.
The op ! amp has an open ! loop gain of A$ so that the output signal is much larger than the error
voltage. &ecause of the phase inversion$ the output signal is +89
9
out ! of ! phase with the input
signal. This means that the feedback signal opposes the input signal and the feedback is negative or
degenerative.
Virtual Ground:
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A virtual ground is a ground which acts like a ground . t may not have physical connection to
ground. This property of an ideal op ! amp indicates that the inverting and non ! inverting
terminals of the op !amp are at the same potential. The non ! inverting input is grounded for the
inverting amplifier circuit. This means that the inverting input of the op !amp is also at ground
potential. Therefore$ a virtual ground is a point that is at the fi7ed ground potential A9%B$ though it
is not practically connected to the actual ground or common terminal of the circuit.
The open ! loop gain of an op ! amp is e7tremely high$ typically 699$999 for a )*+. .or e7$ when
the output voltage is +9%$ the input differential voltage %
id
is given by
V
id
=
V
9
A
fffffff
=
+9
699$999
ffffffffffffffffffff
= 9.91V
.urther more$ the open ! loop input impedance of a )*+ is around 6"I. Therefore$ for an input
differential voltage of 9.91m%$ the input current is only
I
i
=
V
id
R
i
ffffffff
=
9.91V
6.
fffffffffffffffffffff
= 9.61nAA
-ince the input current is so small compared to all other signal currents$ it can be appro7imated as
4ero. .or any input voltage applied at the inverting input$ the input differential voltage %
id
is
negligibly small and the input current is ideally 4ero. <ence$ the inverting input acts as a virtual
ground. The term virtual ground signifies a point whose voltage with respect to ground is 4ero$ and
yet no current can flow into it.
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The e7pression for the closed ! loop voltage gain of an inverting amplifier can be obtained from
figure. -ince the inverting input is at virtual ground$ the input impedance is the resistance between
the inverting input terminal and the ground. That is$ V
i
M #
+.
Therefore$ all of the input voltage
appears across #
+
and it sets up a current through #
+
that e0uals
I
+
=
V
i
R
+
ffffff
. The current must flow
through #
f
because the virtual ground accepts negligible current. The left end of #
f
is ideally
grounded$ and hence the output voltage appears wholly across it. Therefore$
V
9
=@I
6
R
f
=@
R
f
R
+
fffffff
V
i
. The closed !loop voltage gain A
%
is given by A
v
=
V
9
V
i
fffffff
=@
R
f
R
+
fffffff
.
The input impedance can be set by selecting the input resistor #
+
. "oreover$ the above e0uation
shows that the gain of the inverting amplifier is set by selecting a ratio of feedback resistor #
f
to
the input resistor #
+
. The ratio #
f
5#
+
can be set to any value less than or greater than unity. This
feature of the gain e0uation makes the inverting amplifier with feedback very popular and it lends
this configuration to a ma;ority of applications.
Practical Considerations:
+. -etting the input impedance #
+
to be too high will pose problems for the bias current$ and it
is usually restricted to +93I.
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6. The gain cannot be set very high due to the upper limit set by the fain ! bandwidth A(&> M
A
v
J fB product. The A
v
is normally below +99.
:. The peak output of the op ! amp is limited by the power supply voltages$ and it is about 6%
less than supply$ beyond which$ the op ! amp enters into saturation.
*. The output current may not be short ! circuit limited$ and heavy loads may damage the op
! amp. >hen short ! circuit protection is provided$ a heavy load may drastically distort the
output voltage.
Practical Inverting amplifier:
The practical inverting amplifier has finite value of input resistance and input current$ its
open voltage gain A
9
is less than infinity and its output resistance #
9
is not 4ero$ as against the ideal
inverting amplifier with finite input resistance$ infinite open ! loop voltage gain and 4ero output
resistance respectively.
.igure shows the low fre0uency e0uivalent circuit model of a practical inverting amplifier. This
circuit can be simplified using the TheveninHs e0uivalent circuit shown in figure. The signal source
%i and the resistors #
+
and #
i
are replaced by their TheveninHs e0uivalent values. The closed ! loop
gain A
%
and the input impedance #
if
are calculated as follows.
The input impedance of the op- amp is normally much larger than the input resistance #
+.
Therefore$ we can assume %
e0
O %
i
and #
e0
O #
+
. .rom the figure we get$

V
9
= IR
9
+ AV
id
andV
id
+ IR
f
+V
9
= 9
Substituting the value ofV
id
fro above e"n , we get,
V
9
+ + A
` a
= I R
9
@AR
f
b c
Also using the /V% , we get
V
i
= I R
+
+ R
f
b c
+V
9
Substituting the value of I derived fro above e"n and obtaining the closed
loo' gain A
v
, we get
A
v
=
V
9
V
i
fffffff
=
R
9
@AR
f
R
9
+ R
f
+ R
+
+ + A
` a
ffffffffffffffffffffffffffffffffffffffffffffffff

t can be observed from above e0n that when APP +$ #
9
is negligibly small and the product A#
+
PP
#
9
F#
f
$ the closed loop gain is given by
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A
v
=@
R
f
R
+
fffffff

>hich is as the same form as given in above e0n for an ideal inverter.
Input Resistance:
.rom figure we get$

R
if
=
V
id
I
+
ffffffff
!sing /V%, we get,
V
id
+ I
+
R
f
+ R
9
b c
+ AV
id
= 9
which can be si'lified for R
if
as
R
if
=
V
if
I
+
ffffffff
=
R
f
+ R
9
+ + A
fffffffffffffffffff

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Output Resistance:
.igure shows the e0uivalent circuit to determine #
of
. The output impedance #
of
without the load
resistance factor #
L
is calculated from the open circuit output voltage %
oc
and the short circuit
output current
-C
. .rom the figure$ when the output is short circuited$ we get
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I
+
=
V
i
@9
R
+
+ R
f
fffffffffffffffffff
and I
9
=
AV
id
R
9
fffffffffffff
we 0now that V
id
=@I
+
R
f
Therefore, I
9
=@
AI
+
R
f
R
9
fffffffffffffffff
The short circuit current is
I
SC
= I
+
+ I
9
=V
i
R
9
@AR
f
R
9
R
+
+ R
f
b c
fffffffffffffffffffffffffffffff
The out'ut resistance R
of
=
V
oc
I
sc
ffffffff
and the closed o'en loo' gain A
v
=
V
oc
V
i
ffffffff


Therefore,
R
of
=
A
v
V
i
V
i
R
9
@AR
f
R
9
R
+
+R
f
b c
fffffffffffffffffffffffffffffffffffffffffffff
H
J
I
K
fffffffffffffffffffffffffffffffffffffffffffffffff
Substituting the value of A
v
fro above e"n, we get
R
of
=
R
9
R
+
+R
f
b c
R
9
+R
f
+R
+
+ +A
` a
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
=
R
9
R
+
+R
f
b c
R
9
+R
+
+R
f
fffffffffffffffffffffffffffffffffffffffffffff
+ +
R
+
A
R
9
+R
+
+R
f
ffffffffffffffffffffffffffffffffffffffffffff
F G
fffffffffffffffffffffffffffffffffffffffffffffffffff

n the above e0uation$ the numerator contains the term #
9
YY A#
+
F#
f
B and it is smaller than #
9
. The
output resistance #
of
is therefore always smaller than #
9
and from above e0n for Av -P [$ the
output resistance #
of
-P 9.
Non Inverting Amplifier:
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The non ! inverting Amplifier with negative feedback is shown in figure. The input signal drives
the non ! inverting input of op-amp. The op-amp provides an internal gain A. The e7ternal
resistors #
+
and #
f
form the feedback voltage divider circuit with an attenuation factor of d. -ince
the feedback voltage is at the inverting input$ it opposes the input voltage at the non ! inverting
input terminals$ and hence the feedback is negative or degenerative.
The differential voltage %
id
at the input of the op-amp is 4ero$ because node a is at the same voltage
as that of the non- inverting input terminal. As shown in figure$ #
f
and #
+
form a potential divider.
Therefore$

V
i
=
R
+
R
+
+ R
f
fffffffffffffffffff
BV
9

-ince no current flows into the op-amp.
/0n can be written as
V
9
V
i
fffffff
=
R
+
+ R
f
R
f
fffffffffffffffffff
= + +
R
f
R
+
fffffff

<ence$ the voltage gain for the non ! inverting amplifier is given by
A
V
=
V
9
V
i
fffffff
= + +
R
f
R
+
fffffff

Dsing the alternate circuit arrangement shown in figure$ the feedback factor of the feedback
voltage divider network is
=
R
+
R
+
+ R
f
fffffffffffffffffff

Therefore$ the closed loop ! gain is
A
v
=
+

ffff
=
R
+
+ R
f
R
+
fffffffffffffffffff
= + +
R
f
R
+
fffffff

.rom the above e0n$ it can be observed that the closed ! loop gain is always greater than one and it
depends on the ratio of the feedback resistors. f precision resistors are used in the feedback
network$ a precise value of closed ! loop gain can be achieved. The closed ! loop gain does not
drift with temperature changes or op ! amp replacements.
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Closed Loop =on ! nverting Amplifier
The input resistance of the op ! amp is e7tremely large Aappro7imately infinity$B since the op !
amp draws negligible current from the input signal.
Practical Non inverting amplifier:
The e0uivalent circuit of a non- inverting amplifier using the low fre0uency model is shown
below in figure. Dsing 3irchoffHs current law at node a$
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V
i
@V
id
b c
1
+
+V
id
1
i
+ V
i
@V
id
@V
9
b c
1
f
= 9
That is,
@ 1
+
@1
i
+1
f
b c
V
id
+ 1
+
+1
f
b c
V
i
=1
f
V
9
Siilarl& /C% at the out'ut node gives,
V
i
@V
id
@V
9
b c
1
f
+ AV
is
@V
9
b c
1
9
= 9
That gives @ 1
f
@A1
9
b c
V
id
+1
f
V
i
= 1
f
+1
9
b c
V
9
!sing this e"n for
V
9
V
i
fffffff
we get
A
v
=
V
9
V
i
fffffff
=
A1
9
1
+
+1
f
b c
@1
f
1
i
A + +
` a
1
9
1
f
+ 1
+
@1
i
b c
1
f
+1
9
b c
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
when the o'en @loo' gain Aa''roaches infinit&, the e"n becoes
A
v
=
A1
9
1
+
+1
f
b c
A1
9
1
f
ffffffffffffffffffffffffffffffffffff
=
1
+
+1
f
1
f
fffffffffffffffffff
= + +
1
+
1
f
fffffff

Feedback amplifier:
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An op-amp that was feedback is called as feedback amplifier. A feedback amplifier is sometimes
referred to as closed loop amplifier because the feedback forms a closed loop between the input
and output. A closed loop amplifier can be represented by using 6 blocks.
+. ,ne for an op-amp
6. another for an feedback circuit.
There are * ways to connect these 6 blocks according to whether volt or current.
+. %oltage -eries .eedback
6. %oltage -hunt feedback
:. Current -eries .eedback
*. Current shunt .eedback
%oltage series and voltage shunt are important because they are most commonly used.
Voltage Series Feedback Amplifier
Voltage shunt feedback Amplifier
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Voltage Series Feedback Amplifier:
&efore Proceeding$ it is necessary to define some terms.
%oltage gain of the op-amp with a without feedbackE
(ain of the feedback circuit are defined as open loop volt gain Aor gain without feedbackB A M %
9
5
%id
Closed loop volt gain Aor gain with feedbackB A
.
M %
9
5%in
(ain of the feedback circuit MP & M %
.
5%
9
.
1. Negative feedback:
3%L e0uation for the input loop is$
%id M %in -%
f -----A+B
%in M input voltage.
%
f
M feedback voltage.
%id M difference input voltage.
The difference volt is e0ual to the input volt minus the f5b volt. AorB The feedback volt always
opposes the input volt Aor out of phase by +89
9
with respect to the input voltageB hence the
feedback is said to be negative.
t will be performed by computing
+. Closed loop volt gain
6. nput and output resistance
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:. &andwidth
1. Closed loop volt gain:
The closed loop volt gain is A
.
M %
9
5%in
%
9
M Avid MAA%
+
!%
6
B
A M large signal voltage gain.
.rom the above e0n$ %
9
M AA%
+
! %
6
B
#efer fig$ we see that$ %
+
M %in
%
6
M %
f
M #
+
%
9
------
#
+
F#
f
-ince #i PP #
+
%
9
M A%in -

#
+
%
9
------
#
+
F#
f

%
9
F A

#
+
%
9 M
A%in

------
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#
+
F#
f

#earranging$ we get$

V
9
V
in
ffffffffff
=
A
+ +
AR
+
R
+
+ R
F
ffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffff
=
A R
+
+ R
F
b c
R
+
+ R
F
+ AR
+
ffffffffffffffffffffffffffffffffffffffffffff
V
9
=
A R
+
+ R
F
b c
V
in
R
+
+ R
F
+ A R
+
fffffffffffffffffffffffffffffffffffffffffffffffff
Thus
A
F
=
V
9
V
in
ffffffffff
=
A R
+
+ R
F
b c
R
+
+ R
F
+ AR
+
ffffffffffffffffffffffffffffffffffffffffffff
@@@6
` a
2enerall&, A is large t&'icall&+9
1
b c
,
AR
+
PP R
+
+ R
F
b c
and R
+
+ R
F
+ AR
+
b c
AR
+
Thus A
F
=
V
9
V
in
ffffffffff
= + +
R
F
R
+
fffffffff
Ideal
` a
@@@@:
` a
The gain of the feedbac0 circuit B
` a
is the ratio of V
F
andV
9
,
B =
V
F
V
9
fffffffff
@@@*
` a
B =
R
+
R
+
+ R
F
ffffffffffffffffffffffff
Co'are e"n : and * we can conclude
A
F
=
+
B
fffff
ideal
` a
@@@1
` a
This eans that gain of the
f
b
fffff
circuit in the reci'rocal of the closed loo' volt gainA

n other words for given #
+
and #
.
the values of A
.
and & are fi7ed. /0n A1B is an alternative to e0n
A:B
.inally$ the closed loop voltage gain A
.
can be e7pressed in terms of open loop gain A and
feedback circuit gain & as follows$
.rom e0n A6B$
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A
F
=
V
9
V
in
ffffffffff
=
A R
+
+ R
F
b c
R
+
+ R
F
+ AR
+
ffffffffffffffffffffffffffffffffffffffffffff
Rearranging the E"nA
A
F
=
A
R
+
+ R
F
R
+
+ R
F
ffffffffffffffffffffffffffff
f g
R
+
+ R
F
R
+
+ R
F
ffffffffffffffffffffffffffff
+
AR
+
R
+
+ R
F
ffffffffffffffffffffffffffff
using e"n *
` a
B =
V
F
V
9
ffffffffff
=
R
+
R
+
+ R
F
ffffffffffffffffffffffffffff
A
F
=
A
+ + AB
ffffffffffffffffffffffff
@@@2
` a
where A
F
= closed loo' voltage gain
A = o'en loo' voltage gain
B = 2ain of the
F
b
fffffff
circuit
AB = loo' gain
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

3. Difference input voltage ideally zero (Vid)
#econsider e0n %
9
M A %id
%id M %
9
5A
-ince A is very large Aideally N B
%id
t
9 ---A).aB
Ai.eB %
+
t
%
6
--A).bB
/0n A).bB says that the volt at the =on-inverting input terminal of an op-amp is appro7imately
e0ual to that at the inverting input terminal provided that A$ is vey large.
.rom the circuit diagram$
%
+
M %in
%
6
M %
.
M #
+
%
9
5 #
+
F#
.
-ub these values of %
+
and %
6
in e0n A).bB we get
%in M #
+
%
9
5 #
+
F#
.
Ai.eB A
.
M %
9
5%in M +F#
.
5#
+
4. Input Resistance with feedback:
.rom the below circuit diagram #i -P input resistance
#if -P input resistance of an op-amp with feedback
Derivation of input resistance with .eedbackE
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The input resistance with feedback is defined as$

R
if
=
V
in
I
in
ffffffffff
=
V
in
V
id
R
i
ffffffffff
ffffffffff
3owever,
V
id
=
V
9
A
ffffffff
andV
9
=
A
+ + AB
fffffffffffffffffffff
V
in
R
if
= R
i
V
in
V
9
A
ffffffff
ffffffffff
h
l
j
i

k
= AR
i
V
in
AV
in
+ + AB
ffffffffffffffffffffffff
ffffffffffffffffffffff
= AR
i
V
in
+ + AB
` a
A
ffffffffffffffffffffffffffffffffffffff
V
in
a
= R
i
+ + AB
` a
R
if
= R
i
+ + AB
` a
@@8
` a

This means that the input resistance of the op-amp with feedback is AiFA&B times that without
feedback.
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5. Output Resistance with feedback:
This resistance can be obtained by using TheveninHs theorem. To find out o5p
resistance with feedback #
,.
reduce independent source %in to 4ero$ apply an e7ternal voltage %
9
$
and calculate the resulting current i
9
.
The #
,.
is defined as follows$
#
,.
M %
9
5i
9
---A?.aB
3CL at o5p node G=H we get$
i
9
M i
a
F i
b
-ince AA#
.
F #
+
BYY #
i
PP #
9
and i
9
PP i
b
.
i
9

t
i
a
The current i
9
can be found by writing 3%L e0n for the o5p loop
%
9
! #
9
i
9
! A%id M 9
i
9
M %
9
! A%id
---------
#
9

%id M %
+
- %
6
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M 9 - %
.


V
id
=@
R
+
V
9
R
+
+ R
F
ffffffffffffffffffffffff
=@BV
9
i
9
=
V
9
+ ABV
9
R
9
fffffffffffffffffffffffffffffffffff
Sub the value of in'ut is in e"n ?
` a
R
OF
=
V
9
V
9
+
ABV
9
R
9
ffffffffffffffffffff
ffffffffffffffffffffffffffffffff
= R
9
V
9
V
9
+ ABV
9
fffffffffffffffffffffffffffffffffff
R
OF
=
R
9
+ + AB
fffffffffffffffffffff
@@@@?Ab
` a

This result shows that the output resistance of the voltage series feedback amplifier is +5A+FA&B
the output resistance of #
9
the op-amp. Ai.eB The output resistance of the op-amp with feedback is
much smaller than the output resistance without feedback.
6. Bandwidth with feedback:
The bandwidth of the amplifier is defined as the band Arange of fre0uencyB for which
the gain remains constant. The .re0uency at which the gain e0uals + is known as unity gain
bandwidth AD(&B. The relationship between the breakfre0uency f
9
$ open loop volt gain A$
bandwidth with feedback f
.
and closed loop gain A
.
.
.or an op-amp with a single break fre0uency f
9
$ the gain bandwidth product is constant and e0ual
to the unity-gain bandwidth. AD(&B.
D(& M AAB Af
9
B ----A+9.aB
A M open loop volt gain
f
9
M break fre0uency of an op-amp AAorB only for a single break fre0uency op-amp D(& M A
.
f
.
----
A+9.bB
A
.
M closed loop volt gain
f
.
M bandwidth with feedback.
/0uating e0n +9.a and +9.b
Af
9
M A
.
f
.
f
.
M Af
9
5A
.
-----A+9.cB
.or the non-inverting amplifier with feedback
A
.
M A5A+FA&B
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-ub the value of A
.
in e0n +9.c$ we get
f
.
M Af
9
5 A5A+FA&B
f
.
M A+F A&B f
9
----A+9.dB
e0n +9.d -P bandwidth of the non-inverting amplifier with feedback is M bandwidth of the with
feedback f
9
times A+FA&B
7. Total o/p offset voltage with feedback (Vout)
n an open loop op-amp the total o5p offset voltage is e0ual to either the Fve or !ve
saturation volt.
%out M Fve AorB !ve saturation volt.
>ith feedback the gain of the =on-inverting amplifier changes from A to A5A+FA&B$ the total
output offset voltage with feedback must also be +5A+FA&B times the voltage without feedback.
Ai.eB
Total o5p offset %out with feedback M Total o5p offset volt without feedback
---------------------------------------------
+FA&
%out M Z%sat
--------- ----A++B
+FA&
+5A+FA&B is U and Z%sat M -aturation voltages. The ma7imum voltages the output of an op-amp
can reach.
=oteE
,pen-loop even a very small volt at the input of an op-amps can cause to reach ma7imum value AF
%sat Bbecause of its very high volt gain. According to e0n for a gain op-amp circuit the %out is
either Fve or !ve volt because %sat can be either Fve or !ve.
Conclusion of =on-nverting Amplifier with feedbackE
The char of the perfect volt AmplifierE
+. t has very high input resistamce.
6. %ery low output resistance
:. -table volt gain
*. large bandwidth
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8. Voltage Follower: Non-Inverting Buffer]
The lowest gain that can be obtained from a non-inverting amplifier feedback is +.
>hen the =on-nverting amplifier is designed for unity and it is called a voltage follower$ because
the output voltage is e0ual to and inphase with the input or in volt follower the output follows the
input.
t is similar to discrete emitter follower$ the volt follower is preferred$ because it had much higher
input resistance and output amplitude is e7actly e0ual to input.
To obtain the voltage follower$ from this circuit simply open #
+
and short #
.
.
n this figure all the output volt is fed back into the inverting terminal of the op-amp.
The gain of the feedback circuit is + A& M A
.
M+B
A
.
M +
#
i.
M A#
i
#
,.
M#
9
5A
f
.
M Af
9
%out M Z%sat
---------
A
-ince +F A
t
A.
Voltage Shunt Feedback Amplifier:Inverting Amplifier]
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The input voltage drives the inverting terminal$ and amplified as well as inverted output signal also
applied to the inverting input via feedback resistor #
.
.
=oteE
=on-inverting terminal is grounded and feedback circuit has #
.
and e7tra resistor #
+
is connected in
series with the input signal source %in.
>e derive the formula for
+. %oltage gain
6. nput and output resistance
:. &andwidth
*. Total output offset voltage.
1. Closed loop voltage gain A
F
:
A
.
of volt shunt feedback amplifier can be obtained by writhing 3CL e0n at the input
node %
6
.
i
in
M i
.
F
&
----A+6.aB
-ince #
i
is very large$ the input bias current is negligibly small.
i
in
t
i
.
Ai.eB %in ! %
6
%
6
! %
9

------------ M -------------- ----A+6.bB
#
i
#
.

Consider$ from e0n$
%
+
! %
6
M - %
9
5A
-ince %
+
M 9%
%
6
M -%
9
5A
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-ub this value of %
6
in e0n A+6.bB and rearranging$
%in F%
9
5A -A%5AB - %
9
-------------- M ----------------
#
i
#
.
A
.
M %
9
A#
.

---- M - -------- Ae7actB -----A+:B
%in #
+
F#
.
FA#
+
The !ve sign indicates that the input and output signals are out of phase +89
9
. Aor opposite
polaritiesB.
&ecause of this phase inversion the diagram is known as nverting amplifier with feedback. -ince
the internal gain A of the op-amp is very large ANB $ A#
+
PP #
+
F #
.
$ Ai.eB e0n A+:B
A
.
M %
9
5%in M -#
.
5#
+
AdealB
To e7press e0n A+:B in terms of e0nA2B. To begin with$ we divide both numerator and denominator
of e0n A+:B by A#
+
F #
.
B
A
.
M A#
.
5#
+
F #
.
----------------- ---A+1B
+F A#
+
A#
+
F #
.
B
A
.
M - A#5 +FA&B
>here 3 M #
.
5A#
+
F #
.
B
& M #
+
5A#
+
F #
.
B (ain of feedback.
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The comparison of e0n A+1B with feedback A2B indicates that in addition to the phase inversion A-
signB$ the closed loop gain of the inverting amplifier in 3 times the closed loop gain of the =on-
inverting amplifier where 3U +. To derive a ideal closed loop gain$ we can use /0n +1 as follows$
f A& PP +$ then A+FA&B M A& and A
.
M 35& M -#
.
5#
+
----A+2B
2. Input Resistance with feedback:
/asiest method of finding the input resistance is to milleri4e the feedback resistor #
.
.
Ai.eB -plit #
.
in to its 6 "iller components as shown in fig.
n this circuit$ the input resistance with feedback #if is then
#if M #
+
F #
.
----- YY A#iB -----A+8B
+FA
-ince #i and A are very large.
#
+
F #
.
----- YY A#
+
B
t
9I
+FA
3. Output Resistance with feedback:
The output resistance with feedback #
,.
is the resistance measured at the output
terminal of the feedback amplifier. TheveninHs circuit is e7actly for the same as that of =on-
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inverting amplifier because the output resistance #
,.
of the inverting amplifier must be identical to
that of non ! inverting amplifier.
#
9
M ,utput #esistance of the op-amp
A M ,pen loop volt gain of the op-amp
& M (ain of the feedback circuit.
4. Bandwidth with Feedback:
The gain &andwidth product of a single break fre0uency op-amp is always constant.
(ain of the amplifier with feedback U gain without feedback
The bandwidth of amplifier with feedback f
.
must be larger than that without feedback.
f
.
M f
9
A+FA&B ----A6+.aB
f
9
M &reak fre0uency of the op-amp
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M unity gain &andwidth D(&
---------------------------- M -------
,pen- loop voltage gain A
-ub this value of f
9
in e0n A6+.aB
f
.
M D(&
------- A+FA&B
A
f
.
M D(& A3B
------- -----A6+.bB
A
.

>here 3 M #
.
5A#
+
F #
.
B e A
.
M A35+FA&
/0n +9.b and 6+.b MP same for the bandwidth.
-ame closed loop gain the closed loop bandwidth for the inverting amplifier is U that of =on !
inverting amplifier by a factor of 3AU+B
5. Total output offset voltage with feedback:
>hen the temp @ power supply are fi7ed$ the output offset voltage is a function of
the gain of an op-amp.
(ain of the feedback U gain without feedback.
The output offset volt with feedback U without feedback.
Total ,utput offset %oltage with f5b MTotal output offset volt without f5b
------------------------------------------
+FA&
%out M Z%sat
--------- ----A66B
+FA&
Z%sat M -aturation %oltage
A M open-loop volt gain of the op-amp
& M (ain of the f5b circuit
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&M #
+
5A#
+
F #
.
B
n addition$ because of the !ve f5b$
+. /ffect of noise
6. %ariations in supply voltages
:. Changes in temperature on the output voltage of inverting amplifier are reduced.
Differential amplifier:
>e will evaluate 6 different arrangements of the differential amplifier with -ve feedback. Classify
these arrangements according to the number of op-amps used. i.e
+. Differential amplifier with one op-amp
6. Differential amplifier with two op-amps.
Differential amplifier are used in instrumentation and industrial applications to amplify differences
between 6 input signals such as output of the wheat stone bridge circuit.
Differential amplifier preferred to these application because they are better able to re;ect common
mode AnoiseB voltages than single input circuit such as inverting and non-inverting amplifier.
1. Differential Amplifier with one op-amp:
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To analyse this circuit by deriving voltage gain and input resistance. This circuit is a
combination of inverting and non-inverting amplifier. Ai.eB >hen %
7
is reduced to 4ero the circuit is
non-inverting amplifier and when %
y
is reduced to 4ero the circuit is inverting amplifier.
Voltage Gain:
The circuit has 6 inputs %
7
and %
y
. Dse superposition theorem$ when %
y
M 9%$ becomes inverting
amplifier. <ence the o5p due to %
7
only is
%
o7
M -#
.
A%
7
B
------------- -----A6*.aB
#
+

-imilarly$ when %
7
M 9%$ becomes =on-inverting amplifier having a voltage divider network
composed of #
6
and #
:
at the =on ! inverting input.
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V
+
=
R
:
V
&
b c
R
6
+ R
:
fffffffffffffffffff
and the out'ut due toV
&
then is
V
o&
= + +
R
F
R
+
ffffffff
f g
V
+
i Ae
` a
V
o&
=
R
:
R
6
+ R
:
fffffffffffffffffff
R
+
+ R
F
R
+
fffffffffffffffffff
V
&
Since R
+
= R
6
@ R
F
= R
:
,
V
o&
=
R
F
V
&
b c
R
+
ffffffffffffffffffff
@@@@@6*Ab
` a
Fro e"n 6*Aa and 6*Ab , the net ou'ut volt is,
V
o
=V
o(
+V
o&
V
o
=@
R
F
R
+
ffffffff
V
(
@V
&
b c
=@
R
F
V
(&
b c
R
+
fffffffffffffffffffff
or
` a
the voltage gain
A
$
=
V
9
V
(&
ffffffff
=@
R
F
R
+
ffffffff
@@@@@@61
` a

=ote E the gain of the differential amplifier is same as that of inverting amplifier.
Input Resistance:
The input resistance #
if
of the differential amplifier is resistance determined looking
into either one of the 6 input terminals with the other grounded$
>ith %
y
M 9%$
nverting amplifier$ the input resistance which is$
#i.7 O #
+
-----------------A62.aB
-imilarly$ $%
7
M 9%$
=on-inverting amplifier$ the input resistance which is$
#i.y O A#
6
F #
:
B ------A62.bB
%
7
and %
y
are not the same. &oth the input resistance can be made e0ual$ if we modify the basic
differential amplifier. &oth #
+
and A#
6
F #
:
B can be made much larger than the source resistances.
-o that the loading of the signal sources does not occur.
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=oteE f we need a variable gain$ we can use the differential amplifier. n this circuit #
+
M #
6
$ #
.
M
#
:
and the potentiometer #
p
M #
*
.
Depending on the position of the wiper in # voltage can be varied from the closed loop gain of
-6#
.
5#
+
to the open loop gain of A.
2. Differential Amplifier with 2 op-amps:
>e can increase the gain of the differential amplifier and also increase the input
resistance #
if
if we use 6 op-amps.
Voltage gain:
t is compares of 6 stages +. =on-inverting
6. Differential amplifier with gain.
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&y finding the gain of these 6 stages$ we can obtain the overall gain of the circuit$ The o5p
V
6
= + +
R
:
R
6
fffffff
f g
V
&
@@@@6)Aa
` a

&y applying superposition theorem to the second stage$ we can obtain the output voltage$

V
9
=@
R
F
V
4
R
+
ffffffffffffffff
+ + +
R
F
R
+
ffffffff
f g
V
(
@@@@6)Ab
` a
Sub the values of theV
4
fro e"n 6)Aa
` a
V
9
=@
R
F
R
+
ffffffff
f g
+ +
R
:
R
6
fffffff
f g
V
&
+ + +
R
F
F
+
ffffffff
f g
V
(
Since R
+
= R
:
and R
F
= R
6
,
V
9
= + +
R
F
R
+
ffffffff
f g
V
(
@V
&
b c
A
$
=
V
9
V
(&
ffffffff
= + +
R
F
R
+
ffffffff
@@@@68
` a
-hereV
(&
=V
(
@V
&
Input Resistance:
The input resistance #if of the differential amplifier is the resistance determined from either one of
the two non-inverting terminals with the other grounded. The first stage A
+
is the non-inverting
amplifier$ its input resistance is
#i.y M #i A+FA&B -----A6?. aB
>here #i M open loop input resistance of the op-amp.
& M #
6
5#
6
F #
:
-imilarly$ with %
y
shorted to ground A%
y
M 9 %B$ the 6
nd


stage AA
6
B also becomes non-inverting
amplifier$ whose input resistance is
#i.7 M #i A+FA&B -----A6?. bB
>here #i M open loop input resistance of the op-amp
& M #
+
5A#
+
F #
.
B
-ince #
+
M #
:
and #
.
M #
6
$ the #ify b #i.7 because the loading of the input sources %
7
and %
y
may occur. A,rB
The output signal may be smaller in amplitude than e7pected. This possible reduction in the
amplitude of the output signal is drawback of differential amplifier.
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To overcome thisE
>ith proper selection of components$ both #i.y and #i.7 can be made much larger than the
sources resistance so that the loading of the input sources does not occur.
Output resistance and Bandwidth of differential amplifier with feedback:
The output resistance of the differential amplifier should be the same as that of the
non-inverting amplifier e7pect that & M +5A
D
Ai.eB
#
,.
M #
9
5A+FA5A
D
B ----- A:9B
A
D
M closed loop gain of the differential amplifier
#
9
M output resistance of the op-amp
A M open ! loop volt gain of the op-amp
#emember that A
D
is different for differential amplifier.
n the case of nverting and =on-inverting amplifier$ the bandwidth of the differential amplifier
also depends on the closed loop gain of the amplifier and is given by$
f
.
M Dnity gain &andwidth
----------------------------- ------A:+.aB
closed loop gain A
D
AorB
f
.
M AAB Af
9
B
------------ ------A:+.bB
A
D
>here f
9
is the open loop break fre0uency of op-amp.
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Unit II
Applications of Operational Amplifier
SIGN CHANGER (PHASE INVERTER)
V6
%i
V+
%
9
F
-
+
+
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The basic inverting amplifier configuration using an op-amp with input impedance V
+
and
feedback impedance V
f
.
f the impedance V
+
and V
f
are e0ual in magnitude and phase$ then the closed loop voltage
gain is -+$and the input signal will undergo a +89
9
phase shift at the output. <ence$ such circuit is
also called phase inverter. f two such amplifiers are connected in cascade$ then the output from
the second stage is the same as the input signal without any change of sign.
<ence$ the outputs from the two stages are e0ual in magnitude but opposite in phase
and such a system is an e7cellent paraphase amplifier.
Scale Changer:
#eferring the above diagram$ if the ratio V
f
5 V
+
M k$ a real constant$ then the closed loop
gain is !k$ and the input voltage is multiplied by a factor !k and the scaled output is available at
the output. Dsually$ in such applications$ V
f
and V
+
are selected as precision resistors for obtaining
precise and scaled value of input voltage.
PHASE SHIFT CIRCUITS
The phase shift circuits produce phase shifts that depend on the fre0uency and maintain a
constant gain. These circuits are also called constant-delay filters or all-pass filters. That constant
delay refers to the fact the time difference between input and output remains constant when
fre0uency is changed over a range of operating fre0uencies.
This is called all-pass because normally a constant gain is maintained for all the
fre0uencies within the operating range. The two types of circuits$ for lagging phase angles and
leading phase angles.
Phase-lag circuit:
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Phase log circuit is constructed using an op-amp$ connected in both inverting and non
inverting modes. To analy4e the circuit operation$ it is assumed that the input voltage v+ drives a
simple inverting amplifier with inverting input applied atA-Bterminal of op-amp and a non inverting
amplifier with a low-pass filter.
t is also assumed that inverting gain is -+ and non-inverting gain after the low-pass circuit
is + +
R
f
R
+
ffffffff
M+F+M6$ -ince #
f
M#
+
.or the circuit fig a $it can be written as

V
o
+ A
b c
=@V
i +
b c
+ 6
+
+ + +Rc
fffffffffffffffffffffffffff
f g
V
i +
b c

Therefore$
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V
o
+ A
b c
= V i +
b c
d e
+ @+ + 6
+
+ + +Rc
fffffffffffffffffffffffffff
f g
V
i +
b c
h
j
i
k
=V
i +w
b c
+ @+wRC
+ + +wRC
ffffffffffffffffffffffffffffff
The relationshi' between out'ut and in'ut can be e('ressed b&
V
9
+w
b c
V
+
+w
b c
fffffffffffffffffffffffff
=
+ @+wRC
+ + +wRC
ffffffffffffffffffffffffffffff
F G

The relationship is comple7 as defined above e0uation and it shows that it has both
magnitude and phase. -ince the numerator and denominator are comple7 con;ugates$ their
magnitudes are identical and the overall phase angle e0uals the angle of numerator less the angle
of the denominator.
The phase angle is than given by
=@tan
@
+
wRC
` a
@tan
@
+
wRC
` a
=@6 tan
@
+
wRC
` a
@@@@:
` a

<ence$ when wM9$ the phase angle approaches 4ero. >hen wM[$ the phase angle approaches -+89
9
. The /0uation A:B becomes as
=@6tan
@
+
f
f
9
ffffffff
h
j
i
k
@@@@@*
` a
>here the fre0uency f
9
is given by
f
9
=
+
6RC
fffffffffffffffffff
@@@1
` a
<ere$ when fMf
9
in e0.*$ the phase angle f M -?9
9
. The &ode plot
for the phase-lag circuit is shown in fig.b
Phases-lead circuit:
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The phase lead circuit in fig a.in which the #C circuit forms a high pass network.The output
voltage is derived and e7pressed by$
V
9
+
b c
=

@V
i
+
b c
+ 6
+RC
+ + +RC
ffffffffffffffffffffffffffffff
f g
V
i
+
b c

Therefore$
V
o
+
b c
V
i
+
b c
fffffffffffffffffffffffff
=
@+ + +RC
+ + +RC
ffffffffffffffffffffffffffffffffffffff
@@@@@1
` a

.rrom /0uation 1 signifies that the ratio of magnitude is constant and phase is obtained as shown
in e0uation :.
t is to noted that the numerator has a negative real part and overall phase is given by
=+89
9
@tan
@
+
wRC
` a
@tan
@
+
wRC
` a
=+89
9
@6 tan
@
+
wRC
` a
@@@@:
` a
>hen the fre0uency approaches 4ero$the phase angle approaches +89
o
As the fre0uency is
increased$ the leading phase decrease and it finally approaches 4ero at high fre0uencies. <ence can
be written as

=+89
o
@6tan
@
+
f
f
o
ffffffff
h
j
i
k

>here f
o
M
+
6RC
ffffffffffffffffffff

&ode plot for the phase-lead circuit of below fig
Voltage follower:
f #
+
M[ and #fM9 in the non inverting amplifier configuration .
The amplifier act as a unity-gain amplifier or voltage follower.
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That is
A
v
= + +
R
f
R
+
ffffffff
or
R
f
R
+
ffffffff
= A
v
@+
-ince
R
f
R
+
ffffffff
= 9 A
v
= +
The circuit consist of an op-amp and a wire connecting the output voltage to the input $i.e
the output voltage is e0ual to the input voltage$ both in magnitude and phase.%
9
M%
i

-ince the output voltage of the circuit follows the input voltage$ the circuit is called voltage
follower. t offers very high input impedance of the order of "I and very low output impedance.
Therefore$ this circuit draws negligible current from the source. Thus$ the voltage follower
can be used as a buffer between a high impedance source and a low impedance load for impedance
matching applications.
Voltage to Current Converter with floating loads (V/I):
+. %oltage to current converter in which load resistor #
L
is floating Anot connected to groundB.
6. %in is applied to the non inverting input terminal$ and the feedback voltage across #
+
devices the inverting input terminal.
:. This circuit is also called as a current ! series negative feedback amplifier.
*. &ecause the feedback voltage across #
+
Aapplied =on-inverting terminalB depends on the
output current i
9
and is in series with the input difference voltage %
id
.
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>riting 3%L for the input loop$

Vin =V
id
+V
f
V
id
t
9v , since Ais ver& largeA
Vin =V
f
Vin = R
+
i
9
or
` a
i
9
=
Vin
R
+
ffffffff

.rom the fig input voltage %in is converted into output current of %in5#
+
S%in -P i
9
T .
n other words$ input volt appears across #
+.
f #
+
is a precision resistor$ the output current Ai
9
M
%in5#
+
B will be precisely fi7ed.
Applications:
+. Low voltage ac and dc voltmeters
6. Diode match finders
:. L/D
*. Vener diode testers.
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Voltage to current converter with Grounded load:
This is the other type % ! converter$ in which one terminal of the load is connected
to ground.
Analysis of the circuit:
The analysis of the circuit can be done by following 6 steps.
+. To determine the voltage %
+
at the non-inverting AFB terminals and
6. To establish relationship between %
+
and the load current
L
.
Applying 3CL at node %
+
we can write that$
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I
%
= I
+
+ I
6
@@@@+
` a
But I
+
=
V
in
@V
+
R
ffffffffffffffffffff
and I
6
=
V
9
@V
+
R
fffffffffffffffffff
Sub these values into e"n +
` a
I
%
=
V
in
@V
+
R
ffffffffffffffffffff
+
V
9
@V
+
R
fffffffffffffffffff
I
%
=
Vin R@V
+
R +V
9
R@V
+
R
R
6
fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
=
V
inR
+V
9
R@6V
+
R
R
6
ffffffffffffffffffffffffffffffffffffffffffffffffff
=
R V
in
+V
9
b c
@6V
+
R
R
6
fffffffffffffffffffffffffffffffffffffffffffffffffff
I
%
=
V
in
+V
9
@6V
+
R
fffffffffffffffffffffffffffffffffff
RI
%
=V
in
+V
9
@6V
+
@@@@6
` a
V
+
=
V
in
+V
9
@I
%
R
6
fffffffffffffffffffffffffffffffffffff
@@@@@@:
` a
the o' @a' is connected in the non @inverting odeA
gain f the circuit is
A
F
= A +
R
R
fffff
= 6
The out'ut voltage is given b&
V
9
= A
F
BV
+
V
9
= 6V
+
@@@@@@*
` a
SubV
+
e"n :
` a
b c
into *
` a
we get
V
9
=
6 V
in
+V
9
@I
%
R
b c
6
fffffffffffffffffffffffffffffffffffffffffffffff
V
9
=V
in
+V
9
@I
%
R @@@@1
` a
V
in
= I
%
R
I
%
=
V
in
R
ffffffff
@@@@2
` a
e"n 2 gives that the load current I
%
b c
is de'endent on the in'ut voltageV
in
and Resistor R
` a
A

Current to Voltage Converter (I V):
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+. ,pen ! loop gain a of the op-amp is very large. V
+
V
6
@@@@+
` a

6. nput impedance of the op-amp is very high. Ai.eB the currents entering into the 6 input
terminals is very small.
I
B
+
= I
B
6
= 9
---A6B
:. (ain of the inv-amp is given by
A
F
=@
R
F
R
+
ffffffff
=
V
9
V
in
ffffffff
@@@:
` a
V
9
=@
R
F
F
+
ffffffff
V
in
@@@*
` a

&ut V
+
V
6
@@@@+
` a
and %
+
M 9 as the non-inveAFB terminal is connected to
ground. %
6
M9.
Thus the inv !terminal A-B also is at ground and the entire input volt appears across #
+
.

in
M %in5#
+
-----A1B
%
in
Min 5#
+
-ubstituting this e7pression into e0n A*B

V
9
=@
R
F
R
+
ffffffff
I
in
R
+
@@@@2
` a

/0n ?2B indicates that the output volt A%
9
B is proportional to the input current AinB.
Sensitivity of the I V converter:
+. The output voltage %
9
M -#
.

in
.
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6. <ence the gain of this converter is e0ual to -#
.
. The magnitude of the gain Ai.eB is also
called as sensitivity of to % converter.
:. The amount of change in output volt g%
9
for a given change in the input current gin is
decide by the sensitivity of -% converter.
*. &y keeping #
.
variable$ it is possible to vary the sensitivity as per the re0uirements.
Applications of V-I converter with Floating Load:
1. Diode Match finder:
n some applications$ it is necessary to have matched diodes with e0ual voltage drops
at a particular value of diode current. The circuit can be used in finding matched diodes and is
obtained from fig A%- converter with floating loadB by replacing #
L
with a diode. >hen the switch
is in position +E ADiode "atch .inderB #ectifierr diode A= *99+B is placed in the f5b loop$ the
current through this loop is set by input voltage %in and #esistor #
+
. .or %in M +% and #
+
M +99I$
the current through this

9
M %in5#
+
M +5+99 M +9mA.
As long as %
9
and #
+
constant$
9
will be constant. The %oltage drop across the diode can be found
either by measuring the volt across it or o5p voltage. The output voltage is e0ual to A%in F %
D
B %
9
M %in F %
D
. To avoid an error in output voltage the op-amp should be initially nulled. Thus the
matched diodes can be found by connecting diodes one after another in the feedback path and
measuring voltage across them.
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2. Zener diode Tester:
A>hen the switch position 6B
when the switch is in position 6$ the circuit becomes a 4ener diode tester. The circuit can be used to
find the breakdown voltage of 4ener diodes. The 4ener current is set at a constant value by %in and
#
+.
f this current is larger than the knee current A
V3
B of the 4ener$ the 4enerr blocks A%
4
B volts.
.or /7E

V3
M +mA $ %
V
M 2.6%$ %in M +v $ #
+
M +99I -ince the current through the 4ener is $
9
M %in5#
+
M
+5+99 M+9mA P
V3
the voltage across the 4ener will be appro7imately e0ual to 2.6%.
3. When the switch is in position 3: (LED)
The circuit becomes a L/D when the switch is in position :. L/D current is set at a
constant value by %in and #
+.
L/Ds can be tested for brightness one after another at this current.
"atched L/Ds with e0ual brightness at a specific value of current are useful as indicates and
display devices in digital applications.
Applications of I V Converter:
,ne of the most common use of the current to voltage converter is
+. Digital to analog Converter ADACB
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6. -ensing current through Photodetector. -uch as photocell$ photodiodes and photovoltaic
cells.
Photoconductive devices produce a current that is proportional to an incident energy or light Ai.eB t
can be used to detect the light.
1. DAC using I V converter:
t shows a combination of a DAC and current to voltage converter. The 8 digit binary
signal is the input to the DAC and %
9
is the corresponding analog output of the current to voltage
converter. The outputu of the DAC is current
9
$ the value of which depends on the logic state A9 or
+B$ of the binary inputs as indicated by the following e0n.

I
9
=
V
ref
R
h
ffffffffff
$
)
6
fffffff
+
$
2
*
fffffff
+
$
1
8
fffffff
+
$
*
+2
fffffff
+
$
:
:6
fffffff
+
$
6
2*
fffffff
+
$
+
+68
fffffffff
+
$
9
612
fffffffff
F G
@@@@+
` a
I
9
@P
o
'
ffff
current of the $AC A
` a
R
+
@P Resistance 0
` a
V
ref
@Reference Voltage Volts
` a
$
9
thro! $
)
@P Eight binar& in'uts

This means
9
is 4ero when all inputs are logic 9.

9
is ma7 when all inputs are logic +.
The variations in
9
can be converted into a desired o5p voltage range by selecting a proper value
for #
..
since$ %
9
M
9
#
.
>here
9
is given by e0n A+B. t is common to parallel #
.
with capacitance C to minimi4e the
overshoot. n the fig the o5p voltage of the current to voltage converter is positive because the
direction of input current
9
is opposite to that in the basic ! % Converter.
2. Detecting current through photosensitive devices:
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Photocells$ photodiodes$ photovoltaic cells give an output curren that depends on the
intensity of light and independent of the load. The current through this devices can be converted to
voltage by ! % converter and it can be used as a measure of the amount of light. n this fig
photocell is connected to the ! % Converter. Photocell is a passive transducer$ it re0uires an
e7ternal dc voltageA%dcB. The dc voltage can be eliminated if a photovoltaic cell is used instead of
a photocell. The Photovoltaic Cell is a semiconductor device that converts the radiant energy to
electrical power. t is a self generating circuit because it doesnot re0uire dc voltage e7ternally. /7
of Photovoltaic Cell E used in space applications and watches.
Summing Amplifier:
,p-amp may be used to design a circuit whose output is the sum of several input signals.
-uch a circuit is called a summing amplifier or a summer.
An inverting summer or a non-inverting summer may be discussed now.
Inverting Summing Amplifier:
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A typical summing amplifier with three input voltages %
+
$ %
6
and %
:
three input resistors
#
+
$ #
6
$ #
:
and a feedback resistor #
f
is shown in figure 6.
The following analysis is carried out assuming that the op-amp is an ideal one$ that is$ A
,L
M [. -ince the input bias current is assumed to be 4ero$ there is no voltage drop across the resistor
#
comp
and hence the non-inverting input terminal is at ground potential.
The voltage at nod GaH is 4ero as the non-inverting terminal is grounded. The nodal e0uation
be 3CL at node GaH is

V
+
R
+
ffffffff
+
V
6
R
6
ffffffff
+
V
:
R
:
ffffffff
+
V
o
R
f
ffffffff
= 9

,r$
V
o
= @
R
f
R
+
ffffffff
V
+
+
R
f
R
6
ffffffff
V
6
+
R
f
R
:
ffffffff
V
:
h
j
i
k

Thus the output in an inverted$ weighted sum of the inputs. n the special case$ when #
+
M
#
6
M #
:
M #
f
$ we have
V
o
=@ V
+
+ V
6
+ V
:
b c

in such case the output %
o
is the inverted sum of the input signals. >e may also set

R
+
=R
6
=R
:
=:R
f

in which case
V
o
= @
V
+
+ V
6
+ V
:
:
ffffffffffffffffffffffffffffffffffffffff
f g

Thus the output is the average of the input signals AinvertedB. n a practical circuit$ input
bias current compensating resistor #
comp
should be provided.
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To find #
comp
$ make all inputs %
+
M %
6
M %
:
M 9. -o the effective input resistance #
i
M #
+
YY
#
6
YY #
:
. Therefore$ #
comp
M #
i
YY #
f
M #
+
YY #
6
YY #
:
YY #
$f
.
Non-Inverting Summing Amplifier:
A summer that gives a non-inverted sum is the non-inverting summing amplifier of figure
:. Let the voltage at the A-B input teriminal be %
a
.
The voltage at AFB input terminal will also be %
a
. The nodal e0uation at node GaH is given by

V
+
@V
a
R
+
ffffffffffffffffffffffff
+
V
6
@V
a
R
6
ffffffffffffffffffffffff
+
V
:
@V
a
R
:
ffffffffffffffffffffffff
= 9
from which we have$

V
a
=
V
+
R
+
fffffffff
+
V
6
R
6
ffffffffff
+
V
:
R
:
fffffffff
+
R
+
fffffffff
+
+
R
6
ffffffffff
+
+
R
:
fffffffff
fffffffffffffffffffffffffffffffffffff

The op-amp and two resistors and # constitute a non-inverting amplifier with
V
o
= + +
R
f
R
ffffffff
f g
V
a

Therefore$ the output voltage is$
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V
o
= + +
R
f
R
ffffffff
f g
V
+
R
+
fffffffff
+
V
6
R
6
ffffffffff
+
V
:
R
:
fffffffff
f g
+
R
+
fffffffff
+
+
R
6
ffffffffff
+
+
R
:
fffffffff
ffffffffffffffffffffffffffffffffffffffffffff

which is a non-inverting weighted sum of inputs.
Let #
+
M #
6
M #
:
M # M #
f
56$ then %
o
M %
+
F%
6
F%
:
Subtractor:
A basic differential amplifier can be used as a subtractor as shown in the above figure. f all
resistors are e0ual in value$ then the output voltage can be derived by using superposition
principle.
To find the output %
9+
due to %
+
alone$ make %
6
M 9.
Then the circuit of figure as shown in the above becomes a non-inverting amplifier having
input voltage %
+
56 at the non-inverting input terminal and the output becomes

V
9+
=
V
+
6
ffffffff
+ +
R
R
fffff
f g
= V
+

-imilarly the output %
96
due to %
6
alone Awith %
+
groundedB can be written simply for an
inverting amplifier as
V
96
=@V
6

Thus the output voltage %
o
due to both the inputs can be written as
V
o
= V
9+
+ V
96
= V
+
@V
6

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Adder/Subtractor:
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t is possible to perform addition and subtraction simultaneously with a single op-amp
using the circuit shown in figure 1AaB.
The output voltage %
o
can be obtained by using superposition theorem. To find output
voltage %
9+
due to %
+
alone$ make all other input voltages %
6
$ %
:
and %
*
e0ual to 4ero.
The simplified circuit is shown in figure 1AbB. This is the circuit of an inverting amplifier
and its output voltage is$

V
9+
=@
R
R
6
fffffff
ffffff
V
+
6
ffffffff
=@+

Aby TheveninHs e0uivalent circuit at inverting input terminalB.
-imilarly$ the output voltage %
96
due to %
6
alone is$
V
96
=@V
6

=ow$ the output voltage %
9:
due to the input voltage signal %
:
alone applied at the AFB input
terminal can be found by setting %
+
$ %
6
and %
*
e0ual to 4ero.
The circuit now becomes a non-inverting amplifier as shown in figure 1AcB. The voltage %
a
at the non-inverting terminal is
V
a
=
R
6
fffffff
R +
R
6
fffffff
ffffffffffffffffff
V
:
=
V
:
:
ffffffff

-o$ the output voltage %
9:
due to %
:
alone is
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V
9:
= + +
R
R
6
fffffff
ffffff
h
l
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i

k V
a
= :
V
:
:
ffffffff
f g
= V
:

-imilarly$ it can be shown that the output voltage %
9*
due to %
*
alone is
V
9*
= V
*

Thus$ the output voltage %
o
due to all four input voltages is given by
V
o
= V
9+
+ V
96
+ V
9:
+ V
9*

V
o
=@V
+
@V
6
+ V
:
+ V
*

V
o
= V
:
+ V
*
b c
@ V
+
+ V
6
b c

-o$ the circuit is an adder-subtractor.
Instrumentation Amplifier:
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n a number of industrial and consumer applications$ one is re0uired to measure and control
physical 0uantities.
-ome typical e7amples are measurement and control of temperature$ humidity$ light intensity$
water flow etc. these physical 0uantities are usually measured with help of transducers.
The output of transducer has to be amplified so that it can drive the indicator or display system.
This function is performed by an instrumentation amplifier. The important features of an
instrumentation amplifier are
+. high gain accuracy
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6. high C"##
:. high gain stability with low temperature coefficient
*. low output impedance
There are specially designed op-amps such as iA)61 to meet the above stated re0uirements of
a good instrumentation amplifier. "onolithic Asingle chipB instrumentation amplifier are also
available commercially such as AD16+$ AD16*$ AD269$ AD26* by Analog Devices$ L":2:.^^
A^^ --P+9$+99$199B by =ational -emiconductor and =A+9+$ +9*$ :262$ :26? by &urr &rown.
Consider the basic differential amplifier as shown in figure 2AaB. t can be easily seen that
the output voltage %
o
is given by$
V
o
=@
R
6
R
+
fffffff
V
6
+
+
+ +
R
:
R
*
ffffffffff
fffffffffffffffffff
V
+
+ +
R
6
R
+
fffffff
f g
V
+
=
R
*
R
:
+ R
*
fffffffffffffffffffffff
V
+
F G

,r$
V
o
= @
R
6
R
+
fffffff
V
6
@
+
+ +
R
:
R
*
ffffffffff
fffffffffffffffffff
R
+
R
6
fffffff
+ +
f g
V
+
H
L
L
J
I
M
M
K
.or #
+
5#
6
M #
:
5#
*
$ we obtain
V
o
=
R
6
R
+
fffffff
V
+
@V
6
b c

n the circuit of figure 2AaB$ source %
+
sees an input impedance M #
:
F#
*
AM+9+3B and the
impedance seen by source %
6
is only #
+
A+3B. This low impedance may load the signal source
heavily.
Therefore$ high resistance buffer is used preceding each input to avoid this loading effect as
shown in figure 2AbB.
The op-amp A
+
and A
6
have differential input voltage as 4ero. .or %
+
M%
6
$ that is$ under
common mode condition$ the voltage across # will be 4ero. As no current flows through # and #H
the non-inverting amplifier.
A
+
acts as voltage follower$ so its output %
6
HM%
6
. -imilarly op-amp A
6
acts as voltage
follower having output %
+
HM%
+
. <owever$ if %
+
b%
6
$ current flows in # and #H$ and A%
6
H-%
+H
BPA%
6
-
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%
+
B. Therefore$ this circuit has differential gain and C"## more compared to the single op-amp
circuit of figure 2AaB.
The output voltage %
o
can be calculated as follows
The voltage at the AFB input terminal of op-amp A
:
is
R
6
V
+
!
R
+
+ R
6
fffffffffffffffffffffff
. Dsing superposition
theorem$ we have$
V
o
= @
R
6
R
+
fffffff
V
6
!
+ + +
R
6
R
+
fffffff
f g
R
6
V
+
!
R
+
+ R
6
fffffffffffffffffffffff
h
j
i
k

V
o
=
R
6
R
+
fffffff
V
+
!
@V
6
!
b c
Q +
` a

-ince$ no current flows into op-amp$ the current flowing AupwardsB in # is MA%
+
-%
6
B5#
and passes through the resistor #H.

V
+
!
= R
!
I + V
+
=
R
!
R
ffffff
V
+
@V
6
b c
+ V
+

and
V
6
!
= @R
!
I + V
6
= @
R
!
R
ffffff
V
+
@V
6
b c
+ V
6

Putting the values of %
+
H and %
6
H in e0uation A+B$ we obtain$
V
o
=
R
6
R
+
fffffff
6R
!
R
ffffffffff
V
+
@V
6
b c
+ V
+
@V
6
b c
F G

,r$ V
9
=
R
6
R
+
fffffff
+ +
6R
!
R
ffffffffff
f g
V
+
@V
6
b c
Q 6
` a

n e0uation A6B$ if we choose #
6
M #
+
M 613 AsayB and #H M 613e # M 19`$ then a gain of
+ + 6 +
61/
19
ffffffffffffff
f g
= +99+ can be achieved.
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The difference gain of this instrumentation amplifier #$ however should never be made
4ero$ as this will make the gain infinity. To avoid such a situation$ in a practical circuit$ a fi7ed
resistance in series with a potentiometer is used in place of #.
.igure 2AcB shows a differential instrumentation amplifier using Transducer &ridge. The
circuit uses a resistive transducer whose resistance changes as a function of the physical 0uantity to
be measured.
The bridge is initially balanced by a dc supply voltage %
dc
so that %
+
M%
6
. As the physical
0uantity changes$ the resistance #
T
of the transducer also changes$ causing an unbalance in the
bridge A%
+
b%
6
B. This differential voltage now gets amplified by the three op-amp differential
instrumentation amplifier.
There are number differential applications of instrumentation amplifier with the transducer
bridge$ such as temperature indicator$ temperature controller$ and light intensity meter to name a
few.
Differentiator:
,ne of the simplest of the op-amp circuits that contains capacitor in the
differentiating amplifier.
Differentiator:
As the name implies$ the circuit performs the mathematical operation of
differentiation Ai.eB the output waveform is the derivative of the input waveform. The differentiator
may be constructed from a basic inverting amplifier if an input resistor #
+
is replaced by a
capacitor C
+
.
The e7pression for the output voltage can be obtained 3CL e0n written at node %
6
as follows$
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i
c
= I
B
+ i
F
@@@@+
` a
Since I
B
t
9
i
c
= i
f
C
+
d
dt
ffffff
V
in
@V
6
b c
=
V
6
@V
9
R
F
fffffffffffffffffff
ButV
+
=V
6
t
9V, because Ais ver& largeATherefore,
C
+
dVin
dt
ffffffffffff
= @
V
9
R
F
ffffffff
or
V
9
=@ R
F
C
+
b c
dVin
dt
ffffffffffff
@@@6
` a

-ince the differentiator performs the reverse of the integrator function.
Thus the output %
9
is e0ual to #
.
C
+
times the negative rate of change of the input voltage %in with
time.
The !sign MP indicates a +89
9
phase shift of the output waveform %
9
with respect to the input
signal.
The below circuit will not do this because it has some practical problems.
The gain of the circuit A#
.
5^C
+
B " with " in fre0uency at a rate of 69d&5decade. This makes the
circuit unstable.
Also input impedance ^C
+
# with "in fre0uency which makes the circuit very susceptible to high
fre0uency noise.
Basic Differetntiator
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.rom the above fig$ f
a
M fre0uency at which the gain is 9d& and is given by$

f
a
=
+
6R
F
C
+
fffffffffffffffffffff
@@@@:
` a
f
C
@P !nit&@gain bandwidth of the o' @a' and f = relative o'erating fre"uenc&A
&oth stability and high fre0uency noise problems can be corrected by the addition of 6
components. #
+
and C
.
. This circuit is a practical differentiator.
.rom .re0uency f to feedback the gain "s at 69d&5decade after feedback the gain # at
69d&5decade. This *9d&5 decade change in gain is caused by the #
+
C
+
and #
.
C
.
combinations.
The gain limiting fre0uency f
b
is given by$

f
b
=
+
6R
F
C
+
fffffffffffffffffffff
@@@@*
` a

>here #
+
C
+
M #
.
C
.
#
+
C
+
and #
.
C
.
MP helps to reduce the effect of high fre0uency input$ amplifier noise and offsets.
All #
+
C
+
and #
.
C
.
make the circuit more stable by preventing the "in gain with fre0uency.
(enerally$ the value of .eedback and in turn #
+
C
+
and #
.
C
.
values should be selected such that
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f
a
U f
b
U f
C
@@@@6
` a
where
f
a
=
+
6R
F
C
+
fffffffffffffffffffff
f
b
=
+
6R
+
C
+
fffffffffffffffffff
=
+
6R
F
C
F
fffffffffffffffffffffff
f
c
= unit& gain bandwidth

The input signal will be differentiated properly$ if the time period T of the input signal is larger
than or e0ual to #
.
C
+
Ai.eB T P #
.
C
+
Practical Differentiator
A workable differentiator can be designed by implementing the following steps.
+. -elect fa e0ual to the highest fre0uency of the input signal to be differentiated then assuming a
value of C
+
U +Kf. Calculate the value of #
.
.
6. Choose fb M 69fa and calculate the values of #
+
and C
.
so that #
+
C
+
M #
.
C
.
.
Uses:
ts used in waveshaping circuits to detect high fre0uency components in an input signal and also as
a rate of change and detector in ." modulators.
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This o5p for practical differentiator.
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Integrator:
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator or ntegration Amplifier. -uch a circuit is obtained by using a basic
inverting amplifier configuration if the feedback resistor #
.
is replaced by a capacitor C
.
.
The e7pression for the output voltage %
9
can be obtained by 3%L e0n at node %
6
.
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i
+
= I
B
+ i
f
@@@@@@@@+
` a
Since I
B
is negligible sall,
i
+
t
i
F
Relation between current through and voltage across the ca'acitor is
i
C
= C
dV
c
dt
ffffffffff
@@6
` a
V
in
@V
6
R
+
fffffffffffffffffffff
=C
F
d
dt
ffffff
f g
V
6
@V
9
b c
3owever, V
+
=V
6
t
9 because Ais ver& large,
Vin
R
+
ffffffff
=C
F
d
dt
ffffff
@V
9
b c
The out'ut voltage can be obtained b& integrating both sides with res'ect to tieE
$
9
t
V
in
R
+
ffffffff
dt =$
9
t
C
F
d
dt
ffffff
@V
9
b c
dt
=C
F
@V
9
b c
+
V
9
t
fffffff
= 9
V
9
=@
+
R
+
C
F
fffffffffffffff
$
9
t
V
in
dt
c
ffffff
@@@@:
` a
where C@integration constant A

e0n A:B indicates that the output is directly proportional to the negative integral of the input volts
and inversely proportional to the time constant #
+
C
.
.
/7E f the input is sine wave -P output is cosine wave.
f the input is s0uare wave -P output is triangular wave.
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These waveform with assumption of #
+
C
f
M +$ %out M9% Ai.eB C M9.
>hen %in M 9 the integrator works as an open loop amplifier because the capacitor C
.
acts an open
circuit to the input offset voltage %io.
,r
The nput offset voltage %io and the part of the input are charging capacitor C
.
produce the error
voltage at the output of the integrator.
Practical Integrator:
Practical ntegrator to reduce the error voltage at the output$ a resistor #
.
is connected across the
feedback capacitor C
.
.
Thus #
.
limits the low fre0uency gain and hence minimi4es the variations in the output voltages.
The fre0uency response of the basic integrator$ shown from this fb is the fre0uency at which the
gain is d& and is given by$
f
b
=
+
6R
F
C
+
fffffffffffffffffffff
@@@@*
` a
&oth the stability and low fre0uency roll-off problems can be corrected by the addition of a resistor
#
.
in the practical integrator.
-tability -P refers to a constant gain as fre0uency of an input signal is varied over a certain range.
Low fre0uency -P refers to the rate of decrease in gain roll off at lower fre0uencies.
.rom the fig of practical ntegrators$
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f is some relative operating fre0uency and for fre0uencies f to fa to gain #
.
5 #
+
is constant. After fa
the gain decreases at a rate of 69d&5decade or between fa and fb the circuit act as an integrator.
The gain limiting fre0uency fa is given by
f
a
=
+
6R
F
C
F
fffffffffffffffffffffff
@@@1
` a

(enerally the value of fa and in turn #
+
C
.
and #
.
C
.
values should be selected such that faUfb. n
fact$ the input signal will be integrated properly if the time period T of the signal is larger than or
e0ual to #
.
C
.$
Ai.eB
T R
F
C
F
@@@@2
` a

>here

R
F
C
F
=
+
6f
a
fffffffffffff

DsesE
"ost commonly used in analog computers.
ADC
-ignal wave shaping circuits.
Log and Antilog Amplifier:
There are several applications of log and antilog amplifiers. Antilog computation may
re0uire functions such as ln 7$ log 7 or -inh7.
These can be performed continusely with log amps$ and also used for direct d& display on a
digital %oltmeter and -pectrum analy4er.
Log-amp can also be used to compress the dynamic range of a signal.
Log Amplifier:
The fundamental log amp circuit shown in fig
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.ig a. .undamental log-amp Circuit
>here a grounded base transistor is placed in the feedback path. -ince the collector is
placed in the feedback path.
-ince the collector is held at virtual ground and the base is also grounded$ the transistorHs
voltage-current relationship becomes that of a diode and is given by$
I
E
= I
s
e
"V
E
0T
fffffffffffffffffff
@+
d e
---------------A+B
-ince$ c M
/
for a grounded base transistor.
I
C
= I
s
e
"V
E
0T
fffffffffffffffffff
@+
d e
-------------- A6B
s-emitter saturation current O+9
-+:
A
kM&olt4mannHs constant
TMabsolute temperatureAin
o
3B
Therefore
Ic
Is
ffffff
= e
"V
E
0T
fffffffffffffffffff
@+
d e
----------A:B
,r
e
"V
E
0T
fffffffffffffffffff
=
Ic
Is
ffffffff
+ +
O
c
5
s
Aas sO+9
-+:
A$
c
PP
s
B
Taking natural log on both sides$ we get

v
E
=
0T
"
ffffffffff
ln
I
c
I
s
ffffff
f g
----------------A*B
Also in fig a
cM %
i
5#
+
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%
/
M - %
o
-o
V
o
=@
0T
"
ffffffffff
ln
V
i
R
+
I
s
ffffffffffffff
h
j
i
k
=@
0T
"
ffffffffff
ln
v
i
V
ref
ffffffffffff
f g
---------------A1B
>here %
ref
M#
+

s
The output voltage is thus proportional to the logarithm of input voltage.
Although the circuit gives natural log AlnB$one can find log
+9$
by proper scaling
Log+9^M9.*:*: ln ^-----------------------A2B
The circuit have one problem.
The emitter saturation current s varies from transistor to transistor and with temperature.
Thus a stable reference voltage % ref cannot be obtained
This is eliminated by the circuit given in figAbB
The input is applied to one log-amp$ while a reference voltage is applied to one log-amp$while a
reference voltage is applied to another log-amp.
The two transistors are integrated close together in the same silicon wafer. This provides a
close match of saturation currents and ensures good thermal tracking.
.igAbBLog-amp with saturation current and temperature compensation
Assume
-+
M
-6
M
-
--------------------------A)B
And then $
V
+
=
0T
"
ffffffffff
ln
V
i
R
+
I
s
ffffffffffffff
h
j
i
k
--------------A8B
And %
6
M
0T
"
ffffffffff
ln
V
ref
R
+
I
s
ffffffffffffff
h
j
i
k
---------------------A?B
=ow$ %oM%
6
-%
+
M
0T
"
ffffffffff
ln
V
i
R
+
I
s
ffffffffffffff
h
j
i
k
@ln
v
ref
R
+
I
s
ffffffffffffff
f g
H
L
J
I
M
K
----------A+9B
%
o M
0T
"
ffffffffff
ln
V
i
V
ref
ffffffffffff
h
j
i
k

-------------------A++B

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Thus the reference level is now set with a single e7ternal voltage source. ts dependence on
device and temperature has been removed. The voltage vo is still dependent upon temperature and
is directly proportional to T. This is compensated by the last op-amp stage A
*
which provides a
non-inverting gain of A+F#
6
5#
TC
B.=ow$ the output voltage is

v
o
co'
M
+ +
R
6
R
TC
fffffffffff
h
j
i
k
0T
"
ffffffffff
ln
V
i
V
ref
ffffffffffff
h
j
i
k
----------------------A+6B
>here #
TC
is a temperature-sensitive resistance with a positive coefficient of temperature
AsensorB so that the slope of the e0uation becomes constant as the temperature changes.
Antilog Amplifier
The Circuit is shown in fig .The input %i for the antilog-amp is fed into the temperature
compensating voltage divider #
6
and #
TC
and then to the base of L
6 .
The output %
o
of the antilog-
amp is fed back to the inverting input of A
+
through the resistor #
+.
The base to emitter voltage of
transistors L
+
and L
6
can be written as

V
#+ B@E
=
0T
"
ffffffffff
ln
V
o
R
+
I
s
ffffffffffffff
f g
--------------------Ah:B
And

V
#6 B@E
=
0T
#
ffffffffff
ln
V
ref
R
+
I
s
ffffffffffffff
h
j
i
k
----------------------A+*B
-ince the base of L
+
is tied to ground$ we get

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%
AM
@V
#+ B@E
=@
0T
"
ffffffffff
ln
V
o
R
+
I
s
ffffffffffffff
f g

-------------------------A+1B
The base voltage %
&
of L
6
is

V
B
=
R
TC
R6 + R
TC
ffffffffffffffffffffffffffff
h
j
i
k
V
i

The voltage at the emitter of L
6
is

V
#6B@E
=V
B
+V
#6 E@B
,r

V
#6B@E
=
R
TC
R
6
+ R
TC
fffffffffffffffffffffffffff
h
j
i
k
V
i
@
0T
"
ffffffffff
ln
V
ref
R
+
I
s
ffffffffffffff
h
j
i
k
--------------------A+2B
&ut the emitter voltage of L
6
is %
A
$ that is
%
A M
%
L6&-/

,r$
@
0T
"
ffffffffff
ln
V
o
R
+
I
s
ffffffffffffff
=
R
TC
R
6
+ R
TC
b c
fffffffffffffffffffffffffffffffff
V
i
@
0T
"
ffffffffff
ln
V
ref
R
+
I
s
ffffffffffffff
-----------------A+)B
,r$
R
TC
R
6
+ R
TC
fffffffffffffffffffffffffff
V
i
=@
0T
"
ffffffffff
ln
V
o
R
+
I
s
ffffffffffffff
@ln
V
ref
R
+
I
s
ffffffffffffff
h
j
i
k

,r
@
"
0T
ffffffffff
R
TC
R
6
+ R
TC
fffffffffffffffffffffffffff
V
i
= ln
V
o
V
ref
ffffffffffff
h
j
i
k
------------------A+8B
Changing the natural log i.e.$ln to log
+9
using e0nA2B we get

@9.*:*:
"
0T
ffffffffff
d e
R
TC
R
6
+ R
TC
fffffffffffffffffffffffffff
h
j
i
k
V
i
= 9.*:*:B ln
V
o
V
ref
ffffffffffff
h
j
i
k

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,r
@/! V
i
= log
+9
V
o
V
ref
ffffffffffff
h
j
i
k

,r
V
o
V
ref
ffffffffffff
=+9
@0! V
i

,r %
o
M%
ref
S
+9
@0! V
i
T
>here 3HM
9.*:*:
"
0T
ffffffffff
d e
R
TC
R
6
+ R
TC
fffffffffffffffffffffffffff
h
j
i
k

<ence an increase of input by one volt causes the output to decrease by a decade.
Comparator
To obtain for better performance$ we shall also look at integrated designed specifically as
comparators and converters. A comparator as its name implies$ compares a signal voltage on one
input of an op-amp with a known voltage called a reference voltage on the other input.
Comparators are used in circuits such as$
Digital nterfacing
-chmitt Trigger
Discriminator
%oltage level detector and oscillators
1. Non-inverting ComparatorE
A fi7ed reference voltage %ref of + % is applied to the negative terminal and time
varying signal voltage %in is applied tot the positive terminal.>hen %in is less than %ref the
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output becomes %
9
at !%sat S%in U %ref MP %
9
A-%satBT. >hen %in is greater than %ref$ the AFB
input becomes positive$ the %
9
goes to F%sat. S%in P %ref MP %
9
AF%satBT. Thus the %
9
changes
from one saturation level to another. The diodes D
+
and D
6
protects the op-amp from damage due to
the e7cessive input voltage %in. &ecause of these diodes$ the difference input voltage %id of the
op-amp diodes are called clamp diodes. The resistance # in series with %in is used to limit the
current through D
+
and D
6
. To reduce offset problems$ a resistance #comp M # is connected
between the A-veB input and %ref.
Input and Output Waveforms:
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2. Inverting Comparator:
This fig shows an inverting comparator in which the reference voltage %ref is applied to the AFB
input terminal and %in is applied to the A-B input terminal. n this circuit %ref is obtained by using a
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+93 potentiometer that forms a voltage divider with dc supply volt F%cc and -+ and the wiper
connected to the input. As the wiper is moved towards F%cc$ %ref becomes more positive. Thus a
%ref of a desired amplitude and polarity can be obtained by simply ad;usting the +9k
potentiometer.
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3. Zero Crossing Detector: Sine wave to Square wave converter]
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,ne of the application of comparator is the 4ero crossing detector or \sine wave to
-0uare wave Converterj. The basic comparator can be used as a 4ero crossing detector by setting
%ref is set to Vero. A%ref M9%B.
This .ig shows when in what direction an input signal %in crosses 4ero volts. Ai.eB the o5p %
9
is
driven into negative saturation when the input the signal %in passes through 4ero in positive
direction. -imilarly$ when %in passes through Vero in negative direction the output %
9
switches
and saturates positively.
Drawbacks of Zero- crossing detector:
n some applications$ the input %in may be a slowly changing waveform$ Ai.eB a low fre0uency
signal. t will take %in more time to cross 9%$ therefore %
9
may not switch 0uickly from one
saturation voltage to the other. &ecause of the noise at the op-ampHs input terminals the output %
9
may fluctuate between 6 saturations voltages F%sat and !%sat. &oth of these problems can be
cured with the use of regenerative or positive feedback that cause the output %
9
to change faster
and eliminate any false output transitions due to noise signals at the input. nverting comparator
with positive feedback . This is known as \-chmitt Triggerj.
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Schmitt Trigger: Square Circuit]
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This circuit converts an irregular shaped waveform to a s0uare wave or pulse. The
circuit is known as -chmitt Trigger or s0uaring circuit. The input voltage %in triggers Achanges the
state ofB the o5p %
9
every time it e7ceeds certain voltage levels called the upper threshold %ut and
lower threshold voltage. These threshold voltages are obtained by using theh voltage divider #
+
!
#
6$
where the voltage across #
+
is feedback to the AFB input. The voltage across #
+
is variable
reference threshold voltage that depends on the value of the output voltage. >hen %
9
M F%sat$ the
voltage across #
+
is called \upper thresholdj voltage %ut. The input voltage %in must be more
positive than %ut in order to cause the output %
9
to switch from F%sat to !%sat. As long as %in U
%ut $ %
9
is at F%sat$ using voltage divider rule$
V
ut
=
R
+
R
+
+ R
6
ffffffffffffffffff
+V
sat
b c
A
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-imilarly$ when %
9
M -%sat$ the voltage across #
+
is called lower threshold voltage %
lt .
the vin must
be more negative than %
lt
in order to cause %
9
to switch from !%sat to F%sat. n other words$ for
%in P %
lt
$ %
9
is at !%sat. %
lt
is given by the following e0n.
V
lt
=
R
+
R
+
+ R
6
ffffffffffffffffff
@V
sat
b c
A
Thus$ if the threshold voltages %ut and %lt are made larger than the input noise voltages$ the
positive feedback will eliminate the false o5p transitions. Also the positive feedback$ because of its
regenerative action$ will make %
9
switch faster between F%sat and !%sat. #esistance #comp
t

#
+
YY #
6
is used to minimi4e the offset problems. The comparator with positive feedback is said to
e7hibit hysteresis$ a dead band condition. Ai.eB when the input of the comparator e7ceeds %ut its
output switches from F%sat to !%sat and reverts to its original state$ F%sat when the input goes
below %lt. The hysteresis voltage is e0ual to the difference between %ut and %lt. Therefore
%ref M %ut ! %lt
%ref M #
+
---------

#
+
F #
6
SF%sat -A-%satBT
Precision Rectifier:
The signal processing applications with very low voltage$ current and power levels re0uire
rectifier circuits. The ordinary diodes cannot rectify voltages below the cut-in-voltage of the diode.
A circuit which can act as an ideal diode or precision signal ! processing rectifier circuit for
rectifying voltages which are below the level of cut-in voltage of the diode can be designed by
placing the diode in the feedback loop of an op-amp.
Precision diodes:
.igure shows the arrangement of a precision diode. t is a single diode arrangement and functions
as a non-inverting precision half ! wave rectifier circuit. f %
+
in the circuit of figure is positive$
the op-amp output %
,A
also becomes positive. Then the closed loop condition is achieved for the
op-amp and the output voltage %
9
M %
i
. when %
i
U 9$ the voltage %
9A
becomes negative and the
diode is reverse biased. The loop is then broken and the output %
9
M 9.
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nput and ,utput >aveform
Consider the open loop gain A
,L
of the op-amp is appro7imately +9
*
and the cut-in voltage
%
k
for silicon diode is O 9.)%. >hen the input voltage %
i
P %
k
5 A
,L
$ the output of the op-amp %
,A
e7ceeds %
k
and the diode D conducts. Then the circuit acts like a voltage follower for input voltage
level %
i
P %
k
5 A
,L
$Ai.e. when %
i
P 9.)5+9
*
M )9K%B$ and the output voltage %
9
follows the input
voltage during the positive half cycle for input voltages higher than )9K% as shown in figure.
>hen %
i
is negative or less than %
k
5 A
,L
$ the output of op-amp %
,A
becomes negative$ and the
diode becomes reverse biased. The loop is then broken$ and the op-amp swings down to negative
saturation. <owever$ the output terminal is now isolated from both the input signal and the output
of the op-amp terminal thus %
9
M9. =o current is then delivered to the load #
L
e7cept for the small
bias current of the op-amp and the reverse saturation current of the diode.
This circuit is an e7ample of a non-linear circuit$ in which linear operation is achieved over the
remaining region A%
i
U 9B. -ince the output swings to negative saturation level when %
i
U 9$ the
circuit is basically of saturating form. Thus the fre0uency response is also limited. The precision
diodes are used in half wave rectifier$ .ull-wave rectifier$ peak value detector$ clipper and clamper
circuits.
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t can be observed that the precision diode as shown in figure operated in the first 0uadrant with %
i
P 9 and %
9
P 9. The operation in third 0uadrant can be achieved by connecting the diode in reverse
direction.
Half wave Rectifier:
A non-saturating half wave precision rectifier circuit is shown in figure. >hen %
i
P 9% $ the
voltage at the inverting input becomes positive$ forcing the output %
,A
to go negative. This results
in forward biasing the diode D
+
and the op-amp output drops only by O 9.)% below the inverting
input voltage. Diode D
6
becomes reverse biased. The output voltage %
9
is 4ero when the input is
positive. >hen %
i
P 9$ the op-amp output %
,A
becomes positive$ forward biasing the diode D
6
and
reverse biasing the diode D
+
. The circuit then acts like an inverting amplifier circuit with a non-
linear diode in the forward path. The gain of the circuit is unity when #
f
M #
i
.
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The circuit operation can mathematically be e7pressed as

V
9
= 9 when V
i
P 9
and
V
9
=
R
f
R
i
fffffff
V
i
forV
i
U9
The voltageV
OA
at the o' @a' out'ut is
V
OA
t
9.) forV
i
P 9V
and
V
OA
t
R
f
R
i
fffffff
V
i
+ 9.)V forV
i
U 9VA

The input and output waveforms are shown in figure. The op-amp shown in the circuit must be a
high speed op-amp. This accommodates the abrupt changes in the value of %
,A
when %
i
changes
sign and improves the fre0uency response characteristics of the circuit.
The advantages of half wave rectifier are it is a precision half wave rectifier and it is a non
saturating one.
The inverting characteristics of the output %
9
can be circumvented by the use of an additional
inversion for achieving a positive output.
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Full wave Rectifier:
The .ull wave #ectifier circuit commonly used an absolute value circuit is shown in figure. The
first part of the total circuit is a half wave rectifier circuit considered earlier in figure. The second
part of the circuit is an inverting.
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.or positive input voltage %
i
P 9% and assuming that #
.
M#
i
M #$ the output voltage %
,A
M %
i
. The
voltage %
9
appears as A-B input to the summing op-amp circuit formed by A
6
$ The gain for the
input %H
9
is #5A#56B$ as shown in figure. The input %
i
also appears as an input to the summing
amplifier. Then$ the net output is %
9
M -%
i
-6%H
9
M -%
i
-6A-%
i
B M %
i
-ince %
i
P 9%$ %H
9
will be positive$ with its input output characteristics in first 0uadrant. .or
negative input %
i
U 9%$ the output %H
9
of the first part of rectifier circuit is 4ero. Thus$ one input of
the summing circuit has a value of 4ero. <owever$ %
i
is also applied as an input to the summer
circuit formed by the op-amp A
6
. The gain for this input id A-#5#B M -+$ and hence the output is %
9
M -%
i
. -ince %
i
is negative$ v
9
will be inverted and will thus be positive. This corresponds to the
second 0uadrant of the circuit.
To summari4e the operation of the circuit$
%
9
M %
i
when %
i
U 9% and %
9
M %
i
for %
i
P 9%$ and hence %
9
M Y%
i
Y
t can be observed that this circuit is of non-saturating form. The input and output waveforms are
shown in the figure.
Peak detector:
-0uare$ Triangular$ -awtooth and pulse waves are typical e7amples of non-sinusoidal
waveforms. A conventional ac voltmeter cannot be used to measure these sinusoidal waveforms
because it is designed to measure the rms value of the pure sine wave. ,ne possible solution to this
problem is to measure the peak values of the non-sinusoidal waveforms. Peak detector measures
the Fve peak value of the s0uare wave input.
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iB During the positive half cycle of %inE
the o5p of the op-amp drives D
+
on. A.orward biasedB
Charging capacitor C to the positive peak value %
p
of the input volt %in.
iiB During the negative half cycle of %inE
D
+
is reverse biased and voltage across C is retained. The only discharge path for C is
through #
L.
since the input bias
&
is negligible.
.or proper operation of the circuit$ the charging time constant AC#
d
B and discharging time constant
AC#
L
B must satisfy the following condition.
C#
d
UM T5+9 -----A+B
>here #
d
M #esistance of the forward-biased diode.
T M time period of the input waveform.
C#
L
PM+9T -----A6B
>here #
L
M load resistor. f #
L
is very small so that e0n A6B cannot be satisfied. Dse a AbufferB
voltage follower circuit between capacitor C and #
L
load resistor.
# M is used to protect the op-amp against the e7cessive discharge currents.
#comp M minimi4es the offset problems caused by input current
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D
6
M conducts during the !ve half cycle of %in and prevents the op-amp from going into negative
saturation.
=oteE -ve peak of the input signal can be detected simply by reversing diode D
+
and D
6
.
Clippers and Clampers:
>aveshaping circuits are commonly used in digital computers and communication
such as T% and ." receiver. >aveshaping techni0ue include clipping and clamping. n op-amp
clipper circuits a rectifier diode may be used to clip off a certain portion of the input signal to
obtain a desired o5p waveform. The diode works as an ideal diode AswitchB because when on -P the
voltage drop across the diode is divided by the open loop gain of the op-amp. >hen offAreverse
biasedB -P the diode is an open circuit.
n an op-amp clamper circuits$ however a predetermined dc level is deliberately inserted in the o5p
volt. .or this reason$ the clamper is sometimes called a dc inverter.
Positive and Negative Clipper:
Positive Clipper:
A Circuit that removes positive parts of the input signal can be formed by using an
op-amp with a rectifier diode. The clipping level is determined by the reference voltage %ref$
which should less than the i5p range of the op-amp A%ref U %inB. The ,utput voltage has the
portions of the positive half cycles above %ref clipped off.
The circuit works as followsE
During the positive half cycle of the input$ the diode D
+
conducts only until %in M %ref. This
happens because when %in U%ref$ the output volts %
9
G of the op-amp becomes negative to device
D
+
into conduction when D
+
coonducts it closes feedback loop and op-amp operates as a voltage
follower. Ai.eB ,utput %
9
follows input until %in M %ref.
>hen %in P %ref MP the %H
9
becomes Fve to derive D
+
into off. t open the feedback loop and op-
amp operates open loop. >hen %in drops below %ref A%inU%refB the o5p of the op-amp %H
9
again
becomes !ve to device D
+
into conduction. t closed the f5b. Ao5p follows the i5pB. Thus diode D
+
is
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on for vinU%ref Ao5p follows the i5pB and D
+
is off for %inP%ref. The op-amp alternates between
open loop AoffB and closed loop operation as the D
+
is turned off and on respectively. .or this
reason the op-amp used must be high speed and preferably compensated for unity gain.
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/7E for high speed op-amp <A 6199$ L":+9$ KA :+8. n addition the difference input voltage
A%idMhighB is high during the time when the feedback loop is open AD
+
is offB hence an op-amp
with a high difference input voltage is necessary to prevent input breakdown. f #
p
ApotB is
connected to !%
//
instead of F%cc$ the ref voltage %ref will be negative A%ref M -veB. This will
cause the entire o5p waveform above !%ref to be clipped off.
Negative Clipper:
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The positive clipper is converted into a !ve clipper by simply reversing diode D
+
and changing the
polarity of %ref voltage. The negative clipper -P clips off the !ve parts of the input signal below
the reference voltage. Diode D
+
conducts -P when %in P -%ref and therefore during this period o5p
volt %
9
follows the i5p volt %in. The !%e portion of the output volt below !%ref is clipped off
because AD
+
is offB %inU-%ref. f !%ref is changed to !%ref by connecting the potentiometer #
p
to
the F%cc$ the %
9
below F%ref will be clipped off. The diode D
+
must be on for %in P %ref and off
for %in.
Positive and Negative Clampers:
n clamper circuits a predetermined dc level is added to the output voltage. AorB The output is
clamped to a desired dc level.
+. f the clamped dc level is Fve$ the clamper is positive clamper
6. f the clamped dc level is !ve$ the clamper is negative clamper.
,ther e0uivalent terms used for clamper are dc inserter or restorer. nverting and =on-nverting
that use this techni0ue.
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Capacitor:
The %alue of the capacitors in these circuits depends on different input rates and pulse widths.
+. n both circuits the dc level added to the o5p voltage is appro7imately e0ual to %cc56.
6. This Fve fi7ed dc level is needed to obtain a ma7imum undistored symmetrical sine wave.
Peak clamper circuit: Input and output waveform with +Vref:
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Input and Output Waveform with Vref:
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n this circuit$ the input waveform peak is clamped at %ref. .or this reason$ the circuit
is called the peak clamper.
.irst consider the input voltage %ref at the AFB inputE since this volt is Fve$ %H
9
is also Fve which
forward biases D
+
. This closed the feedback loop.
%oltage %in at the A-B inputE During its !ve half cycle$ diode D
+
conducts$ charging ce to the !ve
peak value of %
p
. During the Fve half cycle$ diode D
+
in reverse biased. -ince this voltage %
p
is in
series with the Fve peak volt %
p
the o5p volt %
9
M 6 %
p.
Thus the nett o5p is %ref plus 6 %
p.
so the !
ve peak of 6 %
p
is at %ref. .or precision clamping$ C
i
#
d
UU T56
>here #
d
M resistance of diode D
+
when it is forward biased.
T M time period of the input waveform.
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#esistor r MP is used to protect the op-amp against e7cessive discharge currents from capacitor C
i
especially when the dc supply voltages are switched off. A Fve peak clamping is accomplished by
reversing D
+
and using !ve reference voltage A-%refB.
Note:
nv and =on-nv clamper ! .i7ed dc level
Peak clamper ! %ariable dc level
Active filters:
Another important field of application using op-amp.
Filters and Oscillators:
An electric filter is often a fre0uency selective circuit that passes a specified band of
fre0uencies and blocks or alternates signal and fre0uencies outside this band.
.ilters may be classified as
+. Analog or digital.
6. Active or passive
:. Audio AA.B or #adio .re0uency A#.B
1. Analog or digital filters:
Analog filters are designed to process analog signals$ while digital filters process analog
signals using digital techni0ue.
2. Active or Passive:
Depending on the type of elements used in their construction$ filter may be classified as
passive or Active elements used in passive filters are #esistors$ capacitors$ inductors. /lements
used in active filters are transistor$ or op-amp.
Active filters offers the following advantages over a passive filters:
+. (ain and .re0uency ad;ustment fle7ibilityE
-ince the op-amp is capable of providing a gain$ the i5p signal is not attenuated as it is in a
passive filter. SActive filter is easier to tune or ad;ustT.
6. =o loading problemE
&ecause of the high input resistance and low o5p resistance of the op-amp$ the active filter
does not cause loading of the source or load.
:. CostE
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Active filters are more economical than passive filter. This is because of the variety of
cheaper op-amps and the absence of inductors.
The most commonly used filters are theseE
+. Low pass .ilters
6. <igh pass .ilters
:. &and pass filters
*. &and !re;ect filters
1. All pass filters.
Frequency response of the active filters:
Low pass .ilter
<igh pass .ilter
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&and Pass .ilters
Band Reject
Low pass filters:
+. t has a constant gain from 9 <4 to a high cutoff fre0uency f
+
.
6. At f
<
the gain in down by :db.
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:. The fre0uency between 9h4 and f
<
are known as the passband fre0uencies. >here as the
range of fre0uencies those beyond f
<$
that are attenuated includes the stopband fre0uencies.
*. &utterworth$ clebyshev and cauer filter are some of the most commonly used practical
filters.
1. The key characteristics of the butter worth filter is that it has a flat pass band as well as stop
band. .or this reason$ it is sometimes called a flat-flat filters.
2. Chebyshev filter -P has a ripple pass band @ flat stop band.
). Causer .ilter -P has a ripple pass band @ ripple stopband. t gives best stopband response
among the three.
High pass filter:
<igh pass filter with a stop band
9UfU f
L
and a pass band fP f
L

f
L
-P low cut off fre0uency
f -P operating fre0uency.
&and pass filterE
t has a pass band between 6 cut off fre0uencies f
<
and f
L
where f
<
P f
L
and two$ stop
bands E 9UfU f
L
and f P f
<
between the band pass filter Ae0ual to f
<
- f
L
.
&and !re;ect filterE A&and stop or &and eliminationB
t performs e7actly opposite to the band pass. t has a band stop between 6 cut-off
fre0uency f
L
and f
<
and 6 passbandsE 9UfU f
L
and fP f
<

f
C
-P center fre0uency.
Note:
The actual response curves of the filters in the stopband either "or # or both with "in
fre0uencies.
The rate at which the gain of the filter changes in the stopband is determined by the order
of the filter.
/7E +
st
order low pass filter the gain rolls off at the rate of 69d&5decade in the stopband.
Ai.eB for f P f
<
.
6
nd
order LP. -P the gain roll off rate is *9d&5decade.
+
st
order <P. -P the gain "s at the rate of 69d& Ai.eB until fEf
L
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6
nd
order <P. -P the gain "s at the rate of *9d&5decade
First order LPF Butterworth filter:
.irst order LP. that uses an #C for filtering op-amp is used in the non inverting
configuration. #esistor #+ @ #
f
determine the gain of the filter. According to the voltage !divider
rule$ the voltage at the non-inverting terminal Aacross capacitorB C is$
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V
+
=
@+,
C
R@+,
C
ffffffffffffffffffffff
Vin @@@@@+
` a
a
where
+ = @+
%
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww

+
@+,
C
=
+
+6f
C
ffffffffffffffff
si'lif&ing e"n +
` a
a we get
=
Vin
+
6 f
C
fffffffffffffffff
R +
+
6 f
c
ffffffffffffffff
ffffffffffffffffffffff
=
Vin
+ + +6f RC
fffffffffffffffffffffffffffff
Ou't'ut Voltage, i AeV
9
= A
f
BV
+
V
9
= + +
R
F
R
+
ffffffff
f g
h
j
i
k
V
+
V
9
= + +
R
F
R
+
ffffffff
f g
Vin
+ + 6fRC
ffffffffffffffffffffffffff
V
9
V
in
ffffffff
=
A
F
+ + +
f
f
3
ffffffffff
f g
fffffffffffffffffffffffffff
@@@+
` a
b f
3
=
+
6RC
fffffffffffffff
where
V
9
V
in
ffffffff
= gain of the filter as a function of fre"uenc&
a
F
= + +
R
F
R
h
ffffffff
= 'assband gain of the filter
F = fre"uenc& of the in'ut signal A
f
3
=
+
6RC
fffffffffffffff
= high cut off fre"uenc& of the filter A
The gain magnitude and phase angle of the e0uation of the LP. can be obtained by
converting e0n A+B b into its e0uivalent polar form as follows.
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V
9
V
in
ffffffff
L
L
L
L
L
M
M
M
M
M
=
A
F
+ +
f
f
3
ffffffffff
f g
6
v
u
u
u
t
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww
ffffffffffffffffffffffffffffffff
@@@6
` a
a
=@tan
@+
f
f
3
ffffffff
h
j
i
k
@@@@@6
` a
b

>here l is the phase angle in degrees. The operation of the LP. can be verified from the
magnitude e0n A6Ba
+. At very low fre0uency$ fUf
<

V
9
V
in
ffffffff
L
L
L
L
L
M
M
M
M
M
= A
F

6. At f Mf
<

V
o
V
in
ffffffff
L
L
L
L
L
M
M
M
M
M
=
A
F
6
%
wwwwwwwwwwwwwwwwwwwwww
fffffffff
= 9.)9) A
F

:. At fP f
<

V
o
V
in
ffffffff
L
L
L
L
L
M
M
M
M
M
U A
F

>hen the fre0uency "tenfold Aone decadeB$ the volt gain is divided by +9. AorB The
gain # 69 d&AM69log+9B each time the fre0uency is "by +9.
<ence the rate at which the gain rolls off f
<
M 69 d& or 2d&5octatve Atwofold "in
fre0uencyB. The fre0uency f M f
<
is called the cut off fre0uency because the gain of the filter at
this fre0uency is down by : d&AM69 log 9.)9B
Filter Origin:
A LP. can be designed by implementing the following steps.
+. Choose a value of high cut off fre0uency f
<
.
6. -elect a value of C less than or e0ual to +Kf.
:. Choose the value of # suing$
R =
+
6f
3
C
ffffffffffffffffffff
*. .inally select values of #+ and #
.
dependent on the desired passband gain A
.
using$
A
F
= + +
R
F
R
+
ffffffff

Frequency Scaling:
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,nce a filter is designed$ these may sometimes be a need to change its cutoff
fre0uency.
Convertion of original cutoff fre0uency f
<
to a new cut off fre0uency f
<
G is called
fre0uency scaling.
To change a high cutoff fre0uency multiply # or C$ but not both by the ratio of

,riginal cutoff fre0uency
------------------------------------------------
=ew cut off fre0uency
And fH
<
# or fH
<
C and then calculate f
<
.
Second order LP Butterworth filter:
A second order LP. having a gain *9d&5decade in stop band. A .irst order LP. can
be converted into a order type simply by using an additional #C network.
The gain of the order filter is set by #+ and #
.
$ while the high cut off fre0uency f
<
is determined
by #6$C6$#: and C:.

f
3
=
+
6 R
6
R
:
C
6
C
:
&
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww
ffffffffffffffffffffffffffffffffffffffffffff
@@@+
` a

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This above fig transferred into - domain.
n this circuit all the components and the circuit parameters are e7pressed in the --domain where -
M ; .
>riting 3irchoffHs current law at node %
A
A-B .

+
M
6
F
:
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V
in
@V
A
R
6
ffffffffffffffffffffff
=
V
A
@V
9
+
SC
6
ffffffffffff
ffffffffffffffffffff
+
V
A
@V
+
R
:
ffffffffffffffffffff
@@@@6
` a
using voltage divider rule,
V
+
=
+
SC
:
ffffffffffff
R
:
+
+
SC
6
ffffffffffff
f g
ffffffffffffffffffffffffffff
V
A
V
+
=V
+
=
V
A
R
:
C
:
s + +
fffffffffffffffffffffffffff
V
A
= R
:
C
:
S + +
b c
V
+
@@@@@:
` a
Substituting thhe value ofV
A
in e"n 6
` a
and solving forV
+
, we get,
Fro E"n 6
` a
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V
in
@V
A
R
6
ffffffffffffffffffffff
= SC
6
V
A
@V
9
b c
+
V
A
@V
+
R
:
ffffffffffffffffffff
V
in
@V
A
= R
6
C
6
SV
A
@R
6
C
6
SV
9
+ V
A
@V
+
b c
R
6
R
:
fffffff
V
in
@V
A
= R
6
C
6
SV
A
@R
6
C
6
SV
9
+V
A
R
6
R
:
fffffff
@V
+
R
6
R
:
fffffff
@R
6
C
6
SV
A
@
R
6
R
:
fffffff
V
A
@V
A
=@V
in
@R
6
C
6
SV
9
@V
+
R
6
R
:
fffffff
V
A
R
6
C
6
S +
R
6
R
:
fffffff
+ +
F G
=V
in
+ R
6
C
6
SV
9
+V
+
R
6
R
:
fffffff
V
A
R
:
R
6
C
6
S + R
6
+ R
:
B C
=V
in
R
:
+ R
6
R
:
C
6
SV
9
+V
+
R
6
substitutingV
A
R
:
C
:
S + +
b c
V
+
R
6
R
:
C
6
s + R
6
+ R
:
B C
=V
in
R
:
+ R
6
R
:
C
6
SV
9
R
6
V
+
R
:
C
:
S + +
b c
v
+
R
6
R
:
C
6
S + R
6
+ R
:
B C
@R
6
V
+
=V
in
R
:
+ R
r
:
C
6
SV
+
V
+
=
R
:
V
in
+ R
6
R
:
C
6
SV
9
R
:
C
:
S + +
b c
R
6
R
:
C
6
S + R
6
+ R
:
b c
@R
6
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
@@@@*
` a
V
9
= A
F
V
+
b c
A
F
= + +
R
F
R
+
ffffffff
V
9
=
A
F
V
in
R
:
+ R
6
R
:
C
6
sV
9
B C
R
:
C
:
S + +
b c
R
6
C
6
R
:
S + R
6
+ R
:
b c
@R
6
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
V
9
V
in
ffffffff
= A
F
=
A
F
V
in
R
:
+ r
6
R
:
C
6
S
V
9
V
in
ffffffffff
f g
H
J
I
K
R
6
+ R
:
R
:
R
6
C
6
S + R
:
6
R
6
C
:
C
6
S
6
+ R
:
R
6
C
:
S + R
:
6
C
:
S @R
6
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
=
A
F
V
inR
:
+ + R
6
C
6
SA
F
B C
S
6
R
:
6
R
6
C
6
C
:
+ R
:
6
C
:
S + R
6
R
:
C
:
S + R
:
R
6
C
6
S + R
:
fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
=
A
F
V
in
+ + R
6
C
6
SA
F
B C
S
6
R
:
R
6
C
:
C
6
+ R
:
C
:
S + R
6
C
:
S + R
6
C
6
S + +
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
=
A
F
+ + R
6
C
6
SA
F
B C
S
6
b c
+
R
:
C
:
+ R
6
C
:
+ R
6
C
6
b c
S
R
:
R
6
C
6
C
:
fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
+
+
R
:
R
6
C
6
C
:
fffffffffffffffffffffffffffffffffff
@@@@@@@1
` a
fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
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The denominator 0uadratic in the gain A%
9
5%inB e0n must have two real and e0ual roots. This
means that

6
3 =
+
R
6
R
:
C
6
C
:
fffffffffffffffffffffffffffff
@@@@@2
` a
or3 =
+
R
6
R
:
C
6
C
:
&
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww
ffffffffffffffffffffffffffffffffffff
@@@@@)
` a
f
3
=
+
6 R
6
R
:
C
6
C
:
&
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww
d e
fffffffffffffffffffffffffffffffffffffffffffffffff
@@@8
` a

.or a second-order LP &utterworth response$ the volt gain magnitude e0n is$

V
9
Vin
ffffffff
L
L
L
L
L
M
M
M
M
M
=
A
F
+ +
f
f
3
ffffffffff
f g
*
v
u
u
u
t
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww
ffffffffffffffffffffffffffffffff
A
F
= + +
R
F
R
+
ffffffff
= 'assband gain of the filter A
f = fre"uenc& of the in'ut signal 35
` a
f
3
=
+
6 R
6
R
:
C
6
C
:
&
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww
ffffffffffffffffffffffffffffffffffffffffffff
= high cut off fre"uenc& 35
` a

Filter Design:
+. Choose a value for a high cut off fre0 Af
<
B.
6. To simplify the design calculations$ set #
6
M #
:
M # and C
6
M C
:
M C then choose a value of
cUM+Kf.
:. Calculate the value of # using e0n.A8B
R =
+
6f
3
C
ffffffffffffffffffff
*. .inally$ because of the e0ual resistor A#
6
M #
:
B and capacitor AC
6
M C
:
B values$ the pass
band volt gain A
.
M + F #
.
5 #
+
of the second order had to be M to +.182. #
.
M 9.182 #
+
.
<ence choose a value of #
+
UM+99kI and
1. Calculate the value of #
..
First order HP Butterworth filter:
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<igh pass filters are often formed simply by interchanging fre0uency-determining
resistors and capacitors in low-pass filters.
Ai.eB order <P. is formed from a order LP. by interchanging components # @ C.
-imilarly order <P. is formed from a order LP. by interchanging # @ C.
order <P.
<ere order <P. with a low cut off fre0uency of f
L.
This is the fre0uency at which the
magnitude of the gain is 9.)9) times its passband value.
<ere all the fre0uencies higher than f
L
are passband fre0uencies.
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.or the first order high pass filter$ the output voltage is$

V
9
= + +
R
F
R
h
ffffffff
f g
+6fRC
+ + +6fRC
fffffffffffffffffffffffffff
Vin
V
9
Vin
ffffffff
= A
F
+
f
f
%
ffffffff
f g
+ + +
f
f
%
ffffffff
f g
fffffffffffffffffffffffff
H
L
L
L
L
L
L
J
I
M
M
M
M
M
M
K
@@@@@+
` a
V
+
=
R
R@+,
C
ffffffffffffffffffffff
Vin
=
R
R +
+
+
ffff
6f
C
fffffffffffffffffffffffffffff
Vin
V
+
=
RAVin A+ 6fRC
+6fRC + +
fffffffffffffffffffffffffffffffffffffffff
V
9
= A
F
AV
+
A
F
= + +
R
F
R
+
ffffffff
where A
F
= + +
R
F
R
+
ffffffff
= 'assband gain of the filter
f = fre"uenc&& of the in'ut signal 35
` a
f
%
=
+
6RC
fffffffffffffff
= low cut off Fre"uenc& 35
` a
3ence the agnitude of the voltage gaiin is ,
V
9
Vin
ffffffff
L
L
L
L
L
M
M
M
M
M
=
A
F
f
f
%
ffffffff
f g
+ +
f
f
%
ffffffff
f g
6
v
u
u
u
t
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww
ffffffffffffffffffffffffffffff
@@@@@@6
` a

Note: Design and .re0uency scaling procedure of the LP. are also applicable to the <P..
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Second order High Pass Butterworth FilterE
order .ilter$ order <P. can be formed from a order LP. by interchanging the
fre0uency ! determine resistors and capacitors.
order <P.
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The %olt gain magnitude e0n of the order <P. is as follows$
V
9
Vin
ffffffff
L
L
L
L
L
M
M
M
M
M
=
A
F
+ +
f
%
f
ffffffff
f g
*
v
u
u
u
t
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww
ffffffffffffffffffffffffffffff
@@@@@+
` a
A
F
= +.182 'assband gain for the II order 3)F
f = fre"uenc& of the in'ut signal 35
` a
f
%
= low cut off fre"uenc& 35
` a
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UNIT III ANALOG MULTIPLIER AND PLL
Analog Multipliers:
A multiple produces an output %
9
$ which is proportional to the product of two inputs %
7
and %
y.
That is$ %
9
M 3%
7
%
y
where 3 is the scaling factor that is usually maintained as A+5+9B %
-+
. There
are various methods available for performing analog multiplication. .our of such techni0ues$
namely$
+. Logarithmic summing techni0ue
6. Pulse height5width modulation Techni0ue
:. %ariable trans conductance Techni0ue
*. "ultiplication using (ilbert cell and
1. "ultiplication using variable trans conductance techni0ue.
An actual multiplier has its output voltage %
9
defined by

V
9
=
V
(
+
(
b c
V
&
+
&
b c
+9 + +
` a
ffffffffffffffffffffffffffffffffffffffffffffff
+
9

where m
7
and m
y
are the offsets associated with signals %
7
and %
y$
n is the error signal associated
with 3 and m
9
is the offset voltage of the multiplier output.
The commonly used terminologies associated voltage of the multiplier characteristicsE
Accuracy:
This specifies the derivation of the actual output from the ideal output$ for any combination of ^
and o inputs falling within the permissible operating range of the multiplier.
Linearity:
This defines the accuracy of the multiplier. The figure shows the response of the output as a
function of one input voltage %
7
when the other %
y
is assumed constant. t represents the ma7imum
percentage derivation from the ideal straight line output. An error surface is formed by plotting the
output for different combinations of ^ and o inputs. The Linearity /rror can be defined as the
ma7imum absolute derivation of the error surface. This linearity error imposes a lower limit on the
multiplier accuracy.
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Squaring Mode Accuracy:
The -0uare ! law curve is obtained with both the ^ and o inputs connected together and applied
with the same input signal. The ma7imum derivation of the output voltage from an ideal s0uare !
law curve e7presses the s0uaring mode accuracy.
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Bandwidth:
The &andwidth indicates the operating capability of an analog multiplier at higher fre0uency
values. -mall signal : d& bandwidth defines the fre0uency f
9
at which the output reduces by :d&
from its low fre0uency value for a constant input voltage. This is identified individually for the ^
and o input channels normally.
The transconductance bandwidth represents the fre0uency at which the transconductance of the
multiplier drops by :d& of its low fre0uency value. This characteristics defines the application
fre0uency ranges when used for phase detection or A" detection.
Quadrant:
The 0uadrant defines the applicability of the circuit for bipolar signals at its inputs. .irst ! 0uadrant
device accepts only positive input signals$ the two 0uadrant device accepts one bipolar signal and
one unipolar signal and the four 0uadrant device accepts two bipolar signals.
Logarithmic summing Technique:
This techni0ue uses the relationship
ln%
7
F ln%
y
MlnA%
7
%
y
B
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As shown in figure the input voltages %
7
and %
y
are converted to their logarithmic e0uivalent$
which are then added together by a summer. An antilogarithmic converter produces the output
voltage of the summer. The output is given by$
%
4
M ln
-+
AlnA%
7
%
y
BB M %
7
%
y
The e7ponential relationship between the collector current and base to
emitter voltage of bipolar transistor during its active mode of operation could be e7plained for the
logarithmic and anti-logarithmic conversions. The relationship between
9
and %
&/
of the transistor
is given by

C
M
9
e
A%&/ 5%T B
t is found that the transistor follows the relationship very accurately in the range of
+9nA to +99mA. Logarithmic multiplier has low accuracy and high temperature instability. This
method is applicable only to positive values of %
7
and %
y.
Therefore$ this type of multiplier is
restricted to one 0uadrant operation only.
Pulse Height/ Width Modulation Technique:
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n this method$ the pulse width of a pulse train is made proportional to one input voltage and the
pulse amplitude is made proportional to the second input voltage. Therefore$ %
7
M3
7
A$ %
y
M3
y
t$
and %
4
M3
4
T where 3
7
$ 3
y
$ 3
4
are scaling factors. n figure A is the amplitude of the pulse$ t is the
pulse width and T is the area of the pulse. Therefore$

V
5
= /
5
T = /
5
At =
V
(
V
&
/
(
/
&
ffffffffffffffff

The modulated pulse train is passed through an integrated circuit. Therefore$ the input of the
integrator is proportional to the area of pulse$ which in turn is proportional to the product of two
input voltages.
A simple multiplier using an Emitter coupled Transistor pair:
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A circuit using an emitter coupled pair is shown in figure. The output currents
C+
and
C6
are
related to the differential input voltage %
+
by
I
C+
=
I
EE
+ + e
@
V
+
V
T
fffffffffff
ffffffffffffffffffff
and I
C6
=
I
EE
+ + e
V
+
V
T
fffffffffff
ffffffffffffffff
where %
T
is the
thermal voltage and the base currents have been neglected. Combining above e0n$ we have the
difference between the two output currents as

I
C
= I
C+
@I
C6
= I
EE
+
+ + e
@
V
+
V
T
fffffffffff
ffffffffffffffffffff
@
+
+ + e
V
+
V
T
fffffffffff
ffffffffffffffff
h
j
i
k
= I
EE
tanh
V
+
6V
T
ffffffffff
f g

The dc transfer characteristics of the emitter ! coupled pair is shown in figure. t shows that the
emitter coupled pair can be used as a simple multiplier using this configuration. >hen the
differential input voltage %
+
UU %
T$
we can appropriate as given by

I
EE
tanh
V
+
6V
T
ffffffffff
= I
EE
V
+
6V
T
ffffffffff
A
Then it becoes,
I
C
= I
EE
V
+
6V
T
ffffffffff
f g
---- AJB
The current
//
is the bias current for the emitter ! coupled pair. f the current
//
is made
proportional to a second input signal %
6
$ then
I
EE
= /
9
V
6
@V
BE on
` a
b c

-ubstituting above e0n in AJB$ we get
I
C
=
/
9
V
+
V
6
@V
BE on
` a
b c
6V
T
ffffffffffffffffffffffffffffffffffffffffffffffffff
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This arrangement is shown in figure. t is a simple modulator circuit constructed using a
differential amplifier. t can be used as a multiplier$ provided %
+
is small and much less than
19m%$ and %
6
is greater than %
&/AonB
. &ut$ the multiplier circuit shown in figure has several
limitations. The first limitation is that %
6
is offset by %
&/AonB.
The second is that %
6
must always be
positive which results in only a two-0uadrant multiplier operation. The third limitation is that$ the
tanh A^B is appro7imately as ^$ where ^ M %
+
56%
T .
The first two limitations are overcome in the
(ilbert cell.
Gilbert Multiplier cell:
The (ilbert multiplier cell is a modification of the emitter coupled cell and this allows four !
0uadrant multiplication. Therefore$ it forms the basis of most of the integrated circuit balanced
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multipliers. Two cross- coupled emitter- coupled pairs in series connection with an emitter coupled
pair form the structure of the (ilbert multiplier cell. The operation of the (ilbert cell is shown in
figure.
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The collector current of #
:
and #
*
are given b&
I
C:
=
I
C+
+ + e
@
V
+
V
T
fffffffffff
ffffffffffffffffffff
and I
C*
=
I
C+
+ + e
V
+
V
T
fffffffffff
ffffffffffffffff
Siilarl&,The collector current of #
1
and #
2
are given b&
I
C1
=
I
C6
+ + e
V
+
V
T
fffffffffff
ffffffffffffffff
and I
C2
=
I
C6
+ + e
@
V
+
V
T
fffffffffff
ffffffffffffffffffff
The collector current I
C+
and I
C6
of transistors #
+
and #
6
can be e('ressed as
I
C+
=
I
EE
+ + e
@
V
6
V
T
fffffffffff
ffffffffffffffffffff
and I
C6
=
I
EE
+ + e
V
6
V
T
fffffffffff
ffffffffffffffff
Substituting the above e"uation in I
C:
and I
C*
, we get
I
C:
=
I
EE
+ + e
@
V
+
V
T
fffffffffff
' (
+ + e
@
V
6
V
T
fffffffffff
' (
fffffffffffffffffffffffffffffffffffffffffffffff
and I
C*
=
I
EE
+ + e
V
+
V
T
fffffffffff
' (
+ + e
@
V
6
V
T
fffffffffff
' (
ffffffffffffffffffffffffffffffffffffffffffff
Siilarl& substituting I
c6
in I
c1
and I
C2
, we get,
I
C1
=
I
EE
+ + e
V
+
V
T
fffffffffff
' (
+ + e
@
V
6
V
T
fffffffffff
' (
ffffffffffffffffffffffffffffffffffffffffffff
and
I
C2
=
I
EE
+ + e
@
V
+
V
T
fffffffffff
' (
+ + e
V
6
V
T
fffffffffff
' (
ffffffffffffffffffffffffffffffffffffffffffff
The differential out'ut current I is given b&
I = I
%+
@I
%6
That is,

I = I
C:
+ I
C1
b c
@ I
C*
+ I
C2
b c
orI = I
C:
@I
C2
b c
@ I
C*
@I
C1
b c
Substituting I
C:
to I
C2
in above e"n and e'lo&ing
e('onential forulae for h&'errbolic function, we get
I = I
EE
tanh
V
+
6V
T
ffffffffff
f g
tanh
V
6
6V
T
ffffffffff
f g
H
J
I
K

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I = I
C:
+ I
C1
b c
@ I
C*
+ I
C2
b c
orI = I
C:
@I
C2
b c
@ I
C*
@I
C1
b c
Substituting I
C:
to I
C2
in above e"n and e'lo&ing
e('onential forulae for h&'errbolic function, we get
I = I
EE
tanh
V
+
6V
T
ffffffffff
f g
tanh
V
6
6V
T
ffffffffff
f g
H
J
I
K

The above e0uation shows that when %
+
and %
6
are small$ the (ilbert Cell shown in figure can be
used as a four 0uadrant analog multiplier with the use of current to voltage converters. The dc
transfer characteristic of such a multiplier circuit is the product of the hyperbolic tangent of the
two input voltages. The output voltage %
9
can be generated from g$ by using two e0ual valued
resistors connected to %cc and by sending
L+
AM
C:
F
C1
B through one resistor and
L6
AM
C*
F
C2
B
through the second resistor.
A modulator or a mi7er is a circuit with two inputs$ namely$ carrier input and modulating
input and one modulated output. A linear response is re0uired only for the modulating input$ since
the carrier is usually an ac signal with constant amplitude.
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The multiplier shown in figure can also used as a modulator$ if one of the inputs is very
large and the second input is very small AtanhA^B M ^B. Then$ the transistors operated by the large-
signal input act as switches. This effectively multiplies the small input signal by a s0uare wave.
<ence$ this mode of operation acts as a modulator. These are called synchronous modulators and
they find applications in signal processing$ demodulation and phase detection.
Gilbert multiplier with pre distortion circuits:
>hen the magnitudes of %
+
and %
6
are very small when compared with %
T$
the hyperbolic tan
function is appro7imated as linear$ and the circuit can be used as a multiplier$ for finding the
product of %
+
and %
6.
&ut$ when larger %
+
and %
6
are to be multiplied$ a nonlinearity function can be
used to pre distort the input signals. This compensates for the hyperbolic tangent transfer
characteristic of the basic cell. The re0uired nonlinearity function is an inverse hyperbolic tangent
characteristic whose arrangement is shown in figure.
The generation of the inverse hyperbolic tangent function is shown in figure. Assume that the
circuit within the bo7 generates a differential output current$ and it linearly depends on the input
voltage %
+
.
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Then $
/+
M
9+
F 3
+
%
+
and
/6
M
9+
F 3
+
%
+
>here
9+
is the dc current flowing in each output$ 3
+
is the transconductance of the voltage ! to
current converter$ and it is assumed that %
+
M 9. The differential voltage g% across the diode !
connected transistors L
)
and L
8
is given by
V =V
T
ln
I
9+
+ /
+
V
+
I
9
ffffffffffffffffffffffffff
f g
@V
T
ln
I
9+
@/
+
V
+
I
9
fffffffffffffffffffffffffff
f g
=V
T
ln
I
9+
+ /
+
V
+
I
9+
@/
+
V
+
fffffffffffffffffffffffffff
f g

This can be transformed into V = 6V
T
tanh
@+
/
+
V
+
I
9+
ffffffffffffff
f g
Dsing the identity
tanh
@+
,
` a
=
+
6
fff
ln
+ + ,
+@,
fffffffffffffff
f g

>hen this functional block is used$ it compensates for the nonlinearity of the inputs. Then $
I = I
EE
/
+
V
+
I
9+
ffffffffffffff
f g
/
6
V
6
I
96
fffffffffffffff
f g

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where
9+$
3
+
and
96
$ 3
6
are the parameters of the functional blocks following inputs %
+
and %
6
respectively. The above e0uation shows that the differential output current is proportional to the
product %
+
%
6
.
Complete four ! Luadrant analog multiplierE
The above figure illustrates the circuit diagram of the complete four ! 0uadrant analog multiplier
using (ilbert Cell. The three bo7es are voltage to current converters or current to voltages
converters in effect. The pre- distortion for the input signal is achieved by transistors L
)
and L
8
.
The currents
?
and
+9
passing through the emitters of L
)
and L
8
generate a voltage between the two
emitter terminals$ that is proportional to the inverse hyperbolic tangent of %
+
.
Analysis of the circuit:
A complete four 0uadrant analog multiplier using (ilbert cell is shown in figure. The current
through base ! emitter ;unctions of transistors L
)
$ L
:
$ L
*
$ L
8
connected in series can be e7pressed
by

:
M
*

+9
---A+B
-imilarly$ from the series connections of the transistors L
)
$ L
2
$ L
1
and L
8
we get
?

2
M
1

+9
---A6B

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.rom figure$ we see that$

+
M
:
F
*
--A:B

6
M
1
F
2
--A*B

L+
M
:
F
1
--A1B

L6
M
*
F
2
---A2B

^^
M
?
F
+9
---A)B
The transfer characteristics of the differential voltage to current converter is given by

?
!
+9
M %
+
53
+
---A8B

+
!
6
M %
6
53
6
---A?B
and the transfer characteristics of the differential to single ended current is given by
%
9
M 3
9
A
L6
!
L+
B ---A+9B
>here 3
9
$ 3
+
$ and 3
6
are constants.
-ubstituting for
L+
and
L6
from A1B and A2B in A+9B $ we get
%
9
M 3
9
SA
*
F
2
B ! A
:
F
1
BT
Dsing A+B and A6B $
V
9
= /
9
I
*
+ I
1
I
+9
I
?
fffffff
f g
@ I
*
I
+9
I
?
fffffff
+ I
1
f g
H
J
I
K
@@@++
` a

-implifying the above e0n$ we get
V
9
= /
9
I
?
@I
+9
I
?
ffffffffffffffffff
f g
I
*
@I
1
b c
@@@+6
` a

.rom figure$ we see that

I
+
@I
6
= I
:
+ I
*
b c
@ I
1
+ I
2
b c
= I
*
I
+9
I
?
fffffff
+ I
*
f g
@ I
1
+ I
1
I
+9
I
?
fffffff
f g
@@@+:
` a

-olving for A
*
!
1
B gives
I
*
@I
1
b c
=
I
?
I
?
+ I
+9
ffffffffffffffffff
f g
I
+
@I
6
b c
@@@+*
` a

-ubstituting A+*B in A+6B using A8B and A?B $ we get
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V
9
= /
9
I
?
@I
+9
I
?
+ I
+9
ffffffffffffffffff
f g
I
+
@I
6
b c
=
/
9
V
+
V
6
I
,,
/
+
/
6
fffffffffffffffffffffffff
= /

V
+
V
6
@@@+1
` a

>here

/

=
/
9
I
,,
/
+
/
6
fffffffffffffffffffffffff

/0n A+1B employs no appro7imations. <ence the input signal amplitudes have no constraints.
Practical implementation of the four quadrant analog multiplier:
A practical four !0uadrant analog multiplier circuit is shown in figure. t can be observed that$

I
+
@I
6
=
6V
6
R
1
ffffffffff
@@@@+2
` a
I
?
@I
+9
=
6V
+
R
,
fffffffff
@@@@@+)
` a

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further it is assumed that the drop across base-emitter of L
?
!L
+9
and L
+
! L
6
are small in
comparison with the drop across #
^
and #
o
.
-ubstituting /0n +2 and +) in e0n +1 we get$

V
9
=
* /
9
R
C
V
+
V
6
I
,,
R
,
R
1
ffffffffffffffffffffffffffffffffff
= /

V
+
V
6
where R PP R
C

The circuit is capable of performing precise multiplication of a continuously varying analog signal
by another signal. ,ne of the problems though$ is need to be able to trim the errors due to offsets
and mismatches in the integrated circuit implementation.
Variable Transconductance Technique:
The variable transconductance techni0ue makes use of the dependence characteristic of the
transistor transconductance parameter on the emitter current bias applied. A simple differential
circuit arrangement depicting the principle is shown in figure. The relationship between %
9
and %
7
is given by
%
9
M g
m
#
L
%
^
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>here g
m
M
//
5%
T
is the transconductance of the stage. Application of a second input %
y
to the
reference current source of the differential amplifier can vary g
m
.
Thus$ if #
/

//
PP %
&/
$ the bias voltage %
y
is related to
//
by the relation %
y
M
//
#
/
. Then$ the
overall voltage transfer e7pression is given by
%
9
M g
m
#
L
%
7
M A%
y
5%
T
#
/
B%
7
#
L
M %
7
%
y
#
L
-----
%
T
#
/
Generation of logarithmic bias input for differential stage:
t is assumed that Y%
7
Y UU %
T
and there is no emitter degeneration. #eferring to below figure$ the
collector currents
+
and
6
are related to the applied voltage %
7
by the relation

I
1
I
2
fffff
=e
V
X
V
y
fffffffffff
---A+B
Therefore$ linearity can be achieved by reducing the e7ponential current ! voltage characteristic to
a linear one as shown in figure. The transistor L
+
and L
6
are biased through the diode connected L
A
and L
&$
which are driven by controlled current sources
A
and
&
respectively. Then the net bias
voltage %
7
is represented by
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V
x
= V
T
ln
I
B
I
A
ffffff
f g
@@@2
` a
Substituting eqn 2
` a
in 1
` a
we get
I
1
I
2
fffff
=
I
B
I
A
ffffff
Similarly,
I
A
I
A
+ A
B
fffffffffffffffffff
=
I
2
I
1
+ I
2
fffffffffffffff
=
1
1 +e
V
x
V
T
fffffffffffff
fffffffffffffffff
@@@3
` a
and
I
B
I
A
+ I
B
fffffffffffffffff
=
I
1
I
1
+ I
2
fffffffffffffff
=
e
V
x
V
T
fffffffffffff
1 +e
V
x
V
T
fffffffffffff
fffffffffffffffff
@@@@4
` a

The above e0uations are valid over a wider range$ if the device characteristics are well matched
and %
&/
obeys the basic diode e0uation.
Four Quadrant Variable transconductance multiplier:
A typical four 0uadrant multiplier circuit is shown below. The four 0uadrant operation indicates
that the output voltage is directly proportional to the product of the two input voltages regardless
of the polarity of the inputs and such multipliers can be operated in all the four 0uadrants of
operation.
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The first part of the circuit generates an intermediate voltage %
+
across the transistors L
A
and L
&
in
response to the input signal %
7
. The nonlinear response to the input %
7
in generating %
+
is
compensated by the inverse nonlinearity associated with the base ! emitter ;unctions of the 0uad-
transistors L
1
! L
2
and L
)
! L
8
. Thus the output voltage %
4
is maintained proportional to the linear
product of the two voltages. The emitter degeneration resistors #
7
and #
y
provide linear conversion
of the input voltages to differential currents
7
and
y.
Thus
^
M %
7
5#
7
and
y
M %
y
5#
y
. The value of
#
7
and #
y
are chosen such that #
7
PP %
T
5
+
and #
y
PP %
T
5
6
respectively.
The output voltage %
9
can be written as
%
9
M #
L
AA
2
F
)
B ! A
1
F
8
B ---A1B
Applying e0n : and * to the circuit$ we obtain
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I
2
I
:
+ I
&
ffffffffffffffff
=
I
1
I
:
@I
&
fffffffffffffffff
=
I
+
+ I
(
6I
+
fffffffffffffff
and
I
8
I
:
+ I
&
ffffffffffffffff
=
I
)
I
:
@I
&
fffffffffffffffff
=
I
+
@I
(
6I
+
ffffffffffffffff
Sub e"n 2 and ) into 1 we get,
V
9
=
6R
%
I
+
ffffffffff
I
(
I
&
b c
Since I
(
and I
&
are linearl& related toV
(
andV
&
res'ectivel& we have
V
9
= /V
(
V
&
where the scaling factor / =
6R
%
IR
(
R
&
ffffffffffffffff
, which is norall& chosen as 9.+

Analog Multiplier ICs
Analog multiplier is a circuit whose output voltage at any instant is proportional to the product of
instantaneous value of two individual input voltages. The important applications of these
multipliers are multiplication$ division$ s0uaring and s0uare ! rooting of signals$ modulation and
demodulation. These analog multipliers are available as integrated circuits consisting of op-amps
and other circuit elements. The -chematic of a typical analog multiplier$ namely$ AD2:: is shown
in figure.
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The AD2:: multiplier is a four ! 0uadrant analog multiplier. t possesses high input impedance$
and this characteristic makes the loading effect on the signal source negligible. t can operate with
supply voltages ranging from Z+8%. The C does not re0uire e7ternal components. The calibration
by user is not necessary. The typical range of the two input signals is Z+9%.
-chematic representation of a multiplierE
The schematic representation of an analog multiplier is shown in figure. The output %
9
is the
product of the two inputs %
7
and %
y
is divided by a reference voltage %ref. =ormally$ the reference
voltage %ref is internally set to +9%. Therefore$ %
9
M%7%y5+9. n other words$ the basic input !
output relationship can be defined by 3%
7
%
y
when 3 M +5+9$ a constant. Thus for peak input
voltages of +9%$ the peak magnitude of output voltage is +5+9 J+9 J+9 M+9%. Thus$ it can be noted
that$ as long as %
7
U +9% and %
y
U +9%$ the multiplier output will not saturate.
Multiplier quadrants:
The transfer characteristics of a typical four-0uadrant multiplier is shown in figure. &oth the inputs
can be positive or negative to obtain the corresponding output as shown in the transfer
characteristics.
Applications of Multiplier ICs:
The multiplier Cs are used for the following purposesE
+. %oltage -0uarer
6. .re0uency doubler
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:. %oltage divider
*. -0uare rooter
1. Phase angle detector
2. #ectifier
Voltage Squarer:
.igure shows the multiplier C connected as a s0uaring circuit. The inputs can be positive or
negative$ represented by any corresponding voltage level between 9 and +9%. The input voltage %
i
to be s0uared is simply connected to both the input terminals$ and hence we have$ %
7
M %
y
M %
i
and
the output is %
9
M 3v
6
i
. The circuit thus performs the s0uaring operation. This application can be
e7tended for fre0uency doubling applications.
Frequency doubler:
.igure shows the s0uaring circuit connected for fre0uency doubling operation. A sine-wave signal
%
i
has a peak amplitude of A
v
and fre0uency of f<4. Then$ the output voltage of the doubler circuit
is given by

V
9
=
A
v
sin6ft B A
v
sin6ft
+9
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
=
A
v
6
+9
ffffffff
sin
6
6ft
b c
=
A
v
6
69
ffffffff
+ @cos *ft
b c

Assuming a peak amplitude A
v
of 1% and fre0uency f of +93<4$ %
9
M+.61 ! +.61 cos6aA69999Bt.
The first term represents the dc term of +.61% peak amplitude. The input and output waveforms
are shown in figure. The output waveforms ripples with twice the input fre0uency in the rectified
output of the input signal. This forms the principle of application of analog multiplier as rectifier of
ac signals. The dc component of output %
9
can be removed by connecting a +i. coupling capacitor
between the output terminal and a load resistor$ across which the output can be observed.
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Voltage Divider:
The voltage divider circuit can be constructed using a multiplier and an op-amp as shown in figure.
This circuit produces the ratio of two input signals. The division is achieved by connecting the
multiplier in the feedback loop of an op-amp. The voltages %
den
and %
num
represent the two input
voltages$ %
dm
forms one input of the multiplier$ and output of op-amp %
oA
forms the second input.
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The output %
,A
forms the second input. The output %
,"
of the multiplier is connected back of op-
amp in the feedback loop. Then the characteristic operation of the multiplier gives
%
om
M 3%
,A
%
dm
---A+B
As shown in figure$ no input signal current can flow into the inverting input terminal of op-amp$
which is at virtual ground. Therefore$ at the ;unction a$ i
+
Fi
6
M9$ The current i
+
M %
num
5 #$ where #
is the input resistance and the current i
6
M %
om
5#. >ith virtual ground e7isting at a$

i
+
+ i
6
=
V
nu
R
ffffffffffffff
+
V
o
R
ffffffffffff
= 9,
V
o
=@V
nu
Sub +
` a
in above e"n
/V
OA
V
den
=@V
nu
or
V
OA
=@
V
nu
/V
den
fffffffffffffffffff

>here %
num
and %
den
are the numerator and denominator voltages respectively. Therefore$ the
voltage division operation is achieved. %
num
can be a positive or negative voltage and %
dm
can have
only positive values to ensure negative feedback. >hen %
dm
is changed$ the gain +95%
dm
changes$
and this feature is used in automatic gain control AA(CB circuits.
Square Rooter:
The divider voltage an %
dm
can be used to find the s0uare root of a signal by connecting both inputs
of the multiplier to the output of the op-amp. Then$ the output voltage of the multiplier %
,"
is
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e0ual in magnitude but opposite in polarity Awith respect to groundB to %i. &ut we know that %
om
is
one- term A-cale factorB of %
9
J %
9
or
-%
i
M %
om
M %
6
9
-olving for %
9
and eliminating p-+ yields.
%
9
M p+9Y%
i
Y
/0n states that %
9
e0uals the s0uare root of +9 times the absolute magnitude of %
i
. The input
voltage %
i
must be negative$ or else$ the op-amp saturates. The range of %
i
is between -+ and -+9%.
%oltages less than -+% will cause inaccuracies in the result. The diode prevents negative saturation
for positive polarity %
i
signals. .or positive values of %
i
the diode connections are reversed.
Phase Angle detector:
The multiplier configured for phase angle detection measurement is shown in figure. >hen two
sine-waves of the same fre0uency are applied to the inputs of the multiplier$ the output %
9
has a dc
component and an ac component.
The trigonometric identity shows that
-in A sin & M+56 AcosAA-&B ! cosAAF&BB.
>hen the two fre0uencies are e0ual$ but with different phase angles$ e.g. AM6Wft Ff for signal %
7
amd &M 6Wft for signal %
y$
$ then using the identity

sin 6ft +
b c
' (
sin6ft
b c
' (
=
+
6
fff
cos @cos *ft +
b c
' (
=
+
6
fff
dc the double fre"uenc& ter
b

Therefore$ when the two input signals %
7
and %
y
are applied to the multiplier$ %
9AdcB
is given by
V
9 dc
` a
=
V
('
V
&'
69
ffffffffffffffffff
cos
` a

where %
7p
and %
yp
are the peak voltage amplitudes of the signals %
7
and %
y
. Thus$ the output %
9AdcB
depends on the factor cos f. A dc voltmeter can be calibrated as a phase angle meter when the
product of %
7p
and %
yp
is made e0ual to 69. Then$ a A9-+B % range dc voltmeter can directly read
cos f$ with the meter calibrated directly in degrees from a cosine table. The input and output
waveforms are shown in figure.
Then the above e0n becomes %
9AdcB
M cos f$ if we make the product %
7p
%
yp
M 69 or in other words$
%
7p
! %
yp
M *.*)%
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PHASE LOCKED LOOP:
&asic &lock Diagram of a PLL
.orward path
f
=
f
,DT
nput
fre0uency
.eedback path
phase locked loop construction and operation:
The PLL consists of iB Phase detector iiB LP. iiiB %C,. The phase detector or comparator
compares the input fre0uency f
=
with feedback fre0uency f
,DT.
The output of the phase detector is proportional to the phase difference between f
=
@ f
,DT.
The
output of the phase detector is a dc voltage @ therefore is often referred to as the error voltage.
The output of the phase detector is then applied to the LP.$ which removes the high fre0uency
noise and produces a dc level. This dc level in turn$ is input to the %C,.
The output fre0uency of %C, is directly proportional to the dc level. The %C, fre0uency is
compared with input fre0uency and ad;usted until it is e0ual to the input fre0uencies.
PLL goes through : states$ iB free running iiB Capture iiiB Phase lock.
&efore the input is applied$ the PLL is in free running state. ,nce the input fre0uency is applied
the %C, fre0uency starts to change and PLL is said to be in the capture mode. The %C,
fre0uency continuous to change until it e0uals the input fre0uency and the PLL is in phase lock
mode. >hen Phase locked$ the loop tracks any change in the input fre0uency through its repetitive
action. f an input signal v
s
of fre0uency f
s
is applied to the PLL$ the phase detector compares the
phase and fre0uency of the incoming signal to that of the output v
o
of the %C,. f the two signals
differ in fre0uency of the incoming signal to that of the output v
o
of the %C,. f the two signals
differ in fre0uency and5or phase$ an error voltage v
e
is generated.
Phase
Detector
Low Pass
Filter
Voltage
Controlled
Oscillator
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The phase detector is basically a multiplier and produces the sum Af
s
F f
o
B and difference Af
s
- f
o
B
components at its output. The high fre0uency component Af
s
F f
o
B is removed by the low pass filter
and the difference fre0uency component is amplified then applied as control voltage v
c
to %C,.
The signal v
c
shifts the %C, fre0uency in a direction to reduce the fre0uency difference between f
s
and f
o
. ,nce this action starts$ we say that the signal is in the capture range. The %C, continues to
change fre0uency till its output fre0uency is e7actly the same as the input signal fre0uency. The
circuit is then said to be locked. ,nce locked$ the output fre0uency f
o
of %C, is identical to f
s
e7cept for a finite phase difference m. This phase difference m generates a corrective control
voltage v
c
to shift the %C, fre0uency from f
9
to f
s
and thereby maintain the lock. ,nce locked$
PLL tracks the fre0uency changes of the input signal. Thus$ a PLL goes through three stages AiB
free running$ AiiB capture and AiiiB locked or tracking.
Capture rangeE the range of fre0uencies over which the PLL can ac0uire lock with an input signal
is called the capture range. This parameter is also e7pressed as percentage of f
o
.
Pull-in timeE the total time taken by the PLL to establish lock is called pull-in time. This depends
on the initial phase and fre0uency difference between the two signals as well as on the overall loop
gain and loop filter characteristics.
(a) Phase DetectorE
Phase detector compares the input fre0uency and %C, fre0uency and generates DC voltage
i.e.$ proportional to the phase difference between the two fre0uencies. Depending on whether the
analog5digital phase detector is used$ the PLL is called either an analog5digital type respectively.
/ven though most monolithic PLL integrated circuits use analog phase detectors.
/7 for AnalogE Double-balanced mi7er
/7 for DigitalE /7-,#$ /dge trigger$ monolithic Phase detector.
/7-,# Phase DetectorE
This uses an e7clusive ,# gate. The output of the /7-,# gate is high only when f
=
or f
,DT
is high.
The DC output voltage of the /7-,# phase detector is a function of the phase difference between
its two outputs. The ma7imum dc output voltage occurs when the phase difference is a radians or
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+89 degrees. The slope of the curve between 9 or a radians is the conversion gain k
p
of the phase
detector for ege if the /7-,# gate uses a supply voltage %cc M 1%$ the conversion gain 3
p
is
3
P
M

V 1
M +.1?% 5 #AD
/dge Triggered Phase DetectorE
Advantages of /dge Triggered Phase Detector over /7-,# are
iB The dc output voltage is linear over 6a radians or :29 degrees$ but in /7-,# it is a radians or
+89 degrees.
iiB &etter Capture$ tracking @ locking characteristics.
/dge triggered type of phase detector using #- .lip ! .lop. t is formed from a pair of cross
coupled =,# gates.
#- .. is triggered$ i.e$ the output of the detector changes its logic state on the positive edge of the
inputs f
=
@ f
,DT
"onolithic Phase detectorE
t consists of 6 digital phase detector$ a charge pump and an amplifier.
Phase detector + is used in applications that re0uire 4ero fre0uency and phase difference at
lock.
Phase detector 6$ if 0uadrature lock is desired$ when detector + is used in the main loop$
detector can also be used to indicate whether the main loop is in lock or out of lock.
# #eference
% %ariable or 9feedback input
PD Pump Dp signal
PDPump Down signal
D. Dp fre0uency output signal
D. Down fre0uency output signal
(b) Low Pass filter:
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The function of the LP. is to remove the high fre0uency components in the output of the
phase detector and to remove the high fre0uency noise. LP. controls the characteristics of the
phase locked loop. i.e$ capture range$ lock ranges$ bandwidth
Lock rangeATracking rangeBE
The lock range is defined as the range of fre0uencies over which the PLL system follows
the changes in the input fre0uency f
=
.
Capture rangeE
Capture range is the fre0uency range in which the PLL ac0uires phase lock. Capture
range is always smaller than the lock range.
.ilter &andwidthE
.ilter &andwidth is reduced$ its response time increases. <owever reduced &andwidth
reduces the capture range of the PLL. #educed &andwidth helps to keep the loop in lock
through momentary losses of signal and also minimi4es noise.
(c) Voltage Controlled Oscillator (VCO):
The third section of PLL is the %C,e it generates an output fre0uency that is directly
proportional to its input voltage. The ma7imum output fre0uency of =/5-/ 122 is 199 3h4.
f
=
f
,DT
nput
fre0uency
Feedback path and optional divider:
"ost PLLs also include a divider between the oscillator and the feedback input to the phase
detector to produce a fre0uency synthesi4er. A programmable divider is particularly useful in radio
Voltage
Controlled
Oscillator
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transmitter applications$ since a large number of transmit fre0uencies can be produced from a
single stable$ accurate$ but e7pensive$ 0uart4 crystal!controlled reference oscillator.
-ome PLLs also include a divider between the reference clock and the reference input to the phase
detector. f this divider divides by .$ it allows the %C, to multiply the reference fre0uency by
* 5 .. t might seem simpler to ;ust feed the PLL a lower fre0uency$ but in some cases the
reference fre0uency may be constrained by other issues$ and then the reference divider is useful.
.re0uency multiplication in a sense can also be attained by locking the PLL to the q=qth harmonic
of the signal.
Equations:
The e0uations governing a phase-locked loop with an analog multiplier as the phase detector may
be derived as follows. Let the input to the phase detector be (
c
AtB and the output of the voltage-
controlled oscillator A%C,B is (
r
AtB with fre0uency r
r
AtB$ then the output of the phase detector
(

AtB is given by
the %C, fre0uency may be written as a function of the %C, input &AtB as
where g
v
is the sensitivit& of the %C, and is e7pressed in <4 5 %.
<ence the %C, output takes the form
where
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The loop filter receives this signal as input and produces an output
(
f
AtB M F
filter
A(

AtBB
where F
.ilter
is the operator representing the loop filter transformation.
>hen the loop is closed$ the output from the loop filter becomes the input to the %C, thus
&AtB M (
f
AtB M F
filter
A(

AtBB
>e can deduce how the PLL reacts to a sinusoidal input signalE
(
c
AtB M A
c
sinAr
c
tB.
The output of the phase detector then isE
This can be rewritten into sum and difference components using trigonometric identitiesE
As an appro7imation to the behaviour of the loop filter we may consider only the difference
fre0uency being passed with no phase change$ which enables us to derive a small-signal model of
the phase-locked loop. f we can make $ then the can be appro7imated by its
argument resulting inE . The phase-locked loop is said to be
loc0ed if this is the case.
CONTROL SYSTEM ANALYSIS/ CLOSED LOOP ANALYSIS OF PLL
Phase locked loops can also be analy4ed as control systems by applying the Laplace transform.
The loop response can be written asE
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>here
f
o
is the output phase in radians
f
i
is the input phase in radians
/
'
is the phase detector gain in volts per radian
/
v
is the %C, gain in radians per volt-second
FAsB is the loop filter transfer function AdimensionlessB
The loop characteristics can be controlled by inserting different types of loop filters. The simplest
filter is a one-pole #C circuit. The loop transfer function in this case isE
The loop response becomesE
This is the form of a classic harmonic oscillator. The denominator can be related to that of a
second order systemE
>here
s is the damping factor
r
n
is the natural fre0uency of the loop
.or the one-pole #C filter$
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The loop natural fre0uency is a measure of the response time of the loop$ and the damping factor is
a measure of the overshoot and ringing. deally$ the natural fre0uency should be high and the
damping factor should be near 9.)9) Acritical dampingB. >ith a single pole filter$ it is not possible
to control the loop fre0uency and damping factor independently. .or the case of critical damping$
A slightly more effective filter$ the lag-lead filter includes one pole and one 4ero. This can be
reali4ed with two resistors and one capacitor. The transfer function for this filter is
This filter has two time constants
t
+
M CAR
+
F R
6
B
t
6
M CR
6

-ubstituting above yields the following natural fre0uency and damping factor
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The loop filter components can be calculated independently for a given natural fre0uency and
damping factor
#eal world loop filter design can be much more comple7 eg using higher order filters to reduce
various types or source of phase noise.
Applications of PLLE
The PLL principle has been used in applications such as ." stereo decoders$ motor speed control$
tracking filters$ ." modulation and demodulation$ .-3 modulation$ .re0uency multiplier$
.re0uency synthesis etc.$
/7ample PLL CsE
129 series A129$ 12+$ 126$ 12*$ 121 @ 12)B
VOLTAGE CONTROLLED OSCILLATOR:
A common type of %C, available in C form is -ignetics =/5-/122. The pin configuration and
basic block diagram of 122 %C, are shown in figures below.
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#eferring to the circuit in the above figure$ the capacitor c
+
is linearly charged or discharged by a
constant current source5sink. The amount of current can be controlled by changing the voltage v
c
applied at the modulating input Apin 1B or by changing the timing resistor #
+
e7ternal to the C
chip. The voltage at pin 2 is held at the same voltage as pin 1. Thus$ if the modulating voltage at
pin 1 is increased$ the voltage at pin 2 also increases$ resulting in less voltage across #
+
and
thereby decreasing the charging current.
The voltage across the capacitor C
+
is applied to the inverting input terminal of -chmitt
trigger via buffer amplifier. The output voltage swing of the -chmitt trigger is designed to %
cc
and
9.1 %
cc
. f #
a
M #
b
in the positive feedback loop$ the voltage at the non-inverting input terminal of
-chmitt trigger swings from 9.1 %
cc
to 9.61 %
cc
. >hen the voltage on the capacitor c
+
e7ceeds 9.1
%
cc
during charging$ the output of the -chmitt trigger goes L,> A9.1 %
cc
B. The capacitor now
discharges and when it is at 9.61 %
cc
$ the output of -chmitt trigger goes <(< A%
cc
B. -ince the
source and sink currents are e0ual$ capacitor charges and discharges for the same amount of time.
This gives a triangular voltage waveform across c
+
which is also available at pin *. The s0uare
wave output of the -chmitt trigger is inverted by buffer amplifier at pin :. The output waveforms
are shown near the pins * and :.
The output fre0uency of the %C, can be given as followsE
where %F is %
cc
.
The output fre0uency of the %C, can be changed either by AiB #
+
$ AiiB c
+
or AiiiB the voltage
v
c
at the modulating input terminal pin 1. The voltage v
c
can be varied by connecting a #
+
#
6
circuit
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as shown in the figure below. The components #
+
and c
+
are first selected so that %C, output
fre0uency lies in the centre of the operating fre0uency range. =ow the modulating input voltage is
usually varied from 9.)1 %
cc
to %
cc
which can produce a fre0uency variation of about +9 to +.
MONOLITHIC PHASE LOCKED LOOPS (PLL IC 565):
Pin Configuration of PLL IC 565:
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Basic Block Diagram Representation of IC 565
The signetics =/5-/ 129 series is monolithic phase locked loops. The -/5=/ 129$ 12+$
126$ 12*$ 121 @ 12) differ mainly in operating fre0uency range$ poser supply re0uirements @
fre0uency @ bandwidth ad;ustment ranges. The important electrical characteristics of the 121 PLL
are$
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,perating fre0uency rangeE 9.99+<4 to 199 3h4.
,perating voltage rangeE Z2 to Z+6v
nput level re0uired for trackingE +9mv rms min to : %pp ma7
nput impedanceE +9 3 ohms typically.
,utput sink currentE +mA
,utput source currentE +9 mA

The center fre0uency of the PLL is determined by the free running fre0uency of the %C,$ which is
given by
f
,DT
M
+ + *
6 . +
C R
<V------------A+B
where #+@C+ are an e7ternal resistor @ a capacitor connected to pins 8 @ ?.
The %C, free-running fre0uency f
,DT
is ad;usted e7ternally with #+ @ C+ to be at the center of
the input fre0uency range.
C+ can be any value$ #+ must have a value between 6 k ohms and 69 3 ohms.
Capacitor C6 connected between ) @ F%.
The filter capacitor C6 should be large enough to eliminate variations in the demodulated
output voltage in order to stabili4e the %C, fre0uency.
The lock range f
L
@ capture range fc of PLL is given by$

f
L
M Z
%
fout 8
<4 ------------------A6B
>here f
,DT
M free running fre0uency of %C, A<4B
% M AF%B-A-%B volts
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f
L
f
C
M ZS -------------------- T
u

--------------A:B
A6aBA:.2BA+9
:
BC
6
The circuit diagram of LM565 PLL
Monolithic PLL IC 565 applicationsE
The output from a PLL system can be obtained either as the voltage signal v
c
AtB corresponding to
the error voltage in the feedback loop$ or as a fre0uency signal at %C, output terminal. The
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voltage output is used in fre0uency discriminator applications whereas the fre0uency output is used
in signal conditioning$ fre0uency synthesis or clock recovery applications.
Consider the case of voltage output. >hen PLL is locked to an input fre0uency$ the error voltage
v
c
AtB is proportional to Af
s
-f
o
B. f the input fre0uency is varied as in the case of ." signal$ v
c
will
also vary in order to maintain the lock. Thus the voltage output serves as a fre0uency discriminator
which converts the input fre0uency changes to voltage changes.
n the case of fre0uency output$ if the input signal is comprised of many fre0uency components
corrupted with noise and other disturbances$ the PLL can be made to lock$ selectively on one
particular fre0uency component at the input. The output of %C, would then regenerate that
particular fre0uency Abecause of LP. which gives output for beat fre0uencyB and attenuate heavily
other fre0uencies. %C, output thus can be used for regenerating or reconditioning a desired
fre0uency signal Awhich is weak and buried in noiseB out of many undesirable fre0uency signals.
-ome of the typical applications of PLL are discussed below.
AiB.re0uency "ultiplierE
.re0uency divider is inserted between the %C, @ phase comparator. -ince the output of the
divider is locked to the f
=
$ %C, is actually running at a multiple of the input fre0uency.
The desired amount of multiplication can be obtained by selecting a proper divide-by-=
network$ where = is an integer.
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AiiB.re0uency -hift 3eying A.-3B demodulatorE
n computer peripheral @ radio AwirelessB communication the binary data or code is
transmitted by means of a carrier fre0uency that is shifted between two preset fre0uencies. -ince a
carrier fre0uency is shifted between two preset fre0uencies$ the data transmission is said to use a
.-3. The fre0uency corresponding to logic + @ logic 9 states are commonly called the mark @
space fre0uency.
.or e7ample$ >hen transmitting teletype writer information using a modulator-demodulator
AmodemB a +9)9-+6)9 Amark-spaceB pair represents the originate signal$ while a 6961-6661 <4
Amark-spaceB pair represents the answer signal.
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.-3 (eneratorE
The .-3 generator is formed by using a 111 as an astable multivibrator$ whose fre0uency is
controlled by the sate of transistor L+.
n other words$ the output fre0uency of the .-3 generator depends on the logic state of the
digital data input.
+19 <4 is one the standards fre0uencies at which the data are commonly transmitted.
>hen the input is logic +$ the transistor L+ is off. Dnder the condition$ 111 timer works in its
normal mode as an astable multivibrator i.e.$ capacitor C charges through #
A
@ #
&
to 65: %cc
@ discharges through #
&
to +5: %cc.
Thus capacitor C charges @ discharges between 65: %cc @ +5: %cc as long as the input is logic
+.
The fre0uency of the output waveform is given by$
+.*1
foM--------------- M +9)9 <4 Amark fre0uencyB
A#
A
F6#
&
BC
>hen the input is logic 9$ AL+ is ,= saturatedB which inturn connects the resistance #c across
#
A.
This action reduces the charging time of capacitor C+ increases the output fre0uency$ which
is given by$
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+.*1
foM ------------------ M +6)9 <4 Aspace fre0uencyB
A#
A
YY #
C
F6 #
&
BC
&y proper selection of resistance #c$ this fre0uency is ad;usted to e0ual the space fre0uency of
+6)9 <4. The difference between the .-3 signals of +9)9 <4 @ +6)9 <4 is 699 <4$ this
difference is called \fre0uency shiftj.
The output +19 <4 can be made by connecting a voltage comparator between the output of the
ladder filter and pin 2 of PLL.
The %C, fre0uency is ad;usted with #+ so that at f
=
M +9)9 <4.
.-3 DemodulatorE
The output of 111 .-3 generator is applied to the 121 .-3 demodulator.
Capacitive coupling is used at the input to remove dc line.
At the input of 121$ the loop locks to the input fre0uency @ tracks it between the 6 fre0uencies.
#+ @ C+ determine the free running fre0uency of the %C,$ : stage #C ladder filter is used to
remove the carrier component from the output.
n digital data communication and computer peripheral$ binary data is transmitted by means of a
carrier fre0uency which is shifted between two preset fre0uencies. This type of data transmission is
called fre0uency shift keying A.-3B techni0ue. The binary data can be retrieved using .-3
demodulator. The figure below shows .-3 demodulator using PLL for tele-typewriter signals of
+9)9 <4 and +6)9 <4. As the signal appears at the input$ the loop locks to the input fre0uency and
tracks it between the two fre0uencies with a corresponding dc shift at the output. A three stage
filter removes the carrier component and the output signal is made logic compatible by a voltage
comparator.
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AiiiBA" DemodulationE
A PLL may be used to demodulate A" signals as shown in the figure below. The PLL is locked to
the carrier fre0uency of the incoming A" signal. The output of %C, which has the same
fre0uency as the carrier$ but unmodulated is fed to the multiplier. -ince %C, output is always ?9
9
before being fed to the multiplier. This makes both the signals applied to the multiplier and the
difference signals$ the demodulated output is obtained after filtering high fre0uency components
by the LP.. -ince the PLL responds only to the carrier fre0uencies which are very close to the
%C, output$ a PLL A" detector e7hibits high degree of selectivity and noise immunity which is
not possible with conventional peak detector type A" modulators.
A" input
Demodulated
output

%C, output
AivB." DemodulationE
Phase shift
?9
9
"ultiplier
Low Pass
.ilter
Phase
Locked
Loop
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f PLL is locked to a ." signal$ the %C, tracks the instantaneous fre0uency of the input signal.
The filtered error voltage which controls the %C, and maintains lock with the input signal is the
demodulated ." output. The %C, transfer characteristics determine the linearity of the
demodulated output. -ince$ %C, used in C PLL is highly linear$ it is possible to reali4e highly
linear ." demodulators.
AvBfre0uency multiplication5divisionE
The block diagram shown below shows a fre0uency multiplier5divider using PLL. A divide by =
network is inserter between the %C, output and the phase comparator input. n the locked state$
the %C, output fre0uency f
o
is given by
f
o
M =f
s.
The multiplication factor can be obtained by selecting a proper scaling factor = of the
counter.
.re0uency multiplication can also be obtained by using PLL in its harmonic locking mode. f the
input signal is rich in harmonics e.g. s0uare wave$ pulse train etc.$ then the %C, can be directly
locked to the n-th harmonic of the input signal without connecting any fre0uency divider in
between. <owever$ as the amplitude of the higher order harmonics becomes less$ effective locking
may not take place for high values of n. Typically n is kept less than +9.
The circuit of the figure above can also be used for fre0uency division. -ince the %C, output Aa
s0uare waveB is rich in harmonics$ it is possible to lock the m-th harmonic of the %C, output with
the input signal f
s
. The output fo of %C, is now given by
f
o
Mf
s
5m
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AviBPLL .re0uency -ynthesisE
n digital wireless communication systems A(-"$ CD"A etcB$ PLLqs are used to provide the
Local ,scillator AL,B for up-conversion during transmission$ and down-conversion during
reception. n most cellular handsets this function has been largely integrated into a single
integrated circuit to reduce the cost and si4e of the handset. <owever due to the high performance
re0uired of base station terminals$ the transmission and reception circuits are built with discrete
components to achieve the levels of performance re0uired. (-" L, modules are typically built
with a .re0uency -ynthesi4er integrated circuit$ and discrete resonator %C,qs.
.re0uency -ynthesi4er manufacturers include Analog Devices$ =ational -emiconductor and Te7as
nstruments. %C, manufacturers include -iren4a$ V-Communications$ nc. AV-C,""B
Principle of PLL synthesizers
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A phase locked loop does for fre0uency what the Automatic (ain Control does for voltage. t
compares the fre0uencies of two signals and produces an error signal which is proportional to the
difference between the input fre0uencies. The error signal is then low pass filtered and used to
drive a voltage-controlled oscillator A%C,B which creates an output fre0uency. The output
fre0uency is fed through a fre0uency divider back to the input of the system$ producing a negative
feedback loop. f the output fre0uency drifts$ the error signal will increase$ driving the fre0uency in
the opposite direction so as to reduce the error. Thus the output is loc0ed to the fre0uency at the
other input. This input is called the reference and is derived from a crystal oscillator$ which is very
stable in fre0uency. The block diagram below shows the basic elements and arrangement of a PLL
based fre0uency synthesi4er.
The key to the ability of a fre0uency synthesi4er to generate multiple fre0uencies is the divider
placed between the output and the feedback input. This is usually in the form of a digital counter$
with the output signal acting as a clock signal. The counter is preset to some initial count value$
and counts down at each cycle of the clock signal. >hen it reaches 4ero$ the counter output
changes state and the count value is reloaded. This circuit is straightforward to implement using
flip-flops$ and because it is digital in nature$ is very easy to interface to other digital components or
a microprocessor. This allows the fre0uency output by the synthesi4er to be easily controlled by a
digital system.
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Example:
-uppose the reference signal is +99 k<4$ and the divider can be preset to any value between + and
+99. The error signal produced by the comparator will only be 4ero when the output of the divider
is also +99 k<4. .or this to be the case$ the %C, must run at a fre0uency which is +99 k<4 7 the
divider count value. Thus it will produce an output of +99 k<4 for a count of +$ 699 k<4 for a
count of 6$ + "<4 for a count of +9 and so on. =ote that only whole multiples of the reference
fre0uency can be obtained with the simplest integer = dividers. .ractional = dividers are readily
available
Practical considerationsE
n practice this type of fre0uency synthesi4er cannot operate over a very wide range of fre0uencies$
because the comparator will have a limited bandwidth and may suffer from aliasing problems. This
would lead to false locking situations$ or an inability to lock at all. n addition$ it is hard to make a
high fre0uency %C, that operates over a very wide range. This is due to several factors$ but the
primary restriction is the limited capacitance range of varactor diodes. <owever$ in most systems
where a synthesiser is used$ we are not after a huge range$ but rather a finite number over some
defined range$ such as a number of radio channels in a specific band.
"any radio applications re0uire fre0uencies that are higher than can be directly input to the digital
counter. To overcome this$ the entire counter could be constructed using high-speed logic such as
/CL$ or more commonly$ using a fast initial division stage called a 'rescaler which reduces the
fre0uency to a manageable level. -ince the prescaler is part of the overall division ratio$ a fi7ed
prescaler can cause problems designing a system with narrow channel spacings - typically
encountered in radio applications. This can be overcome using a dual-modulus prescaler.
S++T
.urther practical aspects concern the amount of time the system can switch from channel to
channel$ time to lock when first switched on$ and how much noise there is in the output. All of
these are a function of the loo' filter of the system$ which is a low-pass filter placed between the
output of the fre0uency comparator and the input of the %C,. Dsually the output of a fre0uency
comparator is in the form of short error pulses$ but the input of the %C, must be a smooth noise-
free DC voltage. AAny noise on this signal naturally causes fre0uency modulation of the %C,.B.
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<eavy filtering will make the %C, slow to respond to changes$ causing drift and slow response
time$ but light filtering will produce noise and other problems with harmonics. Thus the design of
the filter is critical to the performance of the system and in fact the main area that a designer will
concentrate on when building a synthesi4er system.
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UNIT IV- ANALOG TO DIGITAL & DIGITAL TO ANALOG CONVERTERS
D TO A CONVERTER- SPECIFICATIONS
D5A converters are available with wide range of specifications specified by manufacturer. -ome of
the important specifications are #esolution$ Accuracy$ linearity$ monotonicity$ conversion time$
settling time and stability.
Resolution:
#esolution is defined as the number of different analog output voltage levels that can be provided
by a DAC. ,r alternatively resolution is defined as the ratio of a change in output voltage resulting
for a change of + L-& at the digital input. -imply$ resolution is the value of L-&.
#esolution A%oltsB M %o
.-
5 A6
n
-

+B M + L-& increment
>here GnH is the number of input bits
G%o
.-
H is the full scale output voltage.
/7ampleE
#esolution for an 8 ! bit DAC for e7ample is said to have
E 8 ! bit resolution
E A resolution of 9.:?6 of full--cale A+5611B
E A resolution of + part in 611.
Thus resolution can be defined in many different ways.
The following table shows the resolution for 2 to +2 bit DACs
S.No. Bits Intervals LSB size ( of full-scale) LSB size (For a 10 V full-scale)
+. 2 2: +.188 +18.8 m%
6. 8 611 9.:?6 :?.6 m%
:. +9 +96: 9.9?)8 ?.)8 m%
*. +6 *9?1 9.96** 6.** m%
1. +* +2:8: 9.992+ 9.2+ m%
2. +2 211:1 9.99+1 9.+1 m%
Accuracy:
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Absolute accuracy is the ma7imum deviation between the actual converter output and the ideal
converter output. The ideal converter is the one which does not suffer from any problem. >hereas$
the actual converter output deviates due to the drift in component values$ mismatches$ aging$ noise
and other sources of errors.
The relative accuracy is the ma7imum deviation after the gain and offset errors have been
removed. Accuracy is also given in terms of L-& increments or percentage of full-scale voltage.
=ormally$ the data sheet of a D5A converter specifies the relative accuracy rather than absolute
accuracy.
Linearity:
Linearity error is the ma7imum deviation in step si4e from the ideal step si4e. -ome D5A
converters are having a linearity error as low as 9.99+Q of full scale. The linearity of a D5A
converter is defined as the precision or e7actness with which the digital input is converted into
analog output. An ideal D5A converter produces e0ual increments or step si4es at output for every
change in e0ual increments of binary input.
Monotonicity:
A Digital to Analog converter is said to be monotonic if the analog output increases for an increase
in the digital input. A monotonic characteristics is essential in control applications. ,therwise it
would lead to oscillations. f a DAC has to be monotonic$ the error should be less than Z A+56B L-&
at each output level. <ence all the D5A converters are designed such that the linearity error
satisfies the above condition.
>hen a D5A Converter doesnHt satisfy the condition described above$ then$ the output voltage may
decrease for an increase in the binary input.
Conversion Time:
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t is the time taken for the D5A converter to produce the analog output for the given binary input
signal. t depends on the response time of switches and the output of the
Amplifier. D5A converters speed can be defined by this parameter. t is also called as setting time.
Settling time:
t is one of the important dynamic parameter. t represents the time it takes for the output to settle
within a specified band Z A+56B L-& of its final value following a code change at the input ADsually
a full-scale changeB. t depends on the switching time of the logic circuitry due to internal parasitic
capacitances and inductances. A typical settling time ranges from +99 ns to +9 is depending on the
word length and type of circuit used.
Stability:
The ability of a DAC to produce a stable output all the time is called as -tability. The performance
of a converter changes with drift in temperature$ aging and power supply variations. -o all the
parameters such as offset$ gain$ linearity error @ monotonicity may change from the values
specified in the datasheet. Temperature sensitivity defines the stability of a D5A converter.
DIGITAL TO ANALOG CONVERSION
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A DAC converts an abstract finite-precision number Ausually a fi7ed-point binary numberB into
a concrete physical 0uantity Ae.g.$ a voltage or a pressureB. n particular$ DACs are often used to
convert finite-precision time series data to a continually-varying physical signal.
A typical DAC converts the abstract numbers into a concrete se0uence of impulses that are then
processed by a reconstruction filter using some form of interpolation to fill in data between the
impulses. ,ther DAC methods Ae.g.$ methods based on Delta-sigma modulationB produce a pulse-
density modulated signal that can then be filtered in a similar way to produce a smoothly-varying
signal.
&y the =y0uist!-hannon sampling theorem$ sampled data can be reconstructed perfectly provided
that its bandwidth meets certain re0uirements Ae.g.$ a baseband signal with bandwidth less than
the =y0uist fre0uencyB. <owever$ even with an ideal reconstruction filter$ digital sampling
introduces 0uanti4ation that makes perfect reconstruction practically impossible. ncreasing the
digital resolution Ai.e.$ increasing the number of bits used in each sampleB or introducing
sampling dither can reduce this error.
DACs are at the beginning of the analog signal chain$ which makes them very important to system
performance. The most important characteristics of these devices areE
ResolutionE This is the number of possible output levels the DAC is designed to reproduce. This is
usually stated as the number of bits it uses$ which is the base two logarithm of the number of
levels. .or instance a + bit DAC is designed to reproduce 6 A6
+
B levels while an 8 bit DAC is
designed for 612 A6
8
B levels. #esolution is related to the effective number of bitsA/=,&B which is
a measurement of the actual resolution attained by the DAC.
Maximum sampling frequencyE This is a measurement of the ma7imum speed at which the
DACs circuitry can operate and still produce the correct output. As stated in the =y0uist!-hannon
sampling theorem$ a signal must be sampled at over twice the fre0uency of the desired signal. .or
instance$ to reproduce signals in all the audible spectrum$ which includes fre0uencies of up to
69 k<4$ it is necessary to use DACs that operate at over *9 k<4. The CD standard samples audio at
**.+ k<4$ thus DACs of this fre0uency are often used. A common fre0uency in cheap
computer sound cards is *8 k<4_many work at only this fre0uency$ offering the use of other
sample rates only through Aoften poorB internal resampling.
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MonotonicityE This refers to the ability of a DACqs analog output to move only in the direction
that the digital input moves Ai.e.$ if the input increases$ the output doesnqt dip before asserting the
correct output.B This characteristic is very important for DACs used as a low fre0uency signal
source or as a digitally programmable trim element.
THD+NE This is a measurement of the distortion and noise introduced to the signal by the DAC. t
is e7pressed as a percentage of the total power of unwanted harmonic distortion and noise that
accompany the desired signal. This is a very important DAC characteristic for dynamic and small
signal DAC applications.
Dynamic rangeE This is a measurement of the difference between the largest and smallest signals
the DAC can reproduce e7pressed in decibels. This is usually related to DAC resolution and noise
floor.
,ther measurements$ such as phase distortion and sampling period instability$ can also be very
important for some applications.
BINARY-WEIGHTED RESISTOR DAC
The binary-weighted-resistor DAC employs the characteristics of the inverting summer ,p Amp
circuit. n this type of DAC$ the output voltage is the inverted sum of all the input voltages. f the
input resistor values are set to multiples of twoE +#$ 6# and *#$ the output voltage would be e0ual
to the sum of %+$ %656 and %:5*. %+ corresponds to the most significant bit A"-&B while %:
corresponds to the least significant bit AL-&B.

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The circuit for a *-bit DAC using binary weighted resistor network is shown belowE
The binary inputs$ a
i
Awhere i M +$ 6$ : and *B have values of either 9 or +. The value$ 9$ represents
an open switch while + represents a closed switch.
The operational amplifier is used as a summing amplifier$ which gives a weighted sum of the
binary input based on the voltage$ %
ref
.
.or a *-bit DAC$ the relationship between %
out
and the binary input is as followsE
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The negative sign associated with the analog output is due to the connection to a summing
amplifier$ which is a polarity-inverting amplifier. >hen a signal is applied to the latter type of
amplifier$ the polarity of the signal is reversed Ai.e. a F input becomes -$ or vice versaB.
.or a n-bit DAC$ the relationship between %
out
and the binary input is as followsE
Analog %oltage ,utputE An /7ample
As an e7ample$ consider the following given parametersE %
ref
M 1 %$ # M 9.1 k and #
f
M + k. The
voltage outputs$ %
out
$ corresponding to the respective binary inputs are as followsE
Digital Input
V
OUT
(Volts)
a
1
a
2
a
3
a
4
9 9 9 9 0
9 9 9 + - 0.625
9 9 + 9 - 1.250
9 9 + + - 1.875
9 + 9 9 - 2.500
9 + 9 + - 3.125
9 + + 9 - 3.750
9 + + + - 4.375
+ 9 9 9 - 5.000
+ 9 9 + - 5.625
+ 9 + 9 - 6.250
+ 9 + + - 6.875
+ + 9 9 - 7.500
+ + 9 + - 8.125
+ + + 9 - 8.750
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+ + + + - 9.375
Table 1: Voltage Output of 4-bit DAC using Binary Weighted Resistor Network
The L-&$ which is also the incremental step$ has a value of - 9.261 % while the "-& or the full
scale has a value of - ?.:)1 %.
Practical LimitationsE
o The most significant problem is the large difference in resistor values re0uired between
the L-& and "-&$ especially in the case of high resolution DACs Ai.e. those that has large
number of bitsB. .or e7ample$ in the case of a +6-bit DAC$ if the "-& is + k $ then
the L-&is a staggering 6 " .
o The maintanence of accurate resistances over a large range of values is problematic. >ith
the current C fabrication technology$ it is difficult to manufacture resistors over a wide
resistance range that maintain an accurate ratio especially with variations in temperature.
R-2R LADDER DAC
An enhancement of the binary-weighted resistor DAC is the #-6# ladder network. This type of
DAC utili4es TheveninHs theorem in arriving at the desired output voltages. The #-6# network
consists of resistors with only two values - # and 67#. f each input is supplied either 9 volts
or reference voltage$ the output voltage will be an analog e0uivalent of the binary value of the
three bits. %-6 corresponds to the most significant bit A"-&B while %-9 corresponds to the
least significant bit AL-&B.
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%out M - A%"-& F %n F %L-&B M - A%#ef F %#ef56 F %#ef5 *B
The R/2R DAC
An alternative to the binary-weighted-input DAC is the so-called #56# DAC$ which uses fewer
uni0ue resistor values. A disadvantage of the former DAC design was its re0uirement of several
different precise input resistor valuesE one uni0ue value per binary input bit. "anufacture may be
simplified if there are fewer different resistor values to purchase$ stock$ and sort prior to assembly.
,f course$ we could take our last DAC circuit and modify it to use a single input resistance value$
by connecting multiple resistors together in seriesE
Dnfortunately$ this approach merely substitutes one type of comple7ity for anotherE volume of
components over diversity of component values. There is$ however$ a more efficient design
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methodology. &y constructing a different kind of resistor network on the input of our summing
circuit$ we can achieve the same kind of binary weighting with only two kinds of resistor values$
and with only a modest increase in resistor count. This CladderC network looks like thisE
"athematically analy4ing this ladder network is a bit more comple7 than for the previous circuit$
where each input resistor provided an easily-calculated gain for that bit. .or those who are
interested in pursuing the intricacies of this circuit further$ you may opt to use Theveninqs theorem
for each binary input Aremember to consider the effects of the virtual groundB$ and5or use a
simulation program like -PC/ to determine circuit response. /ither way$ you should obtain the
following table of figuresE
---------------------------------
Y &inary Y ,utput voltage Y
---------------------------------
Y 999 Y 9.99 % Y
---------------------------------
Y 99+ Y -+.61 % Y
---------------------------------
Y 9+9 Y -6.19 % Y
---------------------------------
Y 9++ Y -:.)1 % Y
---------------------------------
Y +99 Y -1.99 % Y
---------------------------------
Y +9+ Y -2.61 % Y
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---------------------------------
Y ++9 Y -).19 % Y
---------------------------------
Y +++ Y -8.)1 % Y
---------------------------------
As was the case with the binary-weighted DAC design$ we can modify the value of the feedback
resistor to obtain any CspanC desired. .or e7ample$ if weqre using F1 volts for a ChighC voltage level
and 9 volts for a ClowC voltage level$ we can obtain an analog output directly corresponding to the
binary input A9++ M -: volts$ +9+ M -1 volts$ +++ M -) volts$ etc.B by using a feedback resistance
with a value of +.2# instead of 6#.
INVERTED OR CURRENT MODE DAC
As the name implies$ Current mode DACs operates based on the ladder currents. The ladder is
formed by resistance # in the series path and resistance 6# in the shunt path. Thus the current is
divided into i+ $ i6$ i: vvvvin
.
in each arm. The currents are either diverted to the ground bus
AioB or to the %irtual-ground bus A io B.
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The currents are given as
i+ M %#/.56# M A%#/.5#B 6
-+
$ i6 M A%#/.B56B56# M A%#/.5#B 6
-6vvv
i
n
M A%#/.5#B 6
-n
.
And the relationship between the currents are given as
i6 M i
7
82
i: M i
7
89
i* M i
7
8:
in M i
7
82
n;7
Dsing the bits to identify the status of the switches$ and letting %
9
M -#
f
i
o
gives
%
9
M - A#
f
5#B %
#/.
Ab
+
6
-+
F b
6
6
-6
F vvv.. F b
n
6
-n
B
The two currents io and io are complementary to each other and the potential of io bus must be
sufficiently close to that of the io bus. ,therwise$ linearity errors will occur. The final op-amp is
used as current to voltage converter.
Advantages
+. The ma;or advantage of current mode D5A converter is that the voltage change across each
switch is minimal. -o the charge in;ection is virtually eliminated and the switch driver design is
made simpler.
6. n Current mode or inverted ladder type DACs$ the stray capacitance do not affect the
speed of response of the circuit due to constant ladder node voltages. -o improved speed
performance.
VOLTAGE MODE DAC
This is the alternative mode of DAC and is called so because$ the 6# resistance in the shunt path is
switched between two voltages named as %
L
and %
<
. The output of this DAC is obtained from the
leftmost ladder node. As the input is se0uenced through all the possible binary state starting from
All 9s A9v..9B to all +s A+v..+B. The voltage of this node changes in steps of 6
-n
A%
<
- %
L
B from the
minimum voltage of %o M %
L
to the ma7imum of %o M %
<
- 6
-n
A%
<
- %
L
B.
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The diagram also shows a non-inverting amplifier from which the final output is taken. Due to this
buffering with a non- inverting amplifier$ a scaling factor defined by 3 M + F A#
6
5#
+
B results.
Advantages
+. The ma;or advantage of this techni0ue is that it allows us to interpolate between any two
voltages$ neither of which need not be a 4ero.
6. "ore accurate selection and design of resistors # and 6# are possible and simple construction.
:. The binary word length can be easily increased by adding the re0uired number or
#-6# sections.
SWITCHES FOR DAC
The -witches which connects the digital binary input to the nodes of a D5A converter is an
electronic switch. Although switches can be made of using diodes$ &ipolar ;unction Transistors$
.ield /ffect transistors or ",-./Ts$ there are four main configurations used as switches for
DACs. They are
iB -witches using overdriven /mitter .ollowers.
iiB -witches using ",- Transistor- Totem pole ",-./T -witch and C",- nverter -witch.
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iiiB C",- switch for "ultiplying type DACs .
ivB C",- Transmission gate switches.
These configurations are used to ensure the high speed switching operations for different types of
DACs.
Switches using overdriven Emitter Followers:
The bipolar transistors have a negligible resistance when they are operated in saturation. The
bipolar transistor operating in saturation region indicates a minimum resistance and thus represents
,= condition. >hen they are operating in cut-off region indicates a ma7imum resistance and thus
represents ,.. condition.
The circuit shown here is the arrangement of two transistors connected as emitter followers. A
silicon transistor operating in saturation will have a offset voltage of 9.6% dropped across them. To
have a 4ero offset voltage condition$ the transistors must be overdriven because the saturation
factor becomes negative. The two transistors L
+
A=P=B and L
6
AP=PB acts as a double pole switch.
The bases of the transistors are driven by F1.)1% and -1.)1%.
Case +E
>hen %
&+
M %
&6
M F1.)1%$ L
+
is in saturation and L
6
is ,... And %
/
O 1% with
%
&/+
M %
&/6
M 9.)1%
Case 6E
>hen %
&+
M %
&6
M -1.)1%$ L
6
is in saturation and L
+
is ,... And %
/
O - 1% with
%
&/+
M %
&/6
M 9.)1%
Thus the terminal & of the resistor #
e
is connected to either -1% or F1% depending on the input bit.
Switches using MOS transistor:
iB Totem pole ",-./T -witchE
As shown in the figure$ the totem pole ",-./T -witch is connected in series with resistors of #-
6# network. The ",-./T driver is connected to the inverting terminal of the summing op-amp.
The complementary outputs # and
#
drive the gates of the ",-./T "
+
and "
6
respectively.
The -# flipflop holds one bit of digital information of the binary word under conversion.
Assuming the negative logic A-1% for logic + and F1% for logic 9B the operation is given as two
cases.
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Case +E
>hen the bit line is + with -M+ and #M9 makes #M+ and
#
M9. This makes the transistor "
+
,=$
thereby connecting the resistor # to reference voltage -%
#
. The transistor "
6
remains in ,..
condition.
Case 6E
>hen the bit line is 9 with -M9 and #M+ makes #M9 and
#
M+. This makes the transistor "
6
,=$
thereby connecting the resistor # to (round. The transistor "
+
remains in ,.. condition.
iiB C",- nverter -witchE
The figure of C",- inverter is shown here. t consists of a C",- inverter connected with an op-
amp acting as a buffer. The buffer drives the resistor # with a very low output impedance.
Assuming positive logic AF1% for logic + and 9% for logic 9B$ the operation can be e7plained in
two cases.
Case+E
>hen the complement of the bit line
#
is low$ "
+
becomes ,= connecting %
#
to the non-
inverting input of the op-amp. This drives the resistor # <(<.
Case6E
>hen the complement of the bit line
#
is high$ "
6
becomes ,= connecting (round to the non-
inverting input of the op-amp. This pulls the resistor # L,> Ato groundB.
CMOS switch for Multiplying type DACs:
The circuit diagram of C",- -witch is shown here. The heart of the switching element is formed
by transistors "
+
and "
6
. The remaining transistors accept TTl or C",- compatible logic inputs
and provides the anti-phase gate drives for the transistors "
+
and "
6
. The operation for the two
cases is as follows.
Case +E
>hen the logic input is +$ "
+
is ,= and "
6
is ,... Thus current
3
is diverted to oH bus.
Case 6E
>hen the logic input is 9$ "
6
is ,= and "
+
is ,... Thus current
3
is diverted to o bus.
CMOS Transmission gate switches:
The disadvantage of using individual =",- and P",- transistors are threshold voltage drop
A=",- transistor passing only minimum voltage of %
#
- %
T<
and P",- transistor passing
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minimum voltage of %
T<
B. This is eliminated by using transmission gates which uses a parallel
connection of both =",- and P",-. The arrangement shown here can pass voltages from %
#
to
9% acting as a ideal switch. The following cases e7plain the operation.
Case +E
>hen the bit-line b
k
is <(<$ both transistors "
n
and "
p
are ,=$ offering low resistance over the
entire range of bit voltages.
Case 6E
>hen the bit-line b
k
is L,>$ both the transistors are ,..$ and the signal transmission is inhibited
A>ithdrawnB.
Thus the =",- offers low resistance in the lower portion of the signal and P",- offers low
resistance in the upper portion of the signal. As a combination$ they offer a low parallel resistance
throughout the operating range of voltage. >ide varieties of these kinds of switches were
available. /7ampleE CD*922 and CD*91+.
HIGH SPEED SAMPLE AND HOLD CIRCUITS
Introduction:
-ample-and-hold A-5<B is an important analog building block with many applications$
including analog-to-digital converters AADCsB and switched-capacitor filters. The
function of the -5< circuit is to sample an analog input signal and hold this value over a
certain length of time for subse0uent processing.
Taking advantages of the e7cellent properties of ",- capacitors and switches$ traditional
switched capacitor techni0ues can be used to reali4e different -5< circuits S+T. The
simplest -5< circuit in ",- technology is shown in .igure +$ where Vin is the input
signal$ .7 is an ",- transistor operating as the sampling switch$ Ch is the hold capacitor$
c0 is the clock signal$ and Vout is the resulting sample-and-hold output signal.
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Ch
As depicted by .igure +$ in the simplest sense$ a -5< circuit can be achieved using only
one ",- transistor and one capacitor. The operation of this circuit is very
straightforward. >henever
Figure 1: Simplest sample-and-hold circuit in MOS technology.
As depicted by .igure +$ in the simplest sense$ a -5< circuit can be achieved using only
one ",- transistor and one capacitor. The operation of this circuit is very
straightforward. >henever c0 is high$ the ",- switch is on$ which in turn allows Vout to
track Vin. ,n the other hand$ when c0 is low$ the ",- switch is off. During this time$ Ch
will keep Vout e0ual to the value of Vin at the instance when c0 goes low.
Dnfortunately$ in reality$ the performance of this -5< circuit is not as ideal as described
above. The two ma;or types of errors occur. They are charge in;ection and clock feed through$ that
are associated with this -5< implementation. Three new -5< techni0ues$ all of which try to
minimi4e the errors caused by charge in;ection and5or clock feed through.
Alternative CMOS Sample-and-Hold Circuits:
This section covers three alternative C",- -5< circuits that are developed with the
intention to minimi4e charge in;ection and5or clock feedthrough.
-eries -amplingE
The -5< circuit of .igure + is classified as parallel sampling because the hold capacitor is
in parallel with the signal. n parallel sampling$ the input and the output are dc-coupled.
,n the other hand$ the -5< circuit shown in .igure 6 is referred to as series sampling
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because the hold capacitor is in series with the signal.
Figure 2: Series sampling.
>hen the circuit is in sample mode$ both switches S2 and S< are on$ while S7 is off. Then$S2 is
turned off first$ which means Vout is e0ual to VCC Aor V$$ for most circuitsB and the voltage drop
across Ch will be VCC = Vin. -ubse0uently$ S< is turned off and S7 is turned on simultaneously.
&y grounding node ,$ Vout is now e0ual to VCC = Vin$ and the drop from VCC to VCC = Vin is
e0ual to the instantaneous value of the input.
As a result$ this is actually an inverted -5< circuit$ which re0uires inversion of the signal at a later
stage. -ince the hold capacitor is in series with the signal$ series sampling can isolate the common-
mode levels of the input and the output. This is one advantage of series sampling over parallel
sampling. n addition$ unlike parallel sampling$ which suffers from signal-dependent charge
in;ection$ series sampling does not e7hibit such behavior because S2 is turned off before S<. Thus$
the fact that the gate-to-source voltage$ V2S$ of S2 is constant means that charge in;ection coming
from S2 is also constant Aas opposed to being signal-dependentB$ which means this error can be
easily eliminated through differential operation.
,n the other hand$ series sampling suffers from the nonlinearity of the parasitic
capacitance at node 1. This parasitic capacitance introduces distortion to the sample-and hold
value$ thus mandating that Ch be much larger than the parasitic capacitance. ,n top of this
disadvantage$ the settling time of the -5< circuit during hold mode is longer for
series sampling than for parallel sampling. The reason for this is because the value of
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Vout in series sampling is being reset to VCC Aor V$$B for every sample$ but this is not the case
for parallel sampling.
Switched Op-Amp Based Sample-and-Hold Circuit:
This -5< techni0ue takes advantage of the fact that when a ",- transistor is in the
saturation region$ the channel is pinched off and disconnected from the drain. Therefore$
if the hold capacitor is connected to the drain of the ",- transistor$ charge in;ection will
only go to the source ;unction$ leaving the drain unaffected. &ased on this concept$ a switched op-
amp A-,PB based -5< circuit$ as shown in .igure :.
Figure 3: Switched op-amp based sample and hold circuit.
During sample mode$ the -,P behaves ;ust like a regular op-amp$ in which the value of
the output follows the value of the input. During hold mode$ the ",- transistors at the
output node of the -,P are turned off while they are still operating in saturation$ thus
preventing any channel charge from flowing into the output of the -,P. n addition$ the
-,P is shut off and its output is held at high impedance$ allowing the charge on Ch to be
preserved throughout the hold mode. ,n the other hand$ the output buffer of this -5<
circuit is always operational during sample and hold mode and is always providing the
voltage on Ch to the output of the -5< circuit.
>ith the increasing demand for high-resolution and high-speed in date ac0uisition
systems$ the performance of the -5< circuits is becoming more and more important.
This is especially true in ADCs since the performance of -5< circuits greatly affects the
speed and accuracy of ADCs. The fastest -5< circuits operate in open loop$ but when
such circuits are implemented in C",- technology$ their accuracy is low. -5< circuits
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that operate in closed loop configuration can achieve high resolution$ but their
re0uirements for high gain circuit block$ such as an op-amp$ limits the speed of the
circuits. As a result$ better and faster -5< circuits must be developed.
At the same time$ the employment of low-voltage in %L- technology re0uires that the
analog circuits be low-voltage as well. As a result of this$ new researches in analog
circuits are now shifted from voltage-mode to current-mode. The advantages of current mode
circuits include low-voltage$ low-power$ and high-speed. Therefore$ future
researches of -5< circuit should also shift toward current-mode -5< techni0ues.
The above figure shows a sample and hold circuit with ",-./T as -witch acting as a sampling
device and also consists of a holding capacitor Cs to store the sample values until the ne7t sample
comes in. This is a high speed circuit as it is apparent that C",- switch has a very negligible
propagation delay.
-ample-and-hold A-5<B is an important analog building block that has many applications. The
simplest -5< circuit can be constructed using only one ",- transistor and one hold capacitor.
<owever$ due to the limitations of the ",- transistor switches$ errors due to charge in;ection and
clock feed through restrict the performance of -5< circuits. As a result$ different -5< techni0ues
and architectures are developed with the intention to reduce or eliminate these errors. Three of
these alternative -5< circuitsE series sampling$ -,P based -5< circuit$ and bottom plate -5< circuit
with bootstrapped switch$ more new -5< techni0ues and architectures need to be proposed in order
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to meet the increasing demand for high-speed$ low-power$ and low voltage -5< circuits for data
ac0uisition systems.
LF 398 IC- Functional Diagram
Connection Diagram
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A TO D CONVERTER- SPECIFICATIONS
Like DAC$ ADCs are also having many important specifications. -ome of them are #esolution$
Luanti4ation error$ Conversion time$ Analog error$ Linearity error$ D=L error$ =L error @ nput
voltage range.
Resolution:
The resolution refers to the finest minimum change in the signal which is accepted for conversion$
and it is decided with respect to number of bits. t is given as +56
n
$ where GnH is the number of bits
in the digital output word. As it is clear$ that the resolution can be improved by increasing the
number of bits or the number of bits representing the given analog input voltage.
#esolution can also be defined as the ratio of change in the value of input voltage %
i
$ needed to
change the digital output by + L-&. t is given as
#esolution M %i
.-
5 A6
n
! +B
>here G%
i.-H
is the full-scale input voltage.
GnH is the number of output bits.
Quantization error:
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f the binary output bit combination is such that for all the values of input voltage %
i
between any
two voltage levels$ there is a unavoidable uncertainty about the e7act value of %
i
when the output
is a particular binary combination. This uncertainty is termed as 0uanti4ation error. ts value is Z
A+56B L-&. And it is given as$
L
/
M %i
.-
5 6A6
n
! +B
>here G%i
.-
H

is the full-scale input voltage
GnH is the number of output bits.
"a7imum the number of bits selected$ finer the resolution and smaller the 0uanti4ation error.
Conversion Time:
t is defined as the total time re0uired for an A5D converter to convert an analog signal to digital
output. t depends on the conversion techni0ue and propagation delay of the circuit components.
Analog error:
An error occurring due to the variations in DC switching point of the comparator$ resistors$
reference voltage source$ ripples and noises introduced by the circuit components is termed as
Analog error.
Linearity Error:
t is defined as the measure of variation in voltage step si4e. t indicates the difference between the
transitions for a minimum step of input voltage change. This is normally specified as fraction of
L-&.
DNL (Differential Non-Linearity) Error:
The analog input levels that trigger any two successive output codes should differ by + L-&. Any
deviation from this + L-& value is called as D=L error.
INL (Integral Non-Linearity Error:
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The deviation of characteristics of an ADC due to missing codes causes =L error. The ma7imum
deviation of the code from its ideal value after nulling the offset and gain errors is called as
ntegral =on-Linearity /rror.
Input Voltage Range:
t is the range of voltage that an A5D converter can accept as its input without causing any
overflow in its digital output.
ANALOG SWITCHES
There were two types of analog switches. -eries and -hunt switch. The -witch operation is shown
for both the cases %
(-
M9 %
(-
M %
(sAoffB
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ANALOG TO DIGITAL CONVERSION
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The natural state of audio and video signals is analog. >hen digital technology was not yet around$
they are recorded or played back in analog devices like vinyl discs and cassette tapes. The storage
capacity of these devices is limited and doing multiple runs of re-recording and editing produced
poor signal 0uality. Developments in digital technology like the CD$ D%D$ &lu-ray$ flash devices
and other memory devices addressed these problems. .or these devices to be used$ the analog
signals are first converted to digital signals using analog to digital conversion AADCB. .or the
recorded audio and video signals to be heard and viewed again$ the reverse process of digital to
analog conversion ADACB is used. ADC and DAC are also used in interfacing digital circuits to
analog systems. Typical applications are control and monitoring of temperature$ water level$
pressure and other real-world data.
An ADC inputs an analog signal such as voltage or current and outputs a digital signal in the form
of a binary number. A DAC$ on the other hand$ inputs the binary number and outputs the
corresponding analog voltage or current signal.

Sampling rate
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The analog signal is continuous in time and it is necessary to convert this to a flow of digital
values. t is therefore re0uired to define the rate at which new digital values are sampled from the
analog signal. The rate of new values is called the sa'ling rate or sa'ling fre"uenc& of the
converter.
A continuously varying band limited signal can be sampled Athat is$ the signal values at intervals of
time T$ the sampling time$ are measured and storedB and then the original signal can be e(actl&
reproduced from the discrete-time values by an interpolation formula. The accuracy is limited by
0uanti4ation error. <owever$ this faithful reproduction is only possible if the sampling rate is
higher than twice the highest fre0uency of the signal. This is essentially what is embodied in
the -hannon-=y0uist sampling theorem.
-ince a practical ADC cannot make an instantaneous conversion$ the input value must necessarily
be held constant during the time that the converter performs a conversion Acalled theconversion
tieB. An input circuit called a sample and hold performs this task_in most cases by using
a capacitor to store the analog voltage at the input$ and using an electronic switch or gate to
disconnect the capacitor from the input. "any ADC integrated circuits include the sample and hold
subsystem internally.
Accuracy
An ADC has several sources of errors. Luanti4ation error and Aassuming the ADC is intended to be
linearB non-linearity is intrinsic to any analog-to-digital conversion. There is also a so-
called a'erture error which is due to a clock ;itter and is revealed when digiti4ing a time-variant
signal Anot a constant valueB.
These errors are measured in a unit called the %SB$ which is an abbreviation for least significant
bit. n the above e7ample of an eight-bit ADC$ an error of one L-& is +5612 of the full signal
range$ or about 9.*Q.
Quantization error
Luanti4ation error is due to the finite resolution of the ADC$ and is an unavoidable imperfection in
all types of ADC. The magnitude of the 0uanti4ation error at the sampling instant is between 4ero
and half of one L-&.
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n the general case$ the original signal is much larger than one L-&. >hen this happens$
the 0uanti4ation error is not correlated with the signal$ and has a uniform distribution. ts #"-
value is the standard deviation of this distribution$ given by . n the eight-bit
ADC e7ample$ this represents 9.++:Q of the full signal range.
At lower levels the 0uanti4ing error becomes dependent of the input signal$ resulting in distortion.
This distortion is created after the anti-aliasing filter$ and if these distortions are above +56 the
sample rate they will alias back into the audio band. n order to make the 0uanti4ing error
independent of the input signal$ noise with amplitude of + 0uanti4ation step is added to the signal.
This slightly reduces signal to noise ratio$ but completely eliminates the distortion. t is known
as dither.
Non-linearity
All ADCs suffer from non-linearity errors caused by their physical imperfections$ resulting in their
output to deviate from a linear function Aor some other function$ in the case of a deliberately non-
linear ADCB of their input. These errors can sometimes be mitigated by calibration$ or prevented
by testing.
mportant parameters for linearity are integral non-linearity A=LB and differential non-
linearity AD=LB. These non-linearities reduce the dynamic range of the signals that can be digiti4ed
by the ADC$ also reducing the effective resolution of the ADC.
Types of ADC
Direct-conversion ADC/Flash type ADC:
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This process is e7tremely fast with a sampling rate of up to + (<4. The resolution is however$
limited because of the large number of comparators and reference voltages re0uired. The input
signal is fed simultaneously to all comparators. A priority encoder then generates a digital output
that corresponds with the highest activated comparator.

Successive-approximationADCs
-uccessive-appro7imation ADC is a conversion techni0ue based on a successive-appro7imation
register A-A#B. This is also called bit-weighing conversion that employs a comparator to weigh the
applied input voltage against the output of an =-bit digital-to-analog converter ADACB. The final
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result is obtained as a sum of = weighting steps$ in which each step is a single-bit conversion using
the DAC output as a reference. -A# converters sample at rates up to +"bps$ re0uires a low supply
current$ and the cheapest in terms of production cost.
A successive-appro7imation ADC uses a comparator to re;ect ranges of voltages$ eventually
settling on a final voltage range. -uccessive appro7imation works by constantly comparing the
input voltage to the output of an internal digital to analog converter ADAC$ fed by the current value
of the appro7imationB until the best appro7imation is achieved. At each step in this process$ a
binary value of the appro7imation is stored in a successive appro7imation register A-A#B. The
-A# uses a reference voltage Awhich is the largest signal the ADC is to convertB for comparisons.
.or e7ample if the input voltage is 29 % and the reference voltage is +99 %$ in the +st clock cycle$
29 % is compared to 19 % Athe reference$ divided by two. This is the voltage at the output of the
internal DAC when the input is a q+q followed by 4erosB$ and the voltage from the comparator is
positive Aor q+qB Abecause 29 % is greater than 19 %B. At this point the first binary digit A"-&B is set
to a q+q. n the 6nd clock cycle the input voltage is compared to )1 % Abeing halfway between +99
and 19 %E This is the output of the internal DAC when its input is q++q followed by 4erosB because
29 % is less than )1 %$ the comparator output is now negative Aor q9qB. The second binary digit is
therefore set to a q9q. n the :rd clock cycle$ the input voltage is compared with 26.1 % Ahalfway
between 19 % and )1 %E This is the output of the internal DAC when its input is q+9+q followed by
4erosB. The output of the comparator is negative or q9q Abecause 29 % is less than 26.1 %B so the
third binary digit is set to a 9. The fourth clock cycle similarly results in the fourth digit being a q+q
A29 % is greater than 12.61 %$ the DAC output for q+99+q followed by 4erosB. The result of this
would be in the binary form +99+. This is also called bit;weighting conversion$ and is similar to a
binary. The analogue value is rounded to the nearest binary value below$ meaning this converter
type is mid-rise Asee aboveB. &ecause the appro7imations are successive Anot simultaneousB$ the
conversion takes one clock-cycle for each bit of resolution desired. The clock fre0uency must be
e0ual to the sampling fre0uency multiplied by the number of bits of resolution desired. .or
e7ample$ to sample audio at **.+ k<4 with :6 bit resolution$ a clock fre0uency of over +.* "<4
would be re0uired. ADCs of this type have good resolutions and 0uite wide ranges. They are more
comple7 than some other designs.

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IntegratingADCs
n an integrating ADC$ a current$ proportional to the input voltage$ charges a capacitor for a fi7ed
time interval T charge. At the end of this interval$ the device resets its counter and applies an
opposite-polarity negative reference voltage to the integrator input. &ecause of this$ the capacitor
is discharged by a constant current until the integrator output voltage 4ero again. The T discharge
interval is proportional to the input voltage level and the resultant final count provides the digital
output$ corresponding to the input signal. This type of ADCs is e7tremely slow devices with low
input bandwidths. Their advantage$ however$ is their ability to re;ect high-fre0uency noise and AC
line noise such as 19<4 or 29<4. This makes them useful in noisy industrial environments and
typical application is in multi-meters.
An integrating ADC Aalso dual-slope or multi-slope ADCB applies the unknown input voltage to
the input of an integrator and allows the voltage to ramp for a fi7ed time period Athe run-up
periodB. Then a known reference voltage of opposite polarity is applied to the integrator and is
allowed to ramp until the integrator output returns to 4ero Athe run-down periodB. The input voltage
is computed as a function of the reference voltage$ the constant run-up time period$ and the
measured run-down time period. The run-down time measurement is usually made in units of the
converterqs clock$ so longer integration times allow for higher resolutions. Likewise$ the speed of
the converter can be improved by sacrificing resolution. Converters of this type Aor variations on
the conceptB are used in most digital voltmeters for their linearity and fle7ibility.

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Sigma-delta ADCs/ Over sampling Converters:
t consist of 6 main parts - modulator and digital filter. The modulator includes an integrator and a
comparator with a feedback loop that contains a +-bit DAC. The modulator oversamples the input
signal$ converting it to a serial bit stream with a fre0uency much higher than the re0uired sampling
rate. This is then transform by the output filter to a se0uence of parallel digital words at the
sampling rate. The characteristics of sigma-delta converters are high resolution$ high accuracy$ low
noise and low cost. Typical applications are for speech and audio.
A Sigma-Delta ADC Aalso known as a Delta--igma ADCB oversamples the desired signal by a
large factor and filters the desired signal band. (enerally a smaller number of bits than re0uired are
converted using a .lash ADC after the .ilter. The resulting signal$ along with the error generated
by the discrete levels of the .lash$ is fed back and subtracted from the input to the filter. This
negative feedback has the effect of noise shaping the error due to the .lash so that it does not
appear in the desired signal fre0uencies. A digital filter Adecimation filterB follows the ADC which
reduces the sampling rate$ filters off unwanted noise signal and increases the resolution of the
output. Asigma-delta modulation$ also called delta-sigma modulationB
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A/D Using Voltage to time conversion:
The &lock diagram shows the basic voltage to time conversion type of A to D converter. <ere the
cycles of variable fre0uency source are counted for a fi7ed period. t is possible to make an A5D
converter by counting the cycles of a fi7ed-fre0uency source for a variable period. .or this$ the
analog voltage re0uired to be converted to a proportional time period.
As shown in the diagram$ A negative reference voltage -%
#
is applied to an integrator$ whose
output is connected to the inverting input of the comparator. The output of the comparator is at + as
long as the output of the integrator %o is less than %a. At t M T$ %c goes low and switch - remains
open. >hen %
/=
goes high$ the switch - is closed$ thereby discharging the capacitor. Also the
=A=D gate is disabled. The waveforms are shown here.
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UNIT V WAVEFORM GENERATORS AND SPECIAL FUNCTION ICs
BASICS OF OSCILLATORS:
Criteria for oscillation:
The canonical form of a feedback system is shown in .igure +$ and /0uation + describes the
performance of any feedback system Aan amplifier with passive feedback
Components constitutes a feedback systemB.
.igure +E Canonical form of feedback circuit
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,scillation results from an unstable statee i.e.$ the feedback system canHt find a stable state because
its transfer function canHt be satisfied. /0uation + becomes unstable when A+FAdB M 9 because A59
is an undefined state. Thus$ the key to designing an oscillator is to insure that Ad M !+ Acalled the
&arkhausen criterionB$ or using comple7 math the e0uivalent e7pression is Ad M + !+89w. The !
+89w phase shift criterion applies to negative feedback systems$ and 9w phase shift applies to
positive feedback systems.
The output voltage of a feedback system heads for infinite voltage when Ad M !+. >hen the output
voltage approaches either power rail$ the active devices in the amplifiers change gain$ causing the
value of A to change so the value of Ad b+e thus$ the charge to infinite voltage slows down and
eventually halts. At this point one of three things can occur. .irst$ nonlinearity in saturation or
cutoff can cause the system to become stable and lock up. -econd$ the initial charge can cause the
system to saturate Aor cut offB and stay that way for a long time before it becomes linear and heads
for the opposite power rail. Third$ the system stays linear and reverses direction$ heading for the
opposite power rail. Alternative two produces highly distorted oscillations Ausually 0uasi s0uare
wavesB$
and the resulting oscillators are called rela7ation oscillators. Alternative three produces sine wave
oscillators.
All oscillator circuits were built with op amps$ 1Q resistors$ and 69Q capacitorse hence$
component tolerances cause differences between ideal and measured values.
Phase Shift in Oscillators:
The +89w phase shift in the e0uation Ad M + !+89w is introduced by active and passive
components. Like any well-designed feedback circuit$ oscillators are made dependent on passive
component phase shift because it is accurate and almost drift-free. The phase shift contributed by
active components is minimi4ed because it varies with temperature$ has a wide initial tolerance$
and is device dependent. Amplifiers are selected such that they contribute little or no phase shift at
the oscillation fre0uency. A single pole #L or #C circuit contributes up to ?9w phase shift per pole$
and because +89w is re0uired for oscillation$ at least two poles must be used in oscillator design.
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An LC circuit has two polese thus$ it contributes up to +89w phase shift per pole pair$ but LC and
L# oscillators are not considered here because low fre0uency inductors are e7pensive$ heavy$
bulky$ and non-ideal. LC oscillators are designed in high-fre0uency applications$ beyond the
fre0uency range of voltage feedback op amps$ where the inductor si4e$ weight$ and cost are less
significant. "ultiple #C sections are used in low-fre0uency oscillator design in lieu of inductors.
Phase shift determines the oscillation fre0uency because the circuit oscillates at the fre0uency that
accumulates !+89w phase shift. The rate of change of phase with fre0uency$ d

5dt$ determines
fre0uency stability. >hen buffered #C sections Aan op amp buffer provides high input and low-
output impedanceB are cascaded$ the phase shift multiplies by the number of sections$ n Asee .igure
6B.
.igure 6E Phase plot of #C sections
Although two cascaded #C sections provide +89w phase shift$ d

5dt at the oscillator fre0uency is


low$ thus oscillators made with two cascaded #C sections have poor fre0uency stability. Three
e0ual cascaded #C filter sections have a higher d

5dt$ and the resulting oscillator has improved


fre0uency stability. Adding a fourth #C section produces an oscillator with an e7cellent d

5dt$
thus this is the most stable oscillator configuration. .our sections are the ma7imum number used
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because op amps come in 0uad packages$ and the four-section oscillator yields four sine waves that
are *1w phase shifted relative to each other$ so this oscillator can be used to obtain sine5cosine or
0uadrature sine waves.
Crystal or ceramic resonators make the most stable oscillators because resonators have an
e7tremely high d

5dt resulting from their non-linear properties. #esonators are used for high-
fre0uency oscillators$ but low-fre0uency oscillators do not use resonators because of si4e$ weight$
and cost restrictions. ,p amps are not used with crystal or ceramic resonator oscillators because op
amps have low bandwidth. /7perience shows that it is more cost-effective to build a high-
fre0uency crystal oscillator and count down the output to obtain a low fre0uency than it is to use a
low-fre0uency resonator.
Gain in Oscillators:
The oscillator gain must e0ual one AAd M + !+89wB at the oscillation fre0uency. The circuit
becomes stable when the gain e7ceeds one and oscillations cease. >hen the gain e7ceeds one with
a phase shift of !+89w$ the active device non-linearity reduces the gain to one. The non-linearity
happens when the amplifier swings close to either power rail because cutoff or saturation reduces
the active device AtransistorB gain. The parado7 is that worst-case design practice re0uires nominal
gains e7ceeding one for manufacturability$ but e7cess gain causes more distortion of the output
sine wave.
>hen the gain is too low$ oscillations cease under worst-case conditions$ and when the gain is too
high$ the output wave form looks more like a s0uare wave than a sine wave. Distortion is a direct
result of e7cess gain overdriving the amplifiere thus$ gain must be carefully controlled in low
distortion oscillators. Phase-shift oscillators have distortion$ but they achieve low-distortion output
voltages because cascaded #C sections act as distortion filters. Also$ buffered phase-shift
oscillators have low distortion because the gain is controlled and distributed among the buffers.
-ome circuit configurations A>ien-bridgeB or low distortion specifications re0uire an au7iliary
circuit to ad;ust the gain. Au7iliary circuits range from inserting a non-linear component in the
feedback loop$ to automatic gain control AA(CB loops$ to limiting by e7ternal components.
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SINE WAVE GENERATORS (OSCILLATORS)
The sine wave is certainly one of the most fundamental waveforms. A variety of circuits and
techni0ues have been developed for the generation of sine waves. The conventional sine wave
oscillator circuits use phase shifting techni0ues that usually employ
Two #C tuning networks$ and
Comple7 amplitude limiting circuitry
RC PHASE SHIFT OSCILLATOR
#C phase shift oscillator using op-amp in inverting amplifier introduces the phase shift of +89
9
between input and output. The feedback network consists of : #C sections each producing 29
9
phase shift. -uch a #C phase shift oscillator using op-amp is shown in the figure.
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The output of amplifier is given to feedback network. The output of feedback
network drives the amplifier. The total phase shift around a loop is +89
9
of amplifier and +89
9
due
to : #C section$ thus :29
9
. This satisfies the re0uired condition for positive feedback and circuit
works as an oscillator.
>ithout the simplification of all the resistors and capacitors having the same value$ the
calculations become more comple7E
,scillation criterionE


Phase Shift Oscillator Types
i) RC Phase shift oscillator:
A phase-shift oscillator can be built with one op amp as shown in .igure 1. The normal assumption
is that the phase-shift sections are independent of each other.
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.igure 1E #C Phase -hift ,scillator using one op-amp
The /0uation : is writtenE

The loop phase shift is !+89w when the phase shift of each section is !29w$ and this occurs when r
M 6Wf M +.):65#C because the tangent 29w M +.):. The magnitude of d at this point is A+56B
:
$ so the
gain$ A$ must be e0ual to 8 for the system gain to be e0ual to +. The oscillation fre0uency with the
component values shown in .igure 1 is :.)2 k<4 rather than the calculated oscillation fre0uency of
6.)2 k<4. Also$ the gain re0uired to start oscillation is 62 rather than the calculated gain of 8.
These discrepancies are partially due to component variations$ but the biggest contributing factor is
the incorrect assumption that the #C sections do not load each other. This circuit configuration
was very popular when active components were large and e7pensive$ but now op amps are
ine7pensive and small and come four in a package$ so the single op amp phase-shift oscillator is
losing popularity.
ii) Quadrature Phase shift oscillator:
,pamp
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The 0uadrature oscillator is another type of phase-shift oscillator$ but the three #C sections are
configured so that each section contributes ?9w of phase shift. The outputs are labeled sine and
cosine A0uadratureB because there is a ?9w phase shift between op amp outputs Asee .igure 2B.
.igure 2E Luadrature Phase -hift ,scillator
The loop gain is calculated in /0uation *.
>hen #
+
C
+
M #
6
C
6
M#
:
C
:
$ /0uation * reduces to /0uation 1
>hen r M +5#C$ /0uation 1 reduces to + !+89w$ so oscillation occurs at r M 6Wf M +5#C. The
test circuit oscillated at +.21 k<4 rather than the calculated +.1? k<4$ and
the discrepancy is attributed to component variations.
,pamp
,pamp
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,p amp oscillators are restricted to the lower end of the fre0uency spectrum because op amps do
not have the re0uired bandwidth to achieve low phase shift at high fre0uencies. The new current
feedback op amps are very hard to use in oscillator circuits because they are sensitive to feedback
capacitance. %oltage feedback op amps are limited to a few hundred k<4 because they accumulate
too much phase shift.
Wien Bridge Oscillator:
.igure : gives the >ien-bridge circuit configuration. The loop is broken at the positive input$ and
the return signal is calculated in /0uation 6 below.
.igure :E >ien &ridge Circuit -chematic
,pamp
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>hen r M 6Wf M +5#C$ the feedback is in phase Athis is positive feedbackB$ and the gain is +5:$ so
oscillation re0uires an amplifier with a gain of :. >hen #
.
M 6#
(
$ the amplifier gain is : and
oscillation occurs at f M +56W#C. The circuit oscillated at +.21 k<4 rather than +.1? k<4 with the
component values shown in .igure :$ but the distortion is noticeable.
.igure *E >ien &ridge Circuit -chematic with non-linear feedback
.igure * shows a >ien-bridge circuit with non-linear feedback. The lamp resistance$ #
L
$ is
nominally selected as half the feedback resistance$ #
.
$ at the lamp current established by #
.
and
#
L
. The non-linear relationship between the lamp current and resistance keeps output voltage
changes small.
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-ome circuits use diode limiting in place of a non-linear feedback component. The diodes reduce
the distortion by providing a soft limit for the output voltage. A(C must be used when neither of
these techni0ues yields low distortion.
(enerally in an oscillator$ amplifier stage introduces +89
9
phase shift$ to obtain a
phase shift of :29
9
A6W radiansB around a loop. This is re0uired condition for any oscillator. &ut
>ien bridge oscillator uses a non-inverting amplifier and hence does not provide any phase shift
during amplifier stage. As total phase shift re0uired is 9
9
or 6nW radians$ in >ien bridge type no
phase shift is necessary through feedback. Thus the total phase shift around a loop is 9
9
. Let us
study the basic version of the >ien bridge oscillator and its analysis.
A basic >ien bridge used in this oscillator and an amplifier stage is shown in figure.
f a voltage source is applied directly to the input of an ideal amplifier with feedback$ the input
current will beE
>here v
in
is the input voltage$ v
out
is the output voltage$ and 4
f
is the feedback impedance. f the
voltage gain of the amplifier is defined asE
And the input admittance is defined asE
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nput admittance can be rewritten asE
.or the >ien bridge$ 4
f
is given byE
f A
v
is greater than +$ the input admittance is a negative resistance in parallel with an inductance.
The inductance isE
f a capacitor with the same value of C is placed in parallel with the input$ the circuit has a
natural resonance atE
-ubstituting and solving for inductance yieldsE
f A
v
is chosen to be :E
%
in
M R
6
C
-ubstituting this value yieldsE
,rE
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-imilarly$ the input resistance at the fre0uency above isE
.or A
v
M :E
R
in
M x R
f a resistor is placed in parallel with the amplifier input$ it will cancel some of the negative
resistance. f the net resistance is negative$ amplitude will grow until clipping occurs. -imilarly$ if
the net resistance is positive$ oscillation amplitude will decay. f a resistance is added in parallel
with e7actly the value of R$ the net resistance will be infinite and the circuit can sustain stable
oscillation at any amplitude allowed by the amplifier.
=otice that increasing the gain makes the net resistance more negative$ which increases amplitude.
f gain is reduced to e7actly : when a suitable amplitude is reached$ stable$ low distortion
oscillations will result. Amplitude stabili4ation circuits typically increase gain until a suitable
output amplitude is reached. As long as R$ C$ and the amplifier are linear$ distortion will be
minimal.
MULTIVIBRATORS
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Astable Multivibrator
The two states of circuit are only stable for a limited time and the circuit switches between them
with the output alternating between positive and negative saturation values. Analysis of this circuit
starts with the assumption that at time t>y9 the output has ;ust switched to state +$ and the transition
would have occurred when
An op-amp Astable multivibrator is also called as free running oscillator. The basic principle of
generation of s0uare wave is to force an op-amp to operate in the saturation region AZ%satB. A
fraction d M
6 +
6
R R
R
+
of the output is feedback to the positive input terminal of op-amp. The
charge in the capacitor increases @ decreases upto a threshold value called Zd%sat. The charge in
the capacitor triggers the op-amp to stay either at F%sat or !%sat. Asymmetrical s0uare wave can
also be generated with the help of 4ener diodes. Astable multivibrator do not re0uire a e7ternal
trigger pulse for its operation @ output toggles from one state to another and does not contain a
stable state. Astable multivibrator are mainly used in timing applications @ waveforms generators.
Design
An -0uare >ave (enerator at f
9
M + 3<4.
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+. The e7pression of f
o
is obtained from the charging period t+ @ t6 of capacitor as
f
o
M
T 5 6 + lnS 6
+
6 +
R R RC +
6. To simplify the above e7pression$ the value of #+ @ #6 should be taken as #6 M +.+2#$
such that f
o
simplifies to f
o
M
RC 6
+
:. Assume the value of #+ and find #6. #6 M +.+23` A+93B

*. Assume the value of C @ Determine # from f
o
M
RC 6
+
1. Calculate the threshold point from
l%
T
l or ld%
-AT
l M
6 +
+
R R
R
+
ld%
-AT
l where d is the feedback ratio.
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Monostable Multivibrator using Op-amp:
circuit diagram:
Output Waveform:
0
-
RF=R3
R3
0
+15v
O/P
+
-15V
-
Vin
C1
IC 741
R1
6
R2
4
2
D2
C2
3
R4
D1
+
7
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A multivibrator which has only one stable and the other is 0uasi stable state is
called as "onostable multivibrator or one-short multivibrator. This circuit is useful for
generating signal output pulse of ad;ustable time duration in response to a triggering signal.
The width of the output pulse depends only on the e7ternal components connected to the op-
amp. Dsually a negative trigger pulse is given to make the output switch to other state. &ut$ it
then return to its stable state after a time interval determining by circuit components. The pulse
width T can be given as T M 9.2?#C. for "onostable operation the triggering pulse width Tp
should be less then T$ the pulse width of "onostable multivibrator. This circuit is also called as
time delay circuit or gating circuit.
Design:
+. Calculating d from e7pression
$ dM
6 +
+
R R
R
+

6. The value of # @ C from the pulse width time e7pression.
T M #C ln

+
+
B 5 + A
sat $
V V
T M #C ln
1 . 9
B 5 + A
sat $
V V +
T z9.2?#C.
:. Triggering pulse width T
p
must be much smaller then T. T
p
U T.
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TRIANGULAR WAVE GENERATOR
Circuit:
This signal generator gives you two waveforms for the price of oneE a triangle-wave and a s0uare-
wave. The central component of this circuit is the integrator capacitor C. &asically we are
interested in performing two functions on CE charge it, discharge it ; re'eat indefinitel&? The
output waveforms are shown here and it is apparent that a s0uare wave generator followed by an
integrator acts as a triangular wave generator.
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-uppose our design calls for a F5-+9 % triangle wave$ cruising along at +9 k<4. This means that
%thF M F+9 % and %th- M -+9 %. (iven %P M F1 %$ %= M -1 %$ letqs choose #6 M +9 k` and then
calculate #+ M 69 k` from the e0uation above. f the value of Capacitor is+ nf$ then what value of
# is needed for +9 k<4 AT M +99 KsB can be calculated$ because %o needs to swing {%o M +9 - A-
+9B M 69 % in an interval {T M 19 Ks$ we solve the above e0uation in the Linear #amps section for
#.
Changing the voltage thresholds also changes the time re0uired to reach the thresholds. Also$ make
sure %thF and %th- are not outside the F5-+1% limits of the op amp model. And donqt forget the
option of changing the reverse voltage of the 4ener diode via the &% parameter. 'ust remember the
charging currents and thresholds will change too.

oou may have noticed that the triangle peaks and period may not accurately meet our F5-+9%
swing at +99 us. The main reason is that our current source and thresholds are derived from 4ener
diodes - not e7actly the most accurate reference. -ome designs use improved means for deriving
and switching the current sources that charge C.

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LINEAR RAMP GENERATOR
A triangle wave implies that the circuit generates a linear voltage ramp. ,ne way to achieve this
goal is by charging discharging C with a constant current. The ,p Amp ntegrator provides a
handy way to accomplish this.
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Ramp Up
Connect # to %= and >ith %- held at the virtual ground A9%B$ a constant current flows from %- to
%=.
Iin > V* 8 RI.
C integrates Iin creating a positive linear ramp at %o. The ramp is linear because %o changes
proportionally to the time elapsed {T.
{Vo > ; V* 8 @CI A RIB A {T
Ramp Down Connect # to %P and a constant current flows from %P to %-$
Iin > ; V) 8 RI. =ow %o ramps down linearly
{Vo > ; V) 8 @CI A RIB A {T
#ampDpE{Vo8{T> ;V*8@CIRIB
#amp DownE{Vo 8{T > ; V) 8 @ CI A RI B
These e0uations show you the parameters available to control the ramp up 5 down speeds. There is
a possibility of creating asymmetrical voltage swings by including a reference voltage %#/. to the
comparatorqs negative input. AActually$ its been there all along$ ;ust set to 9%.B %#/. letqs you
place the thresholds more freely - they can now both be positive or negative. &asically$ %#/. can
shift the thresholds up or down as shown in the e0uation.
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%thFM%#/.|A#+F#6B5#6-%=|#+5#6
%th- M %#/. | A#+F#6B5#6 -%P | #+ 5 #6
Pick new thresholds by including %#/.. .or e7ample$ set #+ M #6 M +9k and %#/. M 6.1 %. #un
a new simulation and check your new triangle boundaries. "ake sure your %thF and %th- are not
outside the F5-+1% limits of the op amp model.
t is not confined to e0ual ramp up and down rates. =ew voltage source %#/.6 and connect it to
the integratorqs positive input. .or e7ample$ add %#/. and change. .or e7ample$ set %#/.6 to a
voltage like 6%. >ith %#/.6 M 6%$ %P M 1%$ %= M -1 % and # M +6.1 kohms$ you get une0ual
constant currents of inF M -9.6* mA and %in- M 9.12 mA.
Upper and Lower Bounds
>hen do we switch from charging to discharging C} &asically$ there is a need to pick two levels -
an u''er and a lower threshold - to define the bounds of the triangle wave. The circuit ramps up or
down$ reversing at the upper and lower thresholds.
>ith one leg of # at %=$ the output ramps up until the Upper Threshold ( Vth+ ) is
reached. Then # is switched from %= to %P.
>ith one leg of # at %P$ the output ramps down until the Lower Threshold ( Vth- ) is
reached. Then # is switched from %P to %=.

Comparator :
#eplacing the switch and %P5%= levels in the simplified circuit above. An ,p Amp Comparator
with two thresholds. This simple yet wondrous circuit changes itqs output state from %= to %P Aor
vise-versaB depending on the upper %thF and lower %th- thresholds.
%thFM-%=|#+5#6
%th- M -%P | #+ 5 #6
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Comparator >orkingE
o >hen %in P %thF$ the output switches to %P$ the P,-T%/ output state.
o >hen %in U %th-$ the output switches to %=$ the =/(AT%/ output state.
Vener diodes D+ and D6 set the positive and negative output levelsE
V)>Vf$7CV4$2
V* > Vf$2 C V4$7.
These output levels do double duty. =ot only do they set the comparator thresholds$ but also set the
voltage levels for the ne7t stage - the integrator.
SAW-TOOTH WAVE GENERATOR
Circuit Diagram:
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Output Waveform:
The sawtooth wave oscillator which used the operational amplifier.
The composition of this circuit is the same as the triangular wave oscillator basically and is using
two operational amplifiers. At the circuit diagram above$ CA+56B is the -chmitt circuit and CA656B
is the integration circuit.
The difference with the triangular wave oscillator is to be changing the time of the charging and
the discharging of the capacitor. >hen the output of CA+56B is positive voltage$ it charges rapidly
by the small resistanceA#+B value.A>hen the integration output voltage fallsB >hen the output of
CA+56B is negative voltage$ it is made to charge gradually at the big resistanceA#6B value. The
output waveform of the integration circuit becomes a form like the tooth of the saw.
-uch voltage is used for the control of the electron beam Athe scanning lineB of the television$
>hen picturing a picture at the cathode-ray tube$ an electron beam is moved comparative slow.
A>hen the electron beam moves from the left to the right on the screenB
,p-amp
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>hen turning back$ it is rapidly moved.A>hen moving from the right to the leftB
Like the triangular wave oscillator$ the line voltage needs both of the positive power supply and
the negative power supply. Also$ to work in the oscillation$ the condition of #:P#* is necessary.
<owever$ when making the value of #* small compared with #:$ the output voltage becomes
small. The near value is good for #: and #*. oou may make opposite if not oscillating using the
resistor with the same value. The circuit diagram above is using the resistor with the value which is
different to make oscillate surely.
The oscillation fre0uency can be calculated by the following formula.
>hen calculating at the value which is shown with the circuit diagram$
the oscillation fre0uency is as follows.
f M A+56CA#
+
F#
6
BB7A#
:
5#
*
B
M A+5A679.+7+9
-2
7A1.27+9
:
F+997+9
:
BB7A+697+9
:
5+997+9
:
B
M A+5A6+.+67+9
-:
BB7+.6
M 12.8 <4
A Typical Sawtooth Wave Generator Circuit
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The circuit shown here is an another e7ample of a sawtooth wave generator. Like the previous
circuit this circuit produces two outputs. ,ne is the %
-T
$ the sawtooth voltage from the integrator.
And the another output from the comparator switching from negative saturation to 4ero level as
shown in the output waveform. The output from the integrator acts as a comparision voltage for the
comparator with the threshold voltage generated from the potential divider.
OUPUT WAVEFORM
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FUNCTION GENERATOR IC 8038:
.igE .unctional block diagram of .unction generator
Output Waveform:
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t consists of two current sources$ two comparators$ two buffers$ one .. and a sine wave converter.
Pin descriptionE
Pin + @ Pin +6E -ine wave ad;ustsE
The distortion in the sine wave output can be reduced by ad;usting the +993` pots
connected between pin+6 @ pin++ and between pin + @ 2.
Pin 6 -ine >ave ,utputE
-ine wave output is available at this pin. The amplitude of this sine wave is 9.66 %cc.
>here Z 1% R %cc R Z +1 %.
Pin : Triangular >ave outputE
Triangular wave is available at this pin. The amplitude of the triangular wave is 9.::%cc.
>here Z 1% R %cc R Z +1 %.
Pin * @ Pin 1 Duty cycle 5 .re0uency ad;ustE
The symmetry of all the output wave forms @ 19Q duty cycle for the s0uare wave output
is ad;usted by the e7ternal resistors connected from %cc to pin *. These e7ternal resistors @
capacitors at pin +9 will decide the fre0uency of the output wave forms.
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Pin 2 F %ccE
Positive supply voltage the value of which is between +9 @ :9% is applied to this pin.
Pin ) E ." &iasE
This pin along with pin no8 is used to T/-T the C 89:8.
Pin? E -0uare >ave ,utputE
A s0uare wave output is available at this pin. t is an open collector output so that this pin
can be connected through the load to different power supply voltages. This arrangement is very
useful in making the s0uare wave output.
Pin +9 E Timing CapacitorsE
The e7ternal capacitor C connected to this pin will decide the output fre0uency along with
the resistors connected to pin * @ 1.
Pin ++ E -%
//
or (roundE
f a single polarity supply is to be used then this pin is connected to supply ground @ if AZB
supply voltages are to be used then A-B supply is connected to this pin.
Pin +: @ Pin +*E =C A=o ConnectionB
mportant features of C 89:8E
+. All the outputs are simultaneously available.
6. .re0uency range E 9.99+<4 to 199k<4
:. Low distortion in the output wave forms.
*. Low fre0uency drift due to change in temperature.
1. /asy to use.
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ParametersE
AiB .re0uency of the output wave formE
The output fre0uency dependent on the values of resistors #+ @ #6 along with the e7ternal
capacitor C connected at pin +9.
f #
A
M #
&
M # @ if #
C
is ad;usted for 19Q duty cycle then
fo M
RC
: . 9
e #
A
M #+$ #
&
M #:$ #
C
M #6
AiiB Duty cycle 5 .re0uency Ad;ust E APin * @ 1BE
Duty cycle as well as the fre0uency of the output wave form can be ad;usted by controlling the
values of e7ternal resistors at pin * @ 1.
The values of resistors #
A
@ #
&
connected between %cc J pin * @ 1 respectively along
with the capacitor connected at pin +9 decide the fre0uency of the wave form.
The values of #
A
@ #
&
should be in the range of +k` to +"`.
AiiiB ." &iasE
The ." &ias input Apin)B corresponds to the ;unction of resistors #+ @ #6.
The voltage %in is the voltage between %cc @ pin8 and it decides the output fre0uency.
The output fre0uency is proportional to %in as given by the following e7pression
.or #
A
M #
&
A19Q duty cycleB.
fo M
CRAVcc
Vin 1 . +
e where C is the timing capacitor
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>ith pin ) @ 8 connected to each other the output fre0uency is given by
fo M
RC
: . 9
where # M #
A
M #
&
for 19Q duty cycle.
This is because %in M
6 +
+
R R
R
+
%cc
AivB ." -weep input Apin 8BE
This input should be connected to pin )$ if we want a constant output fre0uency.
&ut if the output fre0uency is supposed to vary$ then a variable dc voltage should be
applied to this pin.
The voltage between %cc @ pin 8 is called %in and it decides the output fre0uency as$
+.1 %in
fo M ---------------
C #
A
%cc
A potentiometer can be connected to this pin to obtain the re0uired variable voltage re0uired to
change the output fre0uency.
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THE 555 TIMER IC
The 111 is a monolithic timing circuit that can produce accurate @ highly stable time delays or
oscillation. The timer basically operates in one of two modesE either
AiB "onostable Aone - shotB multivibrator or
AiiB Astable Afree runningB multivibrator
The important features of the 111 timer are theseE
AiB t operates on F1v to F+8 v supply voltages
AiiB t has an ad;ustable duty cycle
AiiiB Timing is from microseconds to hours
AivB t has a current o5p
PIN CONFIGURATION OF 555 TIMER:
Pin description:
Pin 1: Ground:
All voltages are measured with respect to this terminal.
Pin 2: Trigger:
The o5p of the timer depends on the amplitude of the e7ternal trigger pulse applied to this
pin.
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Pin 3: Output:
There are 6 ways a load can be connected to the o5p terminal either between pin: @ ground
or between pin : @ supply voltage
A&etween Pin : @ (round ,= load B
A&etween Pin : @ F %cc ,.. load B
AiB >hen the input is lowE
The load current flows through the load connected between Pin : @ F%cc in to the
output terminal @ is called the sink current.
AiiB >hen the output is highE
The current through the load connected between Pin : @ F%cc Ai.e. ,= loadB is
4ero. <owever the output terminal supplies current to the normally ,.. load. This
current is called the source current.
Pin 4: Reset:
The 111 timer can be reset AdisabledB by applying a negative pulse to this pin. >hen the
reset function is not in use$ the reset terminal should be connected to F%cc to avoid any false
triggering.
Pin 5: Control voltage:
An e7ternal voltage applied to this terminal changes the threshold as well as trigger
voltage. n other words by connecting a potentiometer between this pin @ (=D$ the pulse width of
the output waveform can be varied. >hen not used$ the control pin should be bypassed to ground
with 9.9+ capacitor to prevent any noise problems.
Pin 6: Threshold:
This is the non inverting input terminal of upper comparator which monitors the voltage
across the e7ternal capacitor.
Pin 7: Discharge:
This pin is connected internally to the collector of transistor L+.
>hen the output is high L+ is ,...
>hen the output is low L is AsaturatedB ,=.
Pin 8: +Vcc:
The supply voltage of F1% to F+8% is applied to this pin with respect to ground.
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Block Diagram of 555 Timer IC:
.rom the above figure$ three 1k internal resistors act as voltage divider providing bias voltage of
65: %cc to the upper comparator @ +5: %cc to the lower comparator. t is possible to vary time
electronically by applying a modulation voltage to the control voltage input terminal A1B.
AiB n the -table stateE
The output of the control .. is high. This means that the output is low because of power
amplifier which is basically an inverter. L M +e ,utput M 9
AiiB At the =egative going trigger pulseE
The trigger passes through A%cc5:B the output of the lower comparator goes high @ sets the
... L M +e L M 9
AiiiB At the Positive going trigger pulseE t passes through 65:%cc$ the output of the upper
comparator goes high and resets the ... L M 9e L M +
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The reset input Apin *B provides a mechanism to reset the .. in a manner which overrides the
effect of any instruction coming to .. from lower comparator.
Monostable Operation:
.ig E 111 connected as a "onostable "ultivibrator
Model Graph:
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nitially when the output is low$ i.e. the circuit is in a stable state$ transistor L+ is ,= @ capacitor
C is shorted to ground. The output remains low. During negative going trigger pulse$ transistor L+
is ,..$ which releases the short circuit across the e7ternal capacitor C @ drives the output high.
=ow the capacitor C starts charging toward %cc through #
A
. >hen the voltage across the capacitor
e0uals 65: %cc$ upper comparator switches from low to high. i.e. L

M 9$ the transistor L+ M ,.. e
the output is high.
AaB
AbB
AcB
AdB
AeB
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-ince C is unclamped$ voltage across it rises e7ponentially through # towards %cc with a time
constant #C Afig bB as shown in below. After the time period$ the upper comparator resets the ..$
i.e. L M +$ L+ M ,=e the output is low.Si.e discharging the capacitor C to ground potential Afig cBT.
The voltage across the capacitor as in fig AbB is given by
%c M %cc A+-e
-t5#C
B vvvvv. A+B
Therefore At t M T$ %c M 65: %cc
65: %cc M %ccA+-e
-T5#C
B
or
T M #C ln A+5:B
,r
T M +.+#C seconds vvvvv. A6B
f the reset is applied L6 M ,..$ L+ M ,=$ timing capacitor C immediately discharged. The output
now will be as in figure Ad @ eB. f the reset is released output will still remain low until a negative
going trigger pulse is again applied at pin 6.
Applications of Monostable Mode of Operation:
(a) Frequency Divider:
The 111 timer as a monostable mode. t can be used as a fre0uency divider by ad;usting the
length of the timing cycle t
p
with respect to the time period T of the trigger input. To use the
monostable multivibrator as a divide by 6 circuit$ the timing interval t
p
must be a larger than the
time period of the trigger input. SDivide by 6 t
p
P T of the triggerT
&y the same concept$ to use the monostable multivibrator as a divide by : circuit$ t
p
must
be slightly larger than twice the period of the input trigger signal @ so on$ S divide by : t
p
P 6T
of triggerT
(b) Pulse width modulation:
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.igE Pulse >idth "odulation
,utput >aveform
Pulse width of a carrier wave changes in accordance with the value of a incoming
Amodulating signalB is known as P>". t is basically monostable multivibrator. A modulating
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signal is fed in to the control voltage Apin 1B. nternally$ the control voltage is ad;usted to 65: %cc
e7ternally applied modulating signal changes the control voltage level of upper comparator. As a
result$ the re0uired to change the capacitor up to threshold voltage level changes$ giving P>"
output.
(c) Pulse Stretcher:
This application makes use of the fact that the output pulse width Atiming intervalB of the
monostable multivibrator is of longer duration than the negative pulse width of the input trigger.
As such$ the output pulse width of the monostable multivibrator can be viewed as a stretched
version of the narrow input pulse$ hence the name \ Pulse stretcherj. ,ften$ narrow !pulse width
signals are not suitable for driving an L/D display$ mainly because of their very narrow pulse
widths. n other words$ the L/D may be flashing but not be visible to the eye because its on time is
infinitesimally small compared to its off time. The 11 pulse stretcher can be used to remedy this
problem. The L/D will be ,= during the timing interval t
p
M +.+#
A
C which can be varied by
changing the value of #
A
@ C.

.igE Pulse -tretcher
The 555 timer as an Astable Multivibrator:
An Astable multivibrator$ often called a free running multivibrator$ is a rectangular
wave generating circuit. Dnlike the monostable multivibrator$ this circuit does not re0uire an
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e7ternal trigger to change the state of the output$ hence the name free running. <owever$ the time
during which the output is either high or low is determined by 6 resistors and capacitors$ which are
e7ternally connected to the 11 timer.
Fig: Astable Multivibrator
Model Graph
The above figures show the 111 timer connected as an astable multivibrator and its model graph
Initially, when the output is high E
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Capacitor C starts charging toward %cc through #
A
@ #
&
. <owever$ as soon as voltage across the
capacitor e0uals 65: %cc. Dpper comparator triggers the .. @ output switches low.
When the output becomes Low:
Capacitor C starts discharging through #
&
and transistor L+$ when the voltage across C e0uals +5:
%cc$ lower comparator output triggers the .. @ the output goes <igh. Then cycle repeats. The
capacitor is periodically charged @ discharged between 65: %cc @ +5: %cc respectively. The time
during which the capacitor charges from +5: %cc to 65: %cc e0ual to the time the output is high @
is given by
t
c
M A#
A
F#
&
BC ln 6vvvvvA+B >here Sln 6 M 9.2?T

M 9.2? A#
A
F#
&
BC
>here #
A
@ #
&
are in ohms. And C is in farads.
-imilarly$ the time during which the capacitors discharges from 65: %cc to +5: %cc is e0ual to the
time$ the output is low and is given by$
t
c
M #
&
C ln 6

t
d
M 9.2? #
&
C vvvvvvv..A6B
where #
&
is in ohms and C is in farads.
Thus the total period of the output waveform is
T M t
c
F t
d
M 9.2? A#
A
F6#
&
BC vvvvv.A:B
This$ in turn$ gives the fre0uency of oscillation as$f
9
M +5T M +.*15A#
A
F6#
&
BC vvvA*B
/0uation * indicates that the fre0uency f
9
is independent of the supply voltage %cc. ,ften the term
duty cycle is used in con;unction with the astable multivibrator. The duty cycle is the ratio of the
time t
c
during which the output is high to the total time period T. t is generally e7pressed as a
percentage.
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Q duty cycle M At
c
5 T BJ +99
Q DC M SA#
A
F#
&
B5 5A#
A
F6#
&
BT J +99
Astable Multivibrator Applications:
(a) Square wave oscillator:
.igE -0uare >ave ,scillator
>ith out reducing #
A
M 9 ohm$ the astable multivibrator can be used to produce s0uare
wave output. -imply by connecting diode D across #esistor #
&
. The capacitor C charges through
#
A
@ diode D to appro7imately
65: %cc @ discharges through #
&
@ L+ until the capacitor voltage e0uals appro7imately +5: %cc$
then the cycle repeats.
To obtain a s0uare wave output$ #
A
must be a combination of a fi7ed resistor @ potentiometer so
that the potentiometer can be ad;usted for the e7act s0uare wave.
(b) Free running Ramp generator:
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The astable multivibrator can be used as a free ! running ramp generator when resistor #
A
@ #
&
are replaced by a current mirror.
The current mirror starts charging capacitor C toward %cc at a constant rate.
>hen voltage across C equals to 2/3 Vcc$ upper comparator turns transistor L+ ,= @ C
rapidly discharges through transistor L+.
>hen voltage across C equals to 1/3 Vcc$ lower comparator switches transistor ,.. @
then capacitor C starts charging up again..
Thus the charge ! discharge cycle keeps repeating.
The discharging time of the capacitor is relatively negligible compared to its charging time.
The time period of the ramp waveform is e0ual to the charging time @ is appro7imately is
given by$
T M %ccC5:
C
vvvvvvvvvv A+B

C
M A%cc - %
&/
B5# M constant current
Therefore the free ! running fre0uency of ramp generator is
f
9
M :
C
5 %cc C vvvvvvvvv.A6B
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SWITCHING REGULATORS
Introduction
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The switching regulator is increasing in popularity because it offers the advantages of higher
power conversion efficiency and increased design fle7ibility Amultiple output voltages of different
polarities can be generated from a single input voltageB.

Although most power supplies used in amateur shacks are of the linear regulator type$ an
increasing number of switching power supplies have become available to the amateur. .or
most amateurs the switching regulator is still somewhat of a mystery. ,ne might wonder
why we even bother with these power supplies$ when the e7isting linear types work ;ust fine.
The primary advantage of a switching regulator is very high efficiency$ a lot less heat and
smaller si4e. To understand how these black bo7es work lets take a look at a traditional
linear regulator at right. As we see in the diagram$ the linear regulator is really nothing more
than a variable resistor. The resistance of the regulator varies in accordance with the load
resulting in a constant output voltage


The primary filter capacitor is placed on the input to the regulator to help filter out the 29
cycle ripple. The linear regulator does an e7cellent ;ob but not without cost. .or e7ample$ if
the output voltage is +6 volts and the input voltage is 6* volts then we must drop +6 volts
across the regulator. At output currents of +9 amps this translates into +69 watts A+6 volts
times +9 ampsB of heat energy that the regulator must dissipate. s it any wonder why we
have to use those massive heat sinks} As we can see this results in a mere 19Q efficiency for
the linear regulator and a lot of wasted power which is normally transformed into heat.
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The time that the switch remains closed during each switch cycle is varied to maintain a
constant output voltage. =otice that the primary filter capacitor is on the output of the
regulator and not the input. As is apparent$ the switching regulator is much more efficient
than the linear regulator achieving efficiencies as high as 89Q to ?1Q in some circuits. The
obvious result is smaller heat sinks$ less heat and smaller overall si4e of the power supply.
The previous diagram is really an over simplification of a switching regulator circuit. An
actual switching regulator circuit more closely resembles the circuit belowE =ow lets take a
look at a very basic switching regulator at right.
As we see can see$ the switching regulator is really nothing more than ;ust a simple switch.
This switch goes on and off at a fi7ed rate usually between 193h4 to +993h4 as set by the
circuit.



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As we see above the switching regulator appears to have a few more components than a
linear regulator. Diode D+ and nductor L+ play a very specific role in this circuit and are
found in almost every switching regulator. .irst$ diode D+ has to be a -chottky or other
very fast switching diode. A +=*99+ ;ust wonqt switch fast enough in this circuit. nductor
L+ must be a type of core that does not saturate under high currents. Capacitor C+ is
normally a low /-# A/0uivalent -eries #esistanceB type.
To understand the action of D+ and L+$ lets look at what happens when -+ is closed as
indicated belowE


As we see above$ L+$ which tends to oppose the rising current$ begins to generate an
electromagnetic field in its core. =otice that diode D+ is reversed biased and is essentially
an open circuit at this point. =ow lets take a look at what happens when -+ opens belowE



As we see in this diagram the electromagnetic field that was built up in L+ is now
discharging and generating a current in the reverse polarity. As a result$ D+ is now
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conducting and will continue until the field in L+ is diminished. This action is similar to the
charging and discharging of capacitor C+. The use of this inductor5diode combination gives
us even more efficiency and augments the filtering of C+.
&ecause of the uni0ue nature of switching regulators$ very special design considerations are
re0uired. &ecause the switching system operates in the 19 to +99 k<4 region and has an
almost s0uare waveform$ it is rich in harmonics way up into the <. and even the %<.5D<.
region. -pecial filtering is re0uired$ along with shielding$ minimi4ed lead lengths and all
sorts of toroidal filters on leads going outside the case. The switching regulator also has a
minimum load re0uirement$ which is determined by the inductor value. >ithout the
minimum load$ the regulator will generate e7cessive noise and harmonics and could even
damage itself. AThis is why it is not a good idea to turn on a computer switching power
supply without some type of load connected.B To meet this re0uirement$ many designers use
a cooling fan and or a minimum load which switches out when no longer needed.
.ortunately$ recent switching regulator Cqs address most of these design problems 0uite
well. &ecause of lowered component costs as well as a better understanding of switching
regulator technology$ we are starting to see even more switching power supplies replacing
traditionally linear only applications. t is no doubt that we will see fewer linear power
supplies being used in the future.
n this article we addressed basic switching regulator design concepts and it is hoped that
amateurs will begin to look at switching regulators much more seriously when they decide
to replace an old power supply. n a future construction article$ we will review an actual
switching regulator circuit.
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IC VOLTAGE REGULATORS
.our most commonly used switching converter typesE
&uckE used the reduce a DC voltage to a lower DC voltage.
&oostE provides an output voltage that is higher than the input.
&uck-&oost AinvertBE an output voltage is generated opposite in polarity to the input.
.lybackE an output voltage that is less than or greater than the input can be generated$ as well as
multiple outputs.
ConvertersE
Push-PullE A two-transistor converter that is especially efficient at low input voltages.
<alf-&ridgeE A two-transistor converter used in many off-line applications.
.ull-&ridgeE A four-transistor converter Ausually used in off-line designsB that can
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generate the highest output power of all the types listed.
Application information will be provided along with circuit e7amples that illustrate
some applications of &uck$ &oost$ and .lyback regulators.
Switching Fundamentals
The law of inductance
f a voltage is forced across an inductor$ a current will flow through that inductor Aand
this current will vary with timeB. The current flowing in an inductor will be time-varying even if
the forcing voltage is constant. t is e0ually correct to say that if a time-varying current is forced to
flow in an inductor$ a voltage across the inductor will result. The fundamental law that defines the
relationship between the voltage and current in an inductor is given by the e0uationE
v M L Adi5dtB
Two important characteristics of an inductor that follow directly from the law of
inductance areE
+B A voltage across an inductor results only from a current that changes with
time. A steady ADCB current flowing in an inductor causes no voltage across it
Ae7cept for the tiny voltage drop across the copper used in the windingsB.
6B A current flowing in an inductor can not change value instantly Ain 4ero timeB$ as this would
re0uire infinite voltage to force it to happen. <owever$ the faster the current is changed in an
inductor$ the larger the resulting voltage will be. =oteE Dnlike the current flowing in the inductor$
the voltage across it can change instantly Ain 4ero timeB. The principles of inductance are illustrated
by the information contained in .igure.
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The important parameter is the di5dt term$ which is simply a measure of how the
current changes with time. >hen the current is plotted versus time$ the value of
di5dt is defined as the slope of the current plot at any given point. The graph on the left shows that
current which is constant with time has a di5dt value of 4ero$ and results in no voltage across the
inductor. The center graph shows that a current which is increasing with time has a positive di5dt
value$ resulting in a positive inductor voltage.
Current that decreases with time Ashown in the right-hand graphB gives a negative
value for di5dt and inductor voltage. t is important to note that a linear current ramp in an inductor
Aeither up or downB occurs only when it has a constant voltage across it.
Transformer Operation:
A transformer is a device that has two or more magnetically-coupled windings. The
basic operation is shown in .igure. The action of a transformer is such that a time-varying AACB
voltage or current is transformed to a higher or lower value$ as set by the transformer turns ratio.
The transformer does not add power$ so it follows that the power A% ^ B on either side must be
constant. That is the reason that the winding with more turns has higher voltage but lower current$
while the winding with less turns has lower voltage but higher current.
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The dot on a transformer winding identifies its polarity with respect to another winding$ and
reversing the dot results in inverting the polarity.
/7ample of Transformer ,perationE
An e7cellent e7ample of how a transformer works can be found under the hood of your car$ where
a transformer is used to generate the *9 k% that fires carHs spark plugs.
Spark Firing Circuit:
The CcoilC used to generate the spark voltage is actually a transformer$ with a very high secondary-
to-primary turns ratio. >hen the points first close$ current starts to flow in the primary winding
and eventually reaches the final value set by the +6% battery and the current limiting resistor. At
this time$ the current flow is a fi7ed DC value$ which means no voltage is generated across either
winding of the transformer.
>hen the points open$ the current in the primary winding collapses very 0uickly$ causing a large
voltage to appear across this winding. This voltage on the primary is magnetically coupled to Aand
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stepped up byB the secondary winding$ generating a voltage of :9 k% - *9 k% on the secondary
side. As e7plained previously$ the law of inductance says that it is not possible to instantly break
the current flowing in an inductor Abecause an infinite voltage would be re0uired to make it
happenB.
This principle is what causes the arcing across the contacts used in switches that are in circuits
with highly inductive loads. >hen the switch ;ust begins to open$ the high voltage generated
allows electrons to ;ump the air gap so that the current flow does not actually stop instantly.
Placing a capacitor across the contacts helps to reduce this arcing effect. n the automobile
ignition$ a capacitor is placed across the points to minimi4e damage due to arcing when the points
CbreakC the current flowing in the low-voltage coil winding Ain car manuals$ this capacitor is
referred to as a CcondenserCB.
Pulse Width Modulation (PWM):
All of the switching converters that will be covered in this paper use a form of output voltage
regulation known as Pulse >idth "odulation AP>"B. Put simply$ the feedback loop ad;usts
AcorrectsB the output voltage by changing the ,= time of the switching element in the converter.
As an e7ample of how P>" works$ we will e7amine the result of applying a series of s0uare wave
pulses to an L-C filter Asee .igureB.
The series of s0uare wave pulses is filtered and provides a DC output voltage that is e0ual to the
peak pulse amplitude multiplied times the duty cycle Aduty cycle is defined as the switch ,= time
divided by the total periodB. This relationship e7plains how the output voltage can be directly
controlled by changing the ,= time of the switch.
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-witching Converter Topologies
The most commonly used DC-DC converter circuits will now be presented along with
the basic principles of operation.
Buck Regulator:
The most commonly used switching converter is the &uck$ which is used to down-convert a DC
voltage to a lower DC voltage of the same polarity. This is essential in systems that use distributed
power rails Alike 6*% to *8%B$ which must be locally converted to +1%$ +6% or 1% with very little
power loss. The &uck converter uses a transistor as a switch that alternately connects and
disconnects the input voltage to an inductor Asee .igureB.
The lower diagrams show the current flow paths Ashown as the heavy linesB when the switch is on
and off. >hen the switch turns on$ the input voltage is connected to the inductor. The difference
between the input and output voltages is then forced across the inductor$ causing current through
the inductor to increase. During the on time$ the inductor current flows into both the load and the
outputcapacitor Athe capacitor charges during this timeB.
>hen the switch is turned off$ the input voltage applied to the inductor is removed. <owever$ since
the current in an inductor can not change instantly$ the voltage across the inductor will ad;ust to
hold the current constant. The input end of the inductor is forced negative in voltage by the
decreasing current$ eventually reaching the point where the diode is turned on. The inductor
current then flows through the load and back through the diode. The capacitor discharges into the
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load during the off time$ contributing to the total current being supplied to the load Athe total load
current during the switch off time is the sum of the inductor and capacitor currentB.
The shape of the current flowing in the inductor is similar to previous figure. As e7plained$ the
current through the inductor ramps up when the switch is on$ and ramps down when the switch is
off. The DC load current from the regulated output is the average value of the inductor current.
The peak-to-peak difference in the inductor current waveform is referred to as the inductor ripple
current$ and the inductor is typically selected large enough to keep this ripple current less than 69Q
to :9Q of the rated DC current.
Continuous vs. Discontinuous operation
n most &uck regulator applications$ the inductor current never drops to 4ero during
.ull-load operation Athis is defined as continuous mode operationB. ,verall performance is usually
better using continuous mode$ and it allows ma7imum output power to be obtained from a given
input voltage and switch current rating. n applications where the ma7imum load current is fairly
low$ it can be advantageous to design for discontinuous mode operation. n these cases$ operating
in discontinuous mode can result in a smaller overall converter si4e Abecause a smaller inductor
can be usedB.Discontinuous mode operation at lower load current values is generally harmless$ and
even converters designed for continuous mode operation at full load will become discontinuous as
the load current is decreased Ausually causing no problemsB.
Boost Regulator:
The &oost regulator takes a DC input voltage and produces a DC output voltage that is higher in
value than the input Abut of the same polarityB. The &oost regulator is shown in .igure$ along with
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details showing the path of current flow during the switch on and off time. >henever the switch is
on$ the input voltage is forced across the inductor which causes the current through it to increase
Aramp upB.
>hen the switch is off$ the decreasing inductor current forces the CswitchC end of the inductor to
swing positive. This forward biases the diode$ allowing the capacitor to charge up to a voltage that
is higher than the input voltage. During steady-state operation$ the inductor current flows into both
the output capacitor and the load during the switch off time. >hen the switch is on$ the load
current is supplied only by the capacitor.
Output Current and Load power:
An important design consideration in the &oost regulator is that the output load current and the
switch current are not e0ual$ and the ma7imum available load current is always less than the
current rating of the switch transistor. t should be noted that the ma7imum total power available
for conversion in any regulator is e0ual to the input voltage multiplied times the ma7imum
average input current Awhich is less than the current rating of the switch transistorB. -ince the
output voltage of the &oost is higher than the input voltage$ it follows that the output current must
be lower than the input current.
Buck-Boost (Inverting) Regulator:
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The &uck-&oost or nverting regulator takes a DC input voltage and produces a DC output voltage
that is opposite in polarity to the input. The negative output voltage can be either larger or smaller
in magnitude than the input voltage. The nverting regulator is shown in .igure.
>hen the switch is on$ the input voltage is forced across the inductor$ causing an increasing
current flow through it. During the on time$ the discharge of the output capacitor is the only
source of load current. This re0uires that the charge lost from the output capacitor during the on
time be replenished during the off time. >hen the switch turns off$ the decreasing current flow in
the inductor causes the voltage at the diode end to swing negative. This action turns on the diode$
allowing the current in the inductor to supply both the output capacitor and the load. As shown$ the
load current is supplied by inductor when the switch is off$ and by the output capacitor when the
switch is on.
Flyback Regulator:
The .lyback is the most versatile of all the topologies$ allowing the designer to create one or more
output voltages$ some of which may be opposite in polarity. .lyback converters have gained
popularity in battery-powered systems$ where a single voltage must be converted into the re0uired
system voltages Afor e7ample$ F1%$ F+6% and -+6%B with very high power conversion efficiency.
The basic single-output flyback converter is shown in .igure.
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The most important feature of the .lyback regulator is the transformer phasing$ as shown by the
dots on the primary and secondary windings. >hen the switch is on$ the input voltage is forced
across the transformer primary which causes an increasing flow of current through it. =ote that
the polarity of the voltage on the primary is dot-negative Amore negative at the dotted endB$
causing a voltage with the same polarity to appear at the transformer secondary Athe magnitude of
the secondary voltage is set by the transformer seconday-to-primary turns ratioB.
The dot-negative voltage appearing across the secondary winding turns off the diode$ reventing
current flow in the secondary winding during the switch on time. During this time$ the load
current must be supplied by the output capacitor alone. >hen the switch turns off$ the decreasing
current flow in the primary causes the voltage at the dot end to swing positive. At the same time$
the primary voltage is reflected to the secondary with the same polarity. The dot-positive voltage
occurring across the secondary winding turns on the diode$ allowing current to flow into both the
load and the output capacitor. The output capacitor charge lost to the load during the switch on
time is replenished during the switch off time. .lyback converters operate in either continuous
mode Awhere the secondarycurrent is always P9B or discontinuous mode Awhere the secondary
current falls to 4ero on each cycleB.
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Generating Multiple Outputs:
Another big advantage of a .lyback is the capability of providing multiple outputs .n such
applications$ one of the outputs Ausually the highest currentB is selected to provide P>" feedback
to the control loop$ which means this output is directly regulated. The other secondary windingAsB
are indirectly regulated$ as their pulse widths will follow the regulated winding. The load
regulation on the unregulated secondaries is not great Atypically 1 - +9QB$ but is ade0uate for many
applications.
f tighter regulation is needed on the lower current secondaries$ an LD, post-regulator is an
e7cellent solution. The secondary voltage is set about +% above the desired output voltage$ and
the LD, provides e7cellent output regulation withvery little loss of efficiency.
The Push-Pull converter uses two to transistors perform DC-DC conversion.The converter operates
by turning on each transistor on alternate cycles Athe two transistors are never on at the same timeB.
Transformer secondary current flows at the same time as primary current Awhen either of the
switches is onB. .or e7ample$ when transistor CAC is turned on$ the input voltage is forced across
the upper primary winding with dot-negative polarity. ,n the secondary side$ a dot-negative
voltage will appear across the winding which turns on the bottom diode.This allows current to flow
into the inductor to supply both the output capacitor and the load. >hen transistor C&C is on$ the
input voltage is forced across the lower primary winding with dot-positive polarity.
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The same voltage polarity on the secondary turns on the top diode$ and current flows into the
output capacitor and the load. An important characteristic of a Push-Pull converter is that the
switch transistors have to be able the stand off more than twice the input voltageE when one
transistor is on Aand the input voltage is forced across one primary windingB the same magnitude
voltage is induced across the other primary winding$ but it is CfloatingC on top of the input voltage.
This puts the collector of the turned-off transistor at twice the input voltage with respect to ground.
The Cdouble input voltageC rating re0uirement of the switch transistors means the Push-Pull
converter is best suited for lower input voltage applications. t has been widely used in converters
operating in +6% and 6*% battery-powered systems.
.igure shows a timing diagram which details the relationship of the input and output pulses. t is
important to note that fre0uency of the secondary side voltage pulses is twice the fre0uency of
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operation of the P>" controller driving the two transistors. .or e7ample$ if the P>" control
chip was set up to operate at 19 k<4 on the primary
side$ the fre0uency of the secondary pulses would be +99 k<4.
This highlights why the Push-Pull converter is well-suited for low voltage converters.
The voltage forced across each primary winding Awhich provides the power for conversionB is the
full input voltage minus only the saturation voltage of the switch. f ",--./T power switches are
used$ the voltage drop across the switches can be made e7tremely small$ resulting in very high
utili4ation of the available input voltage. Another advantage of the Push-Pull converter is that it
can also generate multiple output voltages Aby adding more secondary windingsB$ some of which
may be negative in polarity. This allows a power supply operated from a single battery to provide
all of the voltages necessary for system operation.
A disadvantage of Push-Pull converters is that they re0uire very good matching of
the switch transistors to prevent une0ual on times$ since this will result in saturation
of the transformer core Aand failure of the converterB.
Output Capacitor ESR effects:
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The primary function of the output capacitor in a switching regulator is filtering. As the converter
operates$ current must flow into and out of the output filter capacitor. The /-# of the output
capacitor directly affects the performance of the switching regulator. /-# is specified by the
manufacturer on good 0uality capacitors$ but be certain that it is specified at the fre0uency of
intended operation.
(eneral-purpose electrolytes usually only specify /-# at +69 <4$ but capacitors intended for high-
fre0uency switching applications will have the /-# guaranteed at high fre0uency Alike 69 k<4 to
+99 k<4B. -ome /-# dependent parameters areE #ipple %oltageE n most cases$ the ma;ority of
the output ripples voltage results from the /-# of the output capacitor. f the /-# increases Aas it
will at low operating temperaturesB the output ripple voltage will increase accordingly.
/fficiencyE As the switching current flows into and out of the capacitor Athrough the /-#B$ power
is dissipated internally. This CwastedC power reduces overall regulator efficiency$ and can also
cause the capacitor to fail if the ripple current e7ceeds the ma7imum allowable specification for
the capacitor.
Loop -tabilityE The /-# of the output capacitor can affect regulator loop stability. Products such
as the L"61)1 and L"61)) are compensated for stability assumingthe /-# of the output
capacitor will stay within a specified range. 3eeping the /-# within the CstableC range is not
always simple in designs that must operate over a wide temperature range. The /-# of a typical
aluminum electrolytic may increase by *9^ as the temperature drops from 61wC to -*9wC.
n these cases$ an aluminum electrolytic must be paralleled by another type ofcapacitor with a
flatter /-# curve Alike Tantalum or .ilmB so that the effective /-# Awhich is the parallel value of
the two /-#qsB stays within the allowable range. =oteE if operation below -*9wC is necessary$
aluminum electrolytics are probably not feasible for use.
Bypass Capacitors:
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<igh-fre0uency bypass capacitors are always recommended on the supply pins of C devices$ but
if the devices are used in assemblies near switching converters bypass capacitors are absolutely
re0uired. The components which perform the high-speed switching Atransistors and rectifiersB
generate significant /" that easily radiates into PC board traces and wire leads. To assure proper
circuit operation$ all C supply pins must be bypassed to a clean$ low-inductance ground.

Proper Grounding:
The CgroundC in a circuit is supposed to be at one potential$ but in real life it is not.
>hen ground currents flow through traces which have non-4ero resistance$ voltage
differences will result at different points along the ground path. n DC or low-fre0uency circuits$
Cground managementC is comparatively simpleE the only parameter of critical importance is the
DC resistance of a conductor$ since that defines the voltage drop across it for a given current. n
high-fre0uency circuits$ it is the inductance of a trace or conductor that is much more important.
n switching converters$ peak currents flow in high-fre0uency AP 19 k<4B pulses$ which can cause
severe problems if trace inductance is high. "uch of the CringingC and CspikingC seen on voltage
waveforms in switching converters is the result of high current being switched through parasitic
trace Aor wireB inductance.Current switching at high fre0uencies tends to flow near the surface of a
conductor Athis is called Cskin effectCB$ which means that ground traces must be very wide on a PC
board to avoid problems. t is usually best Awhen possibleB to use one side of the PC board as a
ground plane. The following diagram shows the poor grounding.
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The layout shown has the high-power switch return current passing through a trace that also
provides the return for the P>" chip and the logic circuits. The switching current pulses flowing
through the trace will cause a voltage spike Apositive and negativeB to occur as a result of the rising
and falling edge of the switch current. This voltage spike follows directly from the v M L Adi5dtB
law of inductance. t is important to note that the magnitude of the spike will be different at all
points along the trace$ being largest near the power switch. Taking the ground symbol as a point
of reference$ this shows how all three circuits would be bouncing up and down with respect to
ground. "ore important$ they would also be moving with respect to each other.
"is-operation often occurs when sensitive parts of the circuit CrattleC up and down due to ground
switching currents. This can induce noise into the reference used to set the output voltage$
resulting in e7cessive output ripple. %ery often$ regulators that suffer from ground noise problems
appear to be unstable$ and break into oscillations as the load current is increased Awhich increases
ground currentsB. The figure shows good grounding.
A big improvement is made by using single-point grounding. A good high-fre0uency electrolytic
capacitor Alike solid TantalumB is used near the input voltage source to provide a good ground
point. All of the individual circuit elements are returned to this point using separate ground traces.
This prevents high current ground pulses from bouncing the logic circuits up and down.
Another important improvement is that the power switch Awhich has the highest ground pin
currentB is located as close as possible to the input capacitor. This minimi4es the trace inductance
along its ground path. t should also be pointed out that all of the individual circuit blocks have
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ClocalC bypass capacitors tied directly across them. The purpose of this capacitor is #. bypass$ so
it must be a ceramic or film capacitor Aor bothB.
A good value for bypassing logic devices would be 9.9+ K. ceramic capacitorAsB$ distributed as
re0uired.
f the circuit to be bypassed generates large current pulses Alike the power switchB$ more
capacitance is re0uired. A good choice would be an aluminum electrolytic bypassed with a film
and ceramic capacitor. /7act si4e depends on peak current$ but the more capacitance used$ the
better the result. Transformer5nductor Cores and #adiated =oise The type of core used in an
inductor or transformer directly affects its cost$ si4e$ and radiated noise characteristics. /lectrical
noise radiated by a transformer is e7tremely important$ as it may re0uire shielding to prevent
erratic operation of sensitive circuits located near the switching regulator. The most commonly
used core types will be presented$ listing the advantages and disadvantages of each.
Measuring Output Ripple Voltage:
The ripple appearing on the output of the switching regulator can be important to the circuits under
power. (etting an accurate measurement of the output ripple voltage is not always simple. f the
output voltage waveform is measured using an oscilloscope$ an accurate result can only be
obtained using a differential measurement method. The differential measurement shown uses the
second channel of the oscilloscope to Ccancel outC the signal that is common to both channels Aby
inverting the & channel signal and adding it to the A channelB.
The reason this method must be used is because the fast-switching components in a switching
regulator generate voltage spikes that have significant energy at very high fre0uencies. These
signals can be picked up very easily by CantennasC as small as the :C ground lead on the scope
probe. Assuming the probes are reasonably well matched$ the & channel probe will pick up the
same radiated signal as the A channel probe$ which allows this Ccommon-modeC signal to be
eliminated by adding the inverted channel & signal to channel A. t is often necessary to measure
the #"- output ripple voltage$ and this is usually done with some type of digital voltmeter. f the
reading obtained is to be meaningful$ the following must be consideredE
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Measuring Regulator Efficiency of DC-DC Converters:
The efficiency of a switching regulator is defined asE
yyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyy ~yyyyyM PL,AD 5 PT,TAL
n determining converter efficiency$ the first thing that must be measured is the total consumed
power APT,TALB. Assuming a DC input voltage$ PT,TAL is defined as the total power drawn
from the source$ which is e0ual toE
PT,TAL M %= ^ = AA%/B
t must be noted that the input current value used in the calculation must be the average value of
the waveform Athe input current will not be DC or sinusoidalB. &ecause the total power dissipated
must be constant from input to output$ PT,TAL is also e0ual to the load power plus the internal
regulator power lossesE
PT,TAL M PL,AD F PL,--/-
"easuring Aor calculatingB the power to the load is very simple$ since the output voltage and
current are both DC. The load power is found byE
PL,AD M %,DT ^ L,AD
"easuring the input power drawn from the source is not simple. Although the input voltage to the
regulator is DC$ the current drawn at the input of a switching regulator is not. f a typical Cclip-onC
current meter is used to measure the input current$ the taken data will be essentially meaningless.
The average input current to the regulator can be measured with reasonable accuracy by using a
wide-bandwidth current probe connected to an oscilloscope.
The average value of input current can be closely estimated by drawing a hori4ontal
line that divides the waveform in such a way that the area of the figure above the
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line will e0ual the CmissingC area below the line. n this way$ the CaverageC current shown is
e0uivalent to the value of DC current that would produce the same input power.
f more e7act measurements are needed$ it is possible to force the current in the line
going to the input of the DC-DC converter to be DC by using an L-C filter between
the power source and the input of the converter f the L-C filter components are ade0uate$ the
current coming from the output of the DC power supply will be DC current Awith no high-
fre0uency switching componentB which means it can be accurately measured with a cheap clip-on
ammeter and digital volt meter.
t is essential that a large$ low-/-# capacitor be placed at C= to support the input
of the switching converter. The L-C filter that the converter sees looking back into
the source presents a high impedance for switching current$ which means C= is
necessary to provide the switching current re0uired at the input of the converter.
"easuring #egulator /fficiency of ,ff-Line ConvertersE
,ff-Line converters are powered directly from the AC line$ by using a bridge rectifier
and capacitive filter to generate an unregulated DC voltage for conversion.
"easuring the total power drawn from the AC source is fairly difficult because of the
power factor. f both the voltage and current are sinusoidal$ power factor is
defined as the cosine of the phase angle between the voltage and current
waveforms.
The capacitive-input filter in an off-line converter causes the input current to be very
non-sinusoidal. The current flows in narrow$ high-amplitude pulses Acalled
<aversine pulsesB which re0uires that the power factor be re-defined in such cases.
.or capacitive-input filter converters$ power factor is defined asE
P... M P#/AL 5 PAPPA#/=T

LM 2577: An Example of a Complete FlyBack/ Boost Regulator IC
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LINEAR REGULATORS
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All electronic circuits need a dc power supply for their operation. To obtain this dc voltage
from 6:9 % ac mains supply$ we need to use rectifier.
Therefore the filters are used to obtain a \steadyj dc voltage from the pulsating one.
The filtered dc voltage is then applied to a regulator which will try to keep the dc output
voltage constant in the event of voltage fluctuations or load variation.
>e know the combination of rectifier @ filter can produce a dc voltage. &ut the problem with
this type of dc power supply is that its output voltage will not remain constant in the event of
fluctuations in an ac input or changes in the load currentA
L
B.
The output of unregulated power supply is connected at the input of voltage regulator circuit.
The voltage regulator is a specially designed circuit to keep the output voltage constant.
t does not remain e7actly constant. t changes slightly due to changes in certain parameters.
.actors affecting the output voltageE
iB
L
ALoad CurrentB
iiB %
=
Anput %oltageB

iiiB T ATemperatureB
C %oltage #egulatorsE
They are basically series regulators with all the basic blocks present inside the C.
Therefore it is easier to use C voltage regulator instead of discrete voltage regulators.
mportant features of C #egulatorsE
+. Programmable output
6. .acility to boost the voltage5current
:. nternally provided short circuit current limiting
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*. Thermal shutdown
1. .loating operation to facilitate higher voltage output
Classifications of C voltage regulatorsE
C %oltage #egulator
.i7ed %olt #eg. Ad;ustable ,5P %olt #eg -witching #eg
Positive5negative
.i7ed @ Ad;ustable output %oltage #egulators are known as Linear #egulator.
A series pass transistor is used and it operates always in its active region.
-witching #egulatorE
+. -eries Pass Transistor acts as a switch.
6. The amount of power dissipation in it decreases considerably.
:. Power saving result is higher efficiency compared to that of linear.
Ad;ustable %oltage #egulatorE
Advantages of Ad;ustable %oltage #egulator over fi7ed voltage regulator are$
+. Ad;ustable output voltage from +.6v to 1) v
6. ,utput current 9.+9 to +.1 A
:. &etter load @ line regulation
*. mproved overload protection
1. mproved reliability under the +99Q thermal overloading
Ad;ustable Positive %oltage #egulator AL":+)BE
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L":+) series ad;ustable : terminal positive voltage regulator$ the three terminals are %in$
%out @ ad;ustment AAD'B.
L":+) re0uires only 6 e7ternal resistors to set the output voltage.
L":+) produces a voltage of +.61v between its output @ ad;ustment terminals. This voltage is
called as %ref.
%ref A#eference %oltageB is a constant$ hence current + flows through #+ will also be
constant. &ecause resistor #+ sets current +. t is called \current setj or \program resistorj.
#esistor #6 is called as \,utput setj resistors$ hence current through this resistor is the sum of
+ @ ad;
L":+) is designed in such as that ad; is very small @ constant with changes in line voltage @
load current.
The output voltage %o is$ %oM#++FA+Fad;B#6 ------------- A+B
>here +M %ref5#+
%o MA%ref5#+B#+ F %ref5#+ F ad; #6
M %ref F A%ref5#+B#6 F ad; #6
%o M %ref S+ F #65#+T F ad; #6 ------------- A6B
#+ M Current A+B set resistor
#6 M output A%oB set resistor
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%ref M +.61v which is a constant voltage between output and AD' terminals.
Current ad; is very small. Therefore the second term in A6B can be neglected.
Thus the final e7pression for the output voltage is given by
%oM +.61vS+ F #65#+T -------------- A:B
/0n A:B indicates that we can vary the output voltage by varying the resistance #6.
The value of #+ is normally kept constant at 6*9 ohms for all practical applications.
Practical #egulator using L":+)E
f L":+) is far away from the input power supply$ then 9.+Kf disc type or +Kf tantalum
capacitor should be used at the input of L":+).
The output capacitor Co is optional. Co should be in the range of + to +999Kf.
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The ad;ustment terminal is bypassed with a capacitor C6 this will improve the ripple re;ection
ratio as high as 89 d& is obtainable at any output level.
>hen the filter capacitor is used$ it is necessary to use the protective diodes.
These diodes do not allow the capacitor C6 to discharge through the low current point of the
regulator.
These diodes are re0uired only for high output voltages Aabove 61vB @ for higher values of
output capacitance 61Kf and above.
IC 723 GENERAL PURPOSE REGULATOR
Disadvantages of fi7ed voltage regulatorE
+. Do not have the shot circuit protection
6. ,utput voltage is not ad;ustable
These limitations can be overcomes in C)6:.
.eatures of C)6:E
+. Dnregulated dc supply voltage at the input between ?.1% @ *9%
6. Ad;ustable regulated output voltage between 6 to :%.
:. "a7imum load current of +19 mA A
Lma7
M +19mAB.
*. >ith the additional transistor used$
Lma7
upto +9A is obtainable.
1. Positive or =egative supply operation
2. nternal Power dissipation of 899m>.
). &uilt in short circuit protection.
8. %ery low temperature drift.
?. <igh ripple re;ection.
The simplified functional block diagram can be divided in to * blocks.
+. #eference generating block
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6. /rror Amplifier
:. -eries Pass transistor
*. Circuitry to limit the current
+. #eference (enerating blockE
The temperature compensated Vener diode$ constant current source @ voltage
reference amplifier together from the reference generating block. The Vener diode is used
to generate a fi7ed reference voltage internally. Constant current source will make the
Vener diode to operate at affi7ed point @ it is applied to the =on ! inverting terminal of
error amplifier. The Dnregulated input voltage Z%cc is applied to the voltage reference
amplifier as well as error amplifier.
6. /rror AmplifierE
/rror amplifier is a high gain differential amplifier with 6 input
Ainverting @ =on-invertingB. The =on-inverting terminal is connected
to the internally generated reference voltage. The nverting terminal is
connected to the full regulated output voltage.
.igE .unctional block diagram of C)6:
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.ig E Pin diagram of C)6:
:. -eries Pass TransistorE
L+ is the internal series pass transistor which is driven by
the error amplifier. This transistor actually acts as a variable resistor
@ regulates the output voltage. The collector of transistor L+ is
connected to the Dn-regulated power supply. The ma7imum collector
voltage of L+ is limited to :2%olts. The ma7imum current which can
be supplied by L+ is +19mA.
*. Circuitry to limit the currentE
The internal transistor L6 is used for current sensing @ limiting. L6 is
normally ,.. transistor. t turns ,= when the
L
e7ceeds a predetermined limit.
Low voltage $ Low current is capable of supplying load voltage which is e0ual to or
between 6 to )%olts.
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%
load
M 6 to )%

load
M +19mA
IC723 as a LOW voltage LOW current :
Fig: Typical circuit connection diagram
#+ @ #6 from a potential divider between %ref @ (nd.
The %oltage across #6 is connected to the =on ! inverting terminal of the regulator C

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%non-inv M
6 +
6
R R
R
+
%ref
(ain of the internal error amplifier is large
%non-inv M %in
Therefore the %o is connected to the nverting terminal through #: @ #
-C
must also be
e0ual to %
non-inv
%o M %non-inv M
6 +
6
R R
R
+
%ref
#+ @ #6 can be in the range of + 3` to +93` @ value of #: is given by
#: M #+ll #6 M
6
6 +
R R
R R
+
#sc Acurrent sensing resistorB is connected between Cs @ C
L
. The voltage drop across #sc
is proportional to the
L
.
This resistor supplies the output voltage in the range of 6 to ) volts$ but the load current
can be higher than +19mA.
The current sourcing capacity is increased by including a transistor L in the circuit.

The output voltage $ %o M
6 +
6
R R
R
+
%ref
IC723 as a HIGH voltage LOW Current:
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.igE Typical circuit connection diagram
This circuit is capable of supplying a regulated output voltage between the range of ) to
:) volts with a ma7imum load current of +19 mA.
The =on ! inverting terminal is now connected to %ref through resistance #:.
The value of #+ @ #6 are ad;usted in order to get a voltage of %ref at the inverting
terminal at the desired output.
%in M %ref M
6 +
6
R R
R
+
%o
%o M
6
6 +
R
R R +
%ref
,r
%o M S+ F
6
+
R
R
T %ref
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#sc is connected between C
L
@ Cs terminals as before @ it provides the short circuit
current limiting
#sc M
I%iit
2 . 9

The value of resistors #: is given by $
#: M #+ ll #6 M
6
6 +
R R
R R
+

IC723 as a HIGH voltage HIGH Current:
.igE Typical circuit connection diagram
An e7ternal transistor L is added in the circuit for high voltage low current regulator to
improve its current sourcing capacity.
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.or this circuit the output voltage varies between ) @ :)%.
Transistor L increase the current sourcing capacity thus
LA"A^B
ia greater than +19mA.
The output voltage %o is given by $
#+F #6
%oM ------------ %ref
#6

The value of #sc is given by #sc M
I%iit
2 . 9

SWITCHING REGULATOR:
An e7ample of general purpose regulator is "otorolaHs "C+)6:. t can be
used in many different ways$ for e7ample$ as a fi7ed positive or negative output voltage
regulator$ variable regulator or switching regulator because of its fle7ibility.
To minimi4e the power dissipation during switching$ the e7ternal transistor used must be
a switching power transistor.

To improve the efficiency of a regulator$ the series pass transistor is used as a switch
rather than as a variable resistor as in the linear mode.
A regulator constructed to operate in this manner is called a series switching regulator.
n such regulators the series pass transistor is switched between cut off @ saturation at a
high fre0uency which produces a pulse width modulated AP>"B s0uare wave output.
This output is filtered through a low pass LC filter to produce an average dc output
voltage.
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Thus the output voltage is proportional to the pulse width and fre0uency.
The efficiency of a series switching regulator is independent of the input @ output
differential @ can approach ?1Q
.ig E &asic -witching regulator
A basic switching regulator consists of * ma;or components$
+. %oltage source %in
6. -witch -+
:. Pulse generator %pulse
*. .ilter .+
1. Voltage Source Vin:
t may be any dc supply ! a battery or an unregulated or a regulated voltage. The voltage
source must satisfy the following re0uirements.
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t must supply the re0uired output power @ the losses associated with the switching
regulator.
t must be large enough to supply sufficient dynamic range for line @ load
regulations.
t must be sufficiently high to meet the minimum re0uirement of the regulator system
to be designed.
t may be re0uired to store energy for a specified amount of time during power
failures.
2. Switch S1:
t is typically a transistor or thyristor connected as a power switch @ is operated in the
saturated mode. The pulse generator output alternately turns the switch ,= @ ,..
3. Pulse generator Vpulse:
t provides an asymmetrical s0uare wave varying in either fre0uency or pulse width called
fre0uency modulation or pulse width modulation respectively. The most effective fre0uency
range for the pulse generator for optimum efficiency 69 3<4. This fre0uency is inaudible to
the human ear @ also well within the switching speeds of most ine7pensive transistors @
diodes.
The duty cucly of the pulse wave form determines the relationship between the
input @ output voltages. The duty cycle is the ratio of the on time ton$ to the period
T of the pulse waveform.
Duty cycle M
toff ton
ton
+


M
T
ton
M ton f.
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>here ton M ,n-time of the pulse waveform
toffMoff-time of the pulse wave form
T M time period M ton F toff
M +5fre0uency or
T M +5f
Typical operating fre0uencies of switching regulator range from +9 to 19kh4.
Lower operating fre0uency improve efficiency @ reduce electrical noise$ but
re0uire large filter components Ainductors @ capacitorsB.
4. Filter F1:
t converts the pulse waveform from the output of the switch into a dc voltage.
-ince this switching mechanism allows a conversion similar to transformers$ the switching
regulator is often referred to as a dc transformer.
The output voltage %o of the switching regulator is a function of duty cycle @ the
input voltage %in.
%o is e7pressed as follows$
%o M
T
ton
%in

This e0uation indicates that$ if time period T is constant$ %o is directly proportional to
the ,=-time$ ton for a given value of %in. This method of changing the output
voltage by varying ton is referred to as a pulse width modulation.
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-imilarly$ if ton is held constant$ the output voltage %o is inversely proportional to
the period T or directly proportional to the fre0uency of the pulse waveform. This
method of varying the output voltage is referred to as fre0uency modulation A."B.
-witching regulator can operate in any of : modes
iB -tep ! Down
iiB -tep ! Dp
iiiB Polarity inverting
MONOLITHIC SWITCHING REGULATOR A78S40]:
The iA)8-*9 consists of a temperature compensated voltage reference$ duty cycle
controllable oscillator with an active current limit circuit$ a high gain comparator$ a high- current$
high voltage output switch$ a power switching diode @ an uncommitted op-amp.
mportant features of the iA)8-*9 switching regulators areE
-tep up$ down @ nverting operation
,peration from 6.1 to *9% input
89d& line @ load regulations
,utput ad;ustable from +.: to *9%
Peak current to +.1A without e7ternal resistors
%ariable fre0uency$ variable duty cycle device
The internal switching fre0uency is set by the timing capacitor C
T
$ connected between pin+6 @
ground pin ++. the initial duty cycle is 2E+. The switching fre0uency @ duty cycle can be modified
by the current limit circuitry$
P3
sense$ pin+*$ ) the comparator$ pin? @ +9.
Comparator:
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The comparator modifies the ,.. time of the output switch transistor L+ @ L6. n the step
! up @ step down modes$ the non-inverting inputApin?B of the comparator is connected to the
voltage reference of +.:% Apin8B @ the inverting input Apin+9B is connected to the output terminal
via the voltage divider network.
.igE .unctional block diagram of iA)8-*9
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n the nverting mode the non ! inverting input is connected to both the voltage
reference @ the output terminal through 6 resistors @ the inverting terminal is connected to
ground.
>hen the output voltage is correct$ the comparator output is in high state @ has no effect
on the circuit operation.
<owever$ if the output is too high @ the voltage at the inverting terminal is higher than
that at the non-inverting terminal $ then the comparator output goes low.
n the L,> state the comparator inhibits the turn on of the output switching transistors.
This means that$ as long as the comparator output is low$ the system is in off time.
As the output current rises or the output voltage falls$ the off time of the system
decreases.
Conse0uently$ as the output current nears its ma7imum o
"A^
$ the off time approaches its
minimum value.
n all : modes A-tep down$ step up$ nvertingB$ the current limit circuit is completed by connecting
a sense resistor #sc$ between
P3
sense @ %cc.
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The current limit circuit is activated when a ::9m% potential appears across #sc.
#sc is selected such that ::9m% appears across it when the desired peak current
P3
$
flows through it.
>hen the peak current is reached$ the current limit circuit is turned on.
The forward voltage drop$ %
D
$ across the internal power diode is used to determine the value
of inductor L off time @ efficiency of the switching regulator.
Another important 0uantity used in the design of a switching regulator is the saturation voltage
%s
n the step down mode an \output saturation voltj is +.+% typical$ +.:%
"A^
.
n the step up mode an \,utput saturation voltj is 9.*1% typical$ 9.) ma7imum.
#sc M
0Current $esired)ea
V ::9

The desired peak current value is reached$ the current limiting circuit turns ,= @ immediately
terminates the ,= time @ starts ,.. time.
As we increase
L
Aload currentB$ %out will decreased$ to compensate for this$ the ,= time of
the output is increased automatically.
f the
L
decreased then %out increased$ to compensate for this$ the ,.. time of the output is
increased automatically.
(i) Step Down Switching Regulator:
C
T
is the timing capacitor which decides the switching fre0uency.
#sc is the current sensing resistance. ts value is given by
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#sc M
0Current $esired)ea
V ::9


The =on-inverting terminal of the internal op-ampApin?B is connected to the +.:%
reference Apin8B.
#esistances #+ @ #6 from a potential divider$ across the output voltage %o. Their
value should be such that the potential at the inverting input of the op-amp should
be e0ual to +.:% ref when %o is at its desired level.
%
A-B
M +.:% M
6 +
6
R R
R
+
%o

The output capacitance Co is used fro reducing the ripple contents in the output voltage. t acts as a
filter along with the inductor L.
The inductor L is a part of filter connected on the output side$ to reduce the ripple
percentage.
The 9.+K. capacitor connected between pin8 @ ground bypasses any noise voltage
coupled to the reference Apin8B.
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(ii) Step Up Switching Regulator:
=ote that inductor is connected between the collectors of L+ @ L6.
>hen L+ is ,=$ the output is shorted @ the collector current of L+ flows through L.
The diode D+ is reverse biased @ Co supplies the load current.
The inductor stores the energy. >hen the L+ is turned ,..$ there is a self induced emf that
appears across the inductor with polarities.
The output voltage is given by$
%o M %in F %
L
<ence it will be always higher than %in @ step up operation is achieved.
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>ith L+ ,= with L+ o..
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(iii) Inverting Switching Regulator:
nverting switching regulator converts a positive input voltage into a negative
output voltage which is higher in magnitude.
THE SWITCHED CAPACITOR FILTER
Basic Representation:
-witched-capacitor resistor
The simplest switched capacitor A-CB circuit is the switched capacitor resistor$ made of one
capacitor C and two switches -
+
and -
6
which connect the capacitor with a given fre0uency
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alternately to the input and output of the -C. /ach switching cycle transfers a charge " from the
input to the output at the switching fre0uency f. #ecall that the charge " on a capacitor C with a
voltage V between the plates is given byE
where V is the voltage across the capacitor. Therefore$ when -
+
is closed while -
6
is open$ the
charge transferred from the source to C
-
isE
and when -
6
is closed while -
+
is open$ the charge transferred from C
-
to the load isE
Thus$ the charge transferred in each cycle isE
-ince a charge " is transferred at a rate f$ the rate of transfer of charge per unit time isE
=ote that we use I$ the symbol for electric current$ for this 0uantity. This is to demonstrate that a
continuous transfer of charge from one node to another is e0uivalent to a current. -ubstituting for
" in the above$ we haveE
Let us define %$ the voltage across the -C from input to output$ thusE
>e now have a relationship between and %$ which we can rearrange to give an e0uivalent
resistance RE
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Thus$ the -C behaves like a resistor whose value depends on C
S
and f.
The -C resistor is used as a replacement for simple resistors in integrated circuits because it is
easier to fabricate reliably with a wide range of values. t also has the benefit that its value can be
ad;usted by changing the switching fre0uency. -ee alsoE operational amplifier applications.
This same circuit can be used in discrete time systems Asuch as analog to digital convertersB as a
track and hold circuit. During the appropriate clock phase$ the capacitor samples the analog
voltage through switch one and in the second phase presents this held sampled value to an
electronic circuit for processing.
Switched Capacitor Circuits :
n the last decade or so manyactive filters with resistors and capacitors have been replaced
with a special kind of filter called a switched capacitor filter. The switched capacitor filter allows
for very sophisticated$ accurate$ and tuneable analog circuits to be manufactured without using
resistors. This is useful for several reasons. Chief among these is that resistors are hard to build
on integrated circuits Athey take up a lot of roomB$ and the circuits can be made to depend on ratios
of capacitor values Awhich can be set accuratelyB$ and not absolute values Awhich vary between
manufacturing runsB.

The Switched Capacitor Resistor:
To understand how switched capacitor circuits work$ consider the circuit shown with a
capacitor connected to two switches and two different voltages.
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f -
6
closes with -
+
open$ then -
+
closes with switch -
6
open$ a charge A0 is transferred from v
6
to v
+
with
f this switching process is repeated = times in a time At$ the amount of charge transferred per unit
time is given by
#ecogni4ing that the left hand side represents charge per unit time$ or current$ and the the number
of cycles per unit time is the switching fre0uency Aor clock fre0uency$ f
CL3
B we can rewrite the
e0uation as
#earranging we get
which states that the switched capacitor is e0uivalent to a resistor. The value of this resistor
decreases with increasing switching fre0uency or increasing capacitance$ as either will increase the
amount of charge transfered from v
6
to v
+
in a given time.
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The Switched Capacitor Integrator:
=ow consider the integrator circuit. oou have shown Ain a previous labB that the input-output
relationship for this circuit is given by Aneglecting initial conditionsBE
>e can also write this with the CsC notation Aassuming a sinusoidal input$ Ae
st
$ sM;rB
f you replaced the input resistor with a switched capacitor resistor$ you would get
Thus$ you can change the e0uivalent rq of the circuit by changing the clock fre0uency. The value
of rq can be set very precisely because it depends only on the ratio of C
+
and C
6
$ and not their
absolute value.
-witched Capacitor .ilter csE
>e will see some of the -witched capacitor filter cs such as ". 1$ ".+9 and ".+99
MF 5 :
t is the basic type of filter. This is called as universal filter because it can be used to synthesi4e
any type of filters such as &and pass$ Low-pass$ <igh-pass$ notch and all-pass. The block diagram
of ".1 was shown here. t consists of an operational amplifier$ two positive integrators and
summing node. A ",- switch is controlled by the logic input given at pin 1.
This switch is useful in connecting one of the inputs of first integrator to either ground or to the
output of the second integrator. The way in which the e7ternal resistors are connected determines
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the characteristics of the filter. The ma7imum recommended clock fre0uency is + "<
V
. There
were three modes of operation and out of all modes$ mode : is best. All the modes have three
outputs with the combinations of different filter functions. And ".1 Can ,perate with single or
split power supply. The clock fre0uency to center fre0uency ration is selected with a help of pin ?.
There were two ratio options 19E+ and +99E+.
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MF10:
The ".+9 contains two of the second-order universal filter sections found in the ".1. Therefore
with ".+9$ two second order filters or one fourth-order filter can be built. As the ".1 and ".+9
have similar filter sections$ the design procedure for them is same.
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The LMF100 Switched Capacitor Filter:
n this lab you will be using the ".+99$ or L".+99 integrated circuit is a versatile circuit with
four switched capacitor integrators$ that can be connected as two second order filters or one fourth
order filter. >ith this chip you can choose q to either be +519 or +5+99 of the clock fre0uency
Athis is given by the ratio C
+
5C
6
in the discussion aboveB$. &y changing internal and e7ternal
connections to the circuit you can obtain different filter types Alowpass$ highpass$ bandpass$ notch
Abandre;ectB or allpassB.
2
nd
Order Filters
Filter Type Transfer Function
Low Pass
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<igh Pass
&and Pass
=otch A&and #e;ectB
The pinout for the L".+99 is shown below Afrom the data sheetBE
-ee that the chip$ for the most part$ is split into two halves$ left and right. A block diagram of the
left half AAand a few pins from the right halfB is shown below.
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The pins are described as
195+99 - determines if the value of r q is r
CL3
5+99$ or r
CL3
519.
CL3
A
- is r
CL3
.
=%
A
- the inverting input to the op-amp
=5AP5<P
A
- an intermediate output$ and the non-inverting input to the summer. Dsed for
=otch$ All Pass or <igh Pass output.
&P
A
- another intermediate output$ the output of the first integrator. Dsed for &and Pass
output.
LP
A
- the output of the second integrator. Dsed for Low Pass output.
-+
A
- an inverting input to the summer.
-
A&
- determines if the switch is to the left or to the right. That is$ this pin determines if the
second inverting input to the summer is ground AA(=DB$ or the low pass output.
The two integrators are switched capacitor integrators. Their transfer functions are given by$
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where rq is r
CL3
5+99$ or r
CL3
519$ depending on the state of the 195+99 pin. =ote that the
integrator is non-inverting.
A Typical Circuit:
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The diagram below shows one of the modes Amode +B of operations
The filter specifications as given in the datasheet$ and given below.

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The low pass ALP
A
B output is easily given in terms of the band pass output A&P
A
B$ as well as the
band pass output as a function of the summer A-D"$ not labeled on diagramB.
The summer output A-D"B is simply the output of the op amp A=
A
B minus the lowpass output
ALP
A
B. <owever we can see that the op amp is set up as the inverting summing circuit. -o
#eplace -D" on the left hand side using e0uation @2B from above$ and LP
A
using e0uation @7B.
#earranging brings
/0uating this with the transfer function for a bandpass circuit
yields$
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-imilarly$ the relationship between low pass and band pass$ e0uation A+B$ can be used to find the
low pass transfer function. The notch filter transfer function is derived in the same way.




POWER AUDIO AMPLIFIER IC LM380:
Features of LM380:
+. nternally fi7ed gain of 19 A:*d&B
6. ,utput is automatically self centring to one half of the supply voltage.
:. ,utput is short circuit proof with internal thermal limiting.
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*. nput stage allows the input to be ground referenced or ac coupled.
1. >ide supply voltage range A1 to 66%B.
2. <igh peak current capability.
). <igh impedence.
8. Low total harmonic distortion
?. &andwidth of +993<4 at Pout M 6> @ #
L
M 8`
Introduction:
-mall signal amplifier are essentially voltage amplifier that supply their loads with larger
amplifier signal voltage.
,n the other hand $ large signal or power amplifier supply a large signal current to current
operated loads such as speakers @ motors.
n audio applications$ however$ the amplifier called upon to deliver much higher current
than that suppkied by general purpose op-amps. This means that loads such as speakers @ motors
re0uiring substantial currents cannot be driven directly by the output of general purpose opo-amps.
<owever there are two possible solutions$
To use discrete or monolithic power transistors called power boosters at the output of the
op-amp
To use speciali4ed Cs designed as power amplifiers.
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.ig E .unctional block diagram of Audio Power Amplifier
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.igE Pin diagram
.ig E &lock diagram
L":89 circuit descriptionE
t is connected of * stages$
(i) P=P emitter follower
(ii) Different amplifier
(iii) Common emitter
(iv) /mitter follower
AiB P=P /mitter followerE
The input stage is emitter follower composed of P=P transistors L+ @ L6 which drives the
P=P L:-L* differential pair.
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The choice of P=P input transistors L+ @ L6 allows the input to be referenced to ground
i.e.$ the input can be direct coupled to either the inverting @ non-inverting terminals of the
amplifier.
AiiB Differential AmplifierE
The current in the P=P differential pair L:-L* is established by L)$ #: @ F%.
The current mirror formed by transistor L)$ L8 @ associated resistors then establishes the
collector current of L?.
Transistor L1 @ L2 constitute of collector loads for the P=P differential pair.
The output of the differential amplifier is taken at the ;unction of L* @ L2 transistors @ is
applied as an input to the common emitter voltage gain.
AiiiB Common /mitterE
Common /mitter amplifier stage is formed by transistor L? with D+$ D6 @ L8 as a current
source load.
The capacitor C between the base @ collector of L? provides internal compensation @
helps to establish the upper cutoff fre0uency of +99 3<4.
-ince L) @ L8 form a current mirror$ the current through D+ @ D6 is appro7imately the
same as the current through #:.
D+ @ D6 are temperature compensating diodes for transistors L+9 @ L++ in that D+ @ D6
have the same characteristics as the base-emitter ;unctions of L++. Therefore the current
through L+9 @ AL++-L+6B is appro7imately e0ual to the current through diodes D+ @ D6.
AivB A,utput stageB - /mitter followerE
/mitter follower formed by =P= transistor L+9 @ L++. The combination of P=P transistor
L++ @ =P= transistor L+6 has the power capability of an =P= transistors but the
characteristics of a P=P transistor.
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The negative dc feedback applied through #1 balances the differential amplifier so that the
dc output voltage is stabili4ed at F%56e
To decouple the input stage from the supply voltage F%$ by pass capacitor in order of
micro farad should be connected between the by pass terminal Apin +B @ ground Apin )B.
The overall internal gain of the amplifier is fi7ed at 19. <owever gain can be increased by
using positive feedback.
APPLICATIONS:
(i) Audio Power Amplifier:
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Amplifier re0uires very few e7ternal components because of the internal biasing$ compensation
@ fi7ed gain.
>hen the power amplifier is used in the non inverting configuration$ the inverting terminal
may be either shorted to ground$ connected to ground through resistors @ capacitors.
-imilarly when the power amplifier is used in the inverting mode$ the non inverting terminal
may be either shorted to ground or returned to ground through resistor or capacitor.
Dsually a capacitor is connected between the inverting terminal @ ground if the input has a
high internal impedance.
As a precautionary measure$ an #C combination should be used at the output terminal Apin 8B
to eliminate 1-to-+9 "<4 oscillation.
C+ is coupling capacitor which couples the output of the amplifier to the 8 ohms loud speaker
which act as a load. The amplifier will amplify the %
in
applied at the non-inverting terminal.
(ii) LM 380 as a High gain:
The gain of L":89 is internally fi7ed at 19. &ut it can be increased by using the e7ternal
components.
The increase in gain is possible due to the use of positive feedback$ this setup to obtain a gain
699.
(iii) LM 380 as a variable Gain:
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nstead of getting a fi7ed gain of 19$ it is possible to obtain a variable gain up to 19 by
connecting a potentiometer between the input terminals.
(iv) LM 380 as a Bridge Audio Power Amplifier:
f a certain application re0uires more power than what is provided by a single L":89
amplifier$ then 6 L":89 chips can be used in the bridge configuration.
>ith this arrangement we get an output voltage swing which is twice that of a single L":89
amplifier.
As the voltage is doubled$ power output will increase by four times that of a single L":89
amplifier. The pot #* is used to balance the output offset voltages of the two chips.
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(v) Intercom system using LM 380:
>hen the switch is in Talk mode position$ the master speaker acts as a microphone.
>hen the switch is in Listen position$ the remote speaker acts as a microphone.
n either phone the overall gain of the circuit is the same depends on the turns of transformer T.
Fig: Talk mode
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.igE Listen mode
OPTOCOUPLERS/OPTOISOLATORS:
,ptocouplers or ,ptoisolators is a combination of light source @ light detector in the same
package.
They are used to couple signal from one point to other optically$ by providing a completer
electric isolation between them. This kind of isolation is provided between a low power control
circuit @ high power output circuit$ to protect the control circuit.
Depending on the type of light source @ detector used we can get a variety of optocouplers.
They are as follows$
AiB L/D ! LD# optocoupler
AiiB L/D ! Photodiode optocoupler
AiiiB L/D ! Phototransistor optocoupler
Characteristics of optocouplerE
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AiB Current Transfer #atio ACT#B
AiiB solation %oltage
AiiiB #esponse Time
AivB Common "ode #e;ection
AiB Current Transfer #atioE
t is defined as the ratio of output collector current AcB to the input
forward current AfB
CT# M c5f J +99Q
ts value depends on the devices used as source @ detector.
AiiB solation voltage between input @ outputE
t is the ma7imum voltage which can e7ist differentially between the
input @ output without affecting the electrical isolation voltage is
specified in 3 %rms with a relative humidity of *9 to 29Q.
AiiiB#esponse TimeE
#esponse time indicates how fast an optocoupler can change its output
state. #esponse time largely depends on the detector transistor$ input
current @ load resistance.
AivBCommon mode #e;ectionE
/venthough the optocouplers are electrically isolated for dc @ low fre0uency signals$ an
impulsive input signal Athe signal which changes suddenlyB can give rise to a displacement current
cM CfJdv5dt. This current can flow between input @ output due to the capacitance Cf e7isting
between input @ output. This allow the noise to appear in the output.
Types of optocouplerE
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AiB L/D ! Photodiode optocouplerE
L/D photodiode shown in figure$ here the infrared L/D acts as a light source @ photodiode is
used as a detector.
The advantage of using the photodiode is its high linearity. >hen the pulse at the input goes
high$ the L/D turns ,=. t emits light. This light is focused on the photodiode.
n response to this light the photocurrent will start flowing though the photodiode. As soon as
the input pulse reduces to 4ero$ the L/D turns ,.. @ the photocurrent through the photodiode
reduces to 4ero. Thus the pulse at the input is coupled to the output side.
AiiB L/D ! Phototransistor ,ptocouplerE
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The L/D phototransistor optocoupler shown in figure. An infrared L/D acts as a light source
and the phototransistor acts as a photo detector.
This is the most popularly used optocoupler$ because it does not need any additional
amplification.
>hen the pulse at the input goes high$ the L/D turns ,=. The light emitted by the L/D is
focused on the C& ;unction of the phototransistor.
n response to this light photocurrent starts flowing which acts as a base current for the
phototransistor.
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The collector current of phototransistor starts flowing. As soon as the input pulse reduces to
4ero$ the L/D turns ,.. @ the collector current of phototransistor reduces to 4ero. Thus the
pulse at the input is optically coupled to the output side.
Advantages of ,ptocouplerE
Control circuits are well protected due to electrical isolation.
>ideband signal transmission is possible.
Due to unidirectional signal transfer$ noise from the output side does not get coupled to the
input side.
nterfacing with logic circuits is easily possible.
t is small si4e @ light weight device.
DisadvantagesE
-low speed.
Possibility of signal coupling for high power signals.
ApplicationsE
,ptocouplers are used basically to isolate low power circuits from high
power circuits.
At the same time the control signals are coupled from the control circuits to the high power
circuits.
-ome of such applications are$
AiB AC to DC converters used for DC motor speed control
AiiB <igh power choppers
AiiiB <igh power inverters
,ne of the most important applications of an optocoupler is to couple the base driving signals
to a power transistor connected in a DC-DC chopper.
=ote that the input @ output waveforms are +89c out of phase as the output is taken at the
collector of the phototransistor.
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Optocoupler IC:
The optocouplers are available in the C form "CT6/ is the standard optocoupler C
which is used popularly in many electronic application.
This input is applied between pin +@ pin 6. An infrared light emitting diode is connected
between these pins.
The infrared radiation from the L/D gets focused on the internal phototransistor.
The base of the phototransistor is generally left open. &ut sometimes a high value pull down
resistance is connected from the &ase to ground to improve the sensitivity.
The block diagram shows the opto-electronic-integrated ciruit A,/CB and the ma;or
components of a fiber-optic communication facility.
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