IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 52, NO.

9, SEPTEMBER 2005

545

Optimization of MOS Amplier

Performance Through Channel Length and
Inversion Level Selection
Timothy M. Hollis, Student Member, IEEE, David J. Comer, Fellow, IEEE, and Donald T. Comer, Member, IEEE

AbstractThe dependence of MOS amplier performance on

channel length and channel inversion is simulated and discussed.
Suggestions are made regarding the optimization of voltage gain,
nonlinear distortion and the gain-bandwidth product (GBW)
through careful device length and inversion level selection. The
midband voltage gain of the common-source amplier is shown to
remain relatively constant when biased for weak inversion operation, with short-channel devices continuing to amplify effectively
at very low levels of inversion, allowing for extremely low power
circuits. Total harmonic distortion is reduced through decreasing
channel length and/or the level of channel inversion. The GBW is
optimized through the use of minimum sized transistors biased to
operate in the strong inversion region.
Index TermsGain bandwidth, harmonic distortion (HD), inversion coefcient, MOS ampliers, short-channel effects.

I. INTRODUCTION

N INTEGRAL part of modern MOS amplier design is

the balancing of performance tradeoffs through the variation of several device level parameters. FET channel width,
length and inversion level, for example, have been shown to
strongly inuence the speed, gain, noise immunity and power
dissipation of a given circuit design [1], [2].
While digital system design has continually pushed for the increased speed of minimum size devices, analog designers have
often employed longer channels to achieve higher voltage gains
as well as less complicated operation and modeling through the
avoidance of short-channel effects. But, as short-channel devices may be unavoidable in the design of high bandwidth ampliers, it is important to understand short-channel effects on
the overall circuit behavior and performance.
In addition to the designation of channel length, the channelinversion level must be considered in amplier design. The three
regions of possible operation, dened by the drain current
and other device parameters are weak, moderate, and strong inversion. Traditional analysis of MOS circuits is often based on
the assumption that all circuit components are operating in the
strong inversion region. This is because the pertinent equations

Manuscript received January 8, 2004; revised October 25, 2004. This work
was supported by the Micron Foundation as part of the Micron Campus Engineering Research Program, JuneAugust 2003. This paper was recommended
by Associate Editor N. R. Aluru.
The authors are with the Department of Electrical and Computer Engineering,
Brigham Young University, Provo, UT 84602 USA (e-mail: thollis@ieee.org).
Digital Object Identier 10.1109/TCSII.2005.850777

are better known for strongly inverted devices and the boundaries between moderate and strong inversion operation or weak
and moderate inversion operation are not immediately obvious.
The motivation for this work was not only to further the
understanding of the effects of channel length and inversion
on amplier performance, but to demonstrate that such an
understanding unlocks a new set of operating points with corresponding performance benets not realizable in the traditional
long channelstrongly inverted design.
The level of inversion and the size of the channel inuence
midband voltage gain, bandwidth, noise, matching of devices,
power dissipation, nonlinear distortion, and maximum output
current. One recent article [1] discusses guidelines involved
in choosing drain current and channel size to achieve certain
selected performance parameters. It considers the effects of
current and sizing on transconductance, layout area, output
resistance, icker noise, and other parameters involved in
amplier design. A second article [2] considers the effects
of drain current on voltage gain and nonlinear distortion.
This study extends earlier work to the 0.18- device and discusses the optimization of the voltage gain-bandwidth product
(GBW) for this device size. The following section of this article discusses the operation of MOSFETs over the three regions
of inversion and the equation used to dene the level of inversion. The third section considers the effects of channel length
and channel inversion on amplier characteristics including the
optimization of the GBW. The fourth section reports simulations for various combinations of channel length and inversion
level. The fth section presents some guidelines for selecting
device lengths and inversion levels to achieve optimum performance in terms of gain, distortion, power efciency and/or
GBW. A summary of the common-source amplier characteristics is presented using a modied four corners approach.
These four corners correspond to the use of a short-channel
device in weak inversion, short-channel device in strong inversion, long-channel device in weak inversion, and long-channel
device in strong inversion. The nal section will consist of a
summary of the ndings presented throughout this paper.
II. INVERSION LEVELS
MOS devices can effectively amplify signals in any of the
three inversion regions, yet even with this knowledge analog
circuit designers often limit device operation to the strong inversion region. While simple MOS amplier stages have much

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Fig. 1. Simple common-source amplier conguration considered throughout

the study.

higher bandwidths in the strong inversion region, voltage gain,

power dissipation, white noise, and distortion can be optimized
by operation in the weak or moderate inversion regions [1][4].
A large amount of research has been done regarding device
operation at the three levels of inversion [1], [4], some of which
has lead to improved MOS modeling techniques [5]. Within this
work are found the equations that dene the level of inversion.
Moderate inversion characteristic current, often referred to as
, is rst dened as
specic current
(1)
where is a slope factor (about 1.5 in weak inversion and 1.3 in
is the
strong inversion) [1], is the charge carrier mobility,
is the thermal voltage
gate-oxide capacitance per unit area,
and
is the channel width to length ratio.
It has been proposed [4] that the inversion level of a given
device, or the inversion coefcient (IC), then be dened as the
to the specic current. When
ratio of drain current
or IC equals one, the device is said to be biased in the center of
the moderate inversion region, hence the name moderate inversion characteristic current. Using this approach, the weak-tomoderate inversion boundary is then considered to be the point
where IC is equal to 0.1, with the weak inversion region corresponding to IC values less than 0.1. Likewise, the moderate-tostrong inversion boundary is found to occur where IC is equal to
10, with the strong inversion region corresponding to IC values
greater than 10.
III. AMPLIFIER CHARACTERISTICS
Previous studies of amplier dependence on channel
inversion and channel length [1] have focused on the transconof the devices, proposing transconductance
ductance
as the basis for an effective analog deefciency
sign methodology. In the current study, focus was placed on
voltage gain, nonlinear distortion and bandwidth as a function
of channel length and inversion. The majority of this study
was carried out through the characterization of the simple
common-source amplier stage shown in Fig. 1, for device
,
and
.
sizes of
A. Voltage Gain
Often, the voltage gain of CMOS ampliers, with current
source loads, is assumed to be proportional to channel length,

yet this assumption fails to consider the inversion level of the

individual transitors within the amplier. In fact, short-channel
devices often continue to effectively amplify signals at inversion
levels far below the inversion levels at which longer devices essentially turn off. Therefore, it is possible to observe higher
gains from shorter devices if the inversion level is low enough.
At the other end of the inversion spectrum, voltage gain is
signicantly attenuated in strongly inverted devices regardless
of channel length. To some degree, the drop in gain is expected
and can be predicted as follows:
Voltage Gain

(2)

Yet, as the inversion level continues to increase, the observed

rolloff in gain tends to exceed that predicted above. It has been
suggested [1] that the faster than predicted rolloff might occur
at higher levels of inversion. This
as the result of a drop in
limiting of
at high inversion levels is likely due to mobility
degradation or the increased carrier scattering that occurs as carriers are forced closer to the imperfect surface due to the electric eld between the gate and the channel. While the gain of
each device drops off in the strong inversion region, the gain
rolloff of the short-channel device is not as steep as that for the
longer device. While the gain for both devices is proportional
, the shapes of the correto the drain-to-source resistance
sponding
curves are very different. The long-channel
curve drops off as
, while the short-channel curve deviates
from the predicted path near the center of the moderate inversion region boundary as a result of a complex combination of
drain-induced barrier lowering (DIBL), velocity saturation and
values
mobility degradation. As a result, the short-channel
are higher than predicted in strong inversion which translates to
higher than expected gain throughout this region.
A third voltage gain characteristic of CMOS ampliers is that
the peak in gain shifts from the moderate-to-strong inversion region boundary well into the weak inversion region as channel
lengths approach 0.18 . The loss of the peak at higher inversion may be attributed to the effects of velocity saturation on
of the device. While velocity saturation tends to limit
the
across all regions of inversion for
the current and hence the
shorter devices, it is most noticable above the threshold voltage
begin to grow more dramatically. The
where the current and
of the longer devices benet from the rapid increase
gain
around the moderate to strong inversion region boundary,
in
while the short-channel device suffers from an attenuation of
at this inversion level.
It would be incorrect to attribute this peak shifting or attenuation to mobility degradation, as that mechanism is a function
of the electric eld normal to the channel and remains relatively
and channel length for this process techindependent of
nology, while the location of the peak gain is clearly a function
of channel length.
B. Total Harmonic Distortion
For a given input, total harmonic distortion (THD) tends to
decrease with channel length across all three regions of inversion with additional reduction in the weak inversion region.
The additional reduction is likely a by-product of a relatively

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547

constant gain throughout the weak inversion region [2]. The predicted gain is found by rst considering the expression for drain
current in the weak inversion region
(3)
is proportional to the specic current.
where
Then, by denition, the transconductance is found to be
(4)
and
Voltage gain is the product of
replaced by the ratio of Early voltage

where
may be
to drain current.

Gain
(5)
After some cancellation, the following equation emerges:
Gain

. This output capacitance consists

where
of the drain-to-body capacitance, the gate-to-drain capacitance,
and the load capacitance.
If drain voltage is held constant, the capacitance remains approximately constant with IC. The GBW then depends on the
transconductance of the stage.
In a short-channel device, two effects, often neglected in
longer devices [5], must be considered. The rst is velocity
limiting of the free electrons in the channel as the horizontal
electric eld approaches the onset of velocity saturation
for n-type devices) [6]. The second effect is
(
mobility degradation due to the vertical electric eld caused
by the gate-to-channel voltage. While mobility degradation is
technically not a function of channel length, it is becoming
more pronounced as processes shrink and oxide layers continue
to thin. The high electric eld intensity established by the applied gate voltage attracts the free electrons to the surface of the
channel. Surface irregularities tend to increase the scattering of
the free electrons, decreasing the mobility of the carriers [7].
. The
A maximum is reached near a value of
expression for drain current in a short-channel device with
mobility degradation is

(6)
(8)

are constants dened in a previous section.

where and
has been shown to vary in shorter devices, it remains
While
relatively constant through the weak inversion region, even for
device lengths of 0.18 .
To understand the impact of channel inversion on THD, conor IC, as will be shown
sider voltage gain as a function of
in a later section, with constant gain throughout the weak inversion region and dramatically varying gain in the moderate
and strong inversion regions. Then, consider a device biased
to operate in the middle of the weak inversion region. Signal
swings on the nodes of the device will be reected in the level
of channel inversion, yet the gain of the amplier will remain
constant throughout the swing. Signal swings through a device
operating in moderate or strong inversion will also result in a
varying inversion level, but in this case, the gain of the amplier
will vary as a function of the magnitude of the signal resulting
in distortion.
As it is more common to design a circuit to maintain a certain
output value, a more practical consideration might be how THD
varies with inversion for a given output. Under this condition,
the distortion remains low through the weak inversion region
and begins to increase indenitely through the moderate and
strong inversion regions. Comparison of THD with the midband
voltage gain shows an inverse relationship between a devices
ability to amplify and the corresponding distortion produced.
C. Gain Bandwidth
The voltage GBW is dened as the product of the magnitude of the midband voltage gain and the 3-dB bandwidth of
an amplifying stage. In circuits that require high bandwidths,
the GBW is an important gure of merit. For the simple stage
of Fig. 1, the GBW can be expressed as
(7)

where
is the critical electric eld value, typically the ratio
of the velocity saturation constant to the effective mobility, and
is a parameter related to the thickness of the oxide layer [7].
results in
Differentiating the drain current with respect to
the following approximation of transconductance:

(9)
We present (9) as an approximation in that it matches the
shape of the simulated
verses IC curve but must be scaled in
order to match the absolute value of the curve. Yet, even as an
approximation, it is a useful expression that acurately predicts
the inversion level associated with the maximum
, a necessary detail for amplier optimization.
When attempting to optimize the GBW, a simulation of the
device can be done to accurately determine the IC that results
in the maximum value. For the 0.18- device, this value of IC
may be somewhere between 10 and 100 as shown in Fig. 2.
In applications requiring high bandwidth, the bias current
should be chosen to result in an IC value that is relatively high.
This may result in a relatively low midband voltage gain as well
as a quiescent current leading to higher power dissipation, yet
the maximum bandwidth per stage will also result from this bias.
IV. SIMULATION RESULTS
All simulations completed in this study were performed
in Spectre, with TSMCs tsmc18rf-nMOS2v and nMOS3v
BSIM3.v3 models. As was mentioned previously, all of the amplier characterization was completed for the common-source
stage shown in Fig. 1. Each amplier parameter, (voltage

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Fig.2. Simulation results showing the correlation between inversion level and
midband gain for the 0.18-, 0.5-, and 2- devices.

Fig. 3. Simulation results showing the correlation between inversion level and
THD for the 0.18-, 0.5-, and 2- devices..

gain) was simulated for device lengths of 0.18, 0.5, and 2

with width-to-length ratios of two. While each simulation was
repeated for pMOS as well as nMOS devices, only the nMOS
results are reported here.
A. Midband Voltage Gain Simulations
Simulation of the midband gain for the common-source amplier is shown in Fig. 2. The magnitude of the gain for the three
devices tested was normalized to length in order to better show
the shape of the curves.
As expected, the gain of each device remained relatively
constant across the weak inversion region with the gain of
the 0.18- device remaining constant down below the cut-off
points of the 0.5- and 2- devices. The peak gain at the
moderate-to-strong inversion region boundary, which is very
pronounced in the 2- device, decreases with each reduction
in channel length, likely as a result of the attenuation of
at
this level of inversion.
Beyond the moderate-to-strong inversion region boundary,
the fall-off in voltage gain is noticably slower for the 0.18device, partly due to the short-channel effect on
discussed
previously.
B. THD Simulations
Simulation of the THD, based on a given input magnitude,
for the common-source amplier is shown in Fig. 3. The curve
along the bottom of the gure, representing the least amount of
distortion, corresponds to the shortest device and clearly demonstrates the correlation between distortion and channel length.
While there doesnt appear to be a high correlation between
THD and channel inversion in the 0.18- device, such a relationship is clearly evident in the longer devices.
C. Gain-Bandwidth Simulations
Fig. 4 compares the GBW of the amplier for channel lengths
of 0.18, 0.5, and 2 . As expected, all three devices reach a peak
in the GBW within the strong inversion region, with the largest
value corresponding to the shortest device. While the peaks do

Fig. 4. Simulation results showing the correlation between inversion level and
gain bandwidth for the 0.18-, 0.5-, and 2- devices.

not all occur at precisely the same level of inversion, it is clear

that the optimum conguration is the 0.18- device biased near
IC
.
V. AMPLIFIER OPTIMIZATION
Fig. 5 compares the advantages and disadvantages of the four
combinations of channel length and channel inversion. Using
this table, one may quickly decide between the various device
congurations and their corresponding performance tradeoffs.
The following optimization guidelines can be derived from
Fig. 5.
1) Optimum Bandwidth: It is a well-known fact that highest
bandwidth is achieved with minimum sized devices operating well into the strong inversion region.
2) Minimal Distortion: Fig. 3 clearly shows that THD is minimized by operating devices in the weak inversion region.
While this applies to devices of all sizes, there appears to
be some additional advantage in the use of shorter device
lengths.

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549

VI. CONCLUSION

Fig. 5.

Four Corner summary.

3) Optimum Bandwidth and Minimal Distortion: High bandwidth coupled with minimal distortion may be achieved
using minimum sized devices with reduced inversion level
as was shown in Fig. 3. While reducing the inversion level
will degrade the speed of the device somewhat, clearly this
is the most effective way to reduce distortion while minimizing the sacrice in bandwidth.
4) Optimum Voltage Gain: Voltage gain is proportional to
channel length and will therefore be higher in the longer
device across most of the inversion level spectrum. It was
shown, however, in Fig. 2 that at the inversion level extremes this notion does not hold. Disregarding these extreme cases, the voltage gain of the longer device may
then be optimized by targeting operation in the midrange
to higher end of the moderate inversion region, a fact discussed in [3]. If a short-channel device is to be used, then
operation well into the weak inversion region will optimize voltage gain.
5) Optimum Gain Bandwidth: There is a well-known
tradeoff between the high bandwidth/low gain of minimum sized devices and the low bandwidth/high gain
of longer devices. To some degree, the size of the device
will depend on the process technology in which the
circuit will be implemented. In older technologies, the
minimum sized device might correspond to the longer
devices presented in this study. In either case, once the
device size has been established, the GBW may still be
optimized. As was described in Section III-C, there is
a clear maximum in the GBW curve that occurs in the
strong inversion region which may be quickly identied
through simulation or by using (9) and should be targeted
to optimize for this parameter.

This work continues the characterization of the MOS amplier, specically considering voltage gain, THD, and GBW and
their relation to device-channel length and channel inversion in
the common-source stage. As has been done in past studies [1],
these performance parameters were presented as functions of
the amplifying devices inversion coefcient. By comparing the
performance of long- and short-channel devices across all three
regions of inversion, it was possible to derive a set of practical
design guidelines for optimizing MOS ampliers in terms of
particular gain, distortion and bandwidth constraints.
As was stated in the introduction, one purpose of this study
was to further uncover possible performance benets existing
outside of the traditional long channelstrongly inverted amplier design, and clearly many such benets exist. For example,
it has been shown that while gain is maximized through the
use of long-channel devices, when the gain requirement is coupled with distortion and/or bandwidth requirements, then it may
be advisable to move to a short-channel device in order to increase circuit speed and lower distortion. If bandwidth is not a
priority, then it is possible to complement the high gain of the
longer device with lower distortion simply by decreasing the
channel inversion level. Thus, optimal performance with respect
to specic design requirements is often only realizable as circuit
designers more carefully consider not only device length but inversion level as well.
While optimization for several design constraint combinations was presented, additional focus was placed on the gain
bandwidth. An expression accounting for the effects of velocity
saturation and mobility degradation was presented as well as
a discussion of how this expression may be used to identify the
maximum in the GBW behavior. Biasing the amplifying devices
to operate at the corresponding level of inversion then results in
optimum GBW performance. Similar operating points may be
found to optimize for any combination of gain, distortion and/or
bandwidth constraints based on the material presented.
This work, combined with the MOS characterization previously presented [1][4], constitutes a powerful set of design
tools that should facilitate the often complicated process of balancing circuit performance tradeoffs.
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