Progress In Electromagnetics Research Symposium, Cambridge, USA, July 26, 2008 203

Design of a 2.5GHz Dierential CMOS LNA

Xuan Chen, Quanyuan Feng, and Shiyu Li
Institute of Microelectronics, Southwest Jiaotong University, Chengdu 610031, China
Abstract A 2.5 GHz dierential CMOS LNA which fabricated with the 0.18 m CMOS pro-
cess is proposed and the two-input and two-output architecture are designed. Complying with
the aspects of noise optimization, linear gain and impedance matching, the design methodology
of LNA is analyzed in detail, and the source inductive L
s
, input matching capacitance and gate
width W
1
, W
2
is also discussed. Simulation was made by using the ADS software. Consuming
5.4 mA current at 2 V supply voltage, the proposed LNA exhibits a linear gain of 15.053 dB, noise
gure of 1.910 dB, S
11
of 50.687 dB and S
12
of 18.132 dB.
1. INTRODUCTION
With the rapid development of the communication industry, more and more kinds of wireless
communication apparatus are needed, such as small power radiation, far eective distance, big
coverage range, have been the main target of the businessman and the manufacturer of the wireless
communication apparatus. In this condition, swift developmental radio frequency (RF) wireless
communication technology has been widely used in all elds of the world. Low noise amplier
(LNA) which is in the RF front-end circuit has the great value in this eld [13].
The main eect of the LAN is to amplify the faint signal which is received by the antenna. It
should provide enough gain, low noise gure, high linearity, great input and output matching with
restraint of power consumption. There are so many merits to use dierential architecture, such as
abiding the noise. Millimeter wave signal can be easily leaked, and dierential signal can be used
to eliminate the negative eect of leaking signal. Meanwhile dierential LNA can restrain common
mode interference, so the noise of source voltage and underlay voltage can also be restrained.
In this paper, a modied architecture used for input matching in CMOS LNA is proposed and
the noise optimization is also discussed. A two-input and two-output dierential architecture is
presented, in which the inductance is used as the source inductive degeneration of the C-S amplier
to enlarge the linear range.
2. DESIGN OF THE CIRCUIT ARCHITECTURE
2.1. Proposed Architecture of Input Matching
Figure 1(a) shows a single branch of the dierential pair, it is the cascade architecture with source
inductive degeneration, and the expression of input impedance is:
C1
L1
Rp1
L2
Rp2
M1
Ls
Lg
Rs
Vin
(a) (b)
Figure 1: (a) Source inductive degeneration architecture. (b) Parallel LC network and its equivalent circuit.
Z
in
= s(L
g
+L
s
) +
1
sC
gs
+
g
m
C
gs
L
s
s(L
g
+L
s
)+
1
sC
gs
+w
T
L (1)
To achieve input matching, the Z
in
should be 50 , so
Z
in
=
g
m
C
gs
L
s
= 50 (2)
204 PIERS Proceedings, Cambridge, USA, July 26, 2008
In order to reach the input matching, however, the required gate L
g
should be large enough.
In practice, a large-value inductor is dicult to be implement on-chip based on a CMOS process,
and it will contribute much thermal noise [35]. With the consideration of system integration and
reducing the noise gure, a modied architecture is proposed [2], which is illustrated in Fig. 1(b).
A parallel LC network is designed to replace the inductor. L
1
is an ideal inductor in series with
its parasitic resistance R
P1
. The equal impedance can be derived as Z = jwL
2
+ R
P2
, and is
the operating frequency of the LNA. Where w
01
=
1

L
1
C
1
is the resonant frequency of the L
1
C
1
parallel network,
L
2

L
1
1 w
2
L
1
C
1
=
L
1
1 (w/w
01
)
2
(3)
R
P2

R
P1
(1 w
2
L
1
C
1
)
2
=
R
P1
(1 (w/w
01
)
2
)
2
(4)
Here the LC parallel network is equivalent to an ideal inductor L
2
in series with a resistor R
P2
,
let us see (3), when 0 < 1 w
2
L
1
C
1
< 1, that L
2
> L
1
, and as approaches to
01
, L
2
will be
greatly larger than L
1
. Hence a small LC parallel network will generate a larger inductance and
to replace the large L
g
. So,
Z
in
=

jwL
2
+jw(1 +g
m
R
i
)L
s
j
1
wC
gs

g
m1
C
gs
L
s
+R
P2
+R
g
+R
i

(5)
The really denition of the parameters in (5) can be found in [2].
2.2. Noise Optimization
There are several noise source in a CMOS LNA, such as channel noise, gate induced noise, thermal
noise of various parasitic resistance, etc. As [4] illustrates,
F = F
min
+
R
n
G
s

(G
s
G
opt
)
2
+ (B
s
B
opt
)
2

(6)
w
T
=
g
m
C
gs
(7)
And (6) can be simplied with restraint of power consumption, and F can be written as this:
F
min
1 + 2.3

w
w
T

(8)
Combining (7) and (8), and we know that, g
m
is inverse ratio to F, C
gs
is direct ratio to
F. So the low noise gure properly can be implemented by reducing the C
gs
and enhancing the
transconductance g
m
, and this process can be realized by modulating the width of the transistor and
adjusting the bias circuit with restraint of power consumption. Meanwhile, through the introduction
of L
1
C
1
parallel network we know that the R
P2
is not a fully physical resistor and it will not generate
so much thermal noise as a real resistor dose, so the NF might be somehow improved [2].
2.3. The Main Circuit Architecture
Here, a 2.5 GHz LNA will be designed based on the analysis before, with the 0.18 m CMOS process
and BSIM3 model. The architecture of dierential LNA was showed in Fig. 2.
There are some characteristic in this circuit:
1. A two-input and two-output dierential architecture is presented.
2. Cascade topology with source inductance degeneration (L
s
) is used.
3. The active mirror-biasing circuit is set up with LC parallel network in input terminal.
Cascade can reduce the Miller eect eciently and raise S
12
. The inductance L
s
degeneration
and input matching of transistor are tuned. It is the same with narrowband amplifying, and it can
get low noise gure. M
3
and M
1
are current mirrors and impedance R
bais
need to be chosen big
enough so as to neglect the noise of M
3
which can be converted into an equivalent noise current
source at input terminal of the LNA.
Progress In Electromagnetics Research Symposium, Cambridge, USA, July 26, 2008 205
Figure 2: Circuit schematic of a dierential LNA.
The active bias circuit are consist of transistor M
3
, impedance R
bais
and R
REF
, providing tran-
sistor M
1
with gate current. M
3
and M
1
are current mirrors, they can optimize the noise and
enlarge the gain, and we have to choose the best width of the transistor. Meanwhile, in order to
reduce the additive power consumption of bias circuit farthest, the width of MOSFET M
3
has to
be tenth as the width of the M
1
, and bias impedance R
bais
should be big enough, we choose it 6 k.
C
1
is a blocking capacitor. The L
1
and C
1
are set to 1.0 nH and 0.55 pF, according to (3), it can
generate an inductance around 3 nH.
Because the operating frequency of the dierential LNA is 2.5 GHz, each element in circuit is
modulated, and the parameters of the LNA are simulated by ADS software. Then the width W
1
of
2. 0 2. 5 3. 0 1. 5 3. 5
2. 0
2. 2
2. 4
1. 8
2.6
freq, GHz
10
0
20
fr eq, GHz
2.0 2.5 3.0 1.5 3.5
-40
-20
-60
0
freq, GHz
d
B
(
S
(
1
,
1
)
)
2.0 2.5 3.0
1.5
3.5
-40
-30
-20
-50
-10
freq, GHz
d
B
(
S
(
1
,
2
)
)
n
f
(
2
)
d
B
(
S
(
2
,

1
)
)
2. 0 2. 5 3. 0 1. 5 3. 5
(a) (b)
(c)
(d)
Figure 3: Simulation results. (a) Noise gure, (b) Gain, (c) S
12
, (d) Input matching.
206 PIERS Proceedings, Cambridge, USA, July 26, 2008
the transistor is scan with scope range from 100 m to 400 m. Considering the linear and other
relative index of LNA, we set the value that: W
1
= 250 m, W
2
= 195 m, W
3
= 25 m.
3. RESULTS AND DISCUSSION
Based on the BSIM3 0.18 m model, when the operating frequency is 2.5 GHz and the voltage is
2 V, the ADS software is used to simulate the CMOS LNA, and the results are show in the Fig. 3.
S-parameter is usually used to measure the performance of the LNA. S
11
means input matching,
the value of it below 10 dB is reasonable. S
21
is the gain. NF is the noise gure. S
12
is the reverse
isolation. To reach good performance that LNA noise below 2 dB and gain beyond 10 dB are needed.
As the gure shows, when the operating frequency is 2.5 GHz, S
11
is 50.687 dB, S
12
is 18.132 dB,
S
21
is 15.053 dB, NF is 1.910 dB and the LNA consumes 5.4 mA bias current at 2 V supply voltage.
The values of the parameters are ideal and can satisfy the requirements.
According to the meaning of the stability gure K:
K =
1 |S
11
|
2
|S
22
|
2
+||
2
2|S
12
S
21
|
(9)
= |S
11
S
22
S
12
S
21
| (10)
When K > 1, that || < 1, the circuit is stable unconditionally. According to (9), when input
and output matching are good, decreasing the absolute value of S
12
can increase the stability gure
K. So according to Fig. 3, LNA is stable unconditionally.
4. CONCLUSION
Through modulating and optimizing all parameters of the circuit, each index of 2.5 GHz LNA
can satisfy our requirement. The two-input and two-output dierential architecture can restrain
common mode interference eciently and reduce the underlay noise. In this paper, LC parallel
network is proposed to replace gate inductance, not only the input matching is improved, but also
the noise gure is degraded. The LNA can be integrated on chip more easily and compactly with
small inductance. Considering the circuit application and enhancing the integration, the CMOS
dierential LNA is designed, and it can be utilized in wireless RF receiver which is operated at
2.5 GHz.
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