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s
s
s
s
s
INPUT MULTIPLEXER
- 5 STEREO INPUTS
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
ONE STEREO OUTPUT
AGC
TREBLE AND BASS CONTROL IN 2.0dB
STEPS
VOLUME CONTROL IN 1.0dB STEPS
TWO SPEAKER ATTENUATORS:
- TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
- INDEPENDENT MUTE FUNCTION
TWO SURROND MODES AVAILABLE
- MUSIC
PSEUDO STEREO
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
DESCRIPTION
The TDA7443D is a volume tone (bass and treble)
SO28
ORDERING NUMBER: TDA7443D
VS
28
PS1
AGC
27
LP
L-IN1
26
R-IN1
L-IN2
25
R-IN2
L-IN3
24
R-IN3
L-IN4
23
R-IN4
L-IN5
22
R-IN5
L-MUX
21
R-MUX
L-TREBLE
20
R-TREBLE
L-BASSI
10
19
R-BASSI
L-BASSO
11
18
R-BASSO
L-OUT
12
17
R-OUT
SDA
13
16
CREF
SCL
14
15
GND
D01AU1319
July 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/15
1.2nF
0.47F
0.47F
0.47F
0.47F
0.47F
100nF
100nF
0.47F
0.47F
0.47F
0.47F
26
25
24
23
22
PS1
50K
50K
50K
50K
50K
50K
50K
50K
50K
50K
D01AU1328
L-IN5
L-IN4
L-IN3
L-IN2
L-IN1
28
LP
AGC
27
R-IN1
R-IN2
R-IN3
R-IN4
R-IN5
VREF
INPUT
SELECT
1
GND
15
input gain:
0 to 14dB
/2dB step
input gain:
0 to 14dB
/2dB step
SUPPLY
VS
AGC
CONTROL
SURROUND
INPUT
SELECT
16
22F
CREF
AGC gain:
0 to 7dB
/1dB step
AGC gain:
0 to 7dB
/1dB step
8
L-MUX
VOLUME IN
SELECT
MUTE
NON SURROUND
MUTE
SURROUND IN
SELECT
SURROUND IN
SELECT
VOLUME IN
SELECT
MUTE
NON-SURROUND
MUTE
R-MUX
21
SURROUND ON
SURROUND ON
0.47F
SURROUND
2/15
SURROUND
-63dB att.
/1dB step
VOLUME
VOLUME
-63dB att.
/1dB step
19
100nF
5.6K
-63 att.
/1dB step
R-BASSO
18
BALANCE
-14 to
+14dB
/2dB step
RB
R-BASSI
100nF
BASS
5.6nF
L-TREBLE
-14 to
+14dB
/2dB step
TREBLE
10
100nF
100nF
5.6K
L-BASSI
RB
-14 to
+14dB
/2dB step
BASS
11
L-BASSO
-63 att.
/1dB step
BALANCE
TREBLE
-14 to
+14dB
/2dB step
20
R-TREBLE
5.6nF
12
13
14
17
L-OUT
SDA
SCL
R-OUT
TDA7443D
TDA7443D
ABSOLUTE MAXIMUM RATINGS
Symbol
Vs
Parameter
Value
10.5
Unit
V
Tamb
-10 to 85
Tstg
-55 to 150
Value
Unit
85
C/W
THERMAL DATA
Symbol
Rth j-pin
Parameter
Thermal Resistance Junction-pins
Parameter
Min.
Typ.
Max.
Unit
10
VS
Supply Voltage
VCL
THD
0.01
S/N
100
dB
SC
90
dB
Vrms
0.1
14
dB
dB
-63
dB
-14
+14
dB
-14
+14
dB
-63
dB
Mute Attenuation
90
dB
3/15
TDA7443D
ELECTRICAL CHARACTERISTICS
(Refer to the test circuit Tamb=25C, Vs=9V, f=1kHz ,all controls flat, unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
10
SUPPLY
VS
Supply Voltage
IS
Supply Current
SVR
tbd
60
80
dB
35
Ripple Rejection
mA
50
2.5
Vrms
dB
INPUT STAGE
RIN
Input Resistance
VCL
Clipping Level
SIN
Input Separation
80
100
Gin min
-1
dB
Gin max
13
14
15
dB
Gin step
Step Resolution
1.5
2.5
dB
-1
dB
dB
0.5
1.5
dB
Input Resistance
35
50
65
RPS0
Phase Shifter:D1=0,D0=0
8.3
11.8
15.2
RPS1
Phase Shifter:D1=0,D0=1
10
14.1
18.3
RPS2
Phase Shifter:D1=1,D0=0
12.6
17.9
23.3
RPS3
Phase Shifter:D1=1,D0=1
26.4
37.3
48.85
-21
-6
dB
0.5
1.5
dB
THD = 0.3%
65
AGC
CRANGE
Sstep
VOLUME CONTROL
AVOLmin
Minimum Attenuation
-1
dB
AVOLmax
Maximum Attenuation
61
63
65
dB
AVOLstep
Step Resolution
0.5
1.5
dB
EA
AV = 0 to 24 dB
-1
dB
AV = 24 to 63 dB
-2
dB
-3
mV
12
14
16
dB
VDC
DC Steps
BASS CONTROL
GB
4/15
Control Range
Max. Boost/Cut
TDA7443D
ELECTRICAL CHARACTERISTICS (continued)
(Refer to the test circuit Tamb=25C, Vs=9V, f=1kHz ,all controls flat, unless otherwise specified)
Symbol
Bstep
RB
Parameter
Conditions
Min.
Typ.
Max.
Unit
Step Resolution
dB
33
44
55
13
14
15
dB
dB
TREBLE CONTROL
GT
Tstep
RT
Control Range
Max. Boost/Cut
Step Resolution
Internal Feedback Resistance
25
BALANCE CONTROL
ABALmin
Minimum Attenuation
-1
dB
ABALmax
Maximum Attenuation
61
63
65
dB
ABALstep
Step Resolution
dB
VDC
DC Steps
AV = 0 to 24 dB
-1
dB
AV = 24 to 63 dB
EA
-2
dB
-3
mV
THD = 0.3%
2.5
AUDIO OUTPUTS
VOCL
RL
VOUT
NO(OFF)
NO(MUS)
NO(PS)
AMUTE
Clipping Level
Output Load Resistance
DC Voltage Level
Output Noise (OFF)
SC
Distortion
BW=20Hz to 20kHz;
All gains 0dB;
Output muted
flat
5
10
BW=20Hz to 20kHz;
Mode=Music
30
BW=20Hz to 20kHz;
Mode=Pseudo Stereo
30
90
dB
100
dB
90
dB
k
4.5
S/N
Vrms
AV = 0; VI = 1Vrms
0.01
15
V
V
0.1
BUS INPUT
VIL
VIH
IIN
Input Current
VIN = 0.4V
VO
IO = 1.6mA
2.5
V
5
-5
0.4
0.8
5/15
TDA7443D
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7443D and vice versa takes place through the 2 wires I2C BUS
interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
Data Validity
As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and Stop Conditions
As shown in fig. 2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
Acknowledge
The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 3). The
peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of each
byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the P can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 1. Data Validity on the I2CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
START
STOP
SDA
MSB
START
6/15
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
TDA7443D
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
s A start condition (S)
s
A subaddress bytes
CHIP ADDRESS
MSB
S
LSB
0
DATA 1 to DATA n
MSB
ACK
LSB
X
DATA
MSB
ACK
LSB
DATA
ACK
D96AU420
ACK = Acknowledge;
S = Start;
P = Stop;
A = Address;
B = Auto Increment
EXAMPLES
No Incremental Bus
The TDA7443D receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental
bus), N-data (all these data concern the subaddress selected), a stop condition.
SUBADDRESS
CHIP ADDRESS
MSB
S
LSB
0
MSB
ACK
DATA
LSB
0 D3 D2 D1 D0
MSB
ACK
LSB
DATA
ACK
D96AU421
Incremental Bus
The TDA7443D receivea start conditions, the correct chip address, a subaddress with the B = 1 (incremental
bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from
"XXX1000" to "XXX1111" of DATA are ignored.The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
SUBADDRESS
CHIP ADDRESS
MSB
S
LSB
0
MSB
ACK
DATA 1 to DATA n
LSB
1 D3 D2 D1 D0
MSB
ACK
LSB
DATA
ACK
D96AU422
7/15
TDA7443D
POWER ON RESET CONDITION
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTES
Address=(HEX) 10001000
FUNCTION SELECTION: First byte (subaddress)
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
AGC
SURROUND
VOLUME
TONE
BALANCE L
BALANCE R
D3
D2
D1
D0
IN1
IN2
IN3
INPUT
LSB
D6
D5
D4
SUBADDRESS
INPUT SELECT
IN4
IN5
MUTE
Output Mute ON
SURROUND IN SELECT
0
1
Surround ONl
Mute
INPUT GAIN
0dB
2dB
4dB
6dB
8dB
10dB
12dB
8/15
14dB
TDA7443D
AGC
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
AGC MODE
0
OFF
ON
DETECTOR
OFF
ON
RELEASE CURRENT
OFF
ON
ATTACK TIME
ATTACK1
ATTACK2
ATTACK3
ATTACK4
TARGET LEVEL
TARGET1
TARGET2
TARGET3
TARGET4
ZEROCROSS
OFF
ON
9/15
TDA7443D
SURROUND
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
SURROUND MODE
PSEUDO STEREO
MUSIC
EFFECT CONTROL
-6 dB
-7 dB
-8 dB
-9 dB
-10 dB
-11 dB
-12 dB
-13 dB
-14 dB
-15 dB
-16 dB
-17 dB
-18 dB
-19 dB
-20 dB
-21 dB
PHASE SHIFT RESISTOR
12 kohm
14 kohm
18 kohm
37 kohm
10/15
TDA7443D
VOLUME
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
VOLUME IN SELECT
Surround
Non Surround
Mute
1dB STEPS
0dB
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
8dB STEPS
0dB
-8dB
-16dB
-24dB
-32dB
-40dB
-48dB
-56dB
VOLUME=0 to 63dB
11/15
TDA7443D
TREBLE & BASS
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
TREBLE
-14 dB
-12 dB
-10 dB
-8 dB
-6 dB
-4 dB
-2 dB
0 dB
14 dB
12 dB
10 dB
8 dB
6 dB
4 dB
2 dB
0 dB
BASS
-14 dB
-12 dB
-10 dB
-8 dB
-6 dB
-4 dB
-2 dB
0 dB
14 dB
12 dB
10 dB
8 dB
6 dB
4 dB
2 dB
0 dB
12/15
TDA7443D
BALANCE
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
1dB STEPS
0dB
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
8dB STEPS
0dB
-8dB
-16dB
-24dB
-32dB
-40dB
-48dB
-56dB
VOLUME=0 to 63dB
13/15
TDA7443D
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
2.65
MAX.
OUTLINE AND
MECHANICAL DATA
0.104
a1
0.1
0.3
0.004
0.012
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
0.5
c1
0.020
45 (typ.)
17.7
18.1
0.697
0.713
10
10.65
0.394
0.419
1.27
0.050
e3
16.51
0.65
7.4
7.6
0.291
0.299
0.4
1.27
0.016
0.050
14/15
8 (max.)
SO28
TDA7443D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - All Rights Reserved
15/15