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Copyright 2006 ABB. All rights reserved.

Technical reference manual


Transformer protection IED
RET670
About this manual
Document No: 1MRK 504 048-UEN
Issued: J anuary 2006
Revision: A
COPYRIGHT
WE RESERVE ALL RIGHTS TO THIS DOCUMENT, EVEN IN THE EVENT THAT A PATENT IS
ISSUED AND A DIFFERENT COMMERCIAL PROPRIETARY RIGHT IS REGISTERED. IMPROPER
USE, IN PARTICULAR REPRODUCTION AND DISSEMINATION TO THIRD PARTIES, IS NOT
PERMITTED.
THIS DOCUMENT HAS BEEN CAREFULLY CHECKED. HOWEVER, IN CASE ANY ERRORS ARE
DETECTED, THE READER IS KINDLY REQUESTED TO NOTIFY THE MANUFACTURER AT THE
ADDRESS BELOW.
THE DATA CONTAINED IN THIS MANUAL IS INTENDED SOLELY FOR THE CONCEPT OR
PRODUCT DESCRIPTION AND IS NOT TO BE DEEMED TO BE A STATEMENT OF GUARAN-
TEED PROPERTIES. IN THE INTERESTS OF OUR CUSTOMERS, WE CONSTANTLY SEEK TO
ENSURE THAT OUR PRODUCTS ARE DEVELOPED TO THE LATEST TECHNOLOGICAL STAN-
DARDS. AS A RESULT, IT IS POSSIBLE THAT THERE MAY BE SOME DIFFERENCES BETWEEN
THE HW/SW PRODUCT AND THIS INFORMATION PRODUCT.
Manufacturer:
ABB Power Technologies AB
Substation Automation Products
SE-721 59 Vsters
Sweden
Telephone: +46 (0) 21 34 20 00
Facsimile: +46 (0) 21 14 69 18
www.abb.com/substationautomation
Contents
Page Chapter
Chapter 1 Introduction ..................................................................... 1
Introduction to the technical reference manual.................................... 2
About the complete set of manuals for an IED............................... 2
About the technical reference manual ............................................ 2
Design of the Technical reference manual (TRM).......................... 3
Intended audience.......................................................................... 8
Related documents......................................................................... 9
Revision notes.............................................................................. 10
Chapter 2 Local human-machine interface .................................. 11
Human machine interface.................................................................. 12
Small size graphic HMI ...................................................................... 14
Introduction................................................................................... 14
Design .......................................................................................... 14
Medium size graphic HMI .................................................................. 16
Introduction................................................................................... 16
Design .......................................................................................... 16
Keypad............................................................................................... 18
LED.................................................................................................... 20
Introduction................................................................................... 20
Status indication LEDs ................................................................. 20
Indication LEDs ............................................................................ 20
LHMI related functions....................................................................... 22
Introduction................................................................................... 22
General setting parameters.......................................................... 22
Status indication LEDs ................................................................. 22
Design..................................................................................... 22
Function block......................................................................... 23
Input and output signals .......................................................... 23
Indication LEDs ............................................................................ 23
Introduction.............................................................................. 23
Design..................................................................................... 23
Function block......................................................................... 31
Input and output signals .......................................................... 31
Setting parameters .................................................................. 32
Chapter 3 Basic IED functions ...................................................... 35
Analog inputs..................................................................................... 36
Introduction................................................................................... 36
Principle of operation.................................................................... 36
Function block .............................................................................. 37
Output signals............................................................................... 39
Contents
Setting parameters ....................................................................... 41
Self supervision with internal event list.............................................. 48
Introduction................................................................................... 48
Principle of operation.................................................................... 48
Function block............................................................................... 53
Output signals............................................................................... 53
Setting parameters ....................................................................... 53
Technical data .............................................................................. 53
Time synchronization......................................................................... 54
Introduction................................................................................... 54
Principle of operation.................................................................... 54
Function block............................................................................... 58
Output signals............................................................................... 58
Setting parameters ....................................................................... 58
Technical data .............................................................................. 61
Parameter setting groups .................................................................. 62
Introduction................................................................................... 62
Principle of operation.................................................................... 62
Function block............................................................................... 63
Input and output signals................................................................ 64
Setting parameters ....................................................................... 64
Test mode functionality...................................................................... 66
Introduction................................................................................... 66
Principle of operation.................................................................... 66
Function block............................................................................... 67
Input and output signals................................................................ 68
Setting parameters ....................................................................... 68
IED identifiers .................................................................................... 69
Introduction................................................................................... 69
Setting parameters ....................................................................... 69
Signal matrix for binary inputs (SMBI) ............................................... 70
Introduction................................................................................... 70
Principle of operation.................................................................... 70
Function block............................................................................... 70
Input and output signals................................................................ 70
Signal matrix for binary outputs (SMBO) ........................................... 72
Introduction................................................................................... 72
Principle of operation.................................................................... 72
Function block............................................................................... 72
Input and output signals................................................................ 72
Signal matrix for mA inputs (SMMI) ................................................... 74
Introduction................................................................................... 74
Principle of operation.................................................................... 74
Function block............................................................................... 74
Input and output signals................................................................ 74
Signal matrix for analog inputs (SMAI) .............................................. 76
Introduction................................................................................... 76
Principle of operation.................................................................... 76
Function block............................................................................... 76
Input and output signals................................................................ 77
Setting parameters ....................................................................... 79
Summation block 3 phase (SUM3Ph)................................................ 81
Introduction................................................................................... 81
Contents
Principle of operation.................................................................... 81
Function block .............................................................................. 81
Input and output signals ............................................................... 81
Setting parameters ....................................................................... 82
Chapter 4 Differential protection................................................... 83
Transformer differential protection (PDIF, 87T)................................. 84
Introduction................................................................................... 84
Principle of operation.................................................................... 86
Function block ............................................................................ 109
Input and output signals ............................................................. 110
Setting parameters ..................................................................... 114
Technical data............................................................................ 119
Restricted earth fault protection (PDIF, 87N)................................... 120
Introduction................................................................................. 120
Principle of operation.................................................................. 120
Function block ............................................................................ 128
Input and output signals ............................................................. 128
Setting parameters ..................................................................... 129
Technical data............................................................................ 129
High impedance differential protection (PDIF, 87)........................... 130
Introduction................................................................................. 130
Principle of operation.................................................................. 130
Function block ............................................................................ 131
Input and output signals ............................................................. 131
Setting parameters ..................................................................... 132
Technical data............................................................................ 132
Chapter 5 Distance protection..................................................... 133
Distance protection zones (PDIS, 21).............................................. 134
Introduction................................................................................. 134
Principle of operation.................................................................. 134
Function block ............................................................................ 147
Input and output signals ............................................................. 148
Setting parameters ..................................................................... 149
Technical data............................................................................ 150
Phase selection with load encroachment (PDIS, 21)....................... 152
Introduction................................................................................. 152
Principle of operation.................................................................. 152
Function block ............................................................................ 166
Input and output signals ............................................................. 166
Setting parameters ..................................................................... 167
Technical data............................................................................ 168
Power swing detection (RPSB, 78).................................................. 169
Introduction................................................................................. 169
Principle of operation.................................................................. 169
Function block ............................................................................ 175
Input and output signals ............................................................. 175
Contents
Setting parameters ..................................................................... 176
Technical data ............................................................................ 177
Automatic switch onto fault logic (PSOF)......................................... 178
Introduction................................................................................. 178
Principle of operation.................................................................. 178
Function block............................................................................. 180
Input and output signals.............................................................. 180
Setting parameters ..................................................................... 180
Technical data ............................................................................ 181
Chapter 6 Current protection....................................................... 183
Instantaneous phase overcurrent protection (PIOC, 50) ................. 184
Introduction................................................................................. 184
Principle of operation.................................................................. 184
Function block............................................................................. 184
Input and output signals.............................................................. 185
Setting parameters ..................................................................... 185
Technical data ............................................................................ 185
Four step phase overcurrent protection (POCM, 51/67).................. 187
Introduction................................................................................. 187
Principle of operation.................................................................. 187
Function block............................................................................. 191
Input and output signals.............................................................. 192
Setting parameters ..................................................................... 193
Technical data ............................................................................ 199
Instantaneous residual overcurrent protection (PIOC, 50N)............ 201
Introduction................................................................................. 201
Principle of operation.................................................................. 201
Function block............................................................................. 202
Input and output signals.............................................................. 202
Setting parameters ..................................................................... 202
Technical data ............................................................................ 203
Four step residual overcurrent protection (PEFM, 51N/67N)........... 204
Introduction................................................................................. 204
Principle of operation.................................................................. 204
Function block............................................................................. 207
Input and output signals.............................................................. 208
Setting parameters ..................................................................... 209
Technical data ............................................................................ 215
Thermal overload protection, two time constants (PTTR, 49).......... 217
Introduction................................................................................. 217
Principle of operation.................................................................. 217
Function block............................................................................. 221
Input and output signals.............................................................. 221
Setting parameters ..................................................................... 222
Technical data ............................................................................ 223
Breaker failure protection (RBRF, 50BF)......................................... 224
Introduction................................................................................. 224
Principle of operation.................................................................. 224
Function block............................................................................. 227
Contents
Input and output signals ............................................................. 227
Setting parameters ..................................................................... 228
Technical data............................................................................ 229
Pole discordance protection (RPLD, 52PD) .................................... 230
Introduction................................................................................. 230
Principle of operation.................................................................. 230
Function block ............................................................................ 233
Input and output signals ............................................................. 234
Setting parameters ..................................................................... 234
Technical data............................................................................ 235
Chapter 7 Voltage protection....................................................... 237
Two step undervoltage protection (PUVM, 27)................................ 238
Introduction................................................................................. 238
Principle of operation.................................................................. 238
Function block ............................................................................ 247
Input and output signals ............................................................. 247
Setting parameters ..................................................................... 248
Technical data............................................................................ 251
Two step overvoltage protection (POVM, 59).................................. 252
Introduction................................................................................. 252
Principle of operation.................................................................. 252
Function block ............................................................................ 260
Input and output signals ............................................................. 260
Setting parameters ..................................................................... 261
Technical data............................................................................ 263
Two step residual overvoltage protection (POVM, 59N).................. 264
Introduction................................................................................. 264
Principle of operation.................................................................. 264
Function block ............................................................................ 270
Input and output signals ............................................................. 270
Setting parameters ..................................................................... 271
Technical data............................................................................ 273
Overexcitation protection (PVPH, 24).............................................. 274
Introduction................................................................................. 274
Principle of operation.................................................................. 274
Function block ............................................................................ 282
Input and output signals ............................................................. 283
Setting parameters ..................................................................... 283
Technical data............................................................................ 285
Chapter 8 Frequency protection ................................................. 287
Underfrequency protection (PTUF, 81)............................................ 288
Introduction................................................................................. 288
Principle of operation.................................................................. 288
Function block ............................................................................ 294
Input and output signals ............................................................. 295
Setting parameters ..................................................................... 295
Contents
Technical data ............................................................................ 296
Overfrequency protection (PTOF, 81).............................................. 297
Introduction................................................................................. 297
Principle of operation.................................................................. 297
Function block............................................................................. 302
Input and output signals.............................................................. 302
Setting parameters ..................................................................... 302
Technical data ............................................................................ 303
Rate-of-change frequency protection (PFRC, 81) ........................... 304
Introduction................................................................................. 304
Principle of operation.................................................................. 304
Function block............................................................................. 311
Input and output signals.............................................................. 311
Setting parameters ..................................................................... 312
Technical data ............................................................................ 312
Chapter 9 Multipurpose protection ............................................. 313
General current and voltage protection (GAPC).............................. 314
Introduction................................................................................. 314
Principle of operation.................................................................. 314
Function block............................................................................. 328
Input and output signals.............................................................. 329
Setting parameters ..................................................................... 331
Technical data ............................................................................ 340
Chapter 10 Secondary system supervision.................................. 343
Current circuit supervision (RDIF).................................................... 344
Introduction................................................................................. 344
Principle of operation.................................................................. 344
Function block............................................................................. 346
Input and output signals.............................................................. 346
Setting parameters ..................................................................... 347
Technical data ............................................................................ 347
Fuse failure supervision (RFUF)...................................................... 348
Introduction................................................................................. 348
Principle of operation.................................................................. 348
Function block............................................................................. 355
Input and output signals.............................................................. 355
Setting parameters ..................................................................... 356
Technical data ............................................................................ 357
Chapter 11 Control .......................................................................... 359
Synchrocheck and energizing check (RSYN, 25)............................ 360
Introduction................................................................................. 360
Principle of operation.................................................................. 360
Contents
Basic functionality.................................................................. 360
Logic diagrams ...................................................................... 360
Function block ............................................................................ 368
Input and output signals ............................................................. 369
Setting parameters ..................................................................... 371
Technical data............................................................................ 373
Apparatus control (APC).................................................................. 375
Introduction................................................................................. 375
Principle of operation.................................................................. 375
Bay control (QCBAY).................................................................. 376
Introduction............................................................................ 376
Principle of operation............................................................. 376
Function block....................................................................... 377
Input and output signals ........................................................ 378
Setting parameters ................................................................ 378
Local/Remote switch (LocalRemote, LocRemControl)............... 378
Introduction............................................................................ 378
Principle of operation............................................................. 378
Function block....................................................................... 380
Input and output signals ........................................................ 380
Setting parameters ................................................................ 381
Switch controller (SCSWI).......................................................... 382
Introduction............................................................................ 382
Principle of operation............................................................. 382
Function block....................................................................... 388
Input and output signals ........................................................ 388
Setting parameters ................................................................ 389
Circuit breaker (SXCBR)............................................................. 390
Introduction............................................................................ 390
Principle of operation............................................................. 390
Function block....................................................................... 394
Input and output signals ........................................................ 395
Setting parameters ................................................................ 396
Circuit switch (SXSWI)................................................................ 396
Introduction............................................................................ 396
Principle of operation............................................................. 396
Function block....................................................................... 401
Input and output signals ........................................................ 401
Setting parameters ................................................................ 402
Bay reserve (QCRSV) ................................................................ 402
Introduction............................................................................ 402
Principle of operation............................................................. 402
Function block....................................................................... 405
Input and output signals ........................................................ 405
Setting parameters ................................................................ 406
Reservation input (RESIN) ......................................................... 406
Introduction............................................................................ 406
Principle of operation............................................................. 407
Function block....................................................................... 408
Input and output signals ........................................................ 408
Setting parameters ................................................................ 409
Interlocking...................................................................................... 410
Introduction................................................................................. 410
Contents
Principle of operation.................................................................. 410
Logical node for interlocking (SCILO)......................................... 413
Introduction............................................................................ 413
Principle of operation............................................................. 413
Function block ....................................................................... 414
Input and output signals ........................................................ 414
Interlocking for line bay (ABC_LINE).......................................... 415
Introduction............................................................................ 415
Function block ....................................................................... 416
Logic diagram........................................................................ 417
Input and output signals ........................................................ 422
Interlocking for bus-coupler bay (ABC_BC)................................ 424
Introduction............................................................................ 424
Function block ....................................................................... 426
Logic diagram........................................................................ 427
Input and output signals ........................................................ 432
Interlocking for transformer bay (AB_TRAFO)............................ 434
Introduction............................................................................ 434
Function block ....................................................................... 435
Logic diagram........................................................................ 436
Input and output signals ........................................................ 439
Interlocking for bus-section breaker (A1A2_BS)......................... 441
Introduction............................................................................ 441
Function block ....................................................................... 442
Logic diagram........................................................................ 443
Input and output signals ........................................................ 445
Interlocking for bus-section disconnector (A1A2_DC)................ 446
Introduction............................................................................ 446
Function block ....................................................................... 447
Logic diagram........................................................................ 448
Input and output signals ........................................................ 449
Interlocking for busbar earthing switch (BB_ES) ........................ 450
Introduction............................................................................ 450
Function block ....................................................................... 450
Logic diagram........................................................................ 451
Input and output signals ........................................................ 451
Interlocking for double CB bay (DB) ........................................... 451
Introduction............................................................................ 451
Function block ....................................................................... 453
Logic diagrams ...................................................................... 455
Input and output signals ....................................................... 461
Interlocking for 1 1/2 CB diameter (BH)...................................... 464
Introduction............................................................................ 464
Function blocks...................................................................... 466
Logic diagrams ...................................................................... 469
Input and output signals ........................................................ 476
Logic rotating switch for function selection
and LHMI presentation (GGIO)........................................................ 481
Introduction................................................................................. 481
Principle of operation.................................................................. 481
Function block............................................................................. 482
Input and output signals.............................................................. 482
Setting parameters ..................................................................... 484
Contents
Chapter 12 Logic............................................................................. 487
Tripping logic (PTRC, 94) ................................................................ 488
Introduction................................................................................. 488
Principle of operation.................................................................. 488
Function block ............................................................................ 493
Input and output signals ............................................................. 494
Setting parameters ..................................................................... 495
Technical data............................................................................ 495
Trip matrix logic (GGIO, 94X) .......................................................... 496
Introduction................................................................................. 496
Principle of operation.................................................................. 496
Function block ............................................................................ 498
Input and output signals ............................................................. 498
Setting parameters ..................................................................... 500
Configurable logic blocks (LLD)....................................................... 501
Introduction................................................................................. 501
Inverter function block (INV)....................................................... 501
OR function block (OR)............................................................... 501
AND function block (AND).......................................................... 502
Timer function block (Timer)....................................................... 503
Pulse timer function block (PULSE)............................................ 503
Exclusive OR function block (XOR)............................................ 504
Set-reset with memory function block (SRM) ............................. 504
Controllable gate function block (GT)......................................... 505
Settable timer function block (TS)............................................... 506
Technical data............................................................................ 507
Fixed signal function block (FIXD)................................................... 508
Introduction................................................................................. 508
Principle of operation.................................................................. 508
Function block ............................................................................ 508
Input and output signals ............................................................. 508
Setting parameters ..................................................................... 509
Chapter 13 Monitoring.................................................................... 511
Measurements (MMXU, MSQI) ....................................................... 512
Introduction................................................................................. 512
Principle of operation.................................................................. 514
Function block ............................................................................ 524
Input and output signals ............................................................. 526
Setting parameters ..................................................................... 528
Technical data............................................................................ 544
Event counter (GGIO)...................................................................... 545
Introduction................................................................................. 545
Principle of operation.................................................................. 545
Function block ............................................................................ 546
Input signals ............................................................................... 546
Setting parameters ..................................................................... 546
Technical data............................................................................ 546
Event function (EV).......................................................................... 547
Contents
Introduction................................................................................. 547
Principle of operation.................................................................. 547
Function block............................................................................. 548
Input and output signals.............................................................. 549
Setting parameters ..................................................................... 550
Technical data ............................................................................ 552
Measured value expander block...................................................... 553
Introduction................................................................................. 553
Principle of operation.................................................................. 553
Function block............................................................................. 554
Input and output signals.............................................................. 554
Disturbance report (RDRE).............................................................. 555
Introduction................................................................................. 555
Principle of operation.................................................................. 555
Function block............................................................................. 563
Input and output signals.............................................................. 565
Setting parameters ..................................................................... 568
Technical data ............................................................................ 580
Event list (RDRE)............................................................................. 582
Introduction................................................................................. 582
Principle of operation.................................................................. 582
Function block............................................................................. 582
Input signals................................................................................ 582
Technical data ............................................................................ 583
Indications (RDRE).......................................................................... 584
Introduction................................................................................. 584
Principle of operation.................................................................. 584
Function block............................................................................. 585
Input signals................................................................................ 585
Technical data ............................................................................ 585
Event recorder (RDRE).................................................................... 586
Introduction................................................................................. 586
Principle of operation.................................................................. 586
Function block............................................................................. 586
Input signals................................................................................ 586
Technical data ............................................................................ 587
Trip value recorder (RDRE)............................................................. 588
Introduction................................................................................. 588
Principle of operation.................................................................. 588
Function block............................................................................. 588
Input signals................................................................................ 589
Technical data ............................................................................ 589
Disturbance recorder (RDRE).......................................................... 590
Introduction................................................................................. 590
Principle of operation.................................................................. 590
Function block............................................................................. 592
Input and output signals.............................................................. 592
Setting parameters ..................................................................... 593
Technical data ............................................................................ 593
Chapter 14 Metering ....................................................................... 595
Contents
Pulse counter logic (GGIO).............................................................. 596
Introduction................................................................................. 596
Principle of operation.................................................................. 596
Function block ............................................................................ 598
Input and output signals ............................................................. 598
Setting parameters ..................................................................... 599
Technical data............................................................................ 599
Chapter 15 Station communication .............................................. 601
Overview.......................................................................................... 602
IEC 61850-8-1 communication protocol .......................................... 603
Introduction................................................................................. 603
Generic single point function block (SPGGIO) ........................... 603
Introduction............................................................................ 603
Principle of operation............................................................. 603
Function block....................................................................... 603
Input and output signals ........................................................ 603
Setting parameters ................................................................ 603
Generic double point function block (DPGGIO).......................... 604
Introduction............................................................................ 604
Principle of operation............................................................. 604
Function block....................................................................... 604
Input and output signals ........................................................ 604
Setting parameters ................................................................ 604
Generic measured values function block (MVGGIO).................. 605
Introduction............................................................................ 605
Principle of operation............................................................. 605
Function block....................................................................... 605
Input and output signals ........................................................ 605
Setting parameters ................................................................ 606
Technical data............................................................................ 606
LON communication protocol .......................................................... 607
Introduction................................................................................. 607
Principle of operation.................................................................. 607
Setting parameters ..................................................................... 623
Technical data............................................................................ 623
SPA communication protocol........................................................... 624
Introduction................................................................................. 624
Principle of operation.................................................................. 624
Design ........................................................................................ 633
Setting parameters ..................................................................... 633
Technical data............................................................................ 634
IEC 60870-5-103 communication protocol ...................................... 635
Introduction................................................................................. 635
Principle of operation.................................................................. 635
Function block ............................................................................ 645
Input and output signals ............................................................. 648
Setting parameters ..................................................................... 653
Technical data............................................................................ 656
Single command, 16 signals (CD) ................................................... 657
Contents
Introduction................................................................................. 657
Principle of operation.................................................................. 657
Function block............................................................................. 658
Input and output signals.............................................................. 658
Setting parameters ..................................................................... 659
Multiple command (CM) and Multiple transmit (MT)........................ 660
Introduction................................................................................. 660
Principle of operation.................................................................. 660
Design......................................................................................... 660
Function block............................................................................. 661
Input and output signals.............................................................. 661
Setting parameters ..................................................................... 663
Chapter 16 Remote communication.............................................. 665
Binary signal transfer to remote end................................................ 666
Introduction................................................................................. 666
Principle of operation.................................................................. 666
Setting parameters ..................................................................... 667
Chapter 17 Hardware...................................................................... 669
Overview.......................................................................................... 670
Variants of case- and HMI display size....................................... 670
Case from the rear side.............................................................. 673
Hardware modules........................................................................... 676
Overview..................................................................................... 676
Combined backplane module (CBM).......................................... 677
Introduction............................................................................ 677
Functionality .......................................................................... 677
Design ................................................................................... 677
Universal backplane module (UBM) ........................................... 679
Introduction............................................................................ 679
Functionality .......................................................................... 679
Design ................................................................................... 679
Power supply module (PSM) ...................................................... 682
Introduction............................................................................ 682
Design ................................................................................... 682
Technical data....................................................................... 682
Numeric processing module (NUM)............................................ 683
Introduction............................................................................ 683
Functionality .......................................................................... 683
Block diagram........................................................................ 684
Local human-machine interface (LHMI)...................................... 684
Transformer input module (TRM) ............................................... 685
Introduction............................................................................ 685
Design ................................................................................... 685
Technical data....................................................................... 685
Analog digital conversion module,
with time synchronization (ADM) ............................................. 686
Contents
Introduction............................................................................ 686
Design................................................................................... 686
Binary input module (BIM).......................................................... 688
Introduction............................................................................ 688
Design................................................................................... 688
Technical data....................................................................... 692
Binary output modules (BOM) .................................................... 692
Introduction............................................................................ 692
Design................................................................................... 693
Technical data....................................................................... 695
Binary input/output module (IOM)............................................... 695
Introduction............................................................................ 695
Design................................................................................... 695
Technical data....................................................................... 697
Line data communication module (LDCM) ................................. 698
Introduction............................................................................ 698
Design................................................................................... 698
Technical data....................................................................... 698
Serial SPA/LON/IEC 608705103
communication module (SLM) ................................................ 699
Introduction............................................................................ 699
Design................................................................................... 699
Technical data....................................................................... 700
Optical ethernet module (OEM).................................................. 701
Introduction............................................................................ 701
Functionality.......................................................................... 701
Design................................................................................... 701
Technical data....................................................................... 702
mA input module (MIM) .............................................................. 702
Introduction............................................................................ 702
Design................................................................................... 702
Technical data....................................................................... 704
GPS time synchronization module (GSM).................................. 704
Introduction............................................................................ 704
Design................................................................................... 704
Technical data....................................................................... 706
GPS antenna.............................................................................. 707
Introduction............................................................................ 707
Design................................................................................... 707
Technical data....................................................................... 708
Case dimensions ............................................................................. 709
Case without rear cover.............................................................. 709
Case with rear cover................................................................... 710
Panel cut-outs for single case .................................................... 711
Side-by-side flush mounting dimensions.................................... 712
Wall mounting dimensions.......................................................... 714
Mounting alternatives....................................................................... 716
Flush mounting, single case....................................................... 716
Side-by-side flush mounting details............................................ 717
Wall mounting............................................................................. 717
Wall mounting details ............................................................ 718
Side-by-side................................................................................ 720
Mounting in a 19-inch rack ......................................................... 721
Contents
Technical data ................................................................................. 722
Enclosure.................................................................................... 722
Connection system..................................................................... 722
Influencing factors....................................................................... 723
Type tests according to standard................................................ 724
Chapter 18 Connection diagrams.................................................. 727
Chapter 19 Time inverse characteristics ...................................... 743
Application....................................................................................... 744
Principle of operation....................................................................... 748
Mode of operation....................................................................... 748
Inverse characteristics..................................................................... 754
Chapter 20 Glossary ....................................................................... 767
Glossary........................................................................................... 768
1
About this chapter Chapter 1
Introduction
Chapter 1 Introduction
About this chapter
This chapter explains concepts and conventions used in this manual and provides information
necessary to understand the contents of the manual.
2
Introduction to the technical reference manual Chapter 1
Introduction
1 Introduction to the technical reference manual
1.1 About the complete set of manuals for an IED
The users manual (UM) is a complete set of four different manuals:
The Application Manual (AM) contains application descriptions, setting guidelines and setting
parameters sorted per function. The application manual should be used to find out when and for
what purpose a typical protection function could be used. The manual should also be used when
calculating settings.
The Technical Reference Manual (TRM) contains application and functionality descriptions
and it lists function blocks, logic diagrams, input and output signals, setting parameters and tech-
nical data sorted per function. The technical reference manual should be used as a technical ref-
erence during the engineering phase, installation and commissioning phase, and during normal
service.
The Installation and Commissioning Manual (ICM) contains instructions on how to install
and commission the protection IED. The manual can also be used as a reference during periodic
testing. The manual covers procedures for mechanical and electrical installation, energizing and
checking of external circuitry, setting and configuration as well as verifying settings and per-
forming directional tests. The chapters are organized in the chronological order (indicated by
chapter/section numbers) in which the protection IED should be installed and commissioned.
The Operators Manual (OM) contains instructions on how to operate the protection IED dur-
ing normal service once it has been commissioned. The operators manual can be used to find
out how to handle disturbances or how to view calculated and measured network data in order
to determine the cause of a fault.
1.2 About the technical reference manual
The technical reference manual contains the following chapters:
Thechapter IED Overview describes the IED in general.
The chapter Local human-machine interface describes the control panel on the
IED. Display characteristics, control keys and various local human-machine in-
terface features are explained.
Application
manual
Technical
reference
manual
Installation and
commissioning
manual
Operators
manual
en01000044.vsd
3
Introduction to the technical reference manual Chapter 1
Introduction
The chapter Basic IED functions presents functions that are included in all
IEDs regardless of the type of protection they are designed for. These are func-
tions like Time synchronization, Self supervision with event list, Test mode and
other functions of a general nature.
The chapter Distance protection describes the functions for distance zones
with their quadrilateral characteristics, phase selection with load encroachment,
power swing detection and similar.
The chapter Current protection describes functions such as overcurrent pro-
tection, breaker failure protection and pole discordance.
The chapter Voltage protection describes functions like undervoltage and ov-
ervoltage protection as well as residual overvoltage protection.
The chapter Frequency protection describes functions for overfrequency, un-
derfrequency and rate of change of frequency.
The chapter Multipurpose protection describes the general protection function
for current and voltage.
The chapter Secondary system supervision includes descriptions of functions
like current based Current circuit supervision and Fuse failure supervision.
The chapter Control describes the control functions. These are functions like
the Synchronization and energizing check as well as several others which are
product specific.
The chapter Scheme communication describes among others functions related
to current reversal and weak end infeed logic.
The chapter Logic describes trip logic and related functions.
The chapter Monitoring describes measurement related functions used to pro-
vide data regarding relevant quantities, events, faults and the like.
The chapter Metering describes primarily Pulse counter logic.
The chapter Station communication describes Ethernet based communication
in general including the use of IEC61850, and horizontal communication via
GOOSE.
The chapter Remote communication describes binary and analog signal trans-
fer, and the associated hardware.
The chapter Hardware provides descriptions of the IED and its components.
The chapter Connection diagrams provides terminal wiring diagrams and in-
formation regarding connections to and from the IED.
The chapter Time inverse characteristics describes and explains inverse time
delay, inverse time curves and their effects.
The chapter Glossary is a list of terms, acronyms and abbreviations used in
ABB technical documentation.
1.3 Design of the Technical reference manual (TRM)
The description of each IED related function follows the same structure (where applicable). The
different sections are outlined below.
1.3.1 Introduction
Outlines the implementation of a particular protection function.
4
Introduction to the technical reference manual Chapter 1
Introduction
1.3.2 Principle of operation
Describes how the function works, presents a general background to algorithms and measure-
ment techniques. Logic diagrams are used to illustrate functionality.
Logic diagrams
Logic diagrams describe the signal logic inside the function block and are bordered by dashed
lines.
Signal names
Input and output logic signals consist of two groups of letters separated by two dashes. The first
group consists of up to four letters and presents the abbreviated name for the corresponding
function. The second group presents the functionality of the particular signal. According to this
explanation, the meaning of the signal BLKTR in figure4 is as follows:
BLKTR informs the user that the signal will BLOCK the TRIP command from
the under-voltage function, when its value is a logical one (1).
Input signals are always on the left hand side, and output signals on the right hand side. Settings
are not displayed.
Input and output signals
In a logic diagram, input and output signal paths are shown as a lines that touch the outer border
of the diagram.
Input and output signals can be configured using the CAP531 tool. They can be connected to the
inputs and outputs of other functions and to binary inputs and outputs. Examples of input signals
are BLKTR, BLOCK and VTSU. Examples output signals are TRIP, START, STL1, STL2,
STL3.
Setting parameters
Signals in frames with a shaded area on their right hand side represent setting parameter signals.
These parameters can only be set via the PST or LHMI. Their values are high (1) only when the
corresponding setting parameter is set to the symbolic value specified within the frame. Example
is the signal Block TUV=Yes. Their logical values correspond automatically to the selected set-
ting value.
Internal signals
Internal signals are illustrated graphically and end approximately. 2 mm from the frame edge. If
an internal signal path cannot be drawn with a continuous line, the suffix -int is added to the sig-
nal name to indicate where the signal starts and continues, see figure 3.
5
Introduction to the technical reference manual Chapter 1
Introduction
Figure 1: Logic diagram example with -int signals
External signals
Signal paths that extend beyond the logic diagram and continue in another diagram have the suf-
fix -cont., see figure2 and figure3.
TEST
Block TUV=Yes
STUL1N
STUL2N
STUL3N
&
>1 &
TEST
>1
&
&
&
xx04000375.vsd
t
BLKTR
BLOCK
VTSU
TRIP
START
STL1
STL2
STL3
BLOCK-int.
BLOCK-int.
BLOCK-int.
BLOCK-int.
6
Introduction to the technical reference manual Chapter 1
Introduction
Figure 2: Logic diagram example with an outgoing -cont signal
&
&
&
&
&
&
STCND
STNDL1L2-cont.
STNDL2L3-cont.
STNDL3L1-cont.
STNDL1N-cont.
STNDL2N-cont.
STNDL3N-cont.
STZMPP-cont.
STNDPE-cont.
&
1--BLOCK
1--VTSZ
1--STND
BLK-cont.
>1
>1
>1
>1
xx04000376.vsd
1L1L2
1L2L3
1L3L1
1L1N
1L2N
1L3N
7
Introduction to the technical reference manual Chapter 1
Introduction
Figure 3: Logic diagram example with an incoming -cont signal
1.3.3 Input and output signals
Input and output signals are presented in two separate tables. Each table consists of two columns.
The first column contains the name of the signal and the second column contains the description
of the signal.
1.3.4 Function block
Each function block is illustrated graphically.
Input signals are always on the left hand side, and output signals on the right hand side. Settings
are not displayed. Special kinds of settings are sometimes available. These are supposed to be
connected to constants in the configuration scheme, and are therefore depicted as inputs. Such
signals will be found in the signal list but described in the settings table.
xx04000377.vsd
STNDL1N-cont.
STNDL3N-cont.
STNDL1L2-cont.
STNDL2L3-cont.
STNDL3L1-cont.
>1
>1
>1
>1
&
&
&
&
BLK-cont.
t
15 ms
t
15 ms
t
15 ms
t
15 ms
START
STL3
STL2
STL1
STNDL2N-cont.
8
Introduction to the technical reference manual Chapter 1
Introduction
Figure 4: Example of a function block
1.3.5 Setting parameters
These are presented in tables and include all parameters associated with the function in question.
1.3.6 Technical data
The technical data section provides specific technical information about the function or hard-
ware described.
1.4 Intended audience
1.4.1 General
This manual addresses system engineers, installation and commissioning personnel, who use
technical data during engineering, installation and commissioning, and in normal service.
1.4.2 Requirements
The system engineer must have a thorough knowledge of protection systems, protection equip-
ment, protection functions and the configured functional logics in the protective devices. The
installation and commissioning personnel must have a basic knowledge in the handling electron-
ic equipment.
PH2PUVM
TUV1-
U3P
BLOCK
BLKTR1
BLKST1
BLKTR2
BLKST2
TRIP
TR1
TR1L1
TR1L2
TR1L3
TR2
TR2L1
TR2L2
TR2L3
START
ST1
ST1L1
ST1L2
ST1L3
ST2
ST2L1
ST2L2
ST2L3
en05000330.vsd
IEC 61850 - 8 -1
Logical Node CAP531 Name
Outputs
Inputs
Diagram
Number
9
Introduction to the technical reference manual Chapter 1
Introduction
1.5 Related documents
Documents related to RET670 Identity number
Operators manual 1MRK 504 049-UEN
Installation and commissioning manual 1MRK 504 050-UEN
Technical reference manual 1MRK 504 048-UEN
Application manual 1MRK 504 051-UEN
Buyers guide 1MRK 504 080-BEN
Connection diagram, Two winding trasf. Single breaker arrangements 1MRK 002 801-LA
Connection diagram, Two winding transf. Multi breaker arrangements 1MRK 002 801-HA
Connection diagram, Three winding transf. Single breaker arrangements 1MRK 002 801-KA
Connection diagram, Three winding transf. Multi breaker arrangements 1MRK 002 801-GA
Configuration diagram A, Two winding transf. with single or double busbar but
with a single breaker arr. on both sides
1MRK 004 500-93
Configuration diagram B, Two winding transf. in multi breaker arr. on one or
both sides
1MRK 004 500-94
Configuration diagram C, Three winding transf. with single or double busbar
but with a single breaker arr. on both sides
1MRK 004 500-95
Configuration diagram D, Two winding transf. in multi breaker arr. on one or
both sides
1MRK 004 500-96
Setting example 1, 400/230 kV 500 MVA Transformer, YNyn connected 1MRK 504 083-WEN
Setting example 2, 132/230 kV 40 MVA Transformer, YNd1 connected 1MRK 504 084-WEN
Connection and Installation components 1MRK 013 003-BEN
Test system, COMBITEST 1MRK 512 001-BEN
PCM600, Protection and Control IED Manager 1MRS755552
Getting started guide 1MRK 500 065-UEN
SPA signal list for IED670 1MRK 500 075-WEN
IEC 6185081 signal list for IED670 1MRK 500 077-WEN
Latest versions of the described documentation can be found on www.abb.com/substationautomation
10
Introduction to the technical reference manual Chapter 1
Introduction
1.6 Revision notes
Revision Description
- First release
A First revision, addition of SPA protocol, LON protocol and IEC 60870-5-103 proto-
col.
11
About this chapter Chapter 2
Local human-machine interface
Chapter 2 Local
human-machine
interface
About this chapter
This chapter describes the structure and use of the Local human machine interface (LHMI) or in
other words, the control panel on the IED.
12
Human machine interface Chapter 2
Local human-machine interface
1 Human machine interface
The local human machine interface is available in a small, and a medium sized model. The prin-
ciple difference between the two is the size of the LCD. The small size LCD has a four lines and
the medium size LCD can display the single line diagram with up to 15 objects.
The local human machine interface is equipped with an LCD that can display the single line di-
agram with up to 15 objects.
The local human-machine interface is simple and easy to understand the whole front plate is
divided into zones, each of them with a well-defined functionality:
Status indication LEDs
Alarm indication LEDs which consists of 15 LEDs (6 red and 9 yellow) with user
printable label. All LEDs are configurable from the PCM600 tool
Liquid crystal display (LCD)
Keypad with push buttons for control and navigation purposes, switch for selec-
tion between local and remote control and reset
An isolated RJ 45 communication port
Figure 5: Small graphic HMI
13
Human machine interface Chapter 2
Local human-machine interface
Figure 6: Medium graphic HMI, 15 controllable objects
14
Small size graphic HMI Chapter 2
Local human-machine interface
2 Small size graphic HMI
2.1 Introduction
The small sized HMI is available for 1/2, 3/4 and 1/1 x 19 case. The LCD on the small HMI
measures 32 x 90 mm and displays 7 lines with up to 40 characters per line. The first line dis-
plays the product name and the last line displays date and time. The remaining 5 lines are dy-
namic. This LCD has no graphic display potential.
2.2 Design
The LHMI is identical for both the 1/2, 3/4 and 1/1 cases. The different parts of the small LHMI
is shown in figure 7
15
Small size graphic HMI Chapter 2
Local human-machine interface
Figure 7: Small graphic HMI
1 Status indication LEDs
2 LCD
3 Indication LEDs
4 Label
5 Local/Remote LEDs
6 RJ 45 port
7 Communication indication LED
8 Keypad
1 2 3
4
5
6
7 8
en05000055.eps
16
Medium size graphic HMI Chapter 2
Local human-machine interface
3 Medium size graphic HMI
3.1 Introduction
The 1/2, 3/4 and 1/1 x 19 cases can be equipped with the medium size LCD. This is a fully
graphical monochrome LCD which measures 120 x 90 mm. It has 28 lines with up to 40 char-
acters per line. To display the single line diagram, this LCD is required.
3.2 Design
The different parts of the medium size LHMI is shown in figure 8
17
Medium size graphic HMI Chapter 2
Local human-machine interface
Figure 8: Medium size graphic HMI
1 Status indication LEDs
2 LCD
3 Indication LEDs
4 Label
5 Local/Remote LEDs
6 RJ 45 port
7 Communication indication LED
8 Keypad
1 2 3
4
5
6
7 8
en05000056.eps
18
Keypad Chapter 2
Local human-machine interface
4 Keypad
The keypad is used to monitor and operate the IED. The keypad has the same look and feel in
all IEDs in the REx670 series. LCD screens and other details may differ but the way the keys
function is identical. The keypad is illustrated in figure 9.
Figure 9: The HMI keypad
The keys used to operate the IED are described below in table 1.
Table 1: HMI keys on the front of the IED
Key Function
This key closes (energizes) a breaker or disconnector.
This key opens a breaker or disconnector.
The help key brings up two submenus. Key operation and IED information.
This key is used to clear entries, It cancels commands and edits.
Opens the main menu, and used to move to the default screen.
19
Keypad Chapter 2
Local human-machine interface
The Local/Remote key is used to set the IED in local or remote control mode.
This key opens the reset screen.
The E key starts editing mode and confirms setting changes when in editing mode.
The right arrow key navigates forward between screens and moves right in editing mode.
The left arrow key navigates backwards between screens and moves left in editing mode.
The up arrow key is used to move up in the single line diagram and in menu tree.
The down arrow key is used to move down in the single line diagram and in menu tree.
Key Function
20
LED Chapter 2
Local human-machine interface
5 LED
5.1 Introduction
The LED module is a unidirectional means of communicating. This means that events may occur
that activate a LED in order to draw the operators attention to something that has occurred and
needs some sort of action.
5.2 Status indication LEDs
There are three LEDs above the LCD. The information they communicate is described in the
table below.
5.3 Indication LEDs
The LED indication module comprising 15 LEDs is standard in REx670 IEDs. Its main purpose
is to present an immediate visual information for protection indications or alarm signals.
There are alarm indication LEDs and hardware associated LEDs on the right hand side of the
front panel. The alarm LEDs are found to the right of the LCD screen. They can show steady or
flashing light. Flashing would normally indicate an alarm. The alarm LEDs are configurable us-
ing the PCM600 tool. This is because they are dependent on the binary input logic and can there-
fore not be configured locally on the HMI. Some typical alarm examples follow:
Bay controller failure
CB close blocked
Interlocking bypassed
Differential protection trip
SF6 Gas refill
Position error
CB spring charge alarm
Oil temperature alarm
Thermal overload trip
LED Indication Information
Green:
Steady In service
Flashing Internal failure
Dark No power supply
Yellow:
Steady Dist. rep. triggered
Flashing Terminal in test mode
Red:
Steady Trip command issued
21
LED Chapter 2
Local human-machine interface
Bucholtz trip
The RJ 45 port has a yellow LED indicating that communication has been established between
the IED and a computer.
The Local/Remote key on the front panel has two LEDs indicating whether local or remote con-
trol of the IED is active.
22
LHMI related functions Chapter 2
Local human-machine interface
6 LHMI related functions
6.1 Introduction
The adaptation of the LHMI to the application and user preferences is made with:
function block LHMI (LocalHMISign)
function block HLED (LEDMonitor)
setting parameters
6.2 General setting parameters
Table 2: General settings for the localHMI (LHM1-) function
6.3 Status indication LEDs
6.3.1 Design
The function block LHMI (LocalHMISign) controls and supplies information about the status
of the status indication LEDs. The input and output signals of LHMI are configured with the
PCM600 tool.
See section 5.2 "Status indication LEDs" for information about the LEDs.
Parameter Range Step Default Unit Description
Language English
OptionalLanguage
- English - Local HMI language
DisplayTimeout 10 - 120 10 60 Min Local HMI display time-
out
AutoRepeat Off
On
- On - Activation of auto-repeat
(On) or not (Off)
ContrastLevel -10 - 20 1 0 % Contrast level for display
DefaultScreen 0 - 0 1 0 - Default screen
Password SimplePassw
DOEG205.3-1
- SimplePassw - Password type for autho-
rization
EvListSrtOrder Latest on top
Oldest on top
- Latest on top - Sort order of event list
23
LHMI related functions Chapter 2
Local human-machine interface
6.3.2 Function block
Figure 10: LHMI function block
6.3.3 Input and output signals
Table 3: Input signals for the LocalHMI (LHMI-) function block
Table 4: Output signals for the LocalHMI (LHMI-) function block
6.4 Indication LEDs
6.4.1 Introduction
The function block HLED (LEDMonitor) controls and supplies information about the status of
the indication LEDs. The input and output signals of HLED are configured with the PCM600
tool. The input signal for each LED is selected individually with the PCM600 Signal Matrix
Tool (SMT). LEDs (number 16) for trip indications are red and LEDs (number 715) for start
indications are yellow.
Each indication LED on the LHMI can be set individually to operate in six different sequences;
two as follow type and four as latch type. Two of the latching types are intended to be used as a
protection indication system, either in collecting or restarting mode, with reset functionality. The
other two are intended to be used as signalling system in collecting (coll) mode with an acknowl-
edgment functionality. The light from the LEDs can be steady (-S) or flickering (-F).
6.4.2 Design
The information on the LEDs is stored at loss of the auxiliary power to the IED. The latest LED
picture appears immediately after the IED is successfully restarted.
LocalHMI
LHMI-
CLRLEDS HMI-ON
RED-S
YELLOW-S
YELLOW-F
CLRPULSE
LEDSCLRD
en05000773.vsd
Signal Description
CLRLEDS Input to clear the LCD-HMI LEDs
Signal Description
HMI-ON Backlight of the LCD display is active
RED-S Red LED on the LCD-HMI is steady
YELLOW-S Yellow LED on the LCD-HMI is steady
YELLOW-F Yellow LED on the LCD-HMI is flashing
CLRPULSE A pulse is provided when the LEDs on the LCD-HMI are cleared
LEDSCLRD Active when the LEDs on the LCD-HMI are not active
24
LHMI related functions Chapter 2
Local human-machine interface
Operating modes
Collecting mode
- LEDs which are used in collecting mode of operation are accumulated con-
tinuously until the unit is acknowledged manually. This mode is suitable
when the LEDs are used as a simplified alarm system.
Re-starting mode
- In the re-starting mode of operation each new start resets all previous active
LEDs and activates only those which appear during one disturbance. Only
LEDs defined for re-starting mode with the latched sequence type 6 (Latche-
dReset-S) will initiate a reset and a restart at a new disturbance. A distur-
bance is defined to end a settable time after the reset of the activated input
signals or when the maximum time limit has been elapsed.
Acknowledgment/reset
From local HMI
- The active indications can be acknowledged/reset manually. Manual ac-
knowledgment and manual reset have the same meaning and is a common
signal for all the operating sequences and LEDs. The function is positive
edge triggered, not level triggered. The acknowledgment/reset is performed
via the Reset-button and menus on the LHMI. For details, refer to the Op-
erators manual.
From function input
- The active indications can also be acknowledged/reset from an input, RE-
SET, to the function. This input can for example be configured to a binary
input operated from an external push button. The function is positive edge
triggered, not level triggered. This means that even if the button is continu-
ously pressed, the acknowledgment/reset only affects indications active at
the moment when the button is first pressed.
Automatic reset
- The automatic reset can only be performed for indications defined for
re-starting mode with the latched sequence type 6 (LatchedReset-S). When
the automatic reset of the LEDs has been performed, still persisting indica-
tions will be indicated with a steady light.
Operating sequences
The sequences can be of type Follow or Latched. For the Follow type the LED follow the input
signal completely. For the Latched type each LED latches to the corresponding input signal until
it is reset.
The figures below show the function of available sequences selectable for each LED separately.
For sequence 1 and 2 (Follow type), the acknowledgment/reset function is not applicable. Se-
quence 3 and 4 (Latched type with acknowledgement) are only working in collecting mode. Se-
quence 5 is working according to Latched type and collecting mode while sequence 6 is working
according to Latched type and re-starting mode. The letters S and F in the sequence names have
the meaning S =Steady and F =Flash.
25
LHMI related functions Chapter 2
Local human-machine interface
At the activation of the input signal, the indication operates according to the selected sequence
diagrams below.
In the sequence diagrams the LEDs have the characteristics shown in figure11.
Figure 11: Symbols used in the sequence diagrams
Sequence 1 (Follow-S)
This sequence follows all the time, with a steady light, the corresponding input signals. It does
not react on acknowledgment or reset. Every LED is independent of the other LEDs in its oper-
ation.
Figure 12: Operating sequence 1 (Follow-S)
Sequence 2 (Follow-F)
This sequence is the same as sequence 1, Follow-S, but the LEDs are flashing instead of showing
steady light.
Sequence 3 (LatchedAck-F-S)
This sequence has a latched function and works in collecting mode. Every LED is independent
of the other LEDs in its operation. At the activation of the input signal, the indication starts flash-
ing. After acknowledgment the indication disappears if the signal is not present any more. If the
signal is still present after acknowledgment it gets a steady light.
en05000506.vsd
=No indication =Steady light =Flash
Activating
signal
LED
en01000228.vsd
26
LHMI related functions Chapter 2
Local human-machine interface
Figure 13: Operating sequence 3 (LatchedAck-F-S)
Sequence 4 (LatchedAck-S-F)
This sequence has the same functionality as sequence 3, but steady and flashing light have been
alternated.
Sequence 5 (LatchedColl-S)
This sequence has a latched function and works in collecting mode. At the activation of the input
signal, the indication will light up with a steady light. The difference to sequence 3 and 4 is that
indications that are still activated will not be affected by the reset i.e. immediately after the pos-
itive edge of the reset has been executed a new reading and storing of active signals is performed.
Every LED is independent of the other LEDs in its operation.
Figure 14: Operating sequence 5 (LatchedColl-S)
Sequence 6 (LatchedReset-S)
In this mode all activated LEDs, which are set to sequence 6 (LatchedReset-S), are automatically
reset at a new disturbance when activating any input signal for other LEDs set to sequence 6
(LatchedReset-S). Also in this case indications that are still activated will not be affected by
manual reset, i.e. immediately after the positive edge of that the manual reset has been executed
a new reading and storing of active signals is performed. LEDs set for sequence 6 are completely
independent in its operation of LEDs set for other sequences.
Activating
signal
LED
Acknow.
en01000231.vsd
en01000235.vsd
Activating
signal
LED
Reset
27
LHMI related functions Chapter 2
Local human-machine interface
Definition of a disturbance
A disturbance is defined to last from the first LED set as LatchedReset-S is activated until a set-
table time, tRestart, has elapsed after that all activating signals for the LEDs set as Latche-
dReset-S have reset. However if all activating signals have reset and some signal again becomes
active before tRestart has elapsed, the tRestart timer does not restart the timing sequence. A new
disturbance start will be issued first when all signals have reset after tRestart has elapsed. A di-
agram of this functionality is shown in figure 15.
Figure 15: Activation of new disturbance
In order not to have a lock-up of the indications in the case of a persisting signal each LED is
provided with a timer, tMax, after which time the influence on the definition of a disturbance of
that specific LED is inhibited. This functionality is shown i diagram in figure 16.
Figure 16: Length control of activating signals
Timing diagram for sequence 6
Figure 17 shows the timing diagram for two indications within one disturbance.
1
&
1
New
disturbance
t
tRestart
1
&
&
1
From
disturbance
length control
per LED
set to
sequence 6
en01000237.vsd
Activating signal
t
tMax
AND
To disturbance
length control
To LED
en05000507.vsd
28
LHMI related functions Chapter 2
Local human-machine interface
Figure 17: Operating sequence 6 (LatchedReset-S), two indications within same disturbance
Figure18 shows the timing diagram for a new indication after tRestart time has elapsed.
en01000239.vsd
Activating
signal 2
LED 2
Manual
reset
Activating
signal 1
Automatic
reset
LED 1
Disturbance
t Restart
29
LHMI related functions Chapter 2
Local human-machine interface
Figure 18: Operating sequence 6 (LatchedReset-S), two different disturbances
Figure 19 shows the timing diagram when a new indication appears after the first one has reset
but before tRestart has elapsed.
en01000240.vsd
Activating
signal 2
LED 2
Manual
reset
Activating
signal 1
Automatic
reset
LED 1
Disturbance
t Restart
Disturbance
t Restart
30
LHMI related functions Chapter 2
Local human-machine interface
Figure 19: Operating sequence 6 (LatchedReset-S), two indications within same disturbance
but with reset of activating signal between
Figure 20 shows the timing diagram for manual reset.
en01000241.vsd
Activating
signal 2
LED 2
Manual
reset
Activating
signal 1
Automatic
reset
LED 1
Disturbance
t Restart
31
LHMI related functions Chapter 2
Local human-machine interface
Figure 20: Operating sequence 6 (LatchedReset-S), manual reset
6.4.3 Function block
Figure 21: HLED function block
6.4.4 Input and output signals
Table 5: Input signals for the LEDMonitor (HLED-) function block
en01000242.vsd
Activating
signal 2
LED 2
Manual
reset
Activating
signal 1
Automatic
reset
LED 1
Disturbance
t Restart
LEDMonitor
HLED-
BLOCK
RESET
LEDTEST
NEWIND
ACK
en05000508.vsd
Signal Description
BLOCK Input to block the operation of the LED-unit
RESET Input to acknowledge/reset the indications of the LED-unit
LEDTEST Input for external LED test
32
LHMI related functions Chapter 2
Local human-machine interface
Table 6: Output signals for the LEDMonitor (HLED-) function block
6.4.5 Setting parameters
Table 7: General settings for the LEDMonitor (HLED-) function
Signal Description
NEWIND A new signal on any of the indication inputs occurs
ACK A pulse is provided when the LEDs are acknowledged
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation mode for the
LED function
tRestart 0.0 - 100.0 0.1 0.0 s Defines the disturbance
length
tMax 0.0 - 100.0 0.1 0.0 s Maximum time for the
definition of a distur-
bance
SeqTypeLED1 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED 1
SeqTypeLED2 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED 2
SeqTypeLED3 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED 3
SeqTypeLED4 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED 4
SeqTypeLED5 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED 5
33
LHMI related functions Chapter 2
Local human-machine interface
SeqTypeLED6 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED 6
SeqTypeLED7 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED 7
SeqTypeLED8 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - sequence type for LED 8
SeqTypeLED9 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED 9
SeqTypeLED10 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED
10
Parameter Range Step Default Unit Description
34
LHMI related functions Chapter 2
Local human-machine interface
SeqTypeLED11 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED
11
SeqTypeLED12 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED
12
SeqTypeLED13 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED
13
SeqTypeLED14 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED
14
SeqTypeLED15 Follow-S
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
- Follow-S - Sequence type for LED
15
Parameter Range Step Default Unit Description
35
About this chapter Chapter 3
Basic IED functions
Chapter 3 Basic IED functions
About this chapter
This chapter presents functions that are basic to all REx670 IEDs. Typical functions in this cat-
egory are time synchronization, self supervision and test mode.
36
Analog inputs Chapter 3
Basic IED functions
1 Analog inputs
1.1 Introduction
In order to get correct measurement results as well as correct protection operations the analog
input channels must be configured and properly set. It is necessary to define a reference
PhaseAngleRef for correct calculation of phase angles. For power measuring and all directional
and differential functions the directions of the input currents must be properly defined. The mea-
suring and protection algorithms in IED670 are using primary system quantities and the set val-
ues are done in primary quantities as well. Therefore it is extremely important to properly set the
data about the connected current and voltage transformers.
1.2 Principle of operation
The direction of a current to the IED is depending on the connection of the CT. The main CTs
are always supposed to be star connected and can be connected with the star point to the object
or from the object. This information must be set to the IED. The convention of the directionality
is defined as follows: A positive value of current, power etc. means that the quantity has the di-
rection into the object and a negative value means direction out from the object. For directional
functions the direction into the object is defined as Forward and the direction out from the object
is defined as Reverse, see figure 22
Figure 22: Internal convention of the directionality in IED670
With correct setting of the primary CT direction, CTStarPoint set to FromObject or ToObject, a
positive quantities always flowing towards the object and a direction defined as Forward always
is looking towards the object. To be able to use primary system quantities for settings and cal-
culation in the IED the ration of the main CTs and VTs must be known. This information is given
to the IED by setting of the rated secondary and primary currents and voltages of the CTs and
VTs.
Protected Object
Line, transformer, etc
Forward Reverse
Definition of direction
for directional functions
Measured quantity is
positive when flowing
towards the object
e.g. P, Q, I
Reverse Forward
Definition of direction
for directional functions
e.g. P, Q, I
Measured quantity is
positive when flowing
towards the object
Set parameter
CTStarPoint
Correct Setting is
"ToObject"
Set parameter
CTStarPoint
Correct Setting is
"FromObject"
en05000456.vsd
37
Analog inputs Chapter 3
Basic IED functions
1.3 Function block
ANALOGIN12I
TA40-
ERROR
NAMECH1
CH1
CH2
NAMECH2
NAMECH3
CH3
CH4
NAMECH4
NAMECH5
CH5
CH6
NAMECH6
NAMECH7
CH7
CH8
NAMECH8
NAMECH9
CH9
CH10
NAMECH10
NAMECH11
CH11
CH12
NAMECH12
en05000711.vsd
ANALOGIN6I
TB40-
ERROR
NAMECH1
CH1
CH2
NAMECH2
NAMECH3
CH3
CH4
NAMECH4
NAMECH5
CH5
CH6
NAMECH6
en05000712.vsd
38
Analog inputs Chapter 3
Basic IED functions
ANALOGIN9I3U
TC40-
ERROR
NAMECH1
CH1
CH2
NAMECH2
NAMECH3
CH3
CH4
NAMECH4
NAMECH5
CH5
CH6
NAMECH6
NAMECH7
CH7
CH8
NAMECH8
NAMECH9
CH9
CH10
NAMECH10
NAMECH11
CH11
CH12
NAMECH12
en05000713.vsd
ANALOGIN6I6U
TD40-
ERROR
NAMECH1
CH1
CH2
NAMECH2
NAMECH3
CH3
CH4
NAMECH4
NAMECH5
CH5
CH6
NAMECH6
NAMECH7
CH7
CH8
NAMECH8
NAMECH9
CH9
CH10
NAMECH10
NAMECH11
CH11
CH12
NAMECH12
en05000714.vsd
39
Analog inputs Chapter 3
Basic IED functions
1.4 Output signals
Table 8: Output signals for the ANALOGIN12I (TA40-) function block
Table 9: Output signals for the ANALOGIN6I (TB40-) function block
Signal Description
ERROR Analogue input module status
NAMECH1 User define string for analogue input 1
CH1 Analogue input 1
CH2 Analogue input 2
NAMECH2 User define string for analogue input 2
NAMECH3 User define string for analogue input 3
CH3 Analogue input 3
CH4 Analogue input 4
NAMECH4 User define string for analogue input 4
NAMECH5 User define string for analogue input 5
CH5 Analogue input 5
CH6 Analogue input 6
NAMECH6 User define string for analogue input 6
NAMECH7 User define string for analogue input 7
CH7 Analogue input 7
CH8 Analogue input 8
NAMECH8 User define string for analogue input 8
NAMECH9 User define string for analogue input 9
CH9 Analogue input 9
CH10 Analogue input 10
NAMECH10 User define string for analogue input 10
NAMECH11 User define string for analogue input 11
CH11 Analogue input 11
CH12 Analogue input 12
NAMECH12 User define string for analogue input 12
Signal Description
ERROR Analogue input module status
NAMECH1 User define string for analogue input 1
CH1 Analogue input 1
CH2 Analogue input 2
NAMECH2 User define string for analogue input 2
NAMECH3 User define string for analogue input 3
CH3 Analogue input 3
CH4 Analogue input 4
40
Analog inputs Chapter 3
Basic IED functions
Table 10: Output signals for the ANALOGIN9I3U (TC40-) function block
NAMECH4 User define string for analogue input 4
NAMECH5 User define string for analogue input 5
CH5 Analogue input 5
CH6 Analogue input 6
NAMECH6 User define string for analogue input 6
Signal Description
ERROR Analogue input module status
NAMECH1 User define string for analogue input 1
CH1 Analogue input 1
CH2 Analogue input 2
NAMECH2 User define string for analogue input 2
NAMECH3 User define string for analogue input 3
CH3 Analogue input 3
CH4 Analogue input 4
NAMECH4 User define string for analogue input 4
NAMECH5 User define string for analogue input 5
CH5 Analogue input 5
CH6 Analogue input 6
NAMECH6 User define string for analogue input 6
NAMECH7 User define string for analogue input 7
CH7 Analogue input 7
CH8 Analogue input 8
NAMECH8 User define string for analogue input 8
NAMECH9 User define string for analogue input 9
CH9 Analogue input 9
CH10 Analogue input 10
NAMECH10 User define string for analogue input 10
NAMECH11 User define string for analogue input 11
CH11 Analogue input 11
CH12 Analogue input 12
NAMECH12 User define string for analogue input 12
Signal Description
41
Analog inputs Chapter 3
Basic IED functions
Table 11: Output signals for the ANALOGIN6I6U (TD40-) function block
1.5 Setting parameters
Table 12: General settings for the AISERVAL (AISV-) function
Signal Description
ERROR Analogue input module status
NAMECH1 User define string for analogue input 1
CH1 Analogue input 1
CH2 Analogue input 2
NAMECH2 User define string for analogue input 2
NAMECH3 User define string for analogue input 3
CH3 Analogue input 3
CH4 Analogue input 4
NAMECH4 User define string for analogue input 4
NAMECH5 User define string for analogue input 5
CH5 Analogue input 5
CH6 Analogue input 6
NAMECH6 User define string for analogue input 6
NAMECH7 User define string for analogue input 7
CH7 Analogue input 7
CH8 Analogue input 8
NAMECH8 User define string for analogue input 8
NAMECH9 User define string for analogue input 9
CH9 Analogue input 9
CH10 Analogue input 10
NAMECH10 User define string for analogue input 10
NAMECH11 User define string for analogue input 11
CH11 Analogue input 11
CH12 Analogue input 12
NAMECH12 User define string for analogue input 12
Parameter Range Step Default Unit Description
PhaseAngleRef 1 - 24 1 1 Ch Reference channel for
phase angle presentation
42
Analog inputs Chapter 3
Basic IED functions
Table 13: General settings for the ANALOGIN12I (TA40-) function
Parameter Range Step Default Unit Description
CTStarPoint1 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec1 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim1 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint2 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec2 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim2 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint3 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec3 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim3 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint4 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec4 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim4 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint5 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec5 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim5 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint6 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec6 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim6 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint7 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec7 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim7 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint8 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
43
Analog inputs Chapter 3
Basic IED functions
Table 14: General settings for the ANALOGIN6I (TB40-) function
CTsec8 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim8 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint9 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec9 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim9 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint10 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec10 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim10 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint11 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec11 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim11 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint12 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec12 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim12 1 - 99999 1 3000 A Rated CT primary current
Parameter Range Step Default Unit Description
CTStarPoint1 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec1 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim1 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint2 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec2 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim2 1 - 99999 1 3000 A Rated CT primary current
Parameter Range Step Default Unit Description
44
Analog inputs Chapter 3
Basic IED functions
Table 15: General settings for the ANALOGIN9I3U (TC40-) function
CTStarPoint3 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec3 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim3 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint4 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec4 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim4 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint5 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec5 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim5 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint6 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec6 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim6 1 - 99999 1 3000 A Rated CT primary current
Parameter Range Step Default Unit Description
CTStarPoint1 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec1 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim1 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint2 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec2 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim2 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint3 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec3 1 - 10 1 1 A Rated CT secondary cur-
rent
Parameter Range Step Default Unit Description
45
Analog inputs Chapter 3
Basic IED functions
CTprim3 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint4 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec4 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim4 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint5 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec5 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim5 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint6 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec6 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim6 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint7 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec7 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim7 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint8 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec8 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim8 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint9 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec9 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim9 1 - 99999 1 3000 A Rated CT primary current
VTsec10 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
Parameter Range Step Default Unit Description
46
Analog inputs Chapter 3
Basic IED functions
Table 16: General settings for the ANALOGIN6I6U (TD40-) function
VTprim10 0.05 - 2000.00 0.05 400.00 kV Rated VT primary voltage
VTsec11 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
VTprim11 0.05 - 2000.00 0.05 400.00 kV Rated VT primary voltage
VTsec12 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
VTprim12 0.05 - 2000.00 0.05 400.00 kV Rated VT primary voltage
Parameter Range Step Default Unit Description
CTStarPoint1 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec1 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim1 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint2 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec2 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim2 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint3 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec3 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim3 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint4 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec4 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim4 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint5 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
CTsec5 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim5 1 - 99999 1 3000 A Rated CT primary current
CTStarPoint6 FromObject
ToObject
- ToObject - ToObject=towards pro-
tected object, FromOb-
ject=the opposite
Parameter Range Step Default Unit Description
47
Analog inputs Chapter 3
Basic IED functions
CTsec6 1 - 10 1 1 A Rated CT secondary cur-
rent
CTprim6 1 - 99999 1 3000 A Rated CT primary current
VTsec7 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
VTprim7 0.05 - 2000.00 0.05 400.00 kV Rated VT primary voltage
VTsec8 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
VTprim8 0.05 - 2000.00 0.05 400.00 kV Rated VT primary voltage
VTsec9 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
VTprim9 0.05 - 2000.00 0.05 400.00 kV Rated VT primary voltage
VTsec10 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
VTprim10 0.05 - 2000.00 0.05 400.00 kV Rated VT primary voltage
VTsec11 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
VTprim11 0.05 - 2000.00 0.05 400.00 kV Rated VT primary voltage
VTsec12 0.001 - 999.999 0.001 110.000 V Rated VT secondary volt-
age
VTprim12 0.05 - 2000.00 0.05 400.00 kV Rated VT primary voltage
Parameter Range Step Default Unit Description
48
Self supervision with internal event list Chapter 3
Basic IED functions
2 Self supervision with internal event list
2.1 Introduction
The self-supervision function listens and reacts to internal system events, generated by the dif-
ferent built-in self-supervision elements. The internal events are saved in an internal event list.
2.2 Principle of operation
The self-supervision operates continuously and includes:
Normal micro-processor watchdog function.
Checking of digitized measuring signals.
Other alarms, for example hardware and time synchronization.
The self-supervision status can be monitored from the local HMI or a SMS/SCS system.
Under the Diagnostics menu in the local HMI the present information from the self-supervision
function can be reviewed. The information can be found under Diagnostics\Internal Events or
Diagnostics\IED Status\General. Refer to the Installation and Commissioning manual for a
detailed list of supervision signals that can be generated and displayed in the local HMI.
A self-supervision summary can be obtained by means of the potential free alarm contact (IN-
TERNAL FAIL) located on the power supply module. The function of this output relay is an
OR-function between the INTFAIL signal see figure 24 and a couple of more severe faults
that can occur in the IED, see figure 23
Figure 23: Hardware self-supervision, potential-free alarm contact.
49
Self supervision with internal event list Chapter 3
Basic IED functions
Figure 24: Software self-supervision, IES (IntErrorSign) function block.
Some signals are available from the IES (IntErrorSign) function block. The signals from this
function block are sent as events to the station level of the control system. The signals from the
IES function block can also be connected to binary outputs for signalization via output relays or
they can be used as conditions for other functions if required/desired.
Individual error signals from I/O modules can be obtained from respective module in the Signal
Matrix Tool. Error signals from time synchronization can be obtained from the time synchroni-
zation block TIME.
2.2.1 Internal signals
Self supervision provides several status signals, that tells about the condition of the IED. As they
provide information about the internal life of the IED, they are also called internal signals. The
internal signals can be divided into two groups. One group handles signals that are always
present in the IED; standard signals. Another group handles signals that are collected depending
on the hardware configuration. The standard signals are listed in table17. The hardware depen-
dent internal signals are listed in table18. Explanations of internal signals are listed in table19.
50
Self supervision with internal event list Chapter 3
Basic IED functions
Table 17: Self-supervision's standard internal signals
Table 18: Self-supervision's HW dependent internal signals
Name of signal Description
FAIL Internal Fail status
WARNING Internal Warning status
NUMFAIL CPU module Fail status
NUMWARNING CPU module Warning status
RTCERROR Real Time Clock status
TIMESYNCHERROR Time Synchronization status
RTEERROR Runtime Execution Error status
IEC61850ERROR IEC 61850 Error status
WATCHDOG SW Watchdog Error status
LMDERROR LON/Mip Device Error status
APPERROR Runtime Application Error status
SETCHGD Settings changed
SETGRPCHGD Setting groups changed
FTFERROR Fault Tolerant Filesystem status
Card Name of signal Description
ADxx ADxx Analog In Module Error status
BIM BIM-Error Binary In Module Error status
BOM BOM-Error Binary Out Module Error status
IOM IOM-Error In/Out Module Error status
MIM MIM-Error Millampere Input Module Error status
LDCM LDCM-Error Line Differential Communication Error status
51
Self supervision with internal event list Chapter 3
Basic IED functions
Table 19: Explanations of internal signals
2.2.2 Run-time model
The analog signals to the A/D converter is internally distributed into two different converters,
one with low amplification and one with high amplification, see figure 25.
Name of signal Reasons for activation
FAIL This signal will be active if one or more of the following internal sig-
nals are active; INT--NUMFAIL, INT--LMDERROR, INT--WATCH-
DOG, INT--APPERROR, INT--RTEERROR, INT--FTFERROR, or any
of the HW dependent signals
WARNING This signal will be active if one or more of the following internal sig-
nals are active; INT--RTCERROR, INT--IEC61850ERROR,
INT--TIMESYNCHERROR
NUMFAIL This signal will be active if one or more of the following internal sig-
nals are active; INT--WATCHDOG, INT--APPERROR, INT--RTEER-
ROR, INT--FTFERROR
NUMWARNING This signal will be active if one or more of the following internal sig-
nals are active; INT--RTCERROR, INT--IEC61850ERROR
RTCERROR This signal will be active when there is a hardware error with the real
time clock.
TIMESYNCHERROR This signal will be active when the source of the time synchronization
is lost, or when the time system has to make a time reset.
RTEERROR This signal will be active if the Runtime Engine failed to do some
actions with the application threads. The actions can be loading of
settings or parameters for components, changing of setting groups,
loading or unloading of application threads.
IEC61850ERROR This signal will be active if the IEC61850 stack did not succeed in
some actions like reading IEC61850 configuration, startup etc.
WATCHDOG This signal will be activated when the terminal has been under too
heavy load for at least 5 minutes. The operating systems background
task is used for the measurements.
LMDERROR LON network interface, MIP/DPS, is in an unrecoverable error state.
APPERROR This signal will be active if one or more of the application threads are
not in the state that Runtime Engine expects. The states can be
CREATED, INITIALIZED, RUNNING, etc.
SETCHGD This signal will generate an Internal Event to the Internal Event list if
any settings are changed.
SETGRPCHGD This signal will generate an Internal Event to the Internal Event list if
any setting groups are changed.
FTFERROR This signal will be active if both the working file and the backup file
are corrupted and can not be recovered.
52
Self supervision with internal event list Chapter 3
Basic IED functions
Figure 25: Simplified drawing of A/D converter for the 600 platform.
The technique to split the analogue input signal into two converters with different amplification
makes it possible to supervise the incoming signals under normal conditions where the signals
from the two converters should be identical. An alarm is given if the signals are out of the bound-
aries. Another benefit is that it improves the dynamic performance of the A/D conversion.
The self-supervision of the A/D conversion is controlled by the ADx_Controller function. One
of the tasks for the controller is to perform a validation of the input signals. This is done in a
validation filter which has mainly two objects: First is the validation part, i.e. checks that the
A/D conversion seems to work as expected. Secondly, the filter chooses which of the two signals
that shall be sent to the CPU, i.e. the signal that has the most suitable level, the ADx_LO or the
16 times higherADx_HI.
When the signal is within measurable limits on both channels, a direct comparison of the two
channels can be performed. If the validation fails, the CPU will be informed and an alarm will
be given.
The ADx_Controller also supervise other parts of the A/D converter.
53
Self supervision with internal event list Chapter 3
Basic IED functions
2.3 Function block
Figure 26: IS function block
2.4 Output signals
Table 20: Output signals for the InternalSignal (IS---) function block
2.5 Setting parameters
The function does not have any parameters available in Local HMI or Protection and Control
IED Manager (PCM600)
2.6 Technical data
Table 21: Self supervision with internal event list
InternalSignal
IS---
FAIL
WARNING
CPUFAIL
CPUWARN
TSYNCERR
RTCERR
en04000392.vsd
Signal Description
FAIL Internal fail
WARNING Internal warning
CPUFAIL CPU fail
CPUWARN CPU warning
TSYNCERR Time synchronization status
RTCERR Real time clock status
Data Value
Recording manner Continuous, event controlled
List size 1000 events, first in-first out
54
Time synchronization Chapter 3
Basic IED functions
3 Time synchronization
3.1 Introduction
Use the time synchronization source selector to select a common source of absolute time for the
IED when it is a part of a protection system. This makes comparison of events and disturbance
data between all IEDs in a SA system possible.
3.2 Principle of operation
3.2.1 General concepts
Time definitions
The error of a clock is the difference between the actual time of the clock, and the time the clock
is intended to have. The rate accuracy of a clock is normally called the clock accuracy and means
how much the error increases, i.e. how much the clock gains or loses time. A disciplined clock
is a clock that knows its own faults and tries to compensate for them, i.e. a trained clock.
Synchronization principle
From a general point of view synchronization can be seen as a hierarchical structure. A module
is synchronized from a higher level and provides synchronization to lower levels.
Figure 27: Synchronization principle
A module is said to be synchronized when it periodically receives synchronization messages
from a higher level. As the level decreases, the accuracy of the synchronization decreases as
well. A module can have several potential sources of synchronization, with different maximum
errors, which gives the module the possibility to choose the source with the best quality, and to
adjust its internal clock after this source. The maximum error of a clock can be defined as a func-
tion of:
The maximum error of the last used synchronization message
Module
Syncronization from
a higher level
Optional syncronization of
modules at a lower level
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55
Time synchronization Chapter 3
Basic IED functions
The time since the last used synchronization message
The rate accuracy of the internal clock in the module.
3.2.2 Real Time Clock (RTC) operation
The IED has a built-in Real Time Clock (RTC) with a resolution of one nanosecond. The clock
has a built-in calendar that handles leap years through 2098.
RTC at power off
During power off, the time in the IED time is kept by a capacitor backed RTC that will provide
35 ppm accuracy for 5 days. This means that if the power is off, the time in the IED may drift
with 3 seconds per day, during 5 days, and after this time the time will be lost completely.
RTC at startup
At IED startup, the internal time is free running. If the RTC is still alive since the last up time,
the time in the IED will be quite accurate (may drift 35 ppm), but if the RTC power has been
lost during power off (will happen after 5 days), the IED time will start at 1970-01-01. For more
information, please refer to section "Time synchronization startup procedure" and section "Ex-
ample, binary synchronization".
Time synchronization startup procedure
The first message that contains full time (as for instance LON, SNTP, GPS etc.) will give an ac-
curate time to the IED. The IED is brought into a safe state and the time is thereafter set to the
correct value. After the initial setting of the clock, one of three things will happen with each of
the coming synchronization messages, configured as fine:
If the synchronization message, that is similar to the other messages from its or-
igin has an offset compared to the internal time in the IED, the message is used
directly for synchronization, that is for adjusting the internal clock to obtain zero
offset at the next coming time message.
If the synchronization message has an offset that is large compared to the other
messages, a spike-filter in the IED will remove this time-message.
If the synchronization message has an offset that is large, and the following mes-
sage also has a large offset, the spike filter will not act and the offset in the syn-
chronization message will be compared to a threshold that defaults to 100
milliseconds. If the offset is more than the threshold, the IED is brought into a
safe state and the clock is thereafter set to the correct time. If the offset is lower
than the threshold, the clock will be adjusted with 1000 ppm until the offset is
removed. With an adjustment of 1000 ppm, it will take 100 seconds or 1.7 min-
utes to remove an offset of 100 milliseconds.
Synchronization messages configured as coarse will only be used for initial setting of the time.
After this has been done, the messages are checked against the internal time and only an offset
of more than 10 seconds will reset the time.
Rate accuracy
In the REx670 IED, the rate accuracy at cold start is about 100 ppm, but if the IED is synchro-
nized for a while, the rate accuracy will be approximately 1 ppm if the surrounding temperature
is constant. Normally it will take 20 minutes to reach full accuracy.
56
Time synchronization Chapter 3
Basic IED functions
Time-out on synchronization sources
All synchronization interfaces has a time-out, and a configured interface must receive time-mes-
sages regularly, in order not to give a TSYNCERR. Normally, the time-out is set so that one
message can be lost without getting a TSYNCERR, but if more than one message is lost, a
TSYNCERR will be given.
3.2.3 Synchronization alternatives
Three main alternatives of external time synchronization are available. Either the synchroniza-
tion message is applied via any of the communication ports of the IED as a telegram message
including date and time or as a minute pulse, connected to a binary input, or via GPS. The minute
pulse is used to fine tune already existing time in the IEDs.
Synchronization via SNTP
SNTP provides a Ping-Pong method of synchronization. A message is sent from an IED to an
SNTP-server, and the SNTP-server returns the message after filling in a reception time and a
transmission time. SNTP operates via the normal Ethernet network that connects IEDs together
in an IEC61850 network. For SNTP to operate properly, there must be a SNTP-server present,
preferably in the same station. The SNTP synchronization provides an accuracy that will give 1
ms accuracy for binary inputs. The IED itself can be set as a SNTP-time server.
Synchronization via Serial Communication Module (SLM)
On the serial buses (both LON and SPA) two types of synchronization messages are sent.
Coarse message is sent every minute and comprises complete date and time, i.e.
year, month, day, hours, minutes, seconds and milliseconds.
Fine message is sent every second and comprises only seconds and milliseconds.
IEC60870-5-103 is not used to synchronize the relay, but instead the offset between the local
time in the relay and the time received from 103 is added to all times (in events and so on) sent
via 103. In this way the relay acts as it is synchronized from various 103 sessions at the same
time. Actually, there is a local time for each 103 session.
The SLM module is located on the AD conversion Module (ADM).
Synchronization via Built-in-GPS
The built in GPS clock modules receives and decodes time information from the global position-
ing system. The modules are located on the GPS time synchronization Module (GSM).
Synchronization via binary input
The IED accepts minute pulses to a binary input. These minute pulses can be generated from e.g.
station master clock. If the station master clock is not synchronized from a world wide source,
time will be a relative time valid for the substation. Both positive and negative edge on the signal
can be accepted. This signal is also considered as a fine signal.
The minute pulse is connected to any channel on any Binary Input Module in the IED. The elec-
trical characteristic is thereby the same as for any other binary input.
If the objective of synchronization is to achieve a relative time within the substation and if no
station master clock with minute pulse output is available, a simple minute pulse generator can
be designed and used for synchronization of the IEDs. The minute pulse generator can be created
using the logical elements and timers available in the IED.
57
Time synchronization Chapter 3
Basic IED functions
The definition of a minute pulse is that it occurs one minute after the last pulse. As only the
flanks are detected, the flank of the minute pulse shall occur one minute after the last flank.
Binary minute pulses are checked with reference to frequency.
Pulse data:
Period time (a) should be 60 seconds.
Pulse length (b):
- Minimum pulse length should be >50 ms.
- Maximum pulse length is optional.
Amplitude (c) - please refer to section 2.9 "Binary input module (BIM)".
Deviations in the period time larger than 50 ms will cause TSYNCERR.
Figure 28: Binary minute pulses
The default time-out-time for a minute pulse is two minutes, and if no valid minute pulse is re-
ceived within two minutes a SYNCERR will be given.
If contact bounces occurs, only the first pulse will be detected as a minute pulse. The next minute
pulse will be registered first 60 s - 50 ms after the last contact bounce.
If the minute pulses are perfect, e.g. it is exactly 60 seconds between the pulses, contact bounces
might occur 49 ms after the actual minute pulse without effecting the system. If contact bounces
occurs more than 50 ms, e.g. it is less than 59950 ms between the two most adjacent positive (or
negative) flanks, the minute pulse will not be accepted.
Example, binary synchronization
A IED is configured to use only binary input, and a valid binary input is applied to a binary input
card. The HMI is used to tell the IED the approximate time and the minute pulse is used to syn-
chronize the IED thereafter. The definition of a minute pulse is that it occurs one minute after
the previous minute pulse, so the first minute pulse is not used at all. The second minute pulse
will probably be rejected due to the spike filter. The third pulse will give the IED a good time
and will reset the time so that the fourth minute pulse will occur on a minute border. After the
first three minutes, the time in the IED will be good if the coarse time is set properly via the HMI
a
b
c
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58
Time synchronization Chapter 3
Basic IED functions
or the RTC backup still keeps the time since last up-time. If the minute pulse is removed for in-
stance for an hour, the internal time will drift by maximum the error rate in the internal clock. If
the minute pulse is returned, the first pulse automatically is rejected. The second pulse will pos-
sibly be rejected due to the spike filter. The third pulse will either synchronize the time, if the
time offset is more than 100 ms, or adjust the time, if the time offset is small enough. If the time
is set, the application will be brought to a safe state before the time is set. If the time is adjusted,
the time will reach its destination within 1.7 minutes.
3.3 Function block
Figure 29: TIME function block
3.4 Output signals
Table 22: Output signals for the TIME (TIME-) function block
3.5 Setting parameters
Path in local HMI: Setting/Time
Path in PCM600: Settings/Time/Synchronization
TIME
TIME-
TSYNCERR
RTCERR
en05000425.vsd
Signal Description
TSYNCERR Time synchronization error
RTCERR Real time clock error
59
Time synchronization Chapter 3
Basic IED functions
Table 23: General settings for the TimeSynch (TSYN-) function
Table 24: General settings for the TimeSynchBIN (TBIN-) function
Table 25: General settings for the TimeSynchSNTP (TSNT-) function
Parameter Range Step Default Unit Description
CourseSyncSrc Off
SPA
LON
- Off - Course time synchroniza-
tion source
FineSyncSource Off
SPA
LON
BIN
GPS
GPS+SPA
GPS+LON
GPS+BIN
SNTP
GPS+SNTP
- Off - Fine time synchronization
source
SyncMaster Off
SNTP-Server
- Off - Activate IEDas synchro-
nization master
Parameter Range Step Default Unit Description
ModulePosition 3 - 16 1 3 - Hardware position of IO
module for time synchro-
nization
BinaryInput 1 - 16 1 1 - Binary input number for
time synchronization
BinDetection PositiveEdge
NegativeEdge
- PositiveEdge - Positive or negative edge
detection
Parameter Range Step Default Unit Description
ServerIP-Add 0 - 18 1 0.0.0.0 - Server IP-address
RedServIP-Add 0 - 18 1 0.0.0.0 - Redundant server
IP-address
60
Time synchronization Chapter 3
Basic IED functions
Table 26: General settings for the DaySumDSTBegin (TSTB-) function
Parameter Range Step Default Unit Description
MonthInYear J anuary
February
March
April
May
J une
J uly
August
September
October
November
December
- March - Month in year when day-
light time starts
DayInWeek Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
- Sunday - Day in week when day-
light time starts
WeekInMonth Last
First
Second
Third
Fourth
- Last - Week in month when
daylight time starts
UTCTimeOfDay 0 - 86400 1 3600 s UTC Time of day in sec-
onds when daylight time
starts
61
Time synchronization Chapter 3
Basic IED functions
Table 27: General settings for the DaySumTimeEnd (TSTE-) function
Table 28: General settings for the TimeZone (TZON-) function
3.6 Technical data
Table 29: Time synchronization, time tagging
Parameter Range Step Default Unit Description
MonthInYear J anuary
February
March
April
May
J une
J uly
August
September
October
November
December
- October - Month in year when day-
light time ends
DayInWeek Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
- Sunday - Day in week when day-
light time ends
WeekInMonth Last
First
Second
Third
Fourth
- Last - Week in month when
daylight time ends
UTCTimeOfDay 0 - 86400 1 3600 s UTC Time of day in sec-
onds when daylight time
ends
Parameter Range Step Default Unit Description
NoHalfHourUTC -24 - 24 1 0 - Number of half-hours
from UTC
Function Value
Time tagging resolution, Events and Sampled Mea-
surement Values
1 ms
Time tagging error with synchronization once/min
(minute pulse synchronization), Events and Sam-
pled Measurement Values
1.0 ms typically
Time tagging error with SNTP synchronization,
Sampled Measurement Values
1.0 ms typically
62
Parameter setting groups Chapter 3
Basic IED functions
4 Parameter setting groups
4.1 Introduction
Use the six sets of settings to optimize IED operation for different system conditions. By creat-
ing and switching between fine tuned setting sets, either from the human-machine interface or
configurable binary inputs, results in a highly adaptable IED that can cope with a variety of sys-
tem scenarios.
4.2 Principle of operation
The ACGR function block has six functional inputs, each corresponding to one of the setting
groups stored in the IED. Activation of any of these inputs changes the active setting group. Sev-
en functional output signals are available for configuration purposes, so that up to date informa-
tion on the active setting group is always available.
A setting group is selected by using the local HMI, from a front connected personal computer,
remotely from the station control or station monitoring system or by activating the correspond-
ing input to the ACGR function block.
Each input of the function block can be configured to connect to any of the binary inputs in the
IED. To do this the PCM600 configuration tool must be used.
The external control signals are used for activating a suitable setting group when adaptive func-
tionality is necessary. Input signals that should activate setting groups must be either permanent
or a pulse exceeding 400 ms.
More than one input may be activated at the same time. In such cases the lower order setting
group has priority. This means that if for example both group four and group two are set to ac-
tivate, group two will be the one activated.
Every time the active group is changed, the output signal SETCHGD is sending a pulse with the
length according to parameter t, which is set from PCM600 or in the local HMI.
The parameter MAXSETGR defines the maximum number of setting groups in use to switch be-
tween.
63
Parameter setting groups Chapter 3
Basic IED functions
Figure 30: Connection of the function to external circuits
The above example also includes seven output signals, for confirmation of which group that is
active.
The SGC function block has an input where the number of setting groups used is defined.
Switching can only be done within that number of groups. The number of setting groups selected
to be used will be filtered so only the setting groups used will be shown on the PST setting tool.
4.3 Function block
Figure 31: ACGR function block
ActiveGroup
ACGR-
ACTGRP1
ACTGRP2
ACTGRP3
ACTGRP4
ACTGRP5
ACTGRP6
GRP1
GRP2
GRP3
GRP4
GRP5
GRP6
SETCHGD
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64
Parameter setting groups Chapter 3
Basic IED functions
4.4 Input and output signals
Table 30: Input signals for the ActiveGroup (ACGR-) function block
Table 31: Output signals for the ActiveGroup (ACGR-) function block
4.5 Setting parameters
Table 32: General settings for the ActiveGroup (ACGR-) function
NoOfSetGrp
SGC--
MAXSETGR
en05000716.vsd
Signal Description
ACTGRP1 Selects setting group 1 as active
ACTGRP2 Selects setting group 2 as active
ACTGRP3 Selects setting group 3 as active
ACTGRP4 Selects setting group 4 as active
ACTGRP5 Selects setting group 5 as active
ACTGRP6 Selects setting group 6 as active
Signal Description
GRP1 Setting group 1 is active
GRP2 Setting group 2 is active
GRP3 Setting group 3 is active
GRP4 Setting group 4 is active
GRP5 Setting group 5 is active
GRP6 Setting group 6 is active
SETCHGD Pulse when setting changed
Parameter Range Step Default Unit Description
t 0.0 - 10.0 0.1 1.0 s Pulse length of pulse
when setting changed
65
Parameter setting groups Chapter 3
Basic IED functions
Table 33: General settings for the NoOfSetGrp (SGC--) function
Parameter Range Step Default Unit Description
ActiveSetGrp SettingGroup1
SettingGroup2
SettingGroup3
SettingGroup4
SettingGroup5
SettingGroup6
- SettingGroup1 - ActiveSettingGroup
MAXSETGR 1 - 6 1 1 No Max number of setting
groups 1-6
66
Test mode functionality Chapter 3
Basic IED functions
5 Test mode functionality
5.1 Introduction
Most of the functions in the IED can individually be blocked by means of settings from the local
HMI or PST. To enable these blockings the IED must be set in test mode. When leaving the test
mode, i.e. entering normal mode, these blockings are disabled and everything is set to normal
operation. All testing will be done with actually set and configured values within the IED. No
settings will be changed, thus mistakes are avoided.
5.2 Principle of operation
To be able to test the functions in the IED, you must set the terminal in the TEST mode. There
are two ways of setting the terminal in the TEST mode:
By configuration, activating the input of the function block TEST.
By setting TestMode to On in the local HMI, under the menu: TEST/IED test
mode.
While the IED is in test mode, the ACTIVE output of the function block TEST is activated. The
other two outputs of the function block TEST are showing which is the generator of the Test
mode: On state input from configuration (OUTPUT output activated) or setting from LHMI
(SETTING output activated).
While the IED is in test mode, the yellow START LED will flash and all functions are blocked.
Any function can be de-blocked individually regarding functionality and event signalling.
Most of the functions in the IED can individually be blocked by means of settings from the local
HMI. To enable these blockings the IED must be set in test mode (the output ACTIVE in func-
tion block TEST is set to true), see example in figure 32. When leaving the test mode, i.e. enter-
ing normal mode, these blockings are disabled and everything is set to normal operation. All
testing will be done with actually set and configured values within the IED. No settings will be
changed, thus no mistakes are possible.
The blocked functions will still be blocked next time entering the test mode, if the blockings
were not reset.
The blocking of a function concerns all output signals from the actual function, so no outputs
will be activated.
The TEST function block might be used to automatically block functions when a test handle is
inserted in a test switch. A contact in the test switch (RTXP24 contact 29-30) can supply a binary
input which in turn is configured to the TEST function block.
Each of the protection functions includes the blocking from TEST function block. A typical ex-
ample from the undervoltage function is shown in figure 32.
67
Test mode functionality Chapter 3
Basic IED functions
Figure 32: Example of blocking the time delayed undervoltage protection function.
5.3 Function block
Figure 33: TEST function block
Time
U
Normal voltage
U1<
U2<
IntBlkStVal1
IntBlkStVal2
Disconnection
tBlkUV1 <
t1,t1Min
tBlkUV2 <
t2,t2Min
Block step 1
Block step 2
en05000466.vsd
Test
TEST-
INPUT ACTIVE
OUTPUT
SETTING
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68
Test mode functionality Chapter 3
Basic IED functions
5.4 Input and output signals
Table 34: Input signals for the Test (TEST-) function block
Table 35: Output signals for the Test (TEST-) function block
5.5 Setting parameters
Table 36: General settings for the Test (TEST-) function
Signal Description
INPUT Sets terminal in test mode when active
Signal Description
ACTIVE Terminal in test mode when active
OUTPUT Test input is active
SETTING Test mode setting is (On) or not (Off)
Parameter Range Step Default Unit Description
TestMode Off
On
- Off - Test mode in operation
(On) or not (Off)
69
IED identifiers Chapter 3
Basic IED functions
6 IED identifiers
6.1 Introduction
There are two functions that allow you to identify each IED individually: ProductInformation
function has only three pre-set, unchangeable but nevertheless very important settings: Serial-
No., Ordering No., and ProductDate, that you can see on the local HMI, under Diagnostics/IED
Status/Identifiers. They are very helpful in case of support process (such as repair or mainte-
nance).
Identifiers function is actually allowing you to identify the individual IED in your system, not
only in the substation, but in a whole region or a country.
6.2 Setting parameters
Table 37: General settings for the TerminalID (TEID-) function
Parameter Range Step Default Unit Description
StationName 0 - 18 1 Station name - Station name
StationNumber 0 - 99999 1 0 - Station number
ObjectName 0 - 18 1 Object name - Object name
ObjectNumber 0 - 99999 1 0 - Object number
UnitName 0 - 18 1 Unit name - Unit name
UnitNumber 0 - 99999 1 0 - Unit number
70
Signal matrix for binary inputs (SMBI) Chapter 3
Basic IED functions
7 Signal matrix for binary inputs (SMBI)
7.1 Introduction
The SMBI function block is used within the CAP tool in direct relation with the Signal Matrix
Tool SMT (please see the overview of the engineering process in the Application manual,
chapter Engineering of the IED). It represents the way binary inputs are brought in for one
IED670 configuration.
7.2 Principle of operation
The SMBI function block, see figure34, receives its inputs from the real (hardware) binary in-
puts via the SMT, and makes them available to the rest of the configuration via its outputs,
named BI1 to BI10. The inputs, as well as the whole block, can be tag-named. These tags will
be represented in SMT.
7.3 Function block
Figure 34: SI function block
7.4 Input and output signals
Table 38: Input signals for the SMBI (SI01-) function block
SMBI
SI01-
INSTNAME
BI1NAME
BI2NAME
BI3NAME
BI4NAME
BI5NAME
BI6NAME
BI7NAME
BI8NAME
BI9NAME
BI10NAME
BI1
BI2
BI3
BI4
BI5
BI6
BI7
BI8
BI9
BI10
en05000434.vsd
Signal Description
INSTNAME Instance name in Signal Matrix Tool
BI1NAME Signal name for BI1 in Signal Matrix Tool
BI2NAME Signal name for BI2 in Signal Matrix Tool
BI3NAME Signal name for BI3 in Signal Matrix Tool
BI4NAME Signal name for BI4 in Signal Matrix Tool
BI5NAME Signal name for BI5 in Signal Matrix Tool
71
Signal matrix for binary inputs (SMBI) Chapter 3
Basic IED functions
Table 39: Output signals for the SMBI (SI01-) function block
BI6NAME Signal name for BI6 in Signal Matrix Tool
BI7NAME Signal name for BI7 in Signal Matrix Tool
BI8NAME Signal name for BI8 in Signal Matrix Tool
BI9NAME Signal name for BI9 in Signal Matrix Tool
BI10NAME Signal name for BI10 in Signal Matrix Tool
Signal Description
BI1 Binary input 1
BI2 Binary input 2
BI3 Binary input 3
BI4 Binary input 4
BI5 Binary input 5
BI6 Binary input 6
BI7 Binary input 7
BI8 Binary input 8
BI9 Binary input 9
BI10 Binary input 10
Signal Description
72
Signal matrix for binary outputs (SMBO) Chapter 3
Basic IED functions
8 Signal matrix for binary outputs (SMBO)
8.1 Introduction
The SMBO function block is used within the CAP tool in direct relation with the Signal Matrix
Tool SMT (please see the overview of the engineering process in the Application manual,
chapter Engineering of the IED). It represents the way binary outputs are sent from one
IED670 configuration.
8.2 Principle of operation
The SMBO function block, see figure35, receives logical signal from the IED configuration,
which it is transferring to the real (hardware) outputs, via the SMT. The inputs in the SMBO are
named BO1 to BO10 and they, as well as the whole function block, can be tag-named. The name
tags will appear in SMT.
8.3 Function block
Figure 35: SO function block
8.4 Input and output signals
Table 40: Input signals for the SMBO (SO01-) function block
SMBO
SO01-
BO1
BO2
BO3
BO4
BO5
BO6
BO7
BO8
BO9
BO10
INSTNAME
BO1NAME
BO2NAME
BO3NAME
BO4NAME
BO5NAME
BO6NAME
BO7NAME
BO8NAME
BO9NAME
BO10NAME
en05000439.vsd
Signal Description
BO1 Signal name for BO1 in Single Matrix Tool
BO2 Signal name for BO2 in Single Matrix Tool
BO3 Signal name for BO3 in Single Matrix Tool
BO4 Signal name for BO4 in Single Matrix Tool
BO5 Signal name for BO5 in Single Matrix Tool
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Signal matrix for binary outputs (SMBO) Chapter 3
Basic IED functions
Table 41: Output signals for the SMBO (SO01-) function block
BO6 Signal name for BO6 in Single Matrix Tool
BO7 Signal name for BO7 in Single Matrix Tool
BO8 Signal name for BO8 in Single Matrix Tool
BO9 Signal name for BO9 in Single Matrix Tool
BO10 Signal name for BO10 in Single Matrix Tool
Signal Description
INSTNAME Instance name in Single Matrix Tool
BO1NAME Signal name for BO1 in Single Matrix Tool
BO2NAME Signal name for BO2 in Single Matrix Tool
BO3NAME Signal name for BO3 in Single Matrix Tool
BO4NAME Signal name for BO4 in Single Matrix Tool
BO5NAME Signal name for BO5 in Single Matrix Tool
BO6NAME Signal name for BO6 in Single Matrix Tool
BO7NAME Signal name for BO7 in Single Matrix Tool
BO8NAME Signal name for BO8 in Single Matrix Tool
BO9NAME Signal name for BO9 in Single Matrix Tool
BO10NAME Signal name for BO10 in Single Matrix Tool
Signal Description
74
Signal matrix for mA inputs (SMMI) Chapter 3
Basic IED functions
9 Signal matrix for mA inputs (SMMI)
9.1 Introduction
The SMMI function block is used within the CAP tool in direct relation with the Signal Matrix
Tool SMT (please see the overview of the engineering process in the Application manual,
chapter Engineering of the IED). It represents the way milliamp (mA) inputs are brought in
for one IED670 configuration.
9.2 Principle of operation
The SMMI function block, see figure36, receives its inputs from the real (hardware) mA inputs
via the SMT, and makes them available to the rest of the configuration via its analog outputs,
named AI1 to AI6. The inputs, as well as the whole block, can be tag-named. These tags will be
represented in SMT.
The outputs on the SMMI are normally connected to the SPGGIO MVGGIO function block for
further use of the mA signals.
9.3 Function block
Figure 36: SMI function block
9.4 Input and output signals
Table 42: Input signals for the SMMI (SMI1-) function block
SMMI
SMI1-
INSTNAME
AI1NAME
AI2NAME
AI3NAME
AI4NAME
AI5NAME
AI6NAME
AI1
AI2
AI3
AI4
AI5
AI6
en05000440.vsd
Signal Description
INSTNAME Instance name in Signal Matrix Tool
AI1NAME Signal name for AI1 in Signal Matrix Tool
AI2NAME Signal name for AI2 in Signal Matrix Tool
AI3NAME Signal name for AI3 in Signal Matrix Tool
AI4NAME Signal name for IN4 in Signal Matrix Tool
AI5NAME Signal name for AI5 in Signal Matrix Tool
AI6NAME Signal name for AI6 in Signal Matrix Tool
75
Signal matrix for mA inputs (SMMI) Chapter 3
Basic IED functions
Table 43: Output signals for the SMMI (SMI1-) function block
Signal Description
AI1 Analog milliampere input 1
AI2 Analog milliampere input 2
AI3 Analog milliampere input 3
AI4 Analog milliampere input 4
AI5 Analog milliampere input 5
AI6 Analog milliampere input 6
76
Signal matrix for analog inputs (SMAI) Chapter 3
Basic IED functions
10 Signal matrix for analog inputs (SMAI)
10.1 Introduction
The SMAI function block (or the pre-processing function block, as it is also known) is used
within the PCM600 in direct relation with the Signal Matrix Tool SMT (please see the overview
of the engineering process in the Application manual, chapter Engineering of the IED). It
represents the way analog inputs are brought in for one IED670 configuration.
10.2 Principle of operation
Every SMAI function block can receive four analog signals (three phases and one neutral value),
either voltage or current, see figure37 and figure38. The outputs of the SMAI are giving infor-
mation about every aspect of the 3ph analog signals acquired (phase angle, RMS value, frequen-
cy and frequency derivates etc. 244 values in total). The BLOCK input will reset to 0 all the
analog inputs of the function block.
10.3 Function block
Figure 37: PR01 function block
Figure 38: PR0212 function block
en05000705.vsd
SMAI
PR01-
BLOCK
DFTSYNC
DFTSPFC
GRPNAME
AI1NAME
AI2NAME
AI3NAME
AI4NAME
TYPE
SYNCOUT
SPFCOUT
AI3P
AI1
AI2
AI3
AI4
AIN
en05000706.vsd
SMAI
PR02-
BLOCK
GRPNAME
AI1NAME
AI2NAME
AI3NAME
AI4NAME
TYPE
AI3P
AI1
AI2
AI3
AI4
AIN
77
Signal matrix for analog inputs (SMAI) Chapter 3
Basic IED functions
10.4 Input and output signals
Table 44: Input signals for the SMAI (PR01-) function block
Table 45: Output signals for the SMAI (PR01-) function block
Table 46: Input signals for the SMAI (PR02-) function block
Signal Description
BLOCK Block group 1
DFTSYNC Synchronisation of DFT calculation
DFTSPFC Number of samples per fundamental cycle used for DFT calcula-
tion
GRPNAME Group name for GRP1 in Signal Matrix Tool
AI1NAME Signal name for AI1 in Signal Matrix Tool
AI2NAME Signal name for AI2 in Signal Matrix Tool
AI3NAME Signal name for AI3 in Signal Matrix Tool
AI4NAME Signal name for AI4 in Signal Matrix Tool
Signal Description
SYNCOUT Synchronisation signal from internal DFT reference function
SPFCOUT Number of samples per fundamental cycle from internal DFT ref-
erence function
AI3P Group 1 analog input 3-phase group
AI1 Group 1 analog input 1
AI2 Group 1 analog input 2
AI3 Group 1 analog input 3
AI4 Group 1 analog input 4
AIN Group 1 analog input residual for disturbance recorder
Signal Description
BLOCK Block group 2
GRPNAME Group name for GRP2 in Signal Matrix Tool
AI1NAME Signal name for AI1 in Signal Matrix Tool
AI2NAME Signal name for AI2 in Signal Matrix Tool
AI3NAME Signal name for AI3 in Signal Matrix Tool
AI4NAME Signal name for AI4 in Signal Matrix Tool
78
Signal matrix for analog inputs (SMAI) Chapter 3
Basic IED functions
Table 47: Output signals for the SMAI (PR02-) function block
Signal Description
AI3P Group 2 analog input 3-phase group
AI1 Group 2 analog input 1
AI2 Group 2 analog input 2
AI3 Group 2 analog input 3
AI4 Group 2 analog input 4
AIN Group 2 analog input residual for disturbance recorder
79
Signal matrix for analog inputs (SMAI) Chapter 3
Basic IED functions
10.5 Setting parameters
Table 48: General settings for the SMAI (PR01-) function
Parameter Range Step Default Unit Description
DFTRefExtOut InternalDFTRef
AdDFTRefCh1
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
- InternalDFTRef - DFT reference for exter-
nal output
DFTReference InternalDFTRef
AdDFTRefCh1
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
- InternalDFTRef - DFT reference
ConnectionType Ph-N
Ph-Ph
- Ph-N - Input connection type
Negation Off
NegateN
Negate3Ph
Negate3Ph+N
- Off - Negation
MinValFreqMeas 5 - 200 1 10 % Limit for frequency calcu-
lation in % of UBase
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage
TYPE 1 - 2 1 1 Ch 1=Voltage,2=Current
80
Signal matrix for analog inputs (SMAI) Chapter 3
Basic IED functions
Table 49: General settings for the SMAI (PR02-) function
Parameter Range Step Default Unit Description
DFTReference InternalDFTRef
AdDFTRefCh1
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
- InternalDFTRef - DFT reference
ConnectionType Ph-N
Ph-Ph
- Ph-N - Input connection type
Negation Off
NegateN
Negate3Ph
Negate3Ph+N
- Off - Negation
MinValFreqMeas 5 - 200 1 10 % Limit for frequency calcu-
lation in % of UBase
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage
TYPE 1 - 2 1 1 Ch 1=Voltage,2=Current
81
Summation block 3 phase (SUM3Ph) Chapter 3
Basic IED functions
11 Summation block 3 phase (SUM3Ph)
11.1 Introduction
The SUM3Ph function block is used in order to get the sum of two sets of 3 ph analog signals
(of the same type) for those IED functions that might need it.
11.2 Principle of operation
The summation block receives the 3ph signals from the SMAI blocks, see figure39. In the same
way, the BLOCK input will reset to 0 all the analog inputs of the function block.
11.3 Function block
Figure 39: SU function block
11.4 Input and output signals
Table 50: Input signals for the Sum3Ph (SU01-) function block
Table 51: Output signals for the Sum3Ph (SU01-) function block
Sum3Ph
SU01-
BLOCK
DFTSYNC
DFTSPFC
G1AI3P
G2AI3P
AI3P
AI1
AI2
AI3
AI4
en05000441.vsd
Signal Description
BLOCK Block
DFTSYNC Synchronisation of DFT calculation
DFTSPFC Number of samples per fundamental cycle used for DFT calcula-
tion
G1AI3P Group 1 analog input 3-phase group
G2AI3P Group 2 analog input 3-phase group
Signal Description
AI3P Group analog input 3-phase group
AI1 Group 1 analog input
AI2 Group 2 analog input
AI3 Group 3 analog input
AI4 Group 4 analog input
82
Summation block 3 phase (SUM3Ph) Chapter 3
Basic IED functions
11.5 Setting parameters
Table 52: General settings for the Sum3Ph (SU01-) function
Parameter Range Step Default Unit Description
SummationType Group1+Group2
Group1-Group2
Group2-Group1
-(Group1+Group2)
- Group1+Group2 - Summation type
DFTReference InternalDFTRef
AdDFTRefCh1
External DFT ref
- InternalDFTRef - DFT reference
FreqMeasMinVal 5 - 200 1 10 % Amplitude limit for fre-
quency calculation in %
of Ubase
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage
83
About this chapter Chapter 4
Differential protection
Chapter 4 Differential
protection
About this chapter
This chapter describes the measuring principles, functions and parameters used in differential
protection.
84
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
1 Transformer differential protection (PDIF, 87T)
Table 53: Transformer differential protection, two winding
Table 54: Transformer differential protection, three winding
1.1 Introduction
The RET670 differential function for two winding and three winding transformers is provided
with internal CT ratio matching and vector group compensation, which allows connection di-
rectly to star connected main CTs. Zero sequence current elimination is made internally in the
software.
The function can be provided with up to six three phase sets of current inputs. All current inputs
are provided with percentage bias restraint features, making the RET670 suitable for two- or
three winding transformers in multi-breaker station arrangements.
Function block name: T2Dx- IEC 60617 graphical symbol:
ANSI number: 87T
IEC 61850 logical node name:
T2WPDIF
Function block name: T3Dx- IEC 60617 graphical symbol:
ANSI number: 87T
IEC 61850 logical node name:
T3WPDIF
3Id/I
3Id/I
85
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
2-winding applications
2-winding power trans-
former
2-winding power trans-
former with uncon-
nected delta tertiary
winding
2-winding power trans-
former with 2 circuit
breakers on one side
2-winding power trans-
former with 2 circuit
breakers and 2
CT-sets on both sides
3-winding applications
3-winding power trans-
former with all three
windings connected
3-winding power trans-
former with 2 circuit
breakers and 2
CT-sets on one side
Autotransformer with 2
circuit breakers and 2
CT-sets on 2 out of 3
sides
Figure 40: CT group arrangement for differ-
ential protection and other protec-
tions
xx05000048.vsd
xx05000049.vsd
xx05000050.vsd
xx05000051.vsd
xx05000052.vsd
xx05000053.vsd
xx05000057.vsd
86
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
The setting facilities cover for applications of the differential protection to all types of power
transformers and autotransformers with or without on-load tap-changer as well as for shunt re-
actor or a local feeder within the station. An adaptive stabilizing feature is included for heavy
through-faults. By introducing the tap changer position, the differential protection pick-up can
be set to optimum sensitivity covering internal faults with low fault level.
Stabilization is included for inrush currents respectively for overexcitation condition. Adaptive
stabilization is also included for system recovery inrush and CT saturation for external faults. A
fast high set unrestrained differential current protection is included for very high speed tripping
at high internal fault currents.
Innovative sensitive differential protection feature, based on the theory of symmetrical compo-
nents, offers best possible coverage for power transformer windings turn-to-turn faults.
1.2 Principle of operation
The task of the power transformer differential protection is to determine whether a fault is within
the protected zone, or outside the protected zone. The protected zone is delimited by the position
of current transformers (see figure41), and in principle can include more objects than just trans-
former. If the fault is found to be internal, the faulty power transformer must be quickly discon-
nected.
The main CTs are always supposed to be star connected. The main CTs can be stared in any way
(i.e. either "ToObject" or "FromObject"). However internally the differential function will al-
ways use reference directions towards the protected transformer as shown in figure41. Thus the
IED will always internally measure the currents on all sides of the power transformer with the
same reference direction towards the power transformer windings.
Figure 41: Typical CT location and definition of positive current direction
Even in a healthy power transformer, the currents are generally not equal when they flow
through the power transformer, due to the turn's ratio and the connection group of the protected
transformer. Therefore the differential protection must first correlate all currents to each other
before any calculation can be performed.
en05000186.vsd
IED
I
W1
I
W2
I
W1
I
W2
E1
S1
Z1
S1
E1
S2
Z1
S2
87
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
In numerical differential protections this correlation and comparison is performed mathemati-
cally. First, compensation for the protected transformer transformation ratio and connection
group is made, and then the currents are compared. This makes the external auxiliary (i.e. inter-
posing) current transformers unnecessary. Conversion of all currents to the common reference
side of the power transformer is performed by pre-programmed coefficient matrices, which de-
pend on the protected power transform transformation ratio and connection group. Once the
power transformer vector group and rated currents and voltages has been entered by the user, the
differential protection is capable to off-line calculate matrix coefficients in order to perform the
required on-line current comparison in accordance with the fixed equation.
Numerical IEDs have brought a large number of well-known advantages and new functionality
to the protective relaying. One of the benefits is the simplicity and accuracy of calculating sym-
metrical components from individual phase quantities. Within the firmware of a numerical IED,
it is no more difficult to calculate negative-sequence components than it is to calculate zero-se-
quence components. Diversity of operation principles integrated in the same protection function
enhances the overall performance without a significant increase in cost.
A novelty in power transformer differential protection, namely the negative-sequence-cur-
rent-based internal-external fault discriminator, is used with advantage in order to determine
whether a fault is internal or external. Indeed, the internal-external fault discriminator not only
positively discriminates between internal and external faults, but can as well independently de-
tect minor faults which may not be felt by the "usual" differential protection based on operate-re-
strain characteristic.
1.2.1 Function calculation principles
To make a differential IED as sensitive and stable as possible, restrained differential character-
istic have been developed and are now adopted as the general practice in the protection of power
transformers. The protection should be provided with a proportional bias, which makes the pro-
tection operate for a certain percentage differential current related to the current through the
transformer. This stabilizes the protection under through fault conditions while still permitting
the system to have good basic sensitivity. The following chapters explain how these quantities
are calculated.
Fundamental frequency differential currents
The fundamental frequency differential current is a vectorial sum (i.e. sum of fundamental fre-
quency phasors) of the individual phase currents from different side of the protected power
transformer.
Before any differential current can be calculated, the power transformer phase shift, and its
transformation ratio, must be allowed for. Conversion of all currents to a common reference is
performed in two steps:
all current phasors are phase-shifted to (i.e. referred to) the phase-reference side,
(whenever possible a first winding with star connection)
all currents magnitudes are always referred to the first winding of the power
transformer (typically transformer high-voltage side)
The two steps of conversion are made simultaneously on-line by the pre-programmed coeffi-
cient matrices, as shown in equation1 for a two-winding power transformer, and in equation2
for a three-winding power transformer.
88
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
(Equation 1)
(Equation 2)
where:
1. is Differential Currents
2. is Differential current contribution from W1 side
3. is Differential current contribution from W2 side
where:
1. is Differential Currents
2. is Differential current contribution from W1 side
3. is Differential current contribution from W2 side
4. is Differential current contribution from W3 side
and where, for equation 1 and equation 2:
IDL1 is the fundamental frequency differential current in phase L1
(in W1 side primary amperes)
IDL2 is the fundamental frequency differential current in phase L2
(in W1 side primary amperes)
IDL3 is the fundamental frequency differential current in phase L3
(in W1 side primary amperes)
IL1_W1 is the fundamental frequency phase current in phase L1 on W1 side
IL2_W1 is the fundamental frequency phase current in phase L2 on W1 side
IL3_W1 is the fundamental frequency phase current in phase L3 on W1 side
IL1_W2 is the fundamental frequency phase current in phase L1 on W2 side
1 1_ 1 1_ 2
_ 2
2 2_ 1 2_ 2
_ 1
3 3_ 1 3_ 2
IDL IL W IL W
Ur W
IDL A IL W B IL W
Ur W
IDL IL W IL W


= +



2 3 1
1 1_ 1 1_ 2 1_ 3
_ 2 _ 3
2 2_ 1 2_ 2 2_ 3
_ 1 _ 1
3 3_ 1 3_ 2 3_ 3
IDL IL W IL W IL W
Ur W Ur W
IDL A IL W B IL W C IL W
Ur W Ur W
IDL IL W IL W IL W
+


= +



1 2 3 4
89
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Values of the matrix A, B & C coefficients depend on:
1. Power transformer winding connection type, such as star (i.e. Y/y) or delta (i.e.
D/d)
2. Transformer vector group such as Yd1, Dy11, YNautod5, Yy0d5 etc., which in-
troduce phase displacement between individual windings currents in multiples of
30.
3. Settings for elimination of zero sequence currents for individual windings.
When the end user enters all these parameters, transformer differential function automatically
off-line calculates the matrix coefficients. During this calculations the following rules are used:
For the phase reference, the first winding with set star (i.e. Y) connection is always used. For
example, if the power transformer is a Yd1 power transformer, the HV winding (Y) is taken as
the phase reference winding. If the power transformer is a Dy, then the LV winding (y) is taken
for the phase reference. If there is no star connected winding, such as in Dd0 type of power trans-
formers, then the HV delta winding (D) is automatically chosen as the phase reference winding.
The fundamental frequency differential currents are in general composed of currents of all se-
quences, i.e. the positive-, the negative-, and the zero-sequence currents. If the zero-sequence
currents are eliminated (see section "Optional Elimination of Zero-sequence Currents"), then
the differential currents can consist only of the positive-, and the negative-sequence currents.
When the zero-sequence current is subtracted on one power transformer side, then it is subtract-
ed from each individual phase current.
As it can be seen from equation1 and equation2 the first entered winding (i.e. W1) is always
taken for ampere level reference (i.e. current magnitudes from all other sides are always trans-
ferred to W1 side). In other words, within the differential protection function, all differential cur-
rents and bias current are always expressed in HV side primary Amperes.
It can be shown that the values of the matrix A, B & C coefficients (see equation1 and
equation2) can be in advanced pre-calculated depending on the relative phase shift between the
reference winding and other power transformer windings.
Table55 summarizes the values of the matrices for all standard phase shifts between windings.
IL2_W2 is the fundamental frequency phase current in phase L2 on W2 side
IL3_W2 is the fundamental frequency phase current in phase L3 on W2 side
IL1_W3 is the fundamental frequency phase current in phase L1 on W3 side
IL2_W3 is the fundamental frequency phase current in phase L2 on W3 side
IL3_W3 is the fundamental frequency phase current in phase L3 on W3 side
Ur_W1 is transformer rated phase-to-phase voltage on W1 side (setting parameter)
Ur_W2 is transformer rated phase-to-phase voltage on W2 side (setting parameter)
Ur_W3 is transformer rated phase-to-phase voltage on W3 side (setting parameter)
A, B & C are three by three matrices with numerical coefficients
90
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Table 55: Matrices for differential current calculation
Matrix with Zero Sequence
Reduction set to On
Matrix with Zero Sequence
Reduction set to Off
Matrix for Reference Winding
Matrix for winding with 30 lagging Not applicable. Matrix on the left
used.
Matrix for winding with 60 lagging
Matrix for winding with 90 lagging Not applicable. Matrix on the left
used.
Matrix for winding with
120 lagging
Matrix for winding with
150 lagging
Not applicable. Matrix on the left
used.
Matrix for winding which is in
opposite phase
2 1 1
1
1 2 1
3
1 1 2








1 0 0
0 1 0
0 0 1





1 -1 0
1
0 1 1
3
1 0 1






1 2 1
1
1 1 2
3
2 1 1






0 1 0
0 0 1
1 0 0






0 -1 1
1
1 0 1
3
1 1 0






1 1 2
1
2 1 1
3
1 2 1








0 0 1
1 0 0
0 1 0





-1 0 1
1
1 1 0
3
0 1 1






2 1 1
1
1 2 1
3
1 1 2






1 0 0
0 1 0
0 0 1






91
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
By using this table complete equation for calculation of fundamental frequency differential cur-
rents for two winding power transformer with YNd5 vector group and enabled zero sequence
current reduction on HV side will be derived. From the given power transformer vector group
the following is possible to be concluded:
1. HV winding will be used as reference winding and zero sequence currents shall
be subtracted on that side
2. LV winding is lagging for 150
With help of table55, the following matrix equation can be written for this power transformer:
Matrix for winding with
150 leading
Not applicable. Matrix on the left
used.
Matrix for winding with
120 leading
Matrix for winding with 90 leading Not applicable. Matrix on the left
used.
Matrix for winding with 60 leading
Matrix for winding with 30 leading Not applicable. Matrix on the left
used.
Matrix with Zero Sequence
Reduction set to On
Matrix with Zero Sequence
Reduction set to Off
-1 1 0
1
0 1 1
3
1 0 1






1 2 1
1
1 1 2
3
2 1 1








0 1 0
0 0 1
1 0 0





0 1 -1
1
-1 0 1
3
1 1 0






1 1 2
1
2 1 1
3
1 2 1






0 0 1
1 0 0
0 1 0






1 0 -1
1
-1 1 0
3
0 1 1






92
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
(Equation 3)
As marked in equation1 and equation2, the first term on the right hand side of the equation,
represents the total contribution from the individual phase currents from W1 side to the funda-
mental frequency differential currents compensated for eventual power transformer phase shift.
The second term on the right hand side of the equation, represents the total contribution from the
individual phase currents from W2 side to the fundamental frequency differential currents com-
pensated for eventual power transformer phase shift and transferred to the power transformer
W1 side. The third term on the right hand side of the equation, represents the total contribution
from the individual phase currents from W3 side to the fundamental frequency differential cur-
rents compensated for eventual power transformer phase shift and transferred to the power trans-
former W1 side. These current contributions are important, because they are used for calculation
of common bias current.
The fundamental frequency differential currents are the "usual" differential currents, the magni-
tudes of which are applied in a phase-wise manner to the operate - restrain characteristic of the
differential protection. The magnitudes of the differential currents can be read as service values
from the function and they are available as outputs IDL1MAG, IDL2MAG, IDL3MAG from the
differential protection function block. Thus they can be connected to the disturbance recorder
and automatically recorded during any external or internal fault condition.
where:
IDL1 is the fundamental frequency differential current in phase L1
(in W1 side primary amperes)
IDL2 is the fundamental frequency differential current in phase L2
(in W1 side primary amperes)
IDL3 is the fundamental frequency differential current in phase L3
(in W1 side primary amperes)
IL1_W1 is the fundamental frequency phase current in phase L1 on W1 side
IL2_W1 is the fundamental frequency phase current in phase L2 on W1 side
IL3_W1 is the fundamental frequency phase current in phase L3 on W1 side
IL1_W2 is the fundamental frequency phase current in phase L1 on W2 side
IL2_W2 is the fundamental frequency phase current in phase L2 on W2 side
IL3_W2 is the fundamental frequency phase current in phase L3 on W2 side
Ur_W1 is transformer rated phase-to-phase voltage on W1 side (setting parameter)
Ur_W2 is transformer rated phase-to-phase voltage on W2 side (setting parameter)
1 2 1 1 1_ 1 1 0 1 1_ 2
1 _ 1 1
2 1 2 1 2_ 1 1 1 0 2_ 2
3 _ 2 3
3 1 1 2 3_ 1 0 1 1 3_ 2
IDL IL W IL W
Ur W
IDL IL W IL W
Ur W
IDL IL W IL W

= +






93
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Bias current
The bias current is calculated as the highest current amongst individual winding current contri-
butions to the total fundamental frequency differential currents, as shown in equation1 and
equation2. All individual winding current contributions are already referred to the power trans-
former winding one side Amperes (typically power transformer HV winding) and therefore they
can be compared regarding their magnitudes. There are six (or nine in case of three winding
transformer) contributions to the total fundamental differential currents, which are the candi-
dates for the common bias current. The highest individual current contribution is taken as a com-
mon bias (restrain) current for all three phases. This "maximum principle" makes the differential
protection more secure, with less risk to operate for external faults and in the same time brings
more meaning to the breakpoint settings of the operate - restrain characteristic.
It shall be noted that if the zero-sequence currents are subtracted from the separate contributions
to the total differential current, then the zero-sequence component is automatically eliminated
from the bias current as well. This ensures that for secondary injection from just one power
transformer side the bias current is always equal to the highest differential current regardless of
the fault type. During normal through-load operation of the power transformer, the bias current
is equal to the maximum load current from two (three) power transformer windings.
The magnitudes of the common bias (restrain) current expressed in the HV side Amperes can be
read as service values from the function. In the same time it is available as outputs IBIAS from
the differential protection function block. Thus, it can be connected to the disturbance recorder
and automatically recorded during any external or internal fault condition.
For application with so called "T" configuration, i.e. two restraint CT inputs from one side of the
protected power transformer, such as in the case of breaker-and-a-half scheme the primary CT
ratings can be much higher then the rating of the protected power transformer. In order to deter-
mine the bias current for such T configuration, the two separate currents flowing on the T-side
can be scaled by additional setting. This is done in order to prevent unwanted de-sensitizing of
the overall differential protection. In addition to that, the resultant currents into the protected
power transformer winding, which is not directly measured is calculated, and included as well
in the common bias calculation. The rest of the bias calculation procedure is the same as in pro-
tection schemes without breaker-and-a-half scheme.
Optional Elimination of Zero-sequence Currents
To avoid unwanted trips for external earth faults, the zero sequence currents should be subtract-
ed on the side of power transformer, where the zero-sequence currents can flow at external earth
faults. The zero-sequence currents can be explicitly eliminated from the differential currents and
common bias current calculation by parameter settings, which are available for every individual
winding.
Elimination of the zero-sequence component of current is necessary whenever:
protected power transformer cannot transform the zero-sequence currents to the
other side
the zero-sequence currents can only flow on one side of the protected power
transformer.
In most cases, power transformers do not properly transform the zero sequence current to the
other side. A typical example is a power transformer of the star-delta type, e.g. YNd1. Trans-
formers of this type do not transform the zero-sequence quantities, but zero-sequence currents
can flow in the earthed star connected winding. In such cases, an external earth fault on the
94
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
star-side causes the zero-sequence currents to flow on the star-side of the power transformer, but
not on the other side. This results in false differential currents - consisting exclusively of the ze-
ro-sequence currents. If high enough, these false differential currents can cause an unwanted dis-
connection of the healthy power transformer. They must therefore be subtracted from the
fundamental frequency differential currents if an unwanted trip is to be avoided.
Removing the zero-sequence current from the differential currents decreases to some extent sen-
sitivity of the differential protection for the internal earth faults. In order to counteract this effect
to some degree, the zero-sequence currents are subtracted not only from the three fundamental
frequency differential currents, but automatically from the bias current as well.
Restrained, and Unrestrained Limits of the Differential Protection
Power transformer differential protection function uses two limits, to which actual magnitudes
of the three fundamental frequency differential currents are compared at each execution of the
function.
The unrestrained (i.e. non-stabilized) part of the differential protection is used for very big dif-
ferential currents, where it should be beyond any doubt, that the fault is internal. This settable
limit is constant (i.e. not proportional the bias current). Neither harmonic, nor any other restrain
is applied to this limit, which is therefore allowed to trip power transformer instantaneously.
The restrained (i.e. stabilized) part of the differential protection compares the calculated funda-
mental differential (i.e. operating) currents, and the bias (i.e. restrain) current, by applying them
to the operate - restrain characteristic. Practically, the magnitudes of the individual fundamental
frequency differential currents are compared with an adaptive limit. This limit is adaptive be-
cause it is dependent on the bias (i.e. restrain) current magnitude. This limit is called the operate
- restrain characteristic. It is represented by a double-slope, double-breakpoint characteristic, as
shown in figure42. The restrained characteristic is determined by the following 5 settings:
1. IdMin (Sensitivity in section 1, multiple of trans. HV side rated current set under
the parameter RatedCurrentW1)
2. EndSection1 (End of section 1, as multiple of transformer HV side rated current
set under the parameter RatedCurrentW1)
3. EndSection2 (End of section 2, as multiple of transformer HV side rated current
set under the parameter RatedCurrentW1)
4. SlopeSection2 (Slope in section 2, as multiple of transformer HV side rated cur-
rent set under the parameter RatedCurrentW1)
5. SlopeSection3 (Slope in section 2, as multiple of transformer HV side rated cur-
rent set under the parameter RatedCurrentW1)
The restrained characteristic in figure42 is defined by the settings:
1. IdMin
2. EndSection1
3. EndSection2
4. SlopeSection2
5. SlopeSection3
95
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Figure 42: Description of the restrained-, and the unrestrained operate characteristics
The operate - restrain characteristic is tailor-made and can be designed freely by the user after
his needs. A default characteristic is recommended to be used. It gives good results in a majority
of applications. The operate - restrain characteristic has in principle three sections with a sec-
tion-wise proportionality of the operate value to the bias (restrain) current. The reset ratio is in
all parts of the characteristic is equal to 0.95.
Section 1: This is the most sensitive part on the characteristic. In section 1, normal currents flow
through the protected circuit and its current transformers, and risk for higher false differential
currents is relatively low. Un-compensated on-load tap-changer is a typical reason for existence
of the false differential currents in this section. Slope in section 1 is always zero percent.
where:
Section 1
Operate
conditionally
UnrestrainedLimit
Section 2 Section 3
Restrain
Operate
unconditionally
5
4
3
2
1
0
0 1 2 3 4 5
IdMin
EndSection1
EndSection2
restrain current
[ times I1r ]
operate current
[ times I1r ]
SlopeSection2
SlopeSection3
en05000187.vsd
100%
Ioperate
slope
Irestrain


96
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Section 2: In section 2, a certain minor slope is introduced which is supposed to cope with false
differential currents proportional to higher than normal currents through the current transform-
ers.
Section 3: The more pronounced slope in section 3 is designed to result in a higher tolerance to
substantial current transformer saturation at high through-fault currents, which may be expected
in this section.
The operate - restrain characteristic should be designed so that it can be expected that:
for internal faults, the operate (differential) currents are always safely, i.e. with a
good margin, above the operate - restrain characteristic
for external faults, the false (spurious) operate currents are safely, i.e. with a good
margin, below the operate - restrain characteristic
Fundamental frequency negative-sequence differential currents
Existence of relatively high negative-sequence currents is in itself a proof of a disturbance on
the power system, possibly a fault in the protected power transformer. The negative-sequence
currents are measurable indications of abnormal conditions, similar to the zero-sequence cur-
rents. One of the several advantages of the negative-sequence currents compared to the zero-se-
quence currents is however that they provide coverage for phase-to-phase and power
transformer turn-to-turn faults as well, not only for earth-faults. Theoretically the negative se-
quence currents do not exist during symmetrical three-phase faults, however they do appear dur-
ing initial stage of such faults for long enough time for the IED to make proper decision. Further,
the negative sequence currents are not stopped at a power transformer of the Yd, or Dy connec-
tion. The negative sequence currents are always properly transformed to the other side of any
power transformer for any external disturbance. Finally, the negative sequence currents are typ-
ically not affected by through-load currents.
For power transformer differential protection application, the negative-sequence based differen-
tial currents are calculated by using exactly the same matrix equations, which are used to calcu-
late the traditional phase-wise fundamental frequency differential currents. However, the same
equation shall be fed by the negative-sequence currents from the two power transformer sides
instead of individual phase currents, as shown in matrix equation4 for a case of two-winding,
YNd5 power transformer.
(Equation 4)
where:
1. is Neg. Seq. Diff Currents
2. is Negative Sequence current contribution from W1 side
3. is Negative Sequence current contribution from W2 side
2 2
1_ 2 1 1 _ 1 1 0 1 _ 2
1 _ 2 1
2_ 1 2 1 _ 1 1 1 0 _ 2
3 _ 1 3
3_ 1 1 2 _ 1 0 1 1 _ 2
IDL NS INS W INS W
Ur W
IDL NS a INS W a INS W
Ur W
IDL NS a INS W a INS W

= +








1 2 3
97
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Because the negative sequence currents always form the symmetrical three phase current system
on each transformer side (i.e. negative sequence currents in every phase will always have the
same magnitude and be phase displaced for 120 electrical degrees from each other), it is only
necessary to calculate the first negative sequence differential current i.e. IDL1_NS.
As marked in equation4, the first term on the right hand side of the equation, represents the total
contribution of the negative sequence current from W1 side compensated for eventual power
transformer phase shift. The second term on the right hand side of the equation, represents the
total contribution of the negative sequence current from W2 side compensated for eventual pow-
er transformer phase shift and transferred to the power transformer W1 side. These negative se-
quence current contributions are phasors, which are further used in directional comparisons,
made in order to characterize a fault as internal or external. See section "Internal/external fault
discriminator" for more information.
The magnitudes of the negative sequence differential current expressed in the HV side Amperes
can be read as service values from the function. In the same time it is available as outputs IDNS-
MAG from the differential protection function block. Thus, it can be connected to the distur-
bance recorder and automatically recorded during any external or internal fault condition.
Internal/external fault discriminator
The internal / external fault discriminator is a very powerful and reliable supplementary criterion
to the traditional differential protection. It is recommended that this feature shall be always used
(i.e. enabled) when protecting three-phase power transformers. The internal / external fault dis-
criminator detects even minor faults, with a high sensitivity and a high speed, and at the same
time discriminates with a high degree of dependability between internal and external faults.
The algorithm of the internal/external fault discriminator is based on the theory of symmetrical
components. Already in 1933, Wagner and Evans in their famous book "Symmetrical Compo-
nents" have stated that:
and where:
IDL1_NS is the negative sequence differential current in phase L1 (in W1 side primaryamperes)
IDL2_NS is the negative sequence differential current in phase L2 (in W1 side primaryamperes)
IDL3_NS is the negative sequence differential current in phase L3 (in W1 side primaryamperes)
INS_W1 is negative sequence current on W1 side in primary amperes (phase L1 reference)
INS_W2 is negative sequence current on W1 side in primary amperes (phase L1 reference)
Ur_W1 is transformer rated phase-to-phase voltage on W1 side (setting parameter)
Ur_W2 is transformer rated phase-to-phase voltage on W1 side (setting parameter)
a is the complex operator for sequence quantities, e.g.
120
1 3
2 2
j
a e j

= = +
o
98
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
The internal/external fault discriminator responds to magnitudes and the relative phase angles
of the negative-sequence fault currents at different windings (i.e. sides) of the protected power
transformer. The negative sequence fault currents must of course first be referred to the same
phase reference side, and put to the same magnitude reference. This is done by the matrix ex-
pression (see equation4).
Operation of the internal / external fault discriminator is based on the relative position of the two
phasors representing winding one (i.e. W1) and winding two (i.e. W2) negative-sequence cur-
rent contributions, defined by expression shown in equation4. It practically performs directional
comparison between these two phasors. First, the LV side phasors is positioned along the zero
degree line. After that the relevant position of the HV side phasor in the complex plain is deter-
mined. In case of three-winding power transformers, a little more complex algorithm is applied,
with two directional tests. The overall directional characteristic of the internal/external fault dis-
criminator is shown in figure43, where the directional characteristic is defined by two setting
parameters:
1. IMinNegSeq
2. NegSeqROA
1. Source of the negative-sequence currents is at the point of fault,
2. Negative-sequence currents distribute through the negative-sequence network
3. Negative-sequence currents obey the first Kirchhoff"s law
NS NS NS
E I Z =
99
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Figure 43: Operating characteristic of the internal/external fault discriminator
In order to perform directional comparison of the two phasors their magnitudes must be high
enough so that one can be sure that they are due to a fault. On the other hand, in order to guar-
antee a good sensitivity of the internal/external fault discriminator, the value of this minimum
limit must not be too high. Therefore this limit value, called IminNegSeq, is settable in the range
from 1% to 20% of the differential protection's base current, which is the power transformer
winding one rated current. The default value is 4%. Only if magnitudes of both negative se-
quence current contributions are above the set limit, the relative position between these two pha-
sors is checked. If either of the negative sequence current contributions, which should be
compared, is too small (less than the set value for IminNegSeq), no directional comparison is
made in order to avoid the possibility to produce a wrong decision. This magnitude check, as
well guarantee stability of the algorithm, when power transformer is energized. The setting Neg-
SeqROA represents the so-called Relay Operate Angle, which determines the boundary between
the internal and external fault regions. It can be selected in the range from 30 degrees to 90
degrees, with a step of 1 degree. The default value is 60 degrees. The default setting somewhat
favours security in comparison to dependability.
If the above condition concerning magnitudes is fulfilled, the internal/external fault discrimina-
tor compares the relative phase angle between the negative sequence current contributions from
the W1 and W2 sides of the power transformer using the following two rules:
If the negative sequence currents contributions from W1 and W2 sides are in
phase, the fault is internal (i.e. both phasors are within internal fault region)
en05000188.vsd
NegSeqROA
(Relay
Operate
Angle)
0 deg 180 deg
90 deg
270 deg
120 deg
IMinNegSeq
If one or the
other of
currents is too
low, then no
measurement
is done, and
120 degrees
is mapped
External
fault
region
Internal
fault
region
Internal/external
fault boundary
100
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
If the negative sequence currents contributions from W1 and W2 sides are 180
degrees out of phase, the fault is external (i.e. W1 phasors is outside internal fault
region)
For example, for any unsymmetrical external fault, the respective negative sequence current
contributions from the W1 and W2 power transformer sides will be exactly 180 degrees apart
and equal in magnitude, regardless the power transformer turns ratio and phase displacement.
One such example is shown in figure44, which shows trajectories of the two separate phasors
representing the negative-sequence current contributions from HV and LV sides of an Yd5 pow-
er transformer (e.g. after the compensation of the transformer turns ratio and phase displacement
by using equation4) for an unsymmetrical external fault. Observe that the relative phase angle
between these two phasors is 180 electrical degrees at any point in time. There is not any current
transformer saturation for this case.
Figure 44: Trajectories of Negative Sequence Current Contributions from HV and LV sides
of Yd5 power transformer during external fault
Therefore, under all external fault condition, the relative angle is theoretically equal to 180 de-
grees. During internal fault, the angle shall ideally be 0 degrees, but due to possible different
negative sequence source impedance angles on W1 and W2 sides of the protected power trans-
en05000189.vsd
0.1 kA
30
210
60
240
90
270
150
330
180 0
0.2 kA
0.3 kA
0.4 kA
"steady state"
for HV side
neg. seq. phasor
10
ms
10
ms
"steady state"
for LV side
neg. seq. phasor
Contribution to neg. seq. differential current from HV side
Contribution to neg. seq. differential current from LV side
101
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
former, it may differ somewhat from the ideal zero value. However, during heavy faults, CT sat-
uration might cause the measured phase angle to differ from 180 degrees for external, and from
about 0 degrees for internal fault. See figure45 for an example of a heavy internal fault with
transient CT saturation.
Figure 45: Operation of the internal/external fault discriminator for internal fault with CT
saturation
However it shall be noted that additional security measures are implemented in the internal/ex-
ternal fault discriminator algorithm in order to guaranty proper operation with heavily saturated
current transformers. The trustworthy information on whether a fault is internal or external is
typically obtained in about ten milliseconds after the fault inception, depending on the setting
IminNegSeq, and the magnitudes of the fault currents. At heavy faults, approximately five mil-
liseconds time-to-saturation of the main CT is sufficient in order to produce a correct discrimi-
nation between internal and external faults.
Unrestrained-, and sensitive negative-sequence protections
Two sub-functions, which are based on the internal / external fault discriminator with the ability
to trip a faulty power transformer, are complimentary parts to the traditional power transformer
differential protection.
en05000190.vsd
0.5 kA
30
210
60
240
90
270
120
300
150
330
180 0
HV side contribution to the total negative sequence differential current in kA
Directional limit (within the region delimited by 60 degrees is internal fault)
1.0 kA
1.5 kA
definitely
an internal
fault
Internal fault
declared 7 ms
after internal
fault occured
trip command
in 12 ms
excursion
from 0 degrees
due to CT
saturation
external
fault
region
35 ms
Directional Comparison Criterion: Internal fault as seen from the HV side
102
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
The unrestrained negative sequence differential protection
If one or more start signals have been set by the traditional differential protection algorithm, be-
cause one or more of the fundamental frequency differential currents entered the operate region
on the operate - restrain characteristic then the unrestrained negative sequence protection is ac-
tivated.
If the same fault has been positively recognized as internal, then the unrestrained negative se-
quence differential protection places its own trip request. Any block signals by the harmonic and
/ or waveform criteria, which can block the traditional differential protection are overridden, and
the differential protection operates quickly without any further delay. This logic guarantees a
fast disconnection of a faulty power transformer for any heavier internal faults.
If the same fault has been classified as external, then generally, but not unconditionally, a trip
command is prevented. If a fault is classified as external, the further analysis of the fault condi-
tions is initiated. If all the instantaneous differential currents in phases where start signals have
been issued are free of harmonic pollution, then a (minor) internal fault, simultaneous with a pre-
dominant external fault can be suspected. This conclusion can be drawn because at external
faults, major false differential currents can only exist when one or more current transformers sat-
urate. In this case, the false instantaneous differential currents are polluted by higher harmonic
components, the 2
nd
, the 5
th
, etc.
Sensitive negative-sequence based turn-to-turn fault protection
The sensitive, negative-sequence-current-based turn-to-turn fault protection detects the low-lev-
el faults, which are not detected by the traditional differential protection. The sensitive protec-
tion is independent from the traditional differential protection and is a very good complement to
it. The essential part of this sensitive protection is the internal/external fault discriminator pre-
viously described. In order to be activated, the sensitive protection requires no start signal from
the traditional power transformer biased differential protection. If magnitudes of HV and LV
negative sequence current contributions are above the set limit for IminNegSeq, then their rela-
tive positions are determined. If the disturbance is characterized as an internal fault, then a sep-
arate trip request will be placed. Any decision on the way to the final trip request must be
confirmed several times in succession in order to cope with eventual CT transients. This causes
a short additional operating time delay due to this security count. For very low-level turn-to-turn
faults the overall response time of this protection is about thirty milliseconds.
Instantaneous differential currents
The instantaneous differential currents are calculated in order to perform the harmonic analysis
and waveform analysis upon each one of them (see section "Harmonic-, and waveform block
criteria" for more information). The instantaneous differential currents are calculated using the
same matrix expression as shown in equation1 and equation2. The same matrixes A, B and C
are used for these calculations as well. The only difference is that the matrix algorithm is fed by
instantaneous values of currents, i.e. samples.
Harmonic-, and waveform block criteria
The two block criteria are the harmonic restrain and the waveform restrain. These two criteria
have the power to block (i.e. prevent) a trip command by the traditional differential protection,
which produces start signals by applying the differential currents, and the bias current, to the op-
erate - restrain characteristic.
103
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Harmonic restrain
The harmonic restrain is the classical restrain method traditionally used with power transformer
differential protections. The goal is to prevent an unwanted trip command due to magnetizing
inrush currents at switching operations, or due to magnetizing currents at over-voltages.
The magnetizing currents of a power transformer flow only on one side of the power transformer
(one or the other) and are therefore always the cause of false differential currents. The harmonic
analysis (the 2
nd
and the 5
th
harmonic) is applied to instantaneous differential currents. Typically
instantaneous differential currents during power transformer energizing are shown in figure46.
The harmonic analysis is only applied in those phases, where start signals have been set. For ex-
ample, if the content of the 2
nd
harmonic in the instantaneous differential current of phase L1 is
above the setting I2/I1Ratio, then a block signal is set for that phase, which can be read as
BLK2HL1 output of the differential protection.
Waveform restrain
The waveform restrain criterion is a good complement to the harmonic analysis. The waveform
restrain is a pattern recognition algorithm, which looks for intervals within each fundamental
power system cycle with low instantaneous differential current. However, within this function
this criterion actually searches for long-lasting intervals with low rate-of-change in instanta-
neous differential current, which are typical for the power transformer inrush currents. Block
signals BLKWAVLx are set in those phases where such behavior is detected. The algorithm do
not requires any end-user settings. The waveform algorithm is automatically adapted dependent
only on the power transformer rated data.
Figure 46: Inrush currents to a transformer as seen by a protective IED. Typical is a high
amount of the 2
nd
harmonic, and intervals of low current-, and low rate-of-change
of current within each period.
Cross-blocking between phases
Basic definition of the cross-blocking is that one of the three phases can block operation (i.e.
tripping) of the other two phases due to the properties of the differential current in that phase
(i.e. waveform, 2
nd
or 5
th
harmonic content). In differential algorithm the user can control the
cross-blocking between the phases via the setting parameter OpCrossBlock=On.
104
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
When parameter OpCrossBlock=On cross blocking between phases will be introduced. There is
not any time settings involved, but the phase with the operating point above the set bias charac-
teristic (i.e. in the operate region) will be able to cross-block other two phases if it is self-blocked
by any of the previously explained restrained criteria. As soon as the operating point for this
phase is below the set bias characteristic (i.e. in the restrain region) cross blocking from that
phase will be inhibited. In this way cross-blocking of the temporary nature is achieved. In should
be noted that this is the default (i.e. recommended) setting value for this parameter.
When parameter OpCrossBlock=Off, any cross blocking between phases will be disabled. It is
recommended to use the value Off with caution in order to avoid the unwanted tripping during
initial energizing of the power transformer.
1.2.2 Logic diagram
The simplified internal logics, for transformer differential protection are shown in the following
figures.
Figure 47: Treatment of measured currents within IED for transformer differential function
ADM
A
/
D

c
o
n
v
e
r
s
i
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n

s
c
a
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C
T

r
a
t
i
o
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/
D

c
o
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v
e
r
s
i
o
n

s
c
a
l
i
n
g

w
i
t
h
C
T

r
a
t
i
o
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h
a
s
o
r

c
a
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c
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a
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i
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o
f
i
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d
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p
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a
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e

c
u
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r
e
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a
s
o
r

c
a
l
c
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a
t
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o
n

o
f
i
n
d
i
v
i
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u
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l

p
h
a
s
e

c
u
r
r
e
n
t
Differential function
RET670
D
e
r
i
v
e

e
q
u
a
t
i
o
n

t
o

c
a
l
c
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d
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f
f
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c
u
r
r
e
n
t
s
Trafo
Data
P
h
a
s
o
r
s

&
s
a
m
p
l
e
s
P
h
a
s
o
r
s

&
s
a
m
p
l
e
s
Instantaneous (sample based)
Differential current, phase L1
Instantaneous (sample based)
Differential current, phase L2
Instantaneous (sample based)
Differential current, phase L3
Fundamental frequency (phasor
based) Diff current, phase L1 &
phase current contributions from
individual windings
Fundamental frequency (phasor
based) Diff current, phase L2 &
phase current contributions from
individual windings
Fundamental frequency (phasor
based) Diff current, phase L3 &
phase current contributions from
individual windings
Negative sequence diff current
& NS current contribution from
individual windings
en05000166.vsd
MAX
Settings for Zer. Seq.
Current Reduction
IDL1MAG
IDL2MAG
IDL3MAG
IDNSMAG
IDL2
IDL1
IDL3
IBIAS
105
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Figure47 shows how internal treatment of measured currents is done in case of two winding
transformer.
The following currents are inputs to the power transformer differential protection function. They
must all be expressed in true power system (primary) Amperes, i.e. as measured.
1. Instantaneous values of currents (samples) from HV, and LV sides for two-wind-
ing power transformers, and from the HV, the first LV, and the second LV sides
for three-winding power transformers.
2. Currents from all power transformer sides expressed as fundamental frequency
phasors, with their real, and imaginary parts. These currents are calculated within
the protection terminal by the fundamental frequency Fourier filters.
3. Negative-sequence currents from all power transformer sides expressed as pha-
sors. These currents are calculated within the protection terminal by the symmet-
rical components module.
The power transformer differential protection:
1. Calculates three fundamental frequency differential currents, and one common
bias current. The zero-sequence component can optionally be eliminated from
each of the three fundamental frequency differential currents, and at the same
time from the common bias current.
2. Calculates three instantaneous differential currents. They are used for harmonic,
and waveform analysis. Instantaneous differential currents are useful for
post-fault analysis using disturbance recording
3. Calculates negative-sequence differential current. Contributions to it from both
(all three) power transformer sides are used by the internal/external fault discrim-
inator to detect and classify a fault as internal or external.
106
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Figure 48: Transformer differential protection simplified logic diagram for Phase L1.
IdUnre
IDL1MAG
2nd
Harmonic
5th
Harmonic
Wave
block
IDL1
AND
Cross Block
from L2 or L3
OpCrossBlock=On
OR 1
IBIAS
TRIPUNREL1
STL1
TRIPRESL1
BLK2HL1
BLK5HL1
BLKWAVL1
en05000168.vsd
a
b
b>a
OR
AND
Cross Block
to L2 or L3
AND
AND
AND
BLKUNRES
BLOCK
BLKRES
107
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Figure 49: Transformer differential protection simplified logic diagram for external/internal
fault discriminator
Figure 50: Transformer differential protection internal grouping of tripping signals.
Internal/
External
Fault
discrimin
ator
t
STL1
STL2
STL3
OR
AND
EXTFAULT
INTFAULT
TRNSSENS
TRNSUNR
en05000167.vsd
Constant
IBIAS
a
b
b>a
Neg.Seq. Diff
Current
Contributions
OpNegSeqDiff=On
AND
BLKNSSEN
BLKNSUNR
BLOCK
en05000278.vsd
TRIPRESL1
TRIPRESL2
TRIPRESL3
OR
TRIPRES
TRIPUNREL1
TRIPUNREL2
TRIPUNREL3
OR
TRIPUNRE
OR
TRIP
TRNSUNR
TRNSSENS
108
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Figure 51: Transformer differential protection internal grouping of logical signals.
Logic in figures48, 49, 50 and 51 can be summarized as follows:
1. The three fundamental frequency differential currents are applied in a phase-wise
manner to two limits. The first limit is the operate - restrain characteristic, while
the other is the high-set unrestrained limit. If the first limit is exceeded, a start sig-
nal START is set. If the unrestrained limit is exceeded, an immediate unre-
strained trip TRIPUNRE and common trip TRIP are issued.
2. If a start signal is issued in a phase, then the harmonic-, and the waveform block
signals are checked. Only a start signal, which is free of all of its respective block
signals, can result in a trip command. If the cross-block logic scheme is applied,
then only if all phases with set start signal are free of their respective block sig-
nals, a restrained trip TRIPRES and common trip TRIP are issued
3. If a start signal is issued in a phase, and the fault has been classified as internal,
then any eventual block signals (as described above in 2) are overridden and a
unrestrained negative-sequence trip TRNSUNR and common trip TRIP are is-
sued without any further delay. This feature is called the unrestrained nega-
tive-sequence protection.
4. The sensitive negative sequence differential protection is independent of any start
signals. It is meant to detect smaller internal faults, such as turn-to-turn faults,
which are often not detected by the traditional differential protection. The sensi-
tive negative sequence differential protection starts whenever both contributions
to the total negative sequence differential current (that must be compared by the
internal/external fault discriminator) are higher than the value of the setting IMi-
nNegSeq. If a fault is positively recognized as internal, and the condition is stable
with no interruption for at least one fundamental frequency cycle the sensitive
negative sequence differential protection TRNSSENS and common trip TRIP are
issued. This feature is called the sensitive negative sequence differential protec-
tion.
en05000279.vsd
STL1
STL2
STL3
OR
START
BLK2HL1
BLK2HL2
BLK2HL3
OR
BLK2H
BLKWAVL1
BLKWAVL2
BLKWAVL3
OR
BLKWAV
BLK5HL1
BLK5HL2
BLK5HL3
OR
BLK5H
109
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
5. If a start signal is issued in a phase, but the fault has been classified as external,
then the instantaneous differential current of that phase is analyzed for the 2
nd

and the 5
th
harmonic contents. If there is less harmonic pollution, than allowed
by the settings I2/I1Ratio, and I5/I1Ratio, then it is assumed that a minor simul-
taneous internal fault must have occurred. Only under these conditions a trip
command is allowed. The cross-block logic scheme is automatically applied un-
der such circumstances.
6. All start and blocking conditions are available as phase segregated as well as
common (i.e. three-phase) signals.
1.3 Function block
Figure 52: T2D function block
T2WPDIF
T2D1-
I3PW1CT1
I3PW1CT2
I3PW2CT1
I3PW2CT2
BLOCK
BLKRES
BLKUNRES
BLKNSUNR
BLKNSSEN
TRIP
TRIPRES
TRIPUNRE
TRNSUNR
TRNSSENS
START
STL1
STL2
STL3
BLK2H
BLK2HL1
BLK2HL2
BLK2HL3
BLK5H
BLK5HL1
BLK5HL2
BLK5HL3
BLKWAV
BLKWAVL1
BLKWAVL2
BLKWAVL3
ID2HL1
ID2HL2
ID2HL3
ID5HL1
ID5HL2
ID5HL3
IDL1
IDL2
IDL3
IDNSMAG
IDL1MAG
IDL2MAG
IDL3MAG
IBIAS
en05000677.vsd
110
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Figure 53: T3D function block
1.4 Input and output signals
Table 56: Input signals for the T2WPDIF_87T (T2D1-) function block
T3WPDIF
T3D1-
I3PW1CT1
I3PW1CT2
I3PW2CT1
I3PW2CT2
I3PW3CT1
I3PW3CT2
BLOCK
BLKRES
BLKUNRES
BLKNSUNR
BLKNSSEN
TRIP
TRIPRES
TRIPUNRE
TRNSUNR
TRNSSENS
START
STL1
STL2
STL3
BLK2H
BLK2HL1
BLK2HL2
BLK2HL3
BLK5H
BLK5HL1
BLK5HL2
BLK5HL3
BLKWAV
BLKWAVL1
BLKWAVL2
BLKWAVL3
ID2HL1
ID2HL2
ID2HL3
ID5HL1
ID5HL2
ID5HL3
IDL1
IDL2
IDL3
IDNSMAG
IDL1MAG
IDL2MAG
IDL3MAG
IBIAS
en05000676.vsd
Signal Description
I3PW1CT1 Group parameter for abstract block 2
I3PW1CT2 Group parameter 2 for abstract block 2
I3PW2CT1 Group parameter 3 for abstract block 2
I3PW2CT2 Group parameter 4 for abstract block 2
111
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Table 57: Output signals for the T2WPDIF_87T (T2D1-) function block
BLOCK Block of function
BLKRES Block of trip for restrained differential feature
BLKUNRES Block of trip for unrestrained differential feature
BLKNSUNR Block of trip for unrestr. neg. seq. differential feature
BLKNSSEN Block of trip for sensitive neg. seq. differential feature
Signal Description
TRIP General, common trip signal
TRIPRES Trip signal from restrained differential protection
TRIPUNRE Trip signal from unrestrained differential protection
TRNSUNR Trip signal from unrestr. neg. seq. diff. protection
TRNSSENS Trip signal from sensitive neg. seq. diff. protection
START Common start signal from any phase
STL1 Start signal from phase L1
STL2 Start signal from phase L2
STL3 Start signal from phase L3
BLK2H Common second harmonic block signal from any phase
BLK2HL1 Second harmonic block signal, phase L1
BLK2HL2 Second harmonic block signal, phase L2
BLK2HL3 Second harmonic block signal, phase L3
BLK5H Common fifth harmonic block signal from any phase
BLK5HL1 Fifth harmonic block signal, phase L1
BLK5HL2 Fifth harmonic block signal, phase L2
BLK5HL3 Fifth harmonic block signal, phase L3
BLKWAV Common block signal, waveform criterion, from any phase
BLKWAVL1 Block signal, waveform criterion, phase L1
BLKWAVL2 Block signal, waveform criterion, phase L2
BLKWAVL3 Block signal, waveform criterion, phase L3
ID2HL1 Magnitude of the 2nd harmonic differential current, phase L1
ID2HL2 Magnitude of the 2nd harmonic differential current, phase L2
ID2HL3 Magnitude of the 2nd harmonic differential current, phase L3
ID5HL1 Magnitude of the 5th harmonic differential current, phase L1
ID5HL2 Magnitude of the 5th harmonic differential current, phase L2
ID5HL3 Magnitude of the 5th harmonic differential current, phase L3
IDL1 Value of the instantaneous differential current, phase L1
IDL2 Value of the instantaneous differential current, phase L2
IDL3 Value of the instantaneous differential current, phase L3
Signal Description
112
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Table 58: Input signals for the T3WPDIF (T001-) function block
Table 59: Output signals for the T3WPDIF (T001-) function block
IDNSMAG Magnitude of the negative sequence differential current
IDL1MAG Magnitude of fundamental freq. diff. current, phase L1
IDL2MAG Magnitude of fundamental freq. diff. current, phase L2
IDL3MAG Magnitude of fundamental freq. diff. current, phase L3
IBIAS Magnitude of the bias current, which is common to all phases
Signal Description
I3PW1CT1 Group signal for current input primary side channel 1
I3PW1CT1 Group parameter for abstract block 2
I3PW1CT2 Group signal for current input primary side channel 2
I3PW1CT2 Group parameter 2 for abstract block 2
I3PW2CT1 Group signal for current input secondary side channel 1
I3PW2CT1 Group parameter 3 for abstract block 2
I3PW2CT2 Group signal for current input secondary side channel 2
I3PW2CT2 Group parameter 4 for abstract block 2
I3PW3CT1 Group signal for current input secondary side channel 1
I3PW3CT2 Group signal for current input secondary side channel 2
BLOCK Block of function
BLKRES Block of trip for restrained differential feature
BLKUNRES Block of trip for unrestrained differential feature
BLKNSUNR Block of trip for unrestr. neg. seq. differential feature
BLKNSSEN Block of trip for sensitive neg. seq. differential feature
Signal Description
TRIP General, common trip signal
TRIPRES Trip signal from restrained differential protection
TRIPUNRE Trip signal from unrestrained differential protection
TRNSUNR Trip signal from unrestr. neg. seq. diff. protection
TRNSSENS Trip signal from sensitive neg. seq. diff. protection
START Common start signal from any phase
STL1 Start signal from phase L1
STL2 Start signal from phase L2
STL3 Start signal from phase L3
BLK2H Common second harmonic block signal from any phase
BLK2HL1 Second harmonic block signal, phase L1
Signal Description
113
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
BLK2HL2 Second harmonic block signal, phase L2
BLK2HL3 Second harmonic block signal, phase L3
BLK5H Common fifth harmonic block signal from any phase
BLK5HL1 Fifth harmonic block signal, phase L1
BLK5HL2 Fifth harmonic block signal, phase L2
BLK5HL3 Fifth harmonic block signal, phase L3
BLKWAV Common block signal, waveform criterion, from any phase
BLKWAVL1 Block signal, waveform criterion, phase L1
BLKWAVL2 Block signal, waveform criterion, phase L2
BLKWAVL3 Block signal, waveform criterion, phase L3
ID2HL1 Magnitude of the 2nd harmonic differential current, phase L1
ID2HL2 Magnitude of the 2nd harmonic differential current, phase L2
ID2HL3 Magnitude of the 2nd harmonic differential current, phase L3
ID5HL1 Magnitude of the 5th harmonic differential current, phase L1
ID5HL2 Magnitude of the 5th harmonic differential current, phase L2
ID5HL3 Magnitude of the 5th harmonic differential current, phase L3
IDL1 Value of the instantaneous differential current, phase L1
IDL2 Value of the instantaneous differential current, phase L2
IDL3 Value of the instantaneous differential current, phase L3
IDNSMAG Magnitude of the negative sequence differential current
IDL1MAG Magnitude of fundamental freq. diff. current, phase L1
IDL2MAG Magnitude of fundamental freq. diff. current, phase L2
IDL3MAG Magnitude of fundamental freq. diff. current, phase L3
IBIAS Magnitude of the bias current, which is common to all phases
Signal Description
114
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
1.5 Setting parameters
Table 60: General settings for the T2WPDIF_87T (T2D1-) function
Parameter Range Step Default Unit Description
RatedVoltageW1 0.05 - 2000.00 0.05 400.00 kV Rated voltage of trans-
former winding 1 (HV
winding) in kV
RatedVoltageW2 0.05 - 2000.00 0.05 231.00 kV Rated voltage of trans-
former winding 2 in kV
RatedCurrentW1 1 - 99999 1 577 A Rated current of trans-
former winding 1 (HV
winding) in A
RatedCurrentW2 1 - 99999 1 1000 A Rated current of trans-
former winding 2 in A
ConnectTypeW1 WYE (Y)
Delta (D)
- WYE (Y) - Connection type of wind-
ing 1: Y-wye (1) or
D-delta (2)
ConnectTypeW2 wye =y
Delta =d
- wye =y - Connection type of wind-
ing 2: y-wye (1) or
d-delta (2)
ClockNumberW2 0 [0 deg]
1 [30 deg lag]
2 [60 deg lag]
3 [90 deg lag]
4 [120 deg lag]
5 [150 deg lag]
6 [180 deg]
7 [150 deg lead]
8 [120 deg lead]
9 [90 deg lead]
10 [60 deg lead]
11 [30 deg lead]
- 0 [0 deg] - Phase displacement
between W2 & W1=HV
winding, hour notation
ZSCurrSubtrW1 Off
On
- On - Enable zer. seq. current
subtraction for W1 side,
On / Off
ZSCurrSubtrW2 Off
On
- On - Enable zer. seq. current
subtraction for W2 side,
On / Off
TconfigForW1 No
Yes
- No - Two CT inputs (T-con-
fig.) for winding 1, YES /
NO
115
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Table 61: Parameter group settings for the T2WPDIF_87T (T2D1-) function
CT1RatingW1 1 - 99999 1 3000 A CT primary rating in A,
T-branch 1, on transf. W1
side
CT2RatingW1 1 - 99999 1 3000 A CT primary in A,
T-branch 2, on transf. W1
side
TconfigForW2 No
Yes
- No - Two CT inputs (T-con-
fig.) for winding 2, YES /
NO
CT1RatingW2 1 - 99999 1 3000 A CT primary rating in A,
T-branch 1, on transf. W2
side
CT2RatingW2 1 - 99999 1 3000 A CT primary rating in A,
T-branch 2, on transf. W2
side
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
IdMin 0.10 - 0.60 0.01 0.30 IB Section 1 sensitivity,mul-
tiple of Winding 1 rated
current
EndSection1 0.20 - 1.50 0.01 1.25 IB End of section 1, multi-
ple of Winding 1 rated
current
EndSection2 1.00 - 10.00 0.01 3.00 IB End of section 2, multi-
ple of Winding 1 rated
current
SlopeSection2 10.0 - 50.0 0.1 40.0 % Slope in section 2 of
operate-restrain charac-
teristic, in %
SlopeSection3 30.0 - 100.0 0.1 80.0 % Slope in section 3 of
operate-restrain charac-
teristic, in %
IdUnre 1.00 - 50.00 0.01 10.00 IB Unrestr. prot. limit, multi-
ple of Winding 1 rated
current
I2/I1Ratio 5.0 - 100.0 1.0 15.0 % Max. ratio of 2nd harm. to
fundamental harm dif.
curr. in %
Parameter Range Step Default Unit Description
116
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Table 62: General settings for the T3WPDIF (T001-) function
I5/I1Ratio 5.0 - 100.0 1.0 25.0 % Max. ratio of 5th harm. to
fundamental harm dif.
curr. in %
OpCrossBlock Off
On
- On - Operation On / Off for
cross-block logic
between phases
OpNegSeqDiff Off
On
- On - Operation On / Off for
neg. seq. differential pro-
tections
IMinNegSeq 0.02 - 0.20 0.01 0.04 IB Neg. seq. curr. must be
higher than this level to
be used
NegSeqROA 30.0 - 120.0 0.1 60.0 Deg Operate Angle for int. /
ext. neg. seq. fault dis-
criminator
Parameter Range Step Default Unit Description
RatedVoltageW1 0.05 - 2000.00 0.05 400.00 kV Rated voltage of trans-
former winding 1 (HV
winding) in kV
RatedVoltageW2 0.05 - 2000.00 0.05 231.00 kV Rated voltage of trans-
former winding 2 in kV
RatedVoltageW3 0.05 - 2000.00 0.05 10.50 kV Rated voltage of trans-
former winding 3 in kV
RatedCurrentW1 1 - 99999 1 577 A Rated current of trans-
former winding 1 (HV
winding) in A
RatedCurrentW2 1 - 99999 1 1000 A Rated current of trans-
former winding 2 in A
RatedCurrentW3 1 - 99999 1 7173 A Rated current of trans-
former winding 3 in A
ConnectTypeW1 WYE (Y)
Delta (D)
- WYE (Y) - Connection type of wind-
ing 1: Y-wye (1) or
D-delta (2)
ConnectTypeW2 wye =y
Delta =d
- wye =y - Connection type of wind-
ing 2: y-wye (1) or
d-delta (2)
ConnectTypeW3 wye =y
Delta =d
- Delta =d - Connection type of wind-
ing 3: y-wye (1) or d-delta
(2)
Parameter Range Step Default Unit Description
117
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
ClockNumberW2 0 [0 deg]
1 [30 deg lag]
2 [60 deg lag]
3 [90 deg lag]
4 [120 deg lag]
5 [150 deg lag]
6 [180 deg]
7 [150 deg lead]
8 [120 deg lead]
9 [90 deg lead]
10 [60 deg lead]
11 [30 deg lead]
- 0 [0 deg] - Phase displacement
between W2 & W1=HV
winding, hour notation
ClockNumberW3 0 [0 deg]
1 [30 deg lag]
2 [60 deg lag]
3 [90 deg lag]
4 [120 deg lag]
5 [150 deg lag]
6 [180 deg]
7 [150 deg lead]
8 [120 deg lead]
9 [90 deg lead]
10 [60 deg lead]
11 [30 deg lead]
- 5 [150 deg lag] - Phase displacement
between W3 & W1=HV
winding, hour notation
ZSCurrSubtrW1 Off
On
- On - Enable zer. seq. current
subtraction for W1 side,
On / Off
ZSCurrSubtrW2 Off
On
- On - Enable zer. seq. current
subtraction for W2 side,
On / Off
ZSCurrSubtrW3 Off
On
- On - Enable zer. seq. current
subtraction for W3 side,
On / Off
TconfigForW1 No
Yes
- No - Two CT inputs (T-con-
fig.) for winding 1, YES /
NO
CT1RatingW1 1 - 99999 1 3000 A CT primary rating in A,
T-branch 1, on transf. W1
side
CT2RatingW1 1 - 99999 1 3000 A CT primary in A,
T-branch 2, on transf. W1
side
TconfigForW2 No
Yes
- No - Two CT inputs (T-con-
fig.) for winding 2, YES /
NO
Parameter Range Step Default Unit Description
118
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
Table 63: Parameter group settings for the T3WPDIF (T001-) function
CT1RatingW2 1 - 99999 1 3000 A CT primary rating in A,
T-branch 1, on transf. W2
side
CT2RatingW2 1 - 99999 1 3000 A CT primary rating in A,
T-branch 2, on transf. W2
side
TconfigForW3 No
Yes
- No - Two CT inputs (T-con-
fig.) for winding 3, YES /
NO
CT1RatingW3 1 - 99999 1 3000 A CT primary rating in A,
T-branch 1, on transf. W3
side
CT2RatingW3 1 - 99999 1 3000 A CT primary rating in A,
T-branch 2, on transf. W3
side
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
IdMin 0.10 - 0.60 0.01 0.30 IB Section 1 sensitivity,mul-
tiple of Winding 1 rated
current
EndSection1 0.20 - 1.50 0.01 1.25 IB End of section 1, multi-
ple of Winding 1 rated
current
EndSection2 1.00 - 10.00 0.01 3.00 IB End of section 2, multi-
ple of Winding 1 rated
current
SlopeSection2 10.0 - 50.0 0.1 40.0 % Slope in section 2 of
operate-restrain charac-
teristic, in %
SlopeSection3 30.0 - 100.0 0.1 80.0 % Slope in section 3 of
operate-restrain charac-
teristic, in %
IdUnre 1.00 - 50.00 0.01 10.00 IB Unrestr. prot. limit, multi-
ple of Winding 1 rated
current
I2/I1Ratio 5.0 - 100.0 1.0 15.0 % Max. ratio of 2nd harm. to
fundamental harm dif.
curr. in %
Parameter Range Step Default Unit Description
119
Transformer differential protection (PDIF, 87T) Chapter 4
Differential protection
1.6 Technical data
Table 64: Transformer differential protection (PDIF, 87T)
I5/I1Ratio 5.0 - 100.0 1.0 25.0 % Max. ratio of 5th harm. to
fundamental harm dif.
curr. in %
OpCrossBlock Off
On
- On - Operation On / Off for
cross-block logic
between phases
OpNegSeqDiff Off
On
- On - Operation On / Off for
neg. seq. differential pro-
tections
IMinNegSeq 0.02 - 0.20 0.01 0.04 IB Neg. seq. curr. must be
higher than this level to
be used
NegSeqROA 30.0 - 120.0 0.1 60.0 Deg Operate Angle for int. /
ext. neg. seq. fault dis-
criminator
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Operating characteristic Adaptable 2.0% of I
r
for I <I
r
2.0% of I for I >I
r
Reset ratio >95% -
Unrestrained differential current limit (100-5000)% of I
base
on
high voltage winding
2.0% of set value
Base sensitivity function (10-60)% of I
base
2.0% of I
r
Second harmonic blocking (5.0-100.0)% of funda-
mental
2.0% of I
r
Fifth harmonic blocking (5.0-100.0)% of funda-
mental
5.0% of I
r
Connection type for each of the windings Y-wye or D-delta -
Phase displacement between high voltage
winding, W1 and each of the windings, w2
and w3. Hour notation
011 -
Operate time, restrained function 25 ms typically at
0 to 2 x I
d
-
Reset time, restrained function 20 ms typically at
2 to 0 x I
d
-
Operate time, unrestrained function 12 ms typically at
0 to 5 x I
d
-
Reset time, unrestrained function 25 ms typically at
5 to 0 x I
d
-
Critical impulse time 2 ms typically at
0 to 5 x I
d
-
120
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
2 Restricted earth fault protection (PDIF, 87N)
2.1 Introduction
Three low impedance restricted earth fault functions can be included in RET670. The function
can be used on all directly or low impedance earthed windings. The restricted earth fault function
can provide higher sensitivity (down to 5%) and higher speed as it measures individually on each
winding and thus do not need harmonics stabilization.
The low impedance function is a percentage biased function with an additional zero sequence
current directional comparison criteria. This gives excellent stability for through faults. The
function allows use of different CT ratios and magnetizing characteristics on the phase and neu-
tral CT cores and mixing with other functions and protection IED's on the same cores.
Figure 54: Autotransformer low-impedance REF
2.2 Principle of operation
2.2.1 Fundamental principles of the restricted earth fault protection (REF)
The REF protection should detect earth faults on earthed power transformer windings. The REF
protection is a unit protection of differential type. Because this protection is based on the zero
sequence currents, which theoretically only exist in case of an earth fault, the REF can be made
very sensitive; regardless of normal load currents. It is the fastest protection a power transformer
winding can have. It must be borne in mind, however, that the high sensitivity, and the high
speed, tend to make such a protection instable, and special measures must be taken to make it
insensitive to conditions, for which it should not operate, for example heavy through faults of
phase-to-phase type, or heavy external earth faults.
The REF protection is of low impedance type. At least three-phase power transformer termi-
nal currents, and the power transformer neutral point current, must be fed separately to RET670.
These input currents are then conditioned within RET670 by mathematical tools. Fundamental
Function block name: REFx- IEC 60617 graphical symbol:
ANSI number: 87N
IEC 61850 logical node name:
REFPDIF
IdN/I
xx05000058.vsd
121
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
frequency components of all currents are extracted from all input currents, while other eventual
zero sequence components (e.g. the 3rd harmonic currents) are fully suppressed. Then the resid-
ual current phasor is constructed from the three line current phasors. This zero sequence current
phasor is then vectorially added to the neutral current, in order to obtain differential current.
The following facts may be observed from the figure55 and the figure56 (where the three-phase
line CTs are lumped into a single 3Io current, for the sake of simplicity).
Figure 55: Currents at an external earth fault.
A (L1)
B (L2)
Ia = 0 Ia = 0
Ib = 0 Ib = 0
Ic = 0 Ic = 0
Uzs Uzs
3Io=3Izs1
Cur rent i n t he neut r al (I
N
)
serves as a di r ect i onal
t he same di rect i on f or bot h
i nt ernal and ext ernal f aul t s.
ref er ence because i t has
REF i s a cur rent pol ar i zed r el ay
RCA (Rel ay Charact er i st i c Angl e)
RCA = 0 deg.
REF i s permanent l y set t o operat e
f or i nt ernal ear t h f aul t s.
REF shoul d never oper at e f or any
f aul t s ext ernal t o t he pr ot ect ed zone.
180
o
out of phase f or any ext ernal
ear t h f aul t .
REF i s a cur rent pol ar i zed r el ay
RCA (Rel ay Charact er i st i c Angl e)
Current s 3Io and I
N
are t heoret i cal l y
zone of pr ot ect i on
I
N
= -3Izs1 -3I
zs vol t age i s max.
at t he eart h f aul t
zs vol t age i s max.
at t he eart h f aul t
C (L3)
a (L1)
b (L2)
c (L3)
s
o
u
r
c
e
s
o
u
r
c
e
I
N
en05000724.vsd
Izs1
Izs1
Izs1
ROA
MTA
For ext er nal f aul t
Rest rai n f or
ext er nal f aul t
Ref erence i s
neut ral curr ent
ROA
I
N
Oper at e f or
i nt er nal f aul t
3I
0
122
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
Figure 56: Currents at an internal earth fault.
1. For an external earth fault, (figure55) the residual current 3Io and the neutral
conductor current I
N
have equal magnitude, but they are 180 degree out of phase
due to internal CT reference directions used in IED670. This is easy to under-
stand, as both CTs ideally measure exactly the same component of the earth fault
current.
2. For an internal fault, the total earth fault current is composed generally of two ze-
ro-sequence components. One zero-sequence component (i.e. 3I
ZS1
) flows to-
wards the power transformer neutral point and into the earth, while the other
zero-sequence component (i.e. 3I
ZS2
) flows out into the connected power system.
These two primary currents can be expected to be of approximately opposite di-
rections (about the same zero sequence impedance angle is assumed on both
sides of the earth fault).However on the secondary CT sides they will be approx-
imately in phase due to internal CT reference directions used in IED670. The
magnitudes of the two components may be different, dependent on the magni-
tudes of zero sequence impedances of both sides. No current can flow towards
the power system, if the only point where the system is earthed, is at the protected
power transformer. Likewise, no current can flow into the power system, if the
winding is not connected to the power system (circuit breaker open and power
transformer energized from the other side).
3. For both internal and external earth faults, the current in the neutral connection
I
N
has always the same direction, that is, towards the earth.
4. The two measured zero sequence current are 3Io and I
N
. The vectorial sum be-
tween them is the REF differential current, which is equal to Idiff =I
N
+3Io.
currents 3Io and I
N
are approximatel y
in phase for an internal earth fault.
A (L1)
B (L2)
C (L3)
a (L1)
b (L2)
c (L2)
Ia = 0 Ia = 0
Ib = 0 Ib = 0
Ic = 0 Ic = 0
Uzs
3Io = -3Izs2
serves as a directi onal
reference because it has
the same direction for both
i nternal and external faul ts.
Current i n the neutral (I
N
)
serves as a directi onal
reference because it has
the same direction for both
i nternal and external faul ts.
zone of protecti on
I
N
= - 3Izs1
Ifault
power system
contributi on to
faul t current
power system
contributi on to
faul t current
s
o
u
r
c
e
s
o
u
r
c
e
Return path for 3Izs2 Return path for 3Izs1
I
N
en05000725.vsd
Izs2
Izs2
Izs2 Izs1
Izs1
Izs1
ROA
MTA
For internal faul t
Restrain for
external faul t
Reference i s
neutral current
ROA
I
N
Operate for
internal fault
3I
0
123
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
Because REF is a differential protection where the line zero sequence (residual) current is con-
structed from 3 line (terminal) currents, a bias quantity must give stability against false opera-
tions due to high through fault currents. An operate - bias characteristic (only one) has been
devised to the purpose.
It is not only external earth faults that REF should be stable against, but also heavy
phase-to-phase faults, not including earth. These faults may also give rise to false zero sequence
currents due to saturated line CTs. Such faults, however, produce no neutral current, and can
thus be eliminated as a source of danger, at least during the fault.
As an additional measure against unwanted operation, a directional check is made in agreement
with the above points 1, and 2. An operation is only allowed if currents 3Io and I
N
(see the
figure55 and the figure56) are both within operating region. By taking a smaller ROA, the REF
protection can be made more stable under heavy external fault conditions, as well as under the
complex conditions, when external faults are cleared by other protections.
2.2.2 REF as a differential protection
The REF protection is a protection of differential type, a unit protection, whose settings are in-
dependent of any other protection. Compared to the transformer differential protection it has
some advantages. It is simpler, as no current phase correction and magnitude correction are
needed, not even in the case of an eventual On-Load-Tap-Changer (OLTC). REF is not sensitive
to inrush and overexcitation currents. The only danger left is an eventual current transformer sat-
uration.
The REF has only one operate-bias characteristic, which is described in the table 65, and shown
in the figure57.
Table 65: Data of the operate - bias characterize of the REF.
As a differential protection, the REF calculates a differential current and a bias current. In case
of internal earth faults, the differential current is theoretically equal to the total earth fault cur-
rent. The bias current is supposed to give stability to REF protection. The bias current is a mea-
sure of how high the currents are, or better, a measure of how difficult the conditions are under
which the CTs operate. The higher the bias, the more difficult conditions can be suspected, and
the more likely that the calculated differential current has a component of a false current, prima-
rily due to CT saturation. This law is formulated by the operate-bias characteristic. This char-
acteristic divides the Idif - Ibias plane into two parts. The part above the operate - bias
characteristic is the so called operate area, while that below is the block area, see the figure57.
Default sensitivity
Idmin (zone 1)
Max. base
sensitivity
Idmin (zone 1)
Min. base
sensitivity
Idmin (zone 1)
End of
zone 1
First
slope
Second
slope
% Irated % Irated % Irated % Irated % %
30 4 100 125 70 100
124
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
Figure 57: Operate - bias characteristic of the restricted earth fault protection REF.
2.2.3 Calculation of differential current and bias current
The differential current, (=operate current), as a fundamental frequency phasor, is calculated as
(with designations as in the figure55 and the figure56)
(Equation 5)
If there are two three-phase CT inputs on the HV winding side for the REF protection (such as
in breaker-and-a-half configurations), then their respective residual currents are added within
REF function so that:
I3PW1 =I3PW1CT1 +I3PW1CT2
where these are defined in table 66
(98000017)
bias current in per unit
0 1 2 3 4 5 6
1
2
3
4
5
operate current in pu
default base sensitivity 30 %
operate
Base Sensitivity Idmin
*********************************************
Range : 5 % to 50 % rated current
Step : 1 % transformer rated current
minimum base sensitivity 50 %
maximum base sensitivity 5 %
block
zone 1 zone 2
1.25 pu
second slope
first slope
where:
I
N
current in the power transformer neutral as a fundamental frequency phasor,
3Io residual current of the power transformer line (terminal) currents as a phasor.
3 Idiff IN Io = +
125
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
The bias current is a measure (expressed as a current in Amperes) of how difficult the conditions
are under which the instrument current transformers operate. Dependent on the magnitude of the
bias current, the corresponding zone (section) of the operate - bias characteristic ia applied, when
deciding whether to trip, or not to trip. In general, the higher the bias current, the higher the
differential current required to produce a trip.
As the bias current the highest current of all separate input currents to REF protection, that is, of
current in phase L1, phase L2, phase L3, and the current in the neutral point (designated as IN
in the figure55 and in the figure56).
If there are 2 feeders included in the zone of protection of the REF protection, then the respective
bias current is found as the relatively highest of the following currents:
The bias current is thus generally equal to none of the input currents. If all primary ratings of the
CTs were equal to IBase, then the bias current would be equal to the highest current in Amperes.
IBase shall be set equal to the rated current of the protected winding where the REF function is
applied.
2.2.4 Detection of external earth faults
External faults are more common than internal earth faults for which the restricted earth fault
protection should operate. It is important that the restricted earth fault protection remains stable
during heavy external earth and phase-to-phase faults, and also when such a heavy external fault
is cleared by some other protection such as overcurrent, or earth fault protection, etc. The con-
ditions during a heavy external fault, and particularly immediately after the clearing of such a
fault may be complex. The circuit breakers poles may not open exactly at the same moment,
some of the CTs may still be highly saturated, etc.
The detection of external earth faults is based on the fact that for such a fault a high neutral cur-
rent appears first, while a false differential current only appears if and when one, or more, cur-
rent transformers saturate. An external earth fault is thus assumed to have occurred when a high
neutral current suddenly appears, while at the same time the differential current Idif remains low,
at least for a while. This condition must be detected before a trip request is placed within REF
protection. Any search for external fault is aborted if a trip request has been placed. A condition
for a successful detection is that it takes not less than 4 ms for the first CT to saturate.
1
current[1] =max (I3PW1CT1)
CTFactorPri1

1
current[2] =max (I3PW1CT2)
CTFactorPri2

1
current[3] =max (I3PW2CT1)
CTFactorSec1

1
current[4] =max (I3PW2CT2)
CTFactorSec2

current[5] =IN
126
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
For an internal earth fault, a true differential current develops immediately, while for an external
fault it only develops if a CT saturates. If a trip request comes first, before an external fault could
be positively established, then it must be an internal fault.
If an external earth fault has been detected, then the REF is temporarily desensitized.
Directional criterion
The directional criterion is applied in order to positively distinguish between internal- and ex-
ternal earth faults. This check is an additional criterion, which should prevent misoperations at
heavy external earth faults, and during the disconnection of such faults by other protections.
Earth faults on lines connecting the power transformer occur much more often than earth faults
on a power transformer winding. It is important therefore that the restricted earth fault protection
(REF) should remain secure during an external fault, and immediately after the fault has been
cleared by some other protection.
For an external earth fault with no CT saturation, the residual current in the lines (3Io in the
figure55) and the neutral current (I
N
in the figure55) are theoretically equal in magnitude and
are 180 degree out of phase. It is the current in the neutral (IN) which serves as a directional ref-
erence because it flows for all earth faults, and it has the same direction for all earth faults, both
external as well as internal. The directional criterion in REF protection makes REF a current-po-
larized relay.
If one or more CTs saturate, then the measured currents 3Io and IN may no more be equal, nor
will their positions in the complex plane be exactly 180 degree apart.There is a risk that the re-
sulting false differential current Idif enters the operate area when clearing the external fault. If
this happens, a directional test may prevent a misoperation.
A directional check is only executed if:
1. a trip request signal has been issued, (REF function START signal set to 1)
2. if the residual current in lines (3Io) is at least 3% of the IBase current.
If a directional check is either unreliable or not possible to do, due to too small currents, then the
direction is cancelled as a condition for an eventual trip.
If a directional check is executed, the REF protection operation is only allowed if currents 3Io
and I
N
(see the figure55and figure56) are both within the operating region.
RCA determines a direction MTA (Maximum Torque Angle) where the line residual current
3Io should lie for an internal earth fault, while ROA sets a tolerance margin.
2
nd
harmonic analysis
At energizing of a reactor a false differential current may appear in REF even though it does not
exist in the primary net. The phase CTs may saturate due to a high dc-component with long du-
ration where as the current through the neutral CT does not have either the same dc-component
or the same amplitude and the risk for saturation in this CT is much lesser. The appearing dif-
RCA =0 degrees =constant; where RCA stands for the Relay Characteristic Angle,
ROA =60 to 90 degrees; where ROA stands for the Relay Operate Angle.
127
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
ferential current as a result of the saturation may be so high that it reaches the operate character-
istic. A calculation of the content of 2
nd
harmonic in the neutral current is made when neutral
current, residual current and bias current are within some windows and some timing criteria are
fulfilled. If the ratio between second and fundamental harmonic exceeds 60%, the REF function
will be blocked.
2.2.5 Algorithm of the restricted earth fault protection (REF) in short
1. Check if current in the neutral Ineutral (IN) is less than 50% of the base sensitiv-
ity Idmin. If yes, only service values are calculated, then the REF protection al-
gorithm is exited.
2. If current in the Ineutral (IN) is more than 50% of Idmin, then determine the bias
current Ibias.
3. Determine the differential (operate) current Idif as a phasor, and calculate its
magnitude.
4. Check if the point P(Ibias, Idif) is above the operate - bias characteristic. If yes,
increment the trip request counter by 1. If the point P(Ibias, Idif) is found to be
below the operate - bias characteristic, then the trip request counter is reset to 0.
5. If the trip request counter is still 0, search for an eventual heavy external earth
fault. The search is only made if the neutral current is at least 50% of the IBase
current. If an external earth fault has been detected, a flag is set which remains
set until the external fault has been cleared. The external fault flag is reset to 0
when Ineutral falls below 50% of the base sensitivity Idmin. Any search for ex-
ternal fault is aborted if trip request counter is more than 0.
6. For as long as the external fault persists an additional temporary trip condition is
introduced. That means that the REF protection is temporarily desensitized.
7. If point P(Ibias, Idif) is found to be above the operate - bias characteristic), so that
trip request counter is becomes more than 0, a directional check can be made. The
directional check is made only if Iresidual (3Io) is more than 3% of the IBase cur-
rent. If the result of the check means external fault, then the internal trip request
is reset. If the directional check cannot be executed, then direction is no longer a
condition for a trip.
8. When neutral current, residual current and bias current are within some windows
and some timing criteria are fulfilled, the ratio of 2
nd
to fundamental tone is cal-
culated. If it is found to be above 60% the trip request counter is reset and TRIP
remains zero.
9. Finally, a check is made if the trip request counter is equal to, or higher than 2. If
it is, and at the same time, the bias current is at least 50% of the highest bias cur-
rent Ibiasmax (measured during the disturbance) then the REF function block
sets output TRIP to 1. If the counter is less than 2, TRIP signal remains 0.
128
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
2.3 Function block
Figure 58: REF function block
2.4 Input and output signals
Table 66: Input signals for the REFPDIF_87N (REF1-) function block
Table 67: Output signals for the REFPDIF_87N (REF1-) function block
REFPDIF
REF1-
I3P
I3PW1CT1
I3PW1CT2
I3PW2CT1
I3PW2CT2
BLOCK
TRIP
START
DIROK
BLK2H
IRES
IN
IBIAS
IDIFF
ANGLE
I2RATIO
en05000364.vsd
Signal Description
I3P Group signal for neutral current input
I3PW1CT1 Group signal for primary CT1 current input
I3PW1CT2 Group signal for primary CT2 current input
I3PW2CT1 Group signal for secondary CT1 current input
I3PW2CT2 Group signal for secondary CT2 current input
BLOCK Block of function
Signal Description
TRIP Trip by restricted earth fault protection function
START Start by restricted earth fault protection function
DIROK Directional Criteria has operated for internal fault
BLK2H Block due to 2-nd harmonic
IRES Magnitude of fund. freq. residual current
IN Magnitude of fund. freq. neutral current
IBIAS Magnitude of the bias current
IDIFF Magnitude of fund. freq. differential current
ANGLE Direction angle from zerosequence feature
I2RATIO Second harmonic ratio
129
Restricted earth fault protection (PDIF, 87N) Chapter 4
Differential protection
2.5 Setting parameters
Table 68: Parameter group settings for the REFPDIF_87N (REF1-) function
2.6 Technical data
Table 69: Restricted earth fault protection, low impedance (PDIF, 87N)
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
IBase 1 - 99999 1 3000 A Base current
IdMin 4.0 - 100.0 0.1 30.0 %IB Maximum sensitivity in %
of Ibase
ROA 60 - 90 1 60 Deg Relay operate angle for
zero sequence direc-
tional feature
CTFactorPri1 1.0 - 10.0 0.1 1.0 - CT factor for HV side
CT1 (CT1rated/ HVrated
current)
CTFactorPri2 1.0 - 10.0 0.1 1.0 - CT factor for HV side
CT2 (CT2rated/ HVrated
current)
CTFactorSec1 1.0 - 10.0 0.1 1.0 - CT factor for MV side
CT1 (CT1rated/ MVrated
current)
CTFactorSec2 1.0 - 10.0 0.1 1.0 - CT factor for MV side
CT2 (CT2rated/ MVrated
current)
Function Range or value Accuracy
Operate characteristic Adaptable 2.0% of I
r
for I <I
r
2.0% of I for I >I
r
Reset ratio >95% -
Base sensitivity function (4.0-100.0)% of I
base
2.0% of I
r
Directional characteristic Fixed 180 degrees or 60 to 90
degrees
2.0 degree
Operate time 20 ms typically at 0 to 10 x I
d
-
Reset time 25 ms typically at 10 to 0 x I
d
-
Second harmonic blocking (5.0-100.0)% of fundamental 2.0% of I
r
130
High impedance differential protection
(PDIF, 87)
Chapter 4
Differential protection
3 High impedance differential protection (PDIF, 87)
3.1 Introduction
The high impedance differential protection can be used when the involved CT cores have same
turn ratio and similar magnetizing characteristic. It utilizes an external summation of the phases
and neutral current and a series resistor and a voltage dependent resistor externally to the relay.
3.2 Principle of operation
The high impedance differential function is based on one current input with external stabilizing
resistors and voltage dependent resistors. Three functions can be used to provide a three phase
differential protection function. The stabilizing resistor value is calculated from the relay oper-
ating value UR calculated to achieve through fault stability. The supplied stabilizing resistor has
a link to allow setting of the correct resistance value.
3.2.1 Logic diagram
The logic diagram see figure 59 shows the operation principles for the high impedance differen-
tial protection function. It is a basically a simple one step relay with an additional lower alarm
level. The function can be totally blocked totally or only tripping by activating inputs from ex-
ternal signals.
Function block name: HZDx- IEC 60617 graphical symbol:
ANSI number: 87
IEC 61850 logical node name:
HZPDIF
IdN
131
High impedance differential protection
(PDIF, 87)
Chapter 4
Differential protection
Figure 59: Logic diagram for High impedance differential protection.
3.3 Function block
Figure 60: HZD function block
3.4 Input and output signals
Table 70: Input signals for the HZPDIF_87 (HZD1-) function block
HZPDIF
HZD1-
ISI
BLOCK
BLKTR
TRIP
ALARM
MEASVOLT
en05000363.vsd
Signal Description
ISI Group signal for current input
BLOCK Block of function
BLKTR Block of trip
132
High impedance differential protection
(PDIF, 87)
Chapter 4
Differential protection
Table 71: Output signals for the HZPDIF_87 (HZD1-) function block
3.5 Setting parameters
Table 72: Parameter group settings for the HZPDIF_87 (HZD1-) function
3.6 Technical data
Table 73: High impedance differential protection (PDIF, 87)
Signal Description
TRIP Trip signal
ALARM Alarm signal
MEASVOLT Measured RMS voltage on CT secondary side
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
U>Alarm 2 - 500 1 10 V Alarm voltage level in
volts on CT secondary
side
tAlarm 0.000 - 60.000 0.001 5.000 s Time delay to activate
alarm
U>Trip 5 - 900 1 100 V Operate voltage level in
volts on CT secondary
side
SeriesResistor 10 - 20000 1 250 ohm Value of series resistor in
Ohms
Function Range or value Accuracy
Operate voltage (20-400) V 1.0% of U
r
for U <U
r
1.0% of U for U >U
r
Reset ratio >95% -
Maximum continuous voltage U>Trip
2
/series resistor 200 W -
Operate time 10 ms typically at 0 to 10 x U
d
-
Reset time 90 ms typically at 10 to 0 x U
d
-
Critical impulse time 2 ms typically at 0 to 10 x U
d
-
133
About this chapter Chapter 5
Distance protection
Chapter 5 Distance protection
About this chapter
This chapter describes distance protection and associated functions. It includes function blocks,
logic diagrams and data tables with information about distance protection, automatic switch onto
fault, weak end in-feed and other associated functions. Quadrilateral characteristics are also cov-
ered.
134
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
1 Distance protection zones (PDIS, 21)
1.1 Introduction
The distance protection is a five zone full scheme protection with three fault loops for phase to
phase faults and three fault loops for phase to earth fault for each of the independent zones. In-
dividual settings for each zone resistive and reactive reach gives flexibility for use as back-up
protection for transformer connected to overhead lines and cables.
The function has a functionality for load encroachment which increases the possibility to detect
high resistive faults on heavily loaded lines.
The distance protection zones can operate, independent of each other, in directional (forward or
reverse) or non-directional mode.
1.2 Principle of operation
1.2.1 Full scheme measurement
The execution of the different fault loops within the IED670 are of full scheme type, which
means that each fault loop for phase to earth faults and phase to phase faults for forward and
reverse faults are executed in parallel.
Figure61 presents an outline of the different measuring loops for the basic five, imped-
ance-measuring zones l.
Figure 61: The different measuring loops at line-earth fault and phase-phase fault.
Function block name: ZMx-- IEC 60617 graphical symbol:
ANSI number: 21
IEC 61850 logical node name:
ZMQPDIS
en05000458.vsd
L1-N L2-N L3-N
L1-N L2-N L3-N
L1-N L2-N L3-N
L1-N L2-N L3-N
L1-L2 L2-L3 L3-L1
L1-L2 L2-L3 L3-L1
L1-L2 L2-L3 L3-L1
L1-L2 L2-L3 L3-L1
L1-N L2-N L3-N L1-L2 L2-L3 L3-L1
Zone 1
Zone 2
Zone 3
Zone 4
Zone 5
135
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
The use of full scheme technique gives faster operation time compared to switched schemes
which mostly uses a start element to select correct voltages and current depending on fault type.
Each distance protection zone performs like one independent distance protection relay with six
measuring elements.
1.2.2 Impedance characteristic
The distance measuring zone include six impedance measuring loops; three intended for
phase-to-earth faults, and three intended for phase-to-phase as well as three-phase faults.
The distance measuring zone will essentially operate according to the non-directional imped-
ance characteristics presented in figure62 and figure63. The phase-to-earth characteristic is il-
lustrated with the full loop reach while the phase-to-phase characteristic presents the per-phase
reach.
Figure 62: Characteristic for the phase-to-earth measuring loops, ohm/loop domain.
RFPE
X1+Xn
X1+Xn
RFPE R1+Rn RFPE
RFPE
RFPE
RFPE
R
X
R1+Rn
f N f N
R0 R1
RN
3

=
(Ohm/loop)
X0 X1
XN
3

=
en05000661.vsd
136
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
Figure 63: Characteristic for the phase-to-phase measuring loops
The fault loop reach with respect to each fault type may also be presented as in figure64. Note
in particular the difference in definition regarding the (fault) resistive reach for phase-to-phase
faults and three-phase faults.
2R1 RFPP
2X1
2X1
RFPP 2R1 RFPP
RFPP
RFPP
RFPP
R
X (Ohm/phase)
(Ohm/phase)
en05000662.vsd
137
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
Figure 64: Fault loop model
The R1 and jX1 in figure64 represents the positive sequence impedance from the measuring
point to the fault location. The RFPE and RFPP is the eventual fault resistance in the fault place.
Regarding the illustration of three-phase fault in figure64, there is of course fault current flow-
ing also in the third phase during a three-phase fault. The illustration merely reflects the loop
measurement, which is made phase-to-phase.
where:
n designates anyone of the three phases (1, 2 or 3) and
m represents the phase that is leading phase n with 120 degrees (i.e. 3, 1 or 2).
UL1
R1 +j X1
ILn
RFPE
Phase-to-earth
fault in phase L1
Phase-to-phase
fault in phase
L1-L2
Three-phase
fault
(Arc + tower
resistance)
0
(R0-R1)/3 +
j (X0-X1)/3 )
IN
UL1
R1 +j X1
IL1
UL2
R1 +j X1
IL2
RFPP
UL1
R1 +j X1
IL1
UL3
R1 +j X1
IL3
0.5RFPP
0.5RFPP
(Arc resistance)
Phase-to-earth
element
Phase-to-phase
element L1-L2
Phase-to-phase
element L1-L3
en05000181.vsd
138
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
The theoretical parameters p and q outline the area of operation in quadrant 1 when varied from
0 to 1.0. That is, for any combination of p and q, where both are between 0 and 1.0, the corre-
sponding impedance is within the reach of the characteristic.
The zone may be set to operate in Non-directional, Forward or Reverse direction through the
setting OperationDir. The result from respective set value is illustrated in figure65. It may be
convenient to once again mention that the impedance reach is symmetric, in the sense that it is
conform for forward and reverse direction. Therefore, all reach settings apply to both directions.
Figure 65: Directional operating modes of the distance measuring zone
1.2.3 Minimum operating current
The operation of the distance measuring zone is blocked if the magnitude of input currents fall
below certain threshold values.
The phase-to-earth loop Ln is blocked if ILn <IMinOpPE.
For zone 1 with load compensation feature the additional criterion applies, that all phase-to-earth
loops will be blocked when IN <IMinOpIN, regardless of the phase currents.
ILn is the RMS value of the current in phase Ln. IN is the RMS value of the vector sum of the
three phase currents, i.e. residual current 3I0.
The phase-to-phase loop LmLn is blocked if ILmLn <IMinOpPP.
en05000182.vsd
R
X
R
X
R
X
Non-directional Forward Reverse
139
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
ILmLn is the RMS value of the vector difference between phase currents Lm and Ln.
1.2.4 Measuring principles
Fault loop equations use the complex values of voltage, current, and changes in the current. Ap-
parent impedances are calculated and compared with the set limits. The calculation of the appar-
ent impedances at ph-ph faults follows equation6 (example for a phase L1 to phase L2 fault).
(Equation 6)
Here U and I represent the corresponding voltage and current phasors in the respective phase Ln
(n =1, 2, 3)
The earth return compensation applies in a conventional manner to ph-E faults (example for a
phase L1 to earth fault) according to equation7.
(Equation 7)
Here IN is a phasor of the residual current in relay point. This results in the same reach along the
line for all types of faults.
The apparent impedance is considered as an impedance loop with resistance R and reactance X.
The formula given in equation7 is only valid for no loaded radial feeder applications. When load
is considered in the case of single line to earth fault, conventional distance protection might
overreach at exporting end and underreach at importing end. REx670 has an adaptive load com-
pensation which increases the security in such applications.
Note!
All three current limits IminOpPE, IminOpIN and IMinOpPP are automatically reduced to 75%
of regular set values if the zone is set to operate in reverse direction, i.e. OperationDir=Reverse.
Where:
UL1, IL1 and IN are the phase voltage, phase current and residual current present to the IED
KN is defined as:
where X0 and X1 is zero and positive sequence reactance from the measuring point to
the fault on the protected line.
Z
app
U
L1
U
L2

I
L1
I
L2

------------------------- =
Z
app
U
L1
I
L1
I
N
KN +
= ------------------------------
3X1
X1 - X0
= KN
140
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
Measuring elements receive current and voltage information from the A/D converter. The check
sums are calculated and compared, and the information is distributed into memory locations. For
each of the six supervised fault loops, sampled values of voltage (U), current (I), and changes in
current between samples (I) are brought from the input memory and fed to a recursive Fourier
filter.
The filter provides two orthogonal values for each input. These values are related to the loop im-
pedance according to equation8,
(Equation 8)
in complex notation, or:
(Equation 9)
(Equation 10)
with
(Equation 11)
The algorithm calculates Rm measured resistance from the equation for the real value of the volt-
age and substitute it in the equation for the imaginary part. The equation for the Xm measured
reactance can then be solved. The final result is equal to:
(Equation 12)
where:
Re designates the real component of current and voltage,
Im designates the imaginary component of current and voltage and
f
0
designates the rated system frequency
U R i
X

0
------ +
i
t
----- =
Re U ( ) R Re I ( )
X

0
------ +
Re I ( )
t
------------------ =
Im U ( ) R ImI ( )
X

0
------ +
Im I ( )
t
----------------- =

0
2 f
0
=
R
m
Im U ( ) Re I ( ) Re U ( ) Im I ( )
Re I ( ) Im I ( ) Im I ( ) Re I ( )
------------------------------------------------------------------------------------ =
141
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
(Equation 13)
The calculated R
m
and X
m
values are updated each sample and compared with the set zone reach.
The adaptive tripping counter counts the number of permissive tripping results. This effectively
removes any influence of errors introduced by the capacitive voltage transformers or by other
factors.
The directional evaluations are performed simultaneously in both forward and reverse direc-
tions, and in all six fault loops. Positive sequence voltage and a phase locked positive sequence
memory voltage are used as a reference. This ensures unlimited directional sensitivity for faults
close to the relay point.
1.2.5 Directional lines
The evaluation of the directionality is taken place in the function block ZD. Equation14 and
equation15 are used to classify that the fault is in forward direction for line-to-earth fault and
phase-phase fault.
(Equation 14)
For the L1-L2 element, the equation in forward direction is according to.
(Equation 15)
X
m

0
t
Re U ( ) Im I ( ) Im U ( ) Re I ( )
Re I ( ) Im I ( ) Im I ( ) Re I ( )
------------------------------------------------------------------------------- =
where:
ArgDir is the setting for the lower boundary of the forward directional characteristic, by default
set to 15 (=-15 degrees) and
ArgNegRes is the setting for the upper boundary of the forward directional characteristic, by default
set to 115 degrees, see figure 66.
U1
L1
is positive sequence phase voltage in phase L1
U1
L1M
is positive sequence memorized phase voltage in phase L1
I
L1
is phase current in phase L1
U1
L1L2
is voltage difference between phase L1 and L2 (L2 lagging L1)
U1
L1L2M
is memorized voltage difference between phase L1 and L2 (L2 lagging L1)
I
L1L2
is current difference between phase L1 and L2 (L2 lagging L1)
-ArgDir arg
0.8 U1
L1
0.2 + U1
L1M

I
L1
------------------------------------------------------------ ArgNegRes < <
-ArgDir arg
0.8 U1
L1L2
0.2 + U1
L1L2M
I
L1L2
---------------------------------------------------------------------- - ArgNegRes < <
142
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
The setting of ArgDir and ArgNegRes is by default set to 15 (=-15) and 115 degrees respective-
ly.(see figure66) and it should not be changed unless system studies has shown the necessity.
The ZD gives a binary coded signal on the output STDIR depending on the evaluation where
STFWL1N=1 adds 1, STRVL1N=1 adds 2, STFWL2N=1 adds 4 etc.
Figure 66: Setting angles for discrimination of forward and reverse fault
The reverse directional characteristic is equal to the forward characteristic rotated by
180degrees.
The polarizing voltage is available as long as the positive-sequence voltage exceeds 4% of the
set base voltage UBase. So the directional element can use it for all unsymmetrical faults includ-
ing close-in faults.
For close-in three-phase faults, the U1
L1M
memory voltage, based on the same positive se-
quence voltage, ensures correct directional discrimination.
The memory voltage is used for 100ms or until the positive sequence voltage is restored.
After 100ms, the following occurs:
If the current is still above the set value of the minimum operating current
(between10 and 30% of the set terminal rated current IBase), the condition seals
in.
- If the fault has caused tripping, the trip endures.
- If the fault was detected in the reverse direction, the measuring element in
the reverse direction remains in operation.
R
X
Reverse
operation
en05000722.vsd
ArgNegRes
ArgDir
143
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
If the current decreases below the minimum operating value, the memory resets
until the positive sequence voltage exceeds 10% of its rated value.
1.2.6 Simplified logic diagrams
Distance protection zones
The design of distance protection zone 1 is presented for all measuring loops: phase-to-earth as
well as phase-to-phase.
Phase-to-earth related signals are designated by LnE, where n represents the corresponding
phase number (L1E, L2E, and L3E). The phase-to-phase signals are designated by LnLm, where
n and m represent the corresponding phase numbers (L1L2, L2L3, and L3L1).
Fulfillment of two different measuring conditions is necessary to obtain the one logical signal
for each separate measuring loop:
Zone measuring condition, which follows the operating equations described
above.
Group functional input signal (STCND), as presented in figure 67.
The STCND input signal represents a connection of six different integer values from the phase
selection function within the IED, which are converted within the zone measuring function into
corresponding boolean expressions for each condition separately. It is connected to the PHS
function block output STCDZ.
The internal input signal DIRCND is used to give condition for directionality for the distance
measuring zones. The signal contains binary coded information for both forward and reverse di-
rection. The zone measurement function filter out the relevant signals on the STDIR input de-
pending on the setting of the parameter OperationDir. It shall be configured to the STDIR output
on the ZD block.
144
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
Figure 67: Conditioning by a group functional input signal STCND
Composition of the phase starting signals for a case, when the zone operates in a non-directional
mode, is presented in figure 68.
145
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
Figure 68: Composition of starting signals in non-directional operating mode
Results of the directional measurement enter the logic circuits, when the zone operates in direc-
tional (forward or reverse) mode, see figure 69.
146
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
Figure 69: Composition of starting signals in directional operating mode
Tripping conditions for the distance protection zone one are symbolically presented in figure 70.
STNDL1N
DIRL1N
STNDL2N
DIRL2N
STNDL3N
DIRL3N
STNDL1L2
DIRL1L2
STNDL2L3
DIRL2L3
STNDL3L1
DIRL3L1
&
&
&
&
&
&
BLK
t
15 ms
t
15 ms
t
15 ms
t
15 ms
STZMPE.
STL1
STL2
STL3
START
STZMPP
AND
AND
AND
AND
AND
AND
OR
OR
OR
OR
OR
OR
en05000778.vsd
147
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
Figure 70: Tripping logic for the distance protection zone one
1.3 Function block
Figure 71: ZM function block
ZMQPDIS
ZM01-
I3P
U3P
BLOCK
VTSZ
BLKTR
STCND
DIRCND
TRIP
TRL1
TRL2
TRL3
START
STL1
STL2
STL3
STND
en05000695.vsd
148
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
Figure 72: ZD function block
1.4 Input and output signals
Table 74: Input signals for the ZMQPDIS_21 (ZM01-) function block
Table 75: Output signals for the ZMQPDIS_21 (ZM01-) function block
Table 76: Input signals for the ZDRDIR (ZD01-) function block
ZDRDIR
ZD01-
I3P
U3P
STDIR
en05000681.vsd
Signal Description
I3P Group signal for current input
U3P Group signal for voltage input
BLOCK Block of function
VTSZ Blocks all output by fuse failure signal
BLKTR Blocks all trip outputs
STCND External start condition (loop enabler)
DIRCND External directional condition
Signal Description
TRIP General Trip, issued from any phase or loop
TRL1 Trip signal from phase L1
TRL2 Trip signal from phase L2
TRL3 Trip signal from phase L3
START General Start, issued from any phase or loop
STL1 Start signal from phase L1
STL2 Start signal from phase L2
STL3 Start signal from phase L3
STND Non-directional start, issued from any phase or loop
Signal Description
I3P Group connection
U3P Group connection
149
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
Table 77: Output signals for the ZDRDIR (ZD01-) function block
1.5 Setting parameters
Table 78: Parameter group settings for the ZMQPDIS_21 (ZM01-) function
Signal Description
STDIR All start signals binary coded
Parameter Range Step Default Unit Description
Operation Off
On
- On - Operation Off / On
IBase 1 - 99999 1 3000 A Base current, i.e. rated
current
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage, i.e. rated
voltage
OperationDir Off
Non-directional
Forward
Reverse
- Forward - Operation mode of direc-
tionality NonDir / Forw /
Rev
X1 0.10 - 3000.00 0.01 30.00 ohm/p Positive sequence reac-
tance reach
R1 0.10 - 1000.00 0.01 5.00 ohm/p Positive seq. resistance
for zone characteristic
angle
X0 0.10 - 9000.00 0.01 100.00 ohm/p Zero sequence reactance
reach
R0 0.50 - 3000.00 0.01 15.00 ohm/p Zero seq. resistance for
zone characteristic angle
RFPP 1.00 - 3000.00 0.01 30.00 ohm/l Fault resistance reach in
ohm/loop, Ph-Ph
RFPE 1.00 - 9000.00 0.01 100.00 ohm/l Fault resistance reach in
ohm/loop, Ph-E
OperationPP Off
On
- On - Operation mode Off / On
of Phase-Phase loops
Timer tPP Off
On
- On - Operation mode Off / On
of Zone timer, Ph-Ph
tPP 0.000 - 60.000 0.001 0.000 s Time delay of trip, Ph-Ph
OperationPE Off
On
- On - Operation mode Off / On
of Phase-Earth loops
150
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
Table 79: Parameter group settings for the ZDRDIR (ZD01-) function
1.6 Technical data
Table 80: Distance protection zones (PDIS, 21)
Timer tPE Off
On
- On - Operation mode Off / On
of Zone timer, Ph-E
tPE 0.000 - 60.000 0.001 0.000 s Time delay of trip, Ph-E
IMinOpPP 10 - 30 1 20 %IB Minimum operate delta
current for Phase-Phase
loops
IMinOpPE 10 - 30 1 20 %IB Minimum operate phase
current for Phase-Earth
loops
IMinOpIN 5 - 30 1 5 %IB Minimum operate resid-
ual current for
Phase-Earth loops
Parameter Range Step Default Unit Description
ArgNegRes 90 - 175 1 115 Deg Angle to blinder in sec-
ond quadrant for forward
direction
ArgDir 5 - 45 1 15 Deg Angle to blinder in fourth
quadrant for forward
direction
IMinOp 1 - 99999 1 10 %IB Minimum operate cur-
rent in % of IBase
IBase 1 - 99999 1 3000 A Base Current
UBase 0.05 - 2000.00 0.05 400.00 kV Base Voltage
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Number of zones 5 with selectable direction -
Minimum operate current (10-30)% of I
base
-
Positive sequence reactance (0.50-3000.00) /phase 2.0% static accuracy
2.0 degrees static angular accu-
racy
Conditions:
Voltage range: (0.1-1.1) x U
r
Current range: (0.5-30) x I
r
Angle: at 0 degrees and
85 degrees
Positive sequence resistance (0.10-1000.00) /phase
Zero sequence reactance (0.50-9000.00) /phase
Zero sequence resistance (0.50-3000.00) /phase
Fault resistance, Ph-E (1.00-9000.00) /loop
Fault resistance, Ph-Ph (1.00-3000.00) /loop
151
Distance protection zones (PDIS, 21) Chapter 5
Distance protection
Dynamic overreach <5% at 85 degrees measured with
CVTs and 0.5<SIR<30
-
Impedance zone timers (0.000-60.000) s 0.5% 10 ms
Operate time 24 ms typically -
Reset ratio 105% typically -
Reset time 30 ms typically -
Function Range or value Accuracy
152
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
2 Phase selection with load encroachment
(PDIS, 21)
2.1 Introduction
The operation of transmission networks today is in many cases close to the stability limit. Due
to environmental considerations the rate of expansion and reinforcement of the power system is
reduced e.g. difficulties to get permission to build new power lines. The ability to accurate and
reliable classifying the different types of fault so that single pole tripping and auto-reclosing can
be used plays an important roll in this matter. The PHS function is designed to accurate select
the proper fault loop in the distance function dependent on the fault type.
The heavy load transfer that is common in many transmission networks may in some cases be
in opposite to the wanted fault resistance coverage. Therefore the function has an built in algo-
rithm for load encroachment, which gives the possibility to enlarge the resistive setting of both
the PHS and the measuring zones without interfering with the load.
The extensive output signals from the PHS gives also important information about faulty
phase(s) which can be used for fault analysis.
2.2 Principle of operation
The basic impedance algorithm for the operation of the phase-selection measuring elements is
the same as for the distance-measuring function (see section 1 "Distance protection zones (PDIS,
21)"). The "phase selection" includes six impedance measuring loops; three intended for
phase-to-earth faults, and three intended for phase-to-phase as well as for three-phase faults.
The difference, compared to the zone measuring elements, is in the combination of the measur-
ing quantities (currents and voltages) for different types of faults.
The characteristic is basically non-directional, but the PHS function uses information from the
directional function block to discriminate whether the fault is in forward or reverse. The direc-
tional lines are drawn as "line-dot-dot-line" in the figures below.
The start condition STCNDZ is essentially based on the following criteria:
1. Residual current criteria, i.e. separation of faults with and without earth connec-
tion
2. Regular quadrilateral impedance characteristic
Function block name: PHS-- IEC 60617 graphical symbol:
ANSI number: 21
IEC 61850 logical node name:
FDPSPDIS
Z<phs
153
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
3. Load encroachment characteristics is always active but can be switched off by se-
lecting a high setting.
The current start condition STCNDI is based on the following criteria:
1. Residual current criteria
2. No quadrilateral impedance characteristic. The impedance reach outside the load
area is theoretically infinite. The practical reach, however, will be determined by
the minimum operating current limits.
3. Load encroachment characteristic is always active, but can be switched off by se-
lecting a high setting.
The STCNDI-output described above is non-directional. The directionality is determined by the
distance zones direction function block. There are still output from the function that indicate
whether a start is in forward or reverse direction, or in between those (e.g. STFWL1 and
STRVL1, and STNDL1). These directional indications are based on the sector boundaries of the
directional function and the impedance setting of the phase selection function. Their operate
characteristics are illustrated in figure73.
Figure 73: Characteristic for non-directional, forward and reverse operation of PHS
The setting of the load encroachment function may influence the total operating characteristic,
(for more information, refer to section2.2.4 "Load encroachment").
The input DIRCND contains binary coded information about the directionality coming from the
directionality block. It shall be connected to the STDIR output on the ZD block. This informa-
tion is also transferred to the input DIRCND on the distance measuring zones, i.e. the ZM block.
The code built up for the directionality is as follows:
en05000668.vsd
R
X
R
X
R
X
Non-directional (ND) Forward (FW) Reverse (RV)
60
60
60
60
154
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
STDIR=STFWL1*1+STRVL1*2+STFWL2*4+STRVL2*8+STFWL3*16+STRVL3*32+STF
WL1L2*64+
STRVL1L2*128+STFWL2L3*256+STRVL2L3*512+STFWL3L1*1024+STRVL3L1*2048
If the binary information is 1 then it will be considered that we have start in forward direction in
phase L1. If the binary code is 3 then we have start in forward direction in phase L1 and L2 etc.
The STCND (Z or I) output contains, in a similar way as DIRCND, binary coded information,
in this case information about the condition for opening correct fault loop in the distance mea-
suring element. It shall be connected to the STCND input on the ZM blocks. The code built up
for release of the measuring fault loops is as follows:
STCND =L1N*1 +L2N*2 +L3N*4 +L1L2*8 +L2L3*16 +L3L1*32
2.2.1 Phase-to-earth fault
For a phase-to-earth fault, the measured impedance by PHS function will be according to
equation16.
(Equation 16)
The characteristic for the PHS function at phase to earth fault is according to figure74. The char-
acteristic has a fix angle for the resistive boundary in the first quadrant of 60.
The resistance RN and reactance XN is the impedance in the earth return path defined according
to equation17 and equation18.
(Equation 17)
(Equation 18)
where:
n corresponds to the particular phase (n=1, 2 or 3)
PHSn
ULn
Z
ILn
=
0 1
3
R R
RN

=
0 1
3
X X
XN

=
155
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
Figure 74: Characteristic of PHS for phase to earth fault (setting parameters in italic),
ohm/loop domain
Besides this, the 3I0 residual current must fulfil the conditions according to equation19 and
equation20.
(Equation 19)
(Equation 20)
where:
IMinOp is the minimum operation current for forward zones,
INReleasePE is the setting for the minimum residual current needed to enable operation in the ph-E
fault loops (in %) and
I
phmax
is the maximum phase current in any of three phases.
en05000669.vsd
RFFwPE
X1+XN
R (Ohm/phase
X (ohm/phase)
RFRvPE
RFRvPE
RFFwPE
Kr(X1+XN)
RFRvPE
Kr(X1+XN)
X1
RFFwPE
60 deg
60 deg
=
1
Kr
tan(60deg)
3 I
0
0.5 I Mi nOp
3 I0
INReleasePE
100
----------------------------------- -
Iphmax
156
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
2.2.2 Phase-to-phase fault
For a phase-to-phase fault, the measured by the PHS function will be according to equation21.
(Equation 21)
ULm is the leading phase voltage, ULn the lagging phase voltage and ILn the phase current in
the lagging phase n.
The operation characteristic is shown in figure75.
Figure 75: The operation characteristic for PHS at phase-to-phase fault (setting parameters
in Italic), ohm/phase domain
In the same way as the condition for phase-to-earth fault, there are current conditions that have
to be fulfilled in order to release the phase-to-phase loop. Those are according to equation22 or
equation23.
(Equation 22)
2
ULm ULn
ZPHS
ILn

=

en05000670.vsd
X1
R (ohm/phase)
X (ohm/phase)
0.5RFFwPP
KrX1
KrX1
X1
60 deg
60 deg
0.5RFFwPP 0.5FRvPP
0.5RFRvPP
0.5RFRvPP 0.5RFFwPP
1
Kr
tan(60deg)
=
3 0 Re I IN leasePE <
157
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
(Equation 23)
2.2.3 Three phase faults
The operation condition for three phase faults are the same as for phase-to-phase fault i.e.
equation21, equation22 and equation23 are used to release the operation of the function.
However, the reach is expanded by a factor 2/3 (approximately1.1547) in all directions. At the
same time the apparent impedance is rotated 30 degrees, counter-clockwise. The characteristic
is shown in figure76.
Figure 76: The characteristic of PHS for three phase fault (setting parameters in italic)
where:
INRelease is 3I0 limit for releasing phase-to-earth measuring loops,
INBlockPP is 3I0 limit for blocking phase-to-phase measuring loop and
Iphmax is maximal magnitude of the phase currents.
max 3 0 I INBlockPP Iph <
0.5RFFwPPK3
K3 =2 / sqrt(3)
X1K3
90 deg
0.5RFRvPPK3
30 deg
R (ohm/phase)
X (ohm/phase)
4 X1
3

4 RFFwPP
6

en05000671.vsd
158
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
2.2.4 Load encroachment
Each of the six measuring loops has its own load (encroachment) characteristic based on the cor-
responding loop impedance. The load encroachment functionality is always active, but can be
switched off by selecting a high setting.
The outline of the characteristic is presented in figure77. As illustrated, the resistive blinders
are set individually in forward and reverse direction while the angle of the sector is the same in
all four quadrants.
Figure 77: Characteristic of load encroachment function
The influence of load encroachment function depending on the operation characteristic is depen-
dent on the chosen operation mode of the PHS function. When selection mode is STCNDZ, the
characteristic for the PHS (and also zone measurement depending on settings) will be reduced
by the load encroachment characteristic (see figure78, left illustration).
When STCNDI is selected the operation characteristic will be as the right illustration in
figure78. The reach will in this case be limit by the minimum operation current and the distance
measuring zones.
R
X
RLdFw
RLdRv
ARGLd
ARGLd ARGLd
ARGLd
en05000196.vsd
159
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
Figure 78: Difference in operating characteristic depending on operation mode when load
encroachment is activated
When the "phase selection" is set to operate together with a distance measuring zone the result-
ant operate characteristic could look something like in figure79. The figure shows a distance
measuring zone operating in forward direction. Thus, the operate area is highlighted in black.
R
X
STCNDZ STCNDI
R
X
en05000197.vsd
160
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
Figure 79: Operation characteristic in forward direction when load encroachment is enabled
Figure79 is valid for phase-to-earth as well as phase-to-phase faults. During a three-phase fault,
or load, when the "quadrilateral" phase-to-phase characteristic is subject to enlargement and ro-
tation the operate area is transformed according to figure80. Notice in particular what happens
with the resistive blinders of the "phase selection" "quadrilateral" characteristic. Due to the
30-degree rotation, the angle of the blinder in quadrant one is now 90degrees instead of the orig-
inal 60degrees. The blinder that is nominally located to quadrant four will at the same time tilt
outwards and increase the resistive reach around the R-axis. Consequently, it will be more or
less necessary to use the load encroachment characteristic in order to secure a margin to the load
impedance.
R
X
Distance measuring zone
Directional line
Load encroachment
characteristic
"Phase selection"
"quadrilateral" zone
en05000673.vsd
161
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
Figure 80: Operation characteristic for PHS in forward direction for three-phase fault,
ohm/phase domain
2.2.5 Minimum operate currents
The operation of the PHS function is blocked if the magnitude of input currents falls below cer-
tain threshold values.
The phase-to-earth loop Ln is blocked if ILn<IMinOpPE, where ILn is the RMS value of the
current in phase Ln.
The phase-to-phase loop LmLn is blocked if (2ILn<IMinOpPP).
2.2.6 Simplified logic diagrams
Figure81 presents schematically the creation of the phase-to-phase and phase-to-earth operating
conditions. Consider only the corresponding part of measuring and logic circuits, when only a
phase-to-earth or phase-to-phase measurement is available within the terminal.
R
X
Distance measuring zone
Phase selection
Quadrilateral zone
(ohm/phase)
(ohm/phase)
en05000674.vsd
162
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
Figure 81: Phase-to-phase and phase-to-earth operating conditions (residual current crite-
ria)
A special attention is paid to correct phase selection at evolving faults. A STCNDI output signal
is created as a combination of the load encroachment characteristic and current criteria, refer to
figure81. This signal can be configured to STCND functional input signals of the distance pro-
tection zone and this way influence the operation of the ph-ph and ph-E zone measuring ele-
ments and their phase related starting and tripping signals.
Figure82 presents schematically the composition of non-directional phase selective signals
PHS--STNDLn, where n presents the corresponding phase number. Signals ZMLnN and
ZMLmLn(mand n change between one and three according to the phase number) represent the
fulfilled operating criteria for each separate loop measuring element (i.e. within the "quadrilat-
eral" characteristic.
163
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
Figure 82: Composition on non-directional phase selection signals
Composition of the directional (forward and reverse) phase selective signals is presented sche-
matically in figure84 and figure83. The directional criteria appears as a condition for the cor-
rect phase selection in order to secure a high phase selectivity for simultaneous and evolving
faults on lines within the complex network configurations. Signals DFWLn and DFWLnLm
present the corresponding directional signals for measuring loops with phases Ln and Lm. Des-
ignation FW (figure84) represents the forward direction as well as the designation RV
(figure83) represents the reverse direction. All directional signals are derived within the corre-
sponding digital signal processor.
Figure83 presents additionally a composition of a STCNDZ output signal, which is created on
the basis of impedance measuring conditions. This signal can be configured to STCND function-
al input signals of the distance protection zone and this way influence the operation of the ph-ph
and ph-E zone measuring elements and their phase related starting and tripping signals.
164
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
Figure 83: Composition of phase selection signals for reverse direction
165
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
Figure 84: Composition of phase selection signals for forward direction
166
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
2.3 Function block
Figure 85: PHS function block
2.4 Input and output signals
Table 81: Input signals for the FDPSPDIS (PHS--) function block
Table 82: Output signals for the FDPSPDIS (PHS--) function block
FDPSPDIS
PHS--
I3P
U3P
BLOCK
DIRCND
STFWL1
STFWL2
STFWL3
STFWPE
STRVL1
STRVL2
STRVL3
STRVPE
STNDL1
STNDL2
STNDL3
STNDPE
STFW1PH
STFW2PH
STFW3PH
STPE
STPP
STCNDZ
STCNDI
en05000379.vsd
Signal Description
I3P Group signal for current input
U3P Group signal for voltage input
BLOCK Block of function
DIRCND External directional condition
Signal Description
STFWL1 Fault detected in phase L1 - forward direction
STFWL2 Fault detected in phase L2 - forward direction
STFWL3 Fault detected in phase L3 - forward direction
STFWPE Earth fault detected in forward direction
STRVL1 Fault detected in phase L1 - reverse direction
STRVL2 Fault detected in phase L2 - reverse direction
STRVL3 Fault detected in phase L3 - reverse direction
STRVPE Earth fault detected in reverse direction
STNDL1 Fault detected in phase L1-non directional
STNDL2 Non directional start in L2
STNDL3 Non directional start in L3
167
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
2.5 Setting parameters
Table 83: Parameter group settings for the FDPSPDIS (PHS--) function
STNDPE Non directional start, phase-earth
STFW1PH Start in forward direction for single phase
STFW2PH Start in forward direction for two phase fault
STFW3PH Start in forward direction for thre-phase fault
STPE Current conditions release of phase-earth measuring elements
STPP Current conditions release of phase-phase measuring elements
STCNDZ Start condition (PHS,LE and I based)
STCNDI Start condition (LE and I based)
Signal Description
Parameter Range Step Default Unit Description
IBase 1 - 99999 1 3000 A Base current for current
settings
INBlockPP 10 - 100 1 40 %IPh 3I0 limit for blocking
phase-to-phase measur-
ing loops
INReleasePE 10 - 100 1 20 %IPh 3I0 limit for releasing
phase-to-earth measur-
ing loops
RLdFw 1.00 - 3000.00 0.01 80.00 ohm/p Forward resistive reach
within the load imped-
ance area
RLdRv 1.00 - 3000.00 0.01 80.00 ohm/p Reverse resistive reach
within the load imped-
ance area
ArgLd 5 - 70 1 30 Deg Load angle determining
the load impedance area
X1 0.50 - 3000.00 0.01 40.00 ohm/p Positive sequence reac-
tance reach
X0 0.50 - 9000.00 0.01 120.00 ohm/p Zero sequence reactance
reach
RFFwPP 0.50 - 3000.00 0.01 30.00 ohm/l Fault resistance reach,
Ph-Ph, forward
168
Phase selection with load encroachment
(PDIS, 21)
Chapter 5
Distance protection
2.6 Technical data
Table 84: Phase selection with load encroachment (PDIS, 21)
RFRvPP 0.50 - 3000.00 0.01 30.00 ohm/l Fault resistance reach,
Ph-Ph, reverse
RFFwPE 1.00 - 9000.00 0.01 100.00 ohm/l Fault resistance reach,
Ph-E, forward
RFRvPE 1.00 - 9000.00 0.01 100.00 ohm/l Fault resistance reach,
Ph-E, reverse
IMinOpPP 5 - 30 1 10 %IB Minimum operate delta
current for Phase-Phase
loops
IMinOpPE 5 - 30 1 5 %IB Minimum operate phase
current for Phase-Earth
loops
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Minimum operate current (5-30)% of I
base
1.0% of I
r
Reactive reach, positive
sequence, forward and reverse
(0.503000.00) /phase 2.0% static accuracy
2.0 degrees static angular accu-
racy
Conditions:
Voltage range: (0.1-1.1) x U
r
Current range: (0.5-30) x I
r
Angle: at 0 degrees and 85
degrees
Resistive reach, positive
sequence
(0.101000.00) /phase
Reactive reach, zero sequence,
forward and reverse
(0.509000.00) /phase
Resistive reach, zero sequence (0.503000.00) /phase
Fault resistance, phase-earth
faults, forward and reverse
(1.009000.00) /loop
Fault resistance, phase-phase
faults, forward and reverse
(0.503000.00) /loop
Load encroachment criteria:
Load resistance, forward and
reverse
Safety load impedance angle
(1.003000.00) /phase
(5-70) degrees
Reset ratio 105% typically -
169
Power swing detection (RPSB, 78) Chapter 5
Distance protection
3 Power swing detection (RPSB, 78)
3.1 Introduction
Power swings may occur after disconnection of heavy loads or trip of big generation plants.
Power swing detection function is used to detect power swings and initiate block of selected dis-
tance protection zones. Occurrence of earth fault currents during a power swing can block the
power swing detection function to allow fault clearance.
3.2 Principle of operation
The PSD function comprises an inner and an outer quadrilateral measurement characteristic with
load encroachment, see figure86.
Its principle of operation is based on the measurement of the time it takes for a power swing tran-
sient impedance to pass through the impedance area between the outer and the inner character-
istics. Power swings are identified by transition times longer than a transition time set on
corresponding timers. The impedance measuring principle is the same as that used for the dis-
tance protection zones. The impedance and the characteristic passing times are measured in all
three phases separately. One-out-of-three or two-out-of-three operating modes can be selected
according to the specific system operating conditions.
Function block name: PSD-- IEC 60617 graphical symbol:
ANSI number: 78
IEC 61850 logical node name:
ZMRPSB
Zpsb
170
Power swing detection (RPSB, 78) Chapter 5
Distance protection
Figure 86: Operating characteristic for the PSD function
The impedance measurement within the PSD function is performed by solving equation24 and
equation25 (n =1, 2, 3 for each corresponding phase L1, L2 and L3).
(Equation 24)
(Equation 25)
The R
set
and X
set
are R and X boundaries which are more explained in the following sections.
Re
1
1
Rset
I
U
L
L

Im
1
1
Xset
I
U
L
L

171
Power swing detection (RPSB, 78) Chapter 5
Distance protection
3.2.1 Resistive reach in forward direction
To avoid load encroachment the resistive reach is limited in forward direction by setting the pa-
rameter RLdOutFw which is the outer resistive load boundary value while the inner resistive
boundary is calculated according to equation26.
(Equation 26)
The slope of the load encroachment inner and outer boundary is defined by setting the parameter
ARGLd.
The load encroachment in the fourth quadrant uses the same settings as in the first quadrant
(same ARGLd and RLdOutFw and calculated RLdInFw).
The quadrilateral characteristic in the first quadrant is tilted to get a better adaptation to the dis-
tance zones. The angle is the same as the line angle and derived from the setting of the reactive
reach inner boundary X1InFw and the line resistance for the inner boundary R1LIn. The fault
resistance coverage for the inner boundary is set by the parameter R1FInFw.
From the setting parameter RLdOutFw and the calculated value RLdInFw a distance between
the inner and outer boundary, Fw, is calculated. This value is valid for R direction in first and
fourth quadrant and for X direction in first and second quadrant.
3.2.2 Resistive reach in reverse direction
To avoid load encroachment in reverse direction the resistive reach is limited by setting the pa-
rameter RLdOutRv for the outer boundary of the load encroachment cone. The distance to the
inner resistive load boundary RLdInRv is determined by using the setting parameter kLdRRv in
equation27.
(Equation 27)
From the setting parameter RLdOutRv and the calculated value RLdInRv a distance between the
inner and outer boundary, Rv, is calculated. This value is valid for R direction in second and
third quadrant and for X direction in third and fourth quadrant.
The inner resistive characteristic in the second quadrant outside the load encroachment part cor-
responds to the setting parameter R1FInRv for the inner boundary. The outer boundary is inter-
nally calculated as the sum of Rv+R1FInRv.
where:
kLdRFw is a settable multiplication factor less than 1
RLdInFw kLdRFw RLdOutFw =
RLdInRv kLdRRv RLdOutRv =
172
Power swing detection (RPSB, 78) Chapter 5
Distance protection
The inner resistive characteristic in the third quadrant outside the load encroachment zone con-
sist of the sum of the settings R1FInRv and the line resistance R1LIn. The argument of the tilted
lines outside the load encroachment is the same as the tilted lines in the first quadrant. The dis-
tance between the inner and outer boundary is the same as for the load encroachment in reverse
direction i.e. Rv.
3.2.3 Reactive reach in forward and reverse direction
The inner characteristic for the reactive reach in forward direction correspond to the setting pa-
rameter X1InFw and the outer boundary is defined as X1InFw +Fw.
The inner characteristic for the reactive reach in reverse direction correspond to the setting pa-
rameter X1InRv for the inner boundary and the outer boundary is defined as X1InRv +Rv.
3.2.4 Basic detection logic
The operation of the function is only released if the magnitude of the current is above the setting
of the min operating current, IMinOpPE.
The PSD function can operate in two operating modes:
The "1-of-3" operating mode is based on detection of power swing in any of the
three phases. Figure87 presents a composition of a detection signal
PSD-DET-L1 in this particular phase.
The "2-of-3" operating mode is based on detection of power swing in at least two
out of three phases. Figure88 presents a composition of the detection signals
DET1of3 and DET2of3.
Signals ZOUTL1 (external boundary) and ZINL1 (internal boundary) in figure87 are related to
the operation of the impedance measuring elements in each phase separately (Ln represents the
corresponding phase L1, L2, and L3). They are internal signals, calculated by the PSD-function.
ThetP1 timer in figure87 serve as detection of initial power swings, which are usually not as
fast as the later swings are. The tP2 timer become activated for the detection of the consecutive
swings, if the measured impedance exit the operate area and returns within the time delay, set
on the tW waiting timer. The upper part of figure87 (input signal ZOUTL1, ZINL1, AND-gates
and tP-timers etc.) are duplicated for phase L2 and L3. All tP1 and tP2 timers in the figure have
the same settings.
173
Power swing detection (RPSB, 78) Chapter 5
Distance protection
Figure 87: Detection of power-swing in phase L1
Figure 88: Detection of power-swing for 1-of-3 and 2-of-3 operating mode
174
Power swing detection (RPSB, 78) Chapter 5
Distance protection
Figure 89: PSD function-simplified block diagram
3.2.5 Operating and inhibit conditions
Figure89 presents a simplified logic diagram for the PSD function. The internal signals
DET1of3 and DET2of3 relate to the detailed logic diagrams in figure87 and figure88 respec-
tively.
Selection of the operating mode is possible by the proper configuration of the functional input
signals REL1PH, BLK1PH, REL2PH, and BLK2PH.
The load encroachment characteristic can be switched off by setting the parameter Operation-
LdCh = Off, but notice that the Fw and Rv will still be calculated. The characteristic will in
this case be only quadrilateral.
There are four different ways to form the internal INHIBIT signal:
en05000114.vsd
TRSP
t
tEF
I0CHECK
AND
BLKI02
t
10 ms
AND BLKI01
BLOCK
INHIBIT
ZOUTL3
ZOUTL2
ZOUTL1
DET1of3 - int.
REL1PH
BLK1PH
AND
DET2of3 - int.
REL2PH
BLK2PH
AND
EXTERNAL
AND
START
ZOUT
ZINL1
ZINL2
ZINL3
ZIN
AND
t
tR1
t
tR2
OR
AND
AND
OR
OR
OR
OR
OR
t
tH
-loop
-loop
175
Power swing detection (RPSB, 78) Chapter 5
Distance protection
Logical 1 on functional input BLOCK inhibits the output START signal instan-
taneously.
The INHIBIT internal signal is activated, if the power swing has been detected
and the measured impedance remains within its operate characteristic for the
time, which is longer than the time delay set on tR2 timer. It is possible to disable
this condition by connecting the logical 1 signal to the BLKI01 functional input.
The INHIBIT internal signal is activated after the time delay, set on tR1 timer, if
an earth fault appears during the power swing (input IOCHECK is high) and the
power swing has been detected before the earth fault (activation of the signal
I0CHECK). It is possible to disable this condition by connecting the logical 1 sig-
nal to the BLKI02 functional input.
The INHIBIT logical signals becomes logical 1, if the functional input I0CHECK
appears within the time delay, set on tEF timer and the impedance has been seen
within the outer characteristic of the PSD operate characteristic in all three phas-
es. This function prevents the operation of the PSD function in cases, when the
circuit breaker closes onto persistent single-phase fault after single-pole auto-re-
closing dead time, if the initial single-phase fault and single-pole opening of the
circuit breaker causes the power swing in the remaining two phases.
3.3 Function block
Figure 90: PSD function block
3.4 Input and output signals
Table 85: Input signals for the ZMRPSB_78 (PSD1-) function block
ZMRPSB
PSD1-
I3P
U3P
BLOCK
BLKI01
BLKI02
BLK1PH
REL1PH
BLK2PH
REL2PH
I0CHECK
TRSP
EXTERNAL
START
ZOUT
ZIN
en05000383.vsd
Signal Description
I3P Group signal for current input
U3P Group signal for voltage input
BLOCK Block of function
BLKI01 Block inhibit of start output for slow swing condition
BLKI02 Block inhibit of start output for subsequent residual current
detection
BLK1PH Block one-out-of-three-phase operating mode
176
Power swing detection (RPSB, 78) Chapter 5
Distance protection
Table 86: Output signals for the ZMRPSB_78 (PSD1-) function block
3.5 Setting parameters
Table 87: Parameter group settings for the ZMRPSB_78 (PSD1-) function
REL1PH Release one-out-of-three-phase operating mode
BLK2PH Block two-out-of-three-phase operating mode
REL2PH Release two-out-of-three-phase operating mode
I0CHECK Residual current (3I0) detection used to inhibit start output
TRSP Single-pole tripping command issued by tripping function
EXTERNAL Input for external detection of power swing
Signal Description
START Power swing detected
ZOUT Measured impedance within outer impedance boundary
ZIN Measured impedance within inner impedance boundary
Signal Description
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Mode On / Off
X1InFw 0.10 - 3000.00 0.01 30.00 ohm Inner reactive boundary,
forward
R1LIn 0.10 - 1000.00 0.01 30.00 ohm Line resistance for inner
characteristic angle
R1FInFw 0.10 - 1000.00 0.01 30.00 ohm Fault resistance cover-
age to inner resistive line,
forward
X1InRv 0.10 - 3000.00 0.01 30.00 ohm Inner reactive boundary,
reverse
R1FInRv 0.10 - 1000.00 0.01 30.00 ohm Fault resistance line to
inner resistive boundary,
reverse
OperationLdCh Off
On
- On - Operation of load dis-
crimination characteristic
RLdOutFw 0.10 - 3000.00 0.01 30.00 ohm Outer resistive load
boundary, forward
ArgLd 5 - 70 1 25 Deg Load angle determining
load impedance area
RLdOutRv 0.10 - 3000.00 0.01 30.00 ohm Outer resistive load
boundary, reverse
kLdRFw 0.50 - 0.90 0.01 0.75 Mult Multiplication factor for
inner resistive load
boundary, forward
177
Power swing detection (RPSB, 78) Chapter 5
Distance protection
3.6 Technical data
Table 88: Power swing detection (RPSB, 78)
kLdRRv 0.50 - 0.90 0.01 0.75 Mult Multiplication factor for
inner resistive load
boundary, reverse
tP1 0.000 - 60.000 0.001 0.045 s Timer for detection of ini-
tial power swing
tP2 0.000 - 60.000 0.001 0.015 s Timer for detection of
subsequent power
swings
tW 0.000 - 60.000 0.001 0.250 s Waiting timer for activa-
tion of tP2 timer
tH 0.000 - 60.000 0.001 0.500 s Timer for holding power
swing START output
tEF 0.000 - 60.000 0.001 3.000 s Timer for overcoming sin-
gle-pole reclosing dead
time
tR1 0.000 - 60.000 0.001 0.300 s Timer giving delay to
inhibit by the residual cur-
rent
tR2 0.000 - 60.000 0.001 2.000 s Timer giving delay to
inhibit at very slow swing
IMinOpPE 5 - 30 1 10 %IB Minimum operate cur-
rent in % of IBase
IBase 1 - 99999 1 3000 A Base setting for current
level settings
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Reactive reach (0.10-3000.00) /phase 2.0% static accuracy
2.0 degrees static angular accu-
racy
Conditions:
Voltage range: (0.1-1.1) x U
r
Current range: (0.5-30) x I
r
Angle: at 0 degrees and 85
degrees
Resistive reach (0.101000.00) /loop
Timers (0.000-60.000) s 0.5% 10 ms
178
Automatic switch onto fault logic (PSOF) Chapter 5
Distance protection
4 Automatic switch onto fault logic (PSOF)
4.1 Introduction
Automatic switch onto fault logic is a function that gives an instantaneous trip at closing of
breaker onto a fault. A dead line detection check is provided to activate the function when the
line is dead.
4.2 Principle of operation
The switch-onto-fault (SOTF) function can be activated either externally or internally. The in-
ternal start is activated by using the information from a dead-line-detection (DLD) function, see
figure91, which is included in the SOTF function.
Figure 91: SOTF function - simplified diagram
After activation, a distance protection zone (the non-directional starting signal) is allowed to
give an instantaneous trip. The functional output signal from the distance protection zone to be
used, should be connected to the NDACC functional input of the SOTF function, see figure91.
The distance protection zone used together with the switch-onto-fault function shall be set to
cover the entire protected line.
The external activation is achieved by an input (BC), which should be set high for activation,
and low when the breaker has closed. This is carried out by an NC auxiliary contact of the circuit
breaker or by the closing order to the breaker.
Function block name: SOTF- IEC 60617 graphical symbol:
ANSI number:
IEC 61850 logical node name:
ZPSOF
179
Automatic switch onto fault logic (PSOF) Chapter 5
Distance protection
The internal automatic activation is controlled by the internal dead line detection (DLD) func-
tion. The function gives an internal output signal DLD when the current and voltage for each
phase is below the setting parameter IPh< and UPh<, see figure 92. The SOTF function will be
activated if the signal is present for more than 200 ms at the same time as the non-directional
impedance starting signal NDACC is not activated.
The SOTF function can be blocked by the activation of a SOTF-BLOCK functional input.
Figure 92: Dead line detection function in SOTF
en05000737.vsd
1<2
Iph_L1
IPh<
1<2
Uph_L1
UPh<
1<2
Iph_L2
IPh<
1<2
Uph_L2
UPh<
1<2
Iph_L3
IPh<
1<2
Uph_L3
UPh<
AND SOTF-DLD
1
2
1
2
1
2
1
2
1
2
1
2
AND
AND
AND
180
Automatic switch onto fault logic (PSOF) Chapter 5
Distance protection
4.3 Function block
Figure 93: SOTF function block
4.4 Input and output signals
Table 89: Input signals for the ZPSOF (SOTF-) function block
Table 90: Output signals for the ZPSOF (SOTF-) function block
4.5 Setting parameters
Table 91: Parameter group settings for the ZPSOF (SOTF-) function
ZPSOF
SOTF-
I3P
U3P
BLOCK
BC
NDACC
TRIP
en05000377.vsd
Signal Description
I3P Group signal for current input
U3P Group signal for voltage input
BLOCK Block of function
BC Enabling of SOTF
NDACC Non Directional Zone to be accelerated by SOTF
Signal Description
TRIP Trip output
Parameter Range Step Default Unit Description
Operation Off
On
- On - Operation Off / On
IBase 1 - 99999 1 3000 A Base setting for current
levels
UBase 0.05 - 2000.00 0.05 400.00 kV Base setting for voltage
levels
IPh< 1 - 100 1 20 %IB Current level for detec-
tion of dead line in % of
IBase
UPh< 1 - 100 1 70 %UB Voltage level for detec-
tion of dead line in % of
UBase
181
Automatic switch onto fault logic (PSOF) Chapter 5
Distance protection
4.6 Technical data
Table 92: Automatic switch onto fault logic (PSOF)
Parameter Range or value Accuracy
Operate voltage, detection of dead line (1100)% of U
base
1.0% of U
r
Operate current, detection of dead line (1100)% of I
base
1.0% of I
r
Delay following dead line detection input before SOTF
function is automatically enabled
200 ms 0.5% 10 ms
Time period after circuit breaker closure in which
SOTF function is active
1000 ms 0.5% 10 ms
182
Automatic switch onto fault logic (PSOF) Chapter 5
Distance protection
183
About this chapter Chapter 6
Current protection
Chapter 6 Current protection
About this chapter
This chapter describes current protection functions. These include functions like Instantaneous
phase overcurrent protection, Four step phase overcurrent protection, Pole discordance protec-
tion and Residual overcurrent protection.
184
Instantaneous phase overcurrent protection
(PIOC, 50)
Chapter 6
Current protection
1 Instantaneous phase overcurrent protection
(PIOC, 50)
1.1 Introduction
The instantaneous three phase overcurrent function has a low transient overreach and short trip-
ping time to allow use as a high set short-circuit protection function, with the reach limited to
less than typical eighty percent of the power transformer at minimum source impedance.
1.2 Principle of operation
The sampled analogue phase currents are pre-processed in a discrete Fourier filter (DFT) block.
From the fundamental frequency components of each phase current the RMS value of each
phase current is derived. These phase current values are fed to the IOC function. In a comparator
the RMS values are compared to the set operation current value of the function (IP>>). If a
phase current is larger than the set operation current a signal from the comparator for this phase
is set to true. This signal will, without delay, activate the output signal TRLn (n=1,2,3) for this
phase and the TRIP signal that is common for all three phases.
There is an operation mode (OpMode) setting: 1 out of 3 or 2 out of 3. If the parameter is
set to 1 out of 3 any phase trip signal will be activated. If the parameter is set to 2 out of 3
at least two phase signals must be activated for trip.
There is also a possibility to activate a preset change of the set operation current (StValMult) via
a binary input (ENMULT). In some applications the operation value needs to be changed, for
example due to transformer inrush currents.
The function can be blocked from the binary input BLOCK.
1.3 Function block
Figure 94: IOC function block
Function block name: IOCx- IEC 60617 graphical symbol:
ANSI number: 50
IEC 61850 logical node name:
PHPIOC
3I>>
PHPIOC
IOC1-
I3P
BLOCK
ENMULT
TRIP
TRL1
TRL2
TRL3
en04000391.vsd
185
Instantaneous phase overcurrent protection
(PIOC, 50)
Chapter 6
Current protection
1.4 Input and output signals
Table 93: Input signals for the PHPIOC_50 (IOC1-) function block
Table 94: Output signals for the PHPIOC_50 (IOC1-) function block
1.5 Setting parameters
Table 95: Parameter group settings for the PHPIOC_50 (IOC1-) function
1.6 Technical data
Table 96: Instantaneous phase overcurrent protection (PIOC, 50)
Signal Description
I3P Group signal for current input
BLOCK Block of function
ENMULT Enable current start value multiplier
Signal Description
TRIP Trip signal from any phase
TRL1 Trip signal from phase L1
TRL2 Trip signal from phase L2
TRL3 Trip signal from phase L3
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
IBase 1 - 99999 1 3000 A Base setting for current
values
OpMode 2 out of 3
1 out of 3
- 1 out of 3 - Select operation mode
2-out of 3 / 1-out of 3
IP>> 1 - 2500 1 200 %IB Operate phase current
level in % of IBase
StValMult 0.5 - 5.0 0.1 1.0 - Multiplier for operate cur-
rent level
Function Range or value Accuracy
Operate current (1-2500)% of l
base
1.0% of I
r
at I I
r
1.0% of I at I >I
r
Reset ratio >95% -
Operate time 25 ms typically at 0 to 2 x I
set
-
Reset time 25 ms typically at 2 to 0 x I
set
-
186
Instantaneous phase overcurrent protection
(PIOC, 50)
Chapter 6
Current protection
Critical impulse time 10 ms typically at 0 to 2 x I
set
-
Operate time 10 ms typically at 0 to 10 x I
set
-
Reset time 35 ms typically at 10 to 0 x I
set
-
Critical impulse time 2 ms typically at 0 to 10 x I
set
-
Dynamic overreach <5% at =100 ms -
Function Range or value Accuracy
187
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
2 Four step phase overcurrent
protection (POCM, 51/67)
2.1 Introduction
The four step three phase overcurrent function has an inverse or definite time delay independent
for each step separately.
All IEC and ANSI time delayed characteristics are available together with an optional user de-
fined time characteristic.
The function can be set to be directional or non-directional independently for each of the steps.
2.2 Principle of operation
The function is divided into four different sub-functions, one for each step. For each step an op-
eration mode is set (DirModen): Off/Non-directional/Forward/Reverse.
The protection design can be decomposed in four parts:
The direction element, indicates the over current fault direction
The harmonic Restraint Blocking function
The 4 step over current function
The Mode Selection
Function block name: TOCx- IEC 60617 graphical symbol:
ANSI number: 51/67
IEC 61850 logical node name:
PH4POCM
4
4
alt
3I>
188
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
Figure 95: Functional overview of TOC.
A common setting for all steps, StPhaseSel, is used to specify the number of phase currents to
be high to enable operation. The settings can be chosen: 1 out of 3, 2 out of 3 or 3 out of 3.
The sampled analogue phase currents are pre-processed in a discrete Fourier filter (DFT) block.
From the fundamental frequency components of each phase current the RMS value of each
phase current is derived. These phase current values are fed to the TOC function. In a compara-
tor, for each phase current, the RMS values are compared to the set operation current value of
the function (I1>, I2>, I3>or I4>). If a phase current is larger than the set operation current a
signal from the comparator for this phase and step is set to true. This signal will, without delay,
activate the output signal Start for this phase/step, the Start signal common for all three phases
for this step and a common Start signal.
A harmonic restrain of the function can be chosen. A set 2
nd
harmonic current in relation to the
fundamental current is used. The 2
nd
harmonic current is taken from the pre-processing of the
phase currents and compared to a set restrain current level.
en05000740.vsd
Direction
Element
4 step over current
element
One element for each
step
Harmonic
Restraint
Mode Selection
dirPh1Flt
dirPh2Flt
dirPh3Flt
harmRestrBlock
enableDir
enableStep1-4
DirectionalMode1-4
faultState
Element
faultState
I3P
U3P
I3P
START
TRIP
189
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
The function can use a directional option. The direction of the fault current is given as current
angle in relation to the voltage angle. The fault current and fault voltage for the directional func-
tion is dependent of the fault type. To enable directional measurement at close in faults, causing
low measured voltage, the polarization voltage is a combination of the apparent voltage (80%)
and a memory voltage (20%). The following combinations are used.
The directional setting is given as a characteristic angle AngleRCA for the function and an angle
window AngleRCA-maxFwdAng to AngleRCA+minFwdAng.
Phase-phase short circuit:
Phase-earth short circuit:
1 2 1 2 1 2 1 2
= =
refL L L L dirL L L L
U U U I I I
2 3 2 3 2 3 2 3
= =
refL L L L dirL L L L
U U U I I I
3 1 3 1 3 1 3 1
= =
refL L L L dirL L L L
U U U I I I
1 1 1 1
= =
refL L dirL L
U U I I
2 2 2 2
= =
refL L dirL L
U U I I
3 3 3 3
= =
refL L dirL L
U U I I
190
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
Figure 96: Directional characteristic of the phase overcurrent protection
The default value of AngleRCA is 65. The parameters minFwdAng and maxFwdAng gives the
angle sector from AngleRCA for directional borders.
A minimum current for directional phase start current signal can be set: IminOpPhSel.
If no blockings are given the start signals will start the timers of the step. The time characteristic
for each step can be chosen as definite time delay or some type of inverse time characteristic. A
wide range of standardized inverse time characteristics is available. It is also possible to create
a tailor made time characteristic. The possibilities for inverse time characteristics are described
in chapter 19 "Time inverse characteristics".
Different types of reset time can be selected as described in chapter19 "Time inverse character-
istics".
There is also a possibility to activate a preset change (InMult, n=1, 2, 3 or 4) of the set operation
current via a binary input (enable multiplier). In some applications the operation value needs to
be changed, for example due to changed network switching state. The function can be blocked
from the binary input BLOCK. The start signals from the function can be blocked from the bi-
nary input BLKST. The trip signals from the function can be blocked from the binary input
BLKTR.
U
ref
I
dir
RCA
minFwdAng
Forward
Reverse
maxFwdAng
en05000745.vsd
191
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
2.3 Function block
Figure 97: TOC function block
PH4POCM
TOC1-
I3P
U3P
BLOCK
BLKTR
BLKST1
BLKST2
BLKST3
BLKST4
ENMULT1
ENMULT2
ENMULT3
ENMULT4
TRIP
TR1
TR2
TR3
TR4
TRL1
TRL2
TRL3
TR1L1
TR1L2
TR1L3
TR2L1
TR2L2
TR2L3
TR3L1
TR3L2
TR3L3
TR4L1
TR4L2
TR4L3
START
ST1
ST2
ST3
ST4
STL1
STL2
STL3
ST1L1
ST1L2
ST1L3
ST2L1
ST2L2
ST2L3
ST3L1
ST3L2
ST3L3
ST4L1
ST4L2
ST4L3
2NDHARM
DIRL1
DIRL2
DIRL3
en05000708.vsd
192
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
2.4 Input and output signals
Table 97: Input signals for the PH4POCM_51_67 (TOC1-) function block
Table 98: Output signals for the PH4POCM_51_67 (TOC1-) function block
Signal Description
I3P Group signal for current input
U3P Group signal for voltage input
BLOCK Block of function
BLKTR Block of trip
BLKST1 Block of Step1
BLKST2 Block of Step2
BLKST3 Block of Step3
BLKST4 Block of Step4
ENMULT1 When activated, the current multiplier is in use for step1
ENMULT2 When activated, the current multiplier is in use for step2
ENMULT3 When activated, the current multiplier is in use for step3
ENMULT4 When activated, the current multiplier is in use for step4
Signal Description
TRIP Trip
TR1 Common trip signal from step1
TR2 Common trip signal from step2
TR3 Common trip signal from step3
TR4 Common trip signal from step4
TRL1 Trip signal from phase L1
TRL2 Trip signal from phase L2
TRL3 Trip signal from phase L3
TR1L1 Trip signal from step1 phase L1
TR1L2 Trip signal from step1 phase L2
TR1L3 Trip signal from step1 phase L3
TR2L1 Trip signal from step2 phase L1
TR2L2 Trip signal from step2 phase L2
TR2L3 Trip signal from step2 phase L3
TR3L1 Trip signal from step3 phase L1
TR3L2 Trip signal from step3 phase L2
TR3L3 Trip signal from step3 phase L3
TR4L1 Trip signal from step4 phase L1
TR4L2 Trip signal from step4 phase L2
TR4L3 Trip signal from step4 phase L3
START General start signal
193
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
2.5 Setting parameters
Table 99: Parameter group settings for the PH4POCM_51_67 (TOC1-) function
ST1 Common start signal from step1
ST2 Common start signal from step2
ST3 Common start signal from step3
ST4 Common start signal from step4
STL1 Start signal from phase L1
STL2 Start signal from phase L2
STL3 Start signal from phase L3
ST1L1 Start signal from step1 phase L1
ST1L2 Start signal from step1 phase L2
ST1L3 Start signal from step1 phase L3
ST2L1 Start signal from step2 phase L1
ST2L2 Start signal from step2 phase L2
ST2L3 Start signal from step2 phase L3
ST3L1 Start signal from step3 phase L1
ST3L2 Start signal from step3 phase L2
ST3L3 Start signal from step3 phase L3
ST4L1 Start signal from step4 phase L1
ST4L2 Start signal from step4 phase L2
ST4L3 Start signal from step4 phase L3
2NDHARM Block from second harmonic detection
DIRL1 Direction for phase1
DIRL2 Direction for phase2
DIRL3 Direction for phase3
Signal Description
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
IBase 1 - 99999 1 3000 - Base setting for current
values
UBase 0.05 - 2000.00 0.05 400.00 kV Base setting for voltage
levels in kV
MaxFwdAng 40.0 - 70.0 0.1 50.0 Deg Maximum forward angle
MinFwdAng 75.0 - 90.0 0.1 80.0 Deg Minimum forward angle
AngleRCA -70.0 - -50.0 1.0 -65.0 Deg Relay characteristic
angle (RCA)
194
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
IMinOpPhSel 1 - 100 1 7 %IB Minimum current for
phase selection in % of
IBase
StartPhSel Not Used
1 out of 3
2 out of 3
3 out of 3
- 1 out of 3 - Number of phases
required for op (1 of 3, 2
of 3, 3 of 3)
2ndHarmStab 5 - 100 1 20 %IB Operate level of 2nd
harm restrain op in % of
Fundamental
DirMode1 Off
Non-directional
Forward
Reverse
- Non-directional - Directional mode of step
1 (off, nodir, forward,
reverse)
Characterist1 ANSI Ext. inv.
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
- ANSI Def. Time - Selection of time delay
curve type for step 1
I1> 1 - 2500 1 1000 %IB Operate phase current
level for step1 in % of
IBase
t1 0.000 - 60.000 0.001 0.000 s Independent (defenitive)
time delay of step 1
k1 0.05 - 999.00 0.01 0.05 - Time multiplier for the
dependent time delay for
step 1
I1Mult 1.0 - 10.0 0.1 2.0 - Multiplier for operate cur-
rent level for step 1
t1Min 0.000 - 60.000 0.001 0.000 s Minimum operate time for
IEC IDMT curves for step
1
ResetTypeCrv1 Instantaneous
IEC Reset
ANSI reset
- Instantaneous - Selection of reset curve
type for step 1
Parameter Range Step Default Unit Description
195
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
tReset1 0.000 - 60.000 0.001 0.020 s Reset time delay used in
IEC Definite Time curve
step 1
tPCrv1 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 1
tACrv1 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve for step 1
tBCrv1 0.00 - 20.00 0.01 0.00 - Parameter B for cus-
tomer programmable
curve for step 1
tCCrv1 0.1 - 10.0 0.1 1.0 - Parameter C for cus-
tomer programmable
curve for step 1
tPRCrv1 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve for step 1
tTRCrv1 0.005 - 100.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve for step 1
tCRCrv1 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for step 1
HarmRestrain1 Disabled
Enabled
- Enabled - Enable block of step 1
from harmonic restrain
DirMode2 Off
Non-directional
Forward
Reverse
- Non-directional - Directional mode of step
2 (off, nodir, forward,
reverse)
Characterist2 ANSI Ext. inv.
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
- ANSI Def. Time - Selection of time delay
curve type for step 2
Parameter Range Step Default Unit Description
196
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
I2> 1 - 2500 1 500 %IB Operate phase current
level for step2 in % of
IBase
t2 0.000 - 60.000 0.001 0.400 s Independent (defenitive)
time delay of step 2
k2 0.05 - 999.00 0.01 0.05 - Time multiplier for the
dependent time delay for
step 2
I2Mult 1.0 - 10.0 0.1 2.0 - Multiplier for scaling the
current setting value for
step 2
t2Min 0.000 - 60.000 0.001 0.000 s Minimum operate time for
IEC IDMT curves for step
2
ResetTypeCrv2 Instantaneous
IEC Reset
ANSI reset
- Instantaneous - Selection of reset curve
type for step 2
tReset2 0.000 - 60.000 0.001 0.020 s Reset time delay used in
IEC Definite Time curve
step 2
tPCrv2 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 2
tACrv2 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve for step 2
tBCrv2 0.00 - 20.00 0.01 0.00 - Parameter B for cus-
tomer programmable
curve for step 2
tCCrv2 0.1 - 10.0 0.1 1.0 - Parameter C for cus-
tomer programmable
curve for step 2
tPRCrv2 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve for step 2
tTRCrv2 0.005 - 100.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve for step 2
tCRCrv2 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for step 2
HarmRestrain2 Disabled
Enabled
- Enabled - Enable block of step 2
from harmonic restrain
DirMode3 Off
Non-directional
Forward
Reverse
- Non-directional - Directional mode of step
3 (off, nodir, forward,
reverse)
Parameter Range Step Default Unit Description
197
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
Characterist3 ANSI Ext. inv.
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
- ANSI Def. Time - Selection of time delay
curve type for step 3
I3> 1 - 2500 1 250 %IB Operate phase current
level for step3 in % of
IBase
t3 0.000 - 60.000 0.001 0.800 s Independent (definitive)
time delay for step 3
k3 0.05 - 999.00 0.01 0.05 - Time multiplier for the
dependent time delay for
step 3
I3Mult 1.0 - 10.0 0.1 2.0 - Multiplier for scaling the
current setting value for
step 3
t3Min 0.000 - 60.000 0.001 0.000 s Minimum operate time for
IEC IDMT curves for step
3
ResetTypeCrv3 Instantaneous
IEC Reset
ANSI reset
- Instantaneous - Selection of reset curve
type for step 3
tReset3 0.000 - 60.000 0.001 0.020 s Reset time delay used in
IEC Definite Time curve
step 3
tPCrv3 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 3
tACrv3 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve for step 3
tBCrv3 0.00 - 20.00 0.01 0.00 - Parameter B for cus-
tomer programmable
curve for step 3
Parameter Range Step Default Unit Description
198
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
tCCrv3 0.1 - 10.0 0.1 1.0 - Parameter C for cus-
tomer programmable
curve for step 3
tPRCrv3 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve for step 3
tTRCrv3 0.005 - 100.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve for step 3
tCRCrv3 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for step 3
HarmRestrain3 Disabled
Enabled
- Enabled - Enable block of step3
from harmonic restrain
DirMode4 Off
Non-directional
Forward
Reverse
- Non-directional - Directional mode of step
4 (off, nodir, forward,
reverse)
Characterist4 ANSI Ext. inv.
ANSI Very inv.
ANSI Norm. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
- ANSI Def. Time - Selection of time delay
curve type for step 4
I4> 1 - 2500 1 175 %IB Operate phase current
level for step4 in % of
IBase
t4 0.000 - 60.000 0.001 2.000 s Independent (definitive)
time delay of step4
k4 0.05 - 999.00 0.01 0.05 - Time multiplier for the
dependent time delay for
step 4
I4Mult 1.0 - 10.0 0.1 2.0 - Multiplier for scaling the
current setting value for
step 4
Parameter Range Step Default Unit Description
199
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
2.6 Technical data
Table 100: Four step phase overcurrent protection (POCM, 51/67)
t4Min 0.000 - 60.000 0.001 0.000 s Minimum operate time for
IEC IDMT curves for step
4
ResetTypeCrv4 Instantaneous
IEC Reset
ANSI reset
- Instantaneous - Selection of reset curve
type for step 4
tReset4 0.000 - 60.000 0.001 0.020 s Reset time delay used in
IEC Definite Time curve
step 4
tPCrv4 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 4
tACrv4 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve for step 4
tBCrv4 0.00 - 20.00 0.01 0.00 - Parameter B for cus-
tomer programmable
curve for step 4
tCCrv4 0.1 - 10.0 0.1 1.0 - Parameter C for cus-
tomer programmable
curve for step 4
tPRCrv4 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve for step 4
tTRCrv4 0.005 - 100.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve for step 4
tCRCrv4 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for step 4
HarmRestrain4 Disabled
Enabled
- Enabled - Enable block of Step 4
from harmonic restrain
Parameter Range Step Default Unit Description
Function Setting range Accuracy
Operate current (1-2500)% of l
base
1.0% of I
r
at I I
r
1.0% of I at I >I
r
Reset ratio >95% -
Min. operating current (1-100)% of l
base
1.0% of I
r
Directional angle in 2
nd
quadrant (100-150) degrees 2.0 degrees
Directional angle in 4
th
quadrant (5-40) degrees 2.0 degrees
Second harmonic blocking (5100)% of fundamental 2.0% of I
r
Independent time delay (0.000-60.000) s 0.5% 10 ms
200
Four step phase overcurrent
protection (POCM, 51/67)
Chapter 6
Current protection
Minimum operate time (0.000-60.000) s 0.5% 10 ms
Inverse characteristics, see
table 398 and table 399
19 curve types See table 398 and table 399
Operate time, start function 25 ms typically at 0 to 2 x I
set
-
Reset time, start function 25 ms typically at 2 to 0 x I
set
-
Critical impulse time 10 ms typically at 0 to 2 x I
set
-
Impulse margin time 15 ms typically -
Function Setting range Accuracy
201
Instantaneous residual overcurrent protection
(PIOC, 50N)
Chapter 6
Current protection
3 Instantaneous residual overcurrent protection
(PIOC, 50N)
3.1 Introduction
The single input overcurrent function has a low transient overreach and short tripping times to
allow use as a high set short circuit protection function, with the reach limited to less than typical
eighty percent of the power transformer at minimum source impedance. The function can be
configured to measure the residual current from the three phase current inputs or the current
from a separate current input.
3.2 Principle of operation
The sampled analogue residual currents are pre-processed in a discrete Fourier filter (DFT)
block. From the fundamental frequency components of the residual current the RMS value is de-
rived. This current value is fed to the IEF function. In a comparator the RMS value is compared
to the set operation current value of the function (IN>>). If the residual current is larger than the
set operation current a signal from the comparator is set to true. This signal will, without delay,
activate the output signal TRIP.
There is also a possibility to activate a preset change of the set operation current via a binary
input (enable multiplier MULTEN). In some applications the operation value needs to be
changed, for example due to transformer inrush currents.
The function can be blocked from the binary input BLOCK. The trip signals from the function
can be blocked from the binary input BLKAR, that can be activated during single pole trip and
autoreclosing sequences.
Function block name: IEFx- IEC 60617 graphical symbol:
ANSI number: 50N
IEC 61850 logical node name:
EFPIOC
IN>>
202
Instantaneous residual overcurrent protection
(PIOC, 50N)
Chapter 6
Current protection
3.3 Function block
Figure 98: IEF function block
3.4 Input and output signals
Table 101: Input signals for the EFPIOC_50N (IEF1-) function block
Table 102: Output signals for the EFPIOC_50N (IEF1-) function block
3.5 Setting parameters
Table 103: Parameter group settings for the EFPIOC_50N (IEF1-) function
EFPIOC
IEF1-
I3P
BLOCK
BLKAR
MULTEN
TRIP
en04000393.vsd
Signal Description
I3P Group signal for current input
BLOCK Block of function
BLKAR Block input for auto reclose
MULTEN Enable current multiplier
Signal Description
TRIP Trip signal
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
IBase 1 - 99999 1 3000 A Base setting for current
values
IN>> 1 - 2500 1 200 %IB Operate residual current
level in % of IBase
StValMult 0.5 - 5.0 0.1 1.0 - Multiplier for operate cur-
rent level
203
Instantaneous residual overcurrent protection
(PIOC, 50N)
Chapter 6
Current protection
3.6 Technical data
Table 104: Instantaneous residual overcurrent protection (PIOC, 50N)
Function Range or value Accuracy
Operate current (1-2500)% of l
base
1.0% of I
r
at I I
r
1.0% of I at I >I
r
Reset ratio >95% -
Operate time 25 ms typically at 0 to 2 x I
set
-
Reset time 25 ms typically at 2 to 0 x I
set
-
Critical impulse time 10 ms typically at 0 to 2 x I
set
-
Operate time 10 ms typically at 0 to 10 x I
set
-
Reset time 35 ms typically at 10 to 0 x I
set
-
Critical impulse time 2 ms typically at 0 to 10 x I
set
-
Dynamic overreach <5% at =100 ms -
204
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
4 Four step residual overcurrent
protection (PEFM, 51N/67N)
4.1 Introduction
The four step single input overcurrent function has an inverse or definite time delay independent
for each step separately.
All IEC and ANSI time delayed characteristics are available together with an optional user de-
fined characteristic.
The function can be set to be directional, forward, reverse or non-directional independently for
each of the steps.
A second harmonic blocking can be set individually for each step.
The function can be used as main protection for phase to earth faults.
The function can be configured to measure the residual current from the three phase current in-
puts or the current from a separate current input.
4.2 Principle of operation
The function is divided into four different sub-functions, one for each step. For each step an op-
eration modem DirModen is set: Off/Non-directional/Forward/Reverse.
The protection design can be decomposed in four parts:
The direction element, indicate earth current fault direction. The directional
check uses 3I
0
cos(-
RCA
) for comparison
The harmonic Restraint Blocking function
4 step over current function
Switch On To Fault function (SOTF), including Under Time
Mode Selection
Blocking at parallel transformers
Function block name: TEFx- IEC 60617 graphical symbol:
ANSI number:51N/ 67N
IEC 61850 logical node name:
EF4PEFM
4
4
alt
IN
205
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
Figure 99: Functional overview of TEF
The sampled analog residual current is pre-processed in a discrete Fourier filter (DFT) block.
From the fundamental frequency component the RMS value of the residual current is derived.
This residual current value is fed to the TEF function. In a comparator the RMS value is com-
pared to the set operation current value of the function (IN1>, IN2>, IN3> or IN4>). If the re-
sidual current is larger than the set operation current a signal from the comparator for this step
is set to true. This signal will, without delay, activate the output signal Start for this step and a
common Start signal.
A harmonic restrain of the function can be chosen. A set 2
nd
harmonic current in relation to the
fundamental current is used. The 2
nd
harmonic current is taken from the pre-processing of the
phase currents and compared to a set restrain current level.
The function can use a directional option. A fault is in the forward direction if the residual cur-
rent component 3I
0
cos(-
RCA
) is larger than a set level. The angle is the angle between the
residual current and the polarizing voltage (3U
0
). The angle is defined positive when the resid-
ual current lags the reference voltage. The AngleRCA is the characteristic angle of the directional
function.
en05000741.vsd
Direction
Element
4 step over current
element
One element for each
step
Harmonic
Restraint
Mode
Selection
earthFaultDirection
harmRestrBlock
enableDir
enableStep1-4
DirectionalMode1-4
TRIP
Element
enableDir
angleValid
Directional Check
operatingCurrent
SwitchOnToFault
start step 2, 3 and
4
signal to
communication
scheme
TRIP
3U0
3I0
Blocking at parallel
transformers
1
CB
pos
or cmd
Element
3I0
206
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
Figure 100: Characteristic of the directional option
If no blockings are given the start signals will start the timers of the step. The time characteristic
for each step can be chosen as definite time delay or some type of inverse time characteristic. A
wide range of standardized inverse time characteristics is available. It is also possible to create
a tailor made time characteristic. The possibilities for inverse time characteristics are described
in Chapter 19 "Time inverse characteristics".
Different types of reset time can be selected as described in Chapter 19 "Time inverse charac-
teristics".
There is also a possibility to activate a preset change (INxMult, x =1, 2, 3 or 4) of the set oper-
ation current via a binary input (enable multiplier MULTEN). In some applications the operation
value needs to be changed, for example due to changed network switching state.
In case of parallel transformers there is a risk of sympathetic inrush current. If one of the trans-
formers is in operation, and the parallel transformer is switched in, the asymmetric inrush cur-
rent of the switched in transformer will cause partial saturation of the transformer already in
service. This is called transferred saturation. The 2
nd
harmonic of the inrush currents of the two
transformers will be in phase opposition. The summation of the two currents will thus give a
small 2
nd
harmonic current. The residual fundamental current will however be significant. The
inrush current of the transformer in service before the parallel transformer energizing, will be a
little delayed compared to the first transformer. Therefore we will have high 2
nd
harmonic cur-
rent initially. After a short period this current will however be small and the normal 2
nd
harmonic
blocking will reset. If the BlkParTransf function is activated the 2
nd
harmonic restrain signal will
latched as long as the residual current measured by the relay is larger than a selected step current
level.
Upol =-3U
0
IN>Dir
RCA
Operation
en05000285.vsd
207
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
The function can be blocked from the binary input BLOCK. The start signals from the function
can be blocked from the binary input BLKST. The trip signals from the function can be blocked
from the binary input BLKTR.
4.2.1 Switch onto fault logic
Integrated in the four step residual overcurrent protection are Switch on to fault logic (SOTF)
and undertime logic. The parameter SOFT is set to activate either SOTF or undertime function
or both. When the circuit breaker is closing there is a risk to close energize a permanent fault,
for example during an autoreclosing sequence. The SOTF function will enable fast fault clear-
ance during such situations. The time the SOTF/Undertime function will be active after activa-
tion is set by the parameter t4U.
The SOFT function uses the start signal from step 2 or 3, which is set by parameter
Step3ForSOTF. The function is activated from change in circuit breaker position or from circuit
breaker close command pulse. The parameter ActivationSOTF can be set for activation of CB
position open change, CB position closed change or CB close command. In case of a residual
current start from step 2 or 3 (dependent on setting) the function will give a trip after a set delay
tSOTF. This delay is normally set to a short time (default 100 ms).
The undertime function uses the start signal from step 4. The function will normally be set to a
lower current level than the SOTF function. The undertime function can also be blocked by the
2nd harmonic restrain function. This enables high sensitivity even if power transformer inrush
currents can occur. The detection of unsymmetrical CB poles after switching is thus possible.
The function is activated from change in circuit breaker position or from circuit breaker close
and open command pulse. This is set by parameter ActUnderTime. The parameter ActUnder-
Time can be set for activation of CB position change or CB close/open command. In case of a
residual current start from step 4 the function will give a trip after a set delay tUnderTime. This
delay is normally set to a relatively short time (default 300 ms).
4.3 Function block
Figure 101: TEF function block
EF4PEFM
TEF1-
BLOCK
I3P
BLKTR
U3P
BLKST1
BLKST2
BLKST3
BLKST4
ENMULT1
ENMULT2
ENMULT3
ENMULT4
CBPOS
CLOSECB
OPENCB
TRIP
TRIN1
TRIN2
TRIN3
TRIN4
TRSOTF
START
STIN1
STIN2
STIN3
STIN4
STSOTF
STFW
STRV
2NDHARMD
en04000395.vsd
208
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
4.4 Input and output signals
Table 105: Input signals for the EF4PEFM_51N67N (TEF1-) function block
Table 106: Output signals for the EF4PEFM_51N67N (TEF1-) function block
Signal Description
BLOCK Block of function
I3P Group signal for current input
BLKTR Block of trip
U3P Group signal for voltage input
BLKST1 Block of step 1 (Start and trip)
BLKST2 Block of step 2 (Start and trip)
BLKST3 Block of step 3 (Start and trip)
BLKST4 Block of step 4 (Start and trip)
ENMULT1 When activated, the current multiplier is in use for step1
ENMULT2 When activated, the current multiplier is in use for step2
ENMULT3 When activated, the current multiplier is in use for step3
ENMULT4 When activated, the current multiplier is in use for step4
CBPOS Breaker position
CLOSECB Breaker close command
OPENCB Breaker open command
Signal Description
TRIP Trip
TRIN1 Trip signal from step 1
TRIN2 Trip signal from step 2
TRIN3 Trip signal from step 3
TRIN4 Trip signal from step 4
TRSOTF Trip signal from earth fault switch onto fault function
START General start signal
STIN1 Start signal step 1
STIN2 Start signal step 2
STIN3 Start signal step 3
STIN4 Start signal step 4
STSOTF Start signal from earth fault switch onto fault function
STFW Forward directional start signal
STRV Reverse directional start signal
2NDHARMD 2nd harmonic block signal
209
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
4.5 Setting parameters
Table 107: Parameter group settings for the EF4PEFM_51N67N (TEF1-) function
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation mode Off / On
IBase 1 - 99999 1 3000 A Base setting for current
values
UBase 0.05 - 2000.00 0.05 400.00 kV Base setting for voltage
level in kV
IMinOpFund 1 - 2500 1 3 %IB Minimum fundamental
frequency current level in
% of IBase
AngleRCA -180 - 180 1 65 Deg Relay characteristic
angle (RCA)
3UO>Dir 1 - 100 1 5 %UB Minimum polarizing
quantity in % of UBase
IN>DirCmp 1 - 100 1 3 %IB Operate residual current
level for DirComp in % of
IBase
tDirCmp 0.000 - 60.000 0.001 10.000 s Time delay for DirComp
2ndHarmStab 5 - 100 1 20 % Second harmonic
restrain operation in % of
INAMPL
UseStartValue IN1>
IN2>
IN3>
IN4>
- IN1> - Current level blk at paral-
lel transf (step1, 2, 3 or 4)
BlkParTransf Off
On
- Off - Enable blocking at paral-
lel transformers
ActivationSOTF Open
Closed
CloseCommand
- Open - Select signal that shall
activate SOTF
SOTF Off
SOTF
UnderTime
SOTF+UnderTime
- Off - SOFT operation mode
(Off/SOTF/Under-
time/SOTF+undertime)
tSOTF 0.000 - 60.000 0.001 0.100 s Time delay for SOTF
HarmResSOTF Disabled
Enabled
- Disabled - Enable harmonic restrain
functionin SOTF
t4U 0.000 - 60.000 0.001 5.000 s Switch-onto-fault active
time
ActUnderTime CB position
CB command
- CB position - Select signal to activate
under time (CB
Pos/CBCommand)
tUnderTime 0.000 - 60.000 0.001 0.300 s Time delay for under time
210
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
DirMode1 Off
Non-directional
Forward
Reverse
- Non-directional - Directional mode of step
1 (off, nodir, forward,
reverse)
Characterist1 ANSI Ext. inv.
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
- ANSI Def. Time - Selection of time delay
curve type for step 1
IN1> 1 - 2500 1 100 %IB Operate residual current
level for step 1 in % of
IBase
t1 0.000 - 60.000 0.001 0.000 s Independent (defenite)
time delay of step 1
k1 0.05 - 999.00 0.01 0.05 - Time multiplier for the
dependent time delay for
step 1
IN1Mult 1.0 - 10.0 0.1 2.0 - Multiplier for scaling the
current setting value for
step 1
t1Min 0.000 - 60.000 0.001 0.000 s Minimum operate time for
IEC IDMT curves for step
1
ResetTypeCrv1 Instantaneous
IEC Reset
ANSI reset
- Instantaneous - Selection of reset curve
type for step 1
tReset1 0.000 - 60.000 0.001 0.020 s Reset time delay used in
IEC Definite Time curve
step 1
HarmRestrain1 Disabled
Enabled
- Enabled - Enable block of step 1
from harmonic restrain
tPCrv1 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 1
Parameter Range Step Default Unit Description
211
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
tACrv1 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve for step 1
tBCrv1 0.00 - 20.00 0.01 0.00 - Parameter B for cus-
tomer programmable
curve for step 1
tCCrv1 0.1 - 10.0 0.1 1.0 - Parameter C for cus-
tomer programmable
curve for step 1
tPRCrv1 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve for step 1
tTRCrv1 0.005 - 100.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve for step 1
tCRCrv1 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for step 1
DirMode2 Off
Non-directional
Forward
Reverse
- Non-directional - Directional mode of step
2 (off, nodir, forward,
reverse)
Characterist2 ANSI Ext. inv.
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
- ANSI Def. Time - Selection of time delay
curve for step 2
IN2> 1 - 2500 1 50 %IB Operate residual current
level for step 2 in % of
IBase
t2 0.000 - 60.000 0.001 0.400 s Independent (definitive)
time delay of step 2
k2 0.05 - 999.00 0.01 0.05 - Time multiplier for the
dependent time delay for
step 2
Parameter Range Step Default Unit Description
212
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
IN2Mult 1.0 - 10.0 0.1 2.0 - Multiplier for scaling the
current setting value for
step 2
t2Min 0.000 - 60.000 0.001 0.000 s Minimum operate time for
IEC IDMT curves step 2
ResetTypeCrv2 Instantaneous
IEC Reset
ANSI reset
- Instantaneous - Reset mode when cur-
rent drops off step 2
tReset2 0.000 - 60.000 0.001 0.020 s Selection of reset curve
type for step 2
HarmRestrain2 Disabled
Enabled
- Enabled - Enable block of step 2
from harmonic restrain
tPCrv2 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 2
tACrv2 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve for step 2
tBCrv2 0.00 - 20.00 0.01 0.00 - Parameter B for cus-
tomer programmable
curve for step 2
tCCrv2 0.1 - 10.0 0.1 1.0 - Parameter C for cus-
tomer programmable
curve for step 2
tPRCrv2 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve for step 2
tTRCrv2 0.005 - 100.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve for step 2
tCRCrv2 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for step 2
DirMode3 Off
Non-directional
Forward
Reverse
- Non-directional - Directional mode of step
3 (off, nodir, forward,
reverse)
Parameter Range Step Default Unit Description
213
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
Characterist3 ANSI Ext. inv.
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
- ANSI Def. Time - Time delay curve type for
step 3
IN3> 1 - 2500 1 33 %IB Operate residual current
level for step 3 in % of
IBase
t3 0.000 - 60.000 0.001 0.800 s Independent time delay
of step 3
k3 0.05 - 999.00 0.01 0.05 - Time multiplier for the
dependent time delay for
step 3
IN3Mult 1.0 - 10.0 0.1 2.0 - Multiplier for scaling the
current setting value for
step 3
t3Min 0.000 - 60.000 0.001 0.000 s Minimum operate time for
IEC IDMT curves for step
3
ResetTypeCrv3 Instantaneous
IEC Reset
ANSI reset
- Instantaneous - Selection of reset curve
type for step 3
tReset3 0.000 - 60.000 0.001 0.020 s Reset time delay used in
IEC Definite Time curve
for step 3
HarmRestrain3 Disabled
Enabled
- Enabled - Enable block of step 3
from harmonic restrain
tPCrv3 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 3
tACrv3 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve for step 3
tBCrv3 0.00 - 20.00 0.01 0.00 - Parameter B for cus-
tomer programmable
curve for step 3
Parameter Range Step Default Unit Description
214
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
tCCrv3 0.1 - 10.0 0.1 1.0 - Parameter C for cus-
tomer programmable
curve step 3
tPRCrv3 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve step 3
tTRCrv3 0.005 - 100.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve step 3
tCRCrv3 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for step 3
Step3ForSOTF step 2 init
step 3 init
- step 2 init - Select step3 to be con-
nected to SOTF
DirMode4 Off
Non-directional
Forward
Reverse
- Non-directional - Directional mode of step
4 (off, nodir, forward,
reverse)
Characterist4 ANSI Ext. inv.
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Reserved
Programmable
RI type
RD type
- ANSI Def. Time - Time delay curve type for
step 4
IN4> 1 - 2500 1 17 %IB Operate residual current
level for step 4 in % of
IBase
t4 0.000 - 60.000 0.001 1.200 s Independent (definitive)
time delay of step 4
k4 0.05 - 999.00 0.01 0.05 - Time multiplier for the
dependent time delay for
step 4
IN4Mult 1.0 - 10.0 0.1 2.0 - Multiplier for scaling the
current setting value for
step 4
Parameter Range Step Default Unit Description
215
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
4.6 Technical data
Table 108: Four step residual overcurrent protection (PEFM, 51N/67N)
t4Min 0.000 - 60.000 0.001 0.000 s Minimum operate time in
IEC IDMT modes step 4
ResetTypeCrv4 Instantaneous
IEC Reset
ANSI reset
- Instantaneous - Selection of reset curve
type for step 4
tReset4 0.000 - 60.000 0.001 0.020 s Reset time delay used in
IEC Definite Time curve
for step 4
HarmRestrain4 Disabled
Enabled
- Enabled - Enable block of step 4
from harmonic restrain
tPCrv4 0.005 - 3.000 0.001 1.000 - Parameter P for cus-
tomer programmable
curve for step 4
tACrv4 0.005 - 200.000 0.001 13.500 - Parameter A for cus-
tomer programmable
curve step 4
tBCrv4 0.00 - 20.00 0.01 0.00 - Parameter B for cus-
tomer programmable
curve for step 4
tCCrv4 0.1 - 10.0 0.1 1.0 - Parameter C for cus-
tomer programmable
curve step 4
tPRCrv4 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve step 4
tTRCrv4 0.005 - 100.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve step 4
tCRCrv4 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve step 4
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Operate current (1-2500)% of l
base
1.0% of I
r
at I I
r
1.0% of I at I >I
r
Reset ratio >95% -
Operate current for directional
comparison
(1100)% of l
base
1.0% of I
r

Timers (0.000-60.000) s 0.5% 10 ms
Inverse characteristics, see table
398 and table 399
19 curve types See table 398 and table 399
Second harmonic restrain opera-
tion
(5100)% of fundamental 2.0% of I
r
216
Four step residual overcurrent
protection (PEFM, 51N/67N)
Chapter 6
Current protection
Relay characteristic angle (-180 to 180) degrees 2.0 degrees
Minimum polarizing voltage (1100)% of U
base
1.0% of U
r
Operate time, start function 25 ms typically at 0 to 2 x I
set
-
Reset time, start function 25 ms typically at 2 to 0 x I
set
-
Critical impulse time 10 ms typically at 0 to 2 x I
set
-
Impulse margin time 15 ms typically -
Function Range or value Accuracy
217
Thermal overload protection, two time
constants (PTTR, 49)
Chapter 6
Current protection
5 Thermal overload protection, two time constants
(PTTR, 49)
5.1 Introduction
If the temperature of a power transformer reaches too high values the equipment might be dam-
aged. The insulation within the transformer will have forced ageing. As a consequence of this
the risk of internal phase to phase or phase to earth faults will increase. High temperature will
degrade the quality of the transformer oil.
The thermal overload protection estimates the internal heat content of the transformer (temper-
ature) continuously. This estimation is made by using a thermal model of the transformer with
two time constants, which is based on current measurement.
Two warning levels are available. This enables actions in the power system to be done before
dangerous temperatures are reached. If the temperature continues to increase to the trip value,
the protection initiates trip of the protected transformer.
5.2 Principle of operation
The sampled analogue phase currents are pre-processed and for each phase current the RMS val-
ue of each phase current is derived. These phase current values are fed to the THL function.
From the largest of the three phase currents a relative final temperature (heat content) is calcu-
lated according to the expression:
(Equation 28)
If this calculated relative temperature is larger than the relative temperature level corresponding
to the set operate (trip) current a start output signal START is activated.
Function block name: TTRx- IEC 60617 graphical symbol:
ANSI number: 49
IEC 61850 logical node name:
TRPTTR
where:
I is the largest phase current and
I
ref
is a given reference current
2
final
ref
I
I

=



218
Thermal overload protection, two time
constants (PTTR, 49)
Chapter 6
Current protection
The actual temperature at the actual execution cycle is calculated as:
The calculated transformer relative temperature can be monitored as it is exported from the func-
tion as a real figure HEATCONT.
When the transformer temperature reaches any of the set alarm levels Alarm1 or Alarm2 the cor-
responding output signal ALARM1 or ALARM2 is set. When the component temperature
reaches the set trip level which corresponds to continuous current equal to ITrip the output signal
TRIP is set.
There is also a calculation of the present time to operation with the present current. This calcu-
lation is only performed if the final temperature is calculated to be above the operation temper-
ature:
(Equation 31)
The calculated time to trip can be monitored as it is exported from the function as a real figure
TTRIP.
If
(Equation 29)
If
(Equation 30)
where:

n
is the calculated present temperature,

n-1
is the calculated temperature at the previous time step,

final
is the calculated final (steady state) temperature with the actual current,
t is the time step between calculation of the actual temperature and
is the set thermal time constant for the protected transformer
final n
>
( )
1 1
1
t
n n final n
e



= +


final n
<
( )
1
t
n final final n
e

=
ln
final operate
operate
final n
t

=




219
Thermal overload protection, two time
constants (PTTR, 49)
Chapter 6
Current protection
After a trip, caused by the thermal overload protection function, there can be a lockout to recon-
nect the tripped circuit. The output lockout signal LOCKOUT is activated when the device tem-
perature is above the set lockout release temperature setting ResLo.
The time to lockout release is calculated, i.e. a calculation of the cooling time to a set value.
(Equation 32)
Here the final temperature is equal to the set or measured ambient temperature. The calculated
component temperature can be monitored as it is exported from the function as a real figure.
When the current is so high that it has given a start signal START, the estimated time to trip is
continuously calculated and given as analogue output TTRIP. If this calculated time get less than
the setting time Warning, set in minutes, the output WARNING is activated.
In case of trip a pulse with a set duration tPulse is activated.
_
_
ln
final lockout release
lockout release
final n
t

=




220
Thermal overload protection, two time
constants (PTTR, 49)
Chapter 6
Current protection
Figure 102: Functional overview of TTR
Calculation
of final
temperature
I3P
Calculation
of heat
content
Final Temp
>TripTemp
actual heat comtent
Actual Temp >
Alarm1,Alarm2
Temp
Actual Temp
>TripTemp
ALARM1
TRIP
Actual Temp
<Recl
Temp
START
Calculation
of time to
trip
Calculation
of time to
reset of
lockout
time to trip
time to reset of lockout
Management of
setting
parameters: Tau,
IBase
Current base used
Binary input:
Forced cooling
On/Off
Tau used
ALARM2
warning if time to trip <set value
en05000833.vsd
S
R
LOCKOUT
221
Thermal overload protection, two time
constants (PTTR, 49)
Chapter 6
Current protection
5.3 Function block
Figure 103: TTR function block
5.4 Input and output signals
Table 109: Input signals for the TRPTTR_49 (TTR1-) function block
Table 110: Output signals for the TRPTTR_49 (TTR1-) function block
en05000320.vsd
TRPTTR
TTR1-
I3P
BLOCK
COOLING
ENMULT
RESET
TRIP
START
ALARM1
ALARM2
LOCKOUT
WARNING
Signal Description
I3P Group signal for current input
BLOCK Block of function
COOLING Cooling input Off / On. Changes Ib setting and time constant
ENMULT Enable Multiplier for currentReference setting
RESET Reset of function
Signal Description
TRIP Trip Signal
START Start signal
ALARM1 First level alarm signal
ALARM2 Second level alarm signal
LOCKOUT Lockout signal
WARNING Warning signal: Trip within set warning time
222
Thermal overload protection, two time
constants (PTTR, 49)
Chapter 6
Current protection
5.5 Setting parameters
Table 111: Parameter group settings for the TRPTTR_49 (TTR1-) function
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
IBase 1 - 99999 1 3000 A Base current in A
IRef 10.0 - 1000.0 1.0 100.0 %IB Reference current in % of
IBASE
IRefMult 0.01 - 10.00 0.01 1.00 - Multiplication Factor for
reference current
IBase1 30.0 - 250.0 1.0 100.0 %IB Base current,IBase1
without Cooling inpout in
% of IBASE
IBase2 30.0 - 250.0 1.0 100.0 %IB Base Current,IBase2,
with Cooling input ON in
% of IBASE
Tau1 1.0 - 500.0 1.0 60.0 Min Time constant without
cooling input in min, with
IBase1
Tau2 1.0 - 500.0 1.0 60.0 Min Time constant with cool-
ing input in min, with
IBase2
IHighTau1 30.0 - 250.0 1.0 100.0 %IB1 Current Sett, in % of
IBase1 for rescaling TC1
by TC1-IHIGH
Tau1High 5 - 2000 1 100 %tC1 Multiplier in % to TC1
when current is >
IHIGH-TC1
ILowTau1 30.0 - 250.0 1.0 100.0 %IB1 Current Set, in % of
IBase1 for rescaling TC1
by TC1-ILOW
Tau1Low 5 - 2000 1 100 %tC1 Multiplier in % to TC1
when current is <
ILOW-TC1
IHighTau2 30.0 - 250.0 1.0 100.0 %IB2 Current Set, in % of
IBase2 for rescaling TC2
by TC2-IHIGH
Tau2High 5 - 2000 1 100 %tC2 Multiplier in % to TC2
when current is
>IHIGH-TC2
ILowTau2 30.0 - 250.0 1.0 100.0 %IB2 Current Set, in % of
IBase2 for rescaling TC2
by TC2-ILOW
Tau2Low 5 - 2000 1 100 %tC2 Multiplier in % to TC2
when current is <
ILOW-TC2
ITrip 50.0 - 250.0 1.0 110.0 %IBx Steady state operate cur-
rent level in % of IBasex
223
Thermal overload protection, two time
constants (PTTR, 49)
Chapter 6
Current protection
5.6 Technical data
Table 112: Thermal overload protection, two time constants (PTTR, 49)
Alarm1 50.0 - 99.0 1.0 80.0 %Itr First alarm level in % of
heat content trip value
Alarm2 50.0 - 99.0 1.0 90.0 %Itr Second alarm level in %
of heat content trip value
ResLo 10.0 - 95.0 1.0 60.0 %Itr Lockout reset level in %
of heat content trip value
ThetaInit 0.0 - 95.0 1.0 50.0 % Initial Heat content, in %
of heat content trip value
Warning 1.0 - 500.0 0.1 30.0 Min Time setting, below
which warning would be
set (in min)
tPulse 0.01 - 0.30 0.01 0.10 s Length of the pulse for
trip signal (in msec).
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Base current 1 and 2 (30250)% of I
base
1.0% of I
r

Operate time:
I =I
measured
I
p
=load current before
overload occurs
Time constant =(1500) min-
utes
IEC 602558, class 5 +200 ms
Alarm level 1 and 2 (5099)% of heat content trip
value
2.0% of heat content trip
Operate current (50250)% of I
base
1.0% of I
r
Reset level temperature (1095)% of heat content trip 2.0% of heat content trip
2 2
2 2
ln
p
b
I I
t
I I


224
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
6 Breaker failure protection (RBRF, 50BF)
6.1 Introduction
The circuit breaker failure function ensures fast back-up tripping of surrounding breakers.
A current check with extremely short reset time is used as a check criteria to achieve a high se-
curity against unnecessary operation.
The unit can be single- or three-phase started to allow use with single phase tripping applica-
tions. The current criteria can be set to two out of four e.g. two phases or one phase plus the re-
sidual current to achieve a higher security.
The function can be programmed to give single- or three phase re-trip of the own breaker to
avoid unnecessary tripping of surrounding breakers at an incorrect starting due to mistakes dur-
ing testing.
6.2 Principle of operation
The breaker failure protection function is initiated from protection trip command, either from
protection functions within the protection terminal or from external protection devices.
The start signal can be phase selective or general (for all three phases). Phase selective start sig-
nals enable single pole re-trip function. This means that a second attempt to open the breaker is
done. The re-trip attempt can be made after a set time delay. For transmission lines single pole
trip and autoreclosing is often used. The re-trip function can be phase selective if it is initiated
from phase selective line protection. The re-trip function can be done with or without current
check. With the current check the re-trip is only performed if the current through the circuit
breaker is larger than the operate current level.
The start signal can be an internal or external protection trip signal. If this start signal gets high
at the same time as current is detected through the circuit breaker, the back-up trip timer is start-
ed. If the opening of the breaker is successful this is detected by the function, both by detection
of low RMS current and by a special adapted algorithm. The special algorithm enables a very
fast detection of successful breaker opening, i.e. fast resetting of the current measurement. If the
current detection has not detected breaker opening before the back-up timer has run its time a
back-up trip is initiated. There is also a possibility to have a second back-up trip output activated
after an added settable time after the first back-up trip.
Further the following possibilities are available:
Function block name: BFPx- IEC 60617 graphical symbol:
ANSI number: 50BF
IEC 61850 logical node name:
CCRBRF
3I>BF
225
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
The length of the re-trip pulse, the back-up trip pulse and the back-up trip pulse
2 are settable.
In the current detection it is possible to use three different options: 1 out of 3
where it is sufficient to detect failure to open (high current) in one pole, 1 out of
4 where it is sufficient to detect failure to open (high current) in one pole or high
residual current and 2 out of 4 where at least two current (phase current and/or
residual current) shall be high for breaker failure detection.
The current detection for the residual current can be set different from the setting
of phase current detection.
It is possible to have different re-trip time delays for single phase faults and for
multi-phase faults.
The back-up trip can be made without current check. It is possible to have this
option activated for small load currents only.
It is possible to have instantaneous back-up trip function if a signal is high if the
circuit breaker is insufficient to clear faults, for example at low gas pressure.
Figure 104: Simplified logic scheme of the retrip function
en05000832.vsd
STIL1
START
STL1
AND
AND
BLOCK
AND
CBCLDL1
Current
AND
Current &
Contact
AND
AND
Contact
t
t1 tp
TRRETL1
L2 L3
TRRET
OR
OR
226
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
Figure 105: Simplified logic scheme of the back-up trip function
227
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
Figure 106: Simplified logic scheme of the back-up trip function
6.3 Function block
Figure 107: BFP function block
6.4 Input and output signals
Table 113: Input signals for the CCRBRF_50BF (BFP1-) function block
CCRBRF
BFP1-
I3P
BLOCK
START
STL1
STL2
STL3
CBCLDL1
CBCLDL2
CBCLDL3
CBFLT
TRBU
TRBU2
TRRET
TRRETL1
TRRETL2
TRRETL3
CBALARM
en04000397.vsd
Signal Description
I3P Group signal for current input
BLOCK Block of function
START Three phase start of breaker failure protection function
STL1 Start signal of phase L1
STL2 Start signal of phase L2
228
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
Table 114: Output signals for the CCRBRF_50BF (BFP1-) function block
6.5 Setting parameters
Table 115: Parameter group settings for the CCRBRF_50BF (BFP1-) function
STL3 Start signal of phase L3
CBCLDL1 Circuit breaker closed in phase L1
CBCLDL2 Circuit breaker closed in phase L2
CBCLDL3 Circuit breaker closed in phase L3
CBFLT CB faulty, unable to trip. Back-up trip instantanously.
Signal Description
TRBU Back-up trip by breaker failure protection function
TRBU2 Second back-up trip by breaker failure protection function
TRRET Retrip by breaker failure protection function
TRRETL1 Retrip by breaker failure protection function phase L1
TRRETL2 Retrip by breaker failure protection function phase L2
TRRETL3 Retrip by breaker failure protection function phase L3
CBALARM Alarm for faulty circuit breaker
Signal Description
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
IBase 1 - 99999 1 3000 A Base setting for current
level settings
FunctionMode Current
Contact
Current&Contact
- Current - Detection for back-up trip
Current/Cont/Current and
Cont
BuTripMode 2 out of 4
1 out of 3
1 out of 4
- 1 out of 3 - Back-up trip mode, 2 out
of 4, 1 out of 3 or 1 out of
4
RetripMode Retrip Off
I>Check
No I>Check
- Retrip Off - Operation mode of re-trip
logic: OFF/I>check/No I>
check
IP> 5 - 200 1 10 %IB Operate level in % of
IBase
I>BlkCont 5 - 200 1 20 %IB Current for blocking of
CB contact operation in
% of IBase
IN> 2 - 200 1 10 %IB Operate residual level in
% of IBase
t1 0.000 - 60.000 0.001 0.000 s Time delay of re-trip
229
Breaker failure protection (RBRF, 50BF) Chapter 6
Current protection
6.6 Technical data
Table 116: Breaker failure protection (RBRF, 50BF)
t2 0.000 - 60.000 0.001 0.150 s Time delay of back-up
trip
t2MPh 0.000 - 60.000 0.001 0.150 s Time delay of back-up
trip at multi-phase start
t3 0.000 - 60.000 0.001 0.030 s Additional time delay to
t2 for a second back-up
trip
tCBAlarm 0.000 - 60.000 0.001 5.000 s Time delay for CB faulty
signal
tPulse 0.000 - 60.000 0.001 0.200 s Trip pulse duration
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Operate phase current (5-200)% of l
base
1.0% of I
r
at I I
r
1.0% of I at I >I
r
Reset ratio, phase current >95% -
Operate residual current (2-200)% of l
base
1.0% of I
r
at I I
r
1.0% of I at I >I
r
Reset ratio, residual current >95% -
Phase current level for blocking of
contact function
(5-200)% of l
base
1.0% of I
r
at I I
r
1.0% of I at I >I
r
Reset ratio >95% -
Timers (0.000-60.000) s 0.5% 10 ms
Operate time for current detection 10 ms typically -
Reset time for current detection 15 ms maximum -
230
Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
7 Pole discordance protection (RPLD, 52PD)
7.1 Introduction
Single pole operated circuit breakers can due to electrical or mechanical failures end up with the
different poles in different positions (close-open). This can cause negative and zero sequence
currents which gives thermal stress on rotating machines and can cause unwanted operation of
zero sequence current functions.
Normally the own breaker is tripped to correct the positions. If the situation consists the remote
end can be intertripped to clear the unsymmetrical load situation.
The pole discordance function operates based on information from auxiliary contacts of the cir-
cuit breaker for the three phases with additional criteria from unsymmetrical phase current when
required.
7.2 Principle of operation
The detection of pole discordance can be made in two different ways. If the contact based func-
tion is used an external logic can be made by connecting the auxiliary contacts of the circuit
breaker so that a pole discordance is indicated. This is shown in figure 108
Figure 108: Pole discordance external detection logic
Function block name: PDx-- IEC 60617 graphical symbol:
ANSI number: 50PD
IEC 61850 logical node name:
CCRPLD
PD
poleDiscordance Signal from C.B.
+
C.B.
231
Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
This single binary signal is connected to a binary input of the IED. The appearance of this signal
will start a timer that will give a trip signal after the set delay.
There is also a possibility to connect all phase selective auxiliary contacts (phase contact open
and phase contact closed) to binary inputs of the IED. This is shown in figure 109
Figure 109: Pole discordance signals for internal logic
In this case the logic is realized within the function. If the inputs are indicating pole discordance
the trip timer is started. This timer will give a trip signal after the set delay.
Pole discordance can also be detected by means of phase selective current measurement. The
sampled analogue phase currents are pre-processed in a discrete Fourier filter (DFT) block.
From the fundamental frequency components of each phase current the RMS value of each
phase current is derived. These phase current values are fed to the PD function. The difference
between the smallest and the largest phase current is derived. If this difference is larger than a
set ratio the trip timer is started. This timer will give a trip signal after the set delay. The current
based pole discordance function can be set to be active either continuously or only directly in
connection to breaker open or close command.
The function also has a binary input that can be configured from the autoreclosing function, so
that the pole discordance function can be blocked during sequences with a single pole open if
single pole autoreclosing is used.
The simplified block diagram of the current and contact based pole discordance function is
shown in figure 110.
poleTwoOpened from C.B.
+
C.B.
poleOneOpened from C.B.
poleThreeClosed from C.B.
poleTwoClosed from C.B.
poleOneClosed from C.B.
poleThreeOpened from C.B.
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Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
Figure 110: Simplified block diagram of pole discordance function - contact and current based
The pole discordance function is disabled if:
The terminal is in TEST mode (TEST-ACTIVE is high) and the function has
been blocked from the HMI (BlockPD=Yes)
The input signal BLOCK is high
The input signal BLKDBYAR is high
The BLOCK signal is a general purpose blocking signal of the pole discordance function. It can
be connected to a binary input of the terminal in order to receive a block command from external
devices or can be software connected to other internal functions of the terminal itself in order to
receive a block command from internal functions. Through OR gate it can be connected to both
binary inputs and internal function outputs.
The BLKDBYAR signal blocks the pole discordance operation when a single phase autoreclos-
ing cycle is in progress. It can be connected to the output signal AR01-1PT1 if the autoreclosing
function is integrated in the terminal; if the autoreclosing function is an external device, then
BLKDBYAR has to be connected to a binary input of the terminal and this binary input is con-
nected to a signalization 1phase autoreclosing in progress from the external autoreclosing de-
vice.
If the pole discordance function is enabled, then two different criteria will generate a trip signal
TRIP:
Pole discordance signalling from the circuit breaker.
Unsymmetrical current detection.
en05000747.vsd
OR
BLOCK
BLKDBYAR
POLE1OPN
POLE1CL
POLE2OPN
POLE2CL
POLE3OPN
POLE3CL
Discordance
detection
PolPosAuxCont
AND
PolPosAuxCont
AND
EXTPDIND
Unsymmetry current
detection
OR
CLOSECMD
OPENCMD
t+200 ms
AND
OR
AND
TRIP
t
t 150 ms
233
Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
7.2.1 Pole discordance signalling from circuit breaker
If one or two poles of the circuit breaker have failed to open or to close (pole discordance status),
then the function input EXTPDIND is activated from the pole discordance signal derived from
the circuit breaker auxiliary contacts (one NO contact for each phase connected in parallel, and
in series with one NC contact for each phase connected in parallel) and, after a settable time in-
terval t (0-60 s), a 150 ms trip pulse command TRIP is generated by the pole discordance func-
tion.
7.2.2 Unsymmetrical current detection
Unsymmetrical current detection is based on checking that:
any phase current is lower than 80% of the highest current in the remaining two
phases
the highest phase current is greater than 10% of the rated current
If these conditions are true, an unsymmetrical condition is detected and the internal signal INPS
is turned high. This detection is enabled to generate a trip after a set time delay t (0-60 s) if the
detection occurs in the next 200 ms after the circuit breaker has received a command to open trip
or close and if the unbalance persists. The 200 ms limitation is for avoiding unwanted operation
during unsymmetrical load conditions.
The pole discordance function is informed that a trip or close command has been given to the
circuit breaker through the inputs CLOSECMD (for closing command information) and
OPENCMD (for opening command information). These inputs can be connected to terminal bi-
nary inputs if the information are generated from the field (i.e. from auxiliary contacts of the
close and open push buttons) or may be software connected to the outputs of other integrated
functions (i.e. close command from a control function or a general trip from integrated protec-
tions).
7.3 Function block
Figure 111: PD function block
CCRPLD
PD01-
I3P
BLOCK
BLKDBYAR
CLOSECMD
OPENCMD
EXTPDIND
POLE1OPN
POLE1CL
POLE2OPN
POLE2CL
POLE3OPN
POLE3CL
TRIP
START
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Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
7.4 Input and output signals
Table 117: Input signals for the CCRPLD_52PD (PD01-) function block
Table 118: Output signals for the CCRPLD_52PD (PD01-) function block
7.5 Setting parameters
Table 119: Parameter group settings for the CCRPLD_52PD (PD01-) function
Signal Description
I3P Group signal for current input
BLOCK Block of function
BLKDBYAR Block of function at CB single phase auto re-closing cycle
CLOSECMD Close order to CB
OPENCMD Open order to CB
EXTPDIND Pole discordance signal from CB logic
POLE1OPN Pole one opened indication from CB
POLE1CL Pole one closed indication from CB
POLE2OPN Pole two opened indication from CB
POLE2CL Pole two closed indication from CB
POLE3OPN Pole three opened indication from CB
POLE3CL Pole three closed indication from CB
Signal Description
TRIP Trip signal to CB
START Trip condition TRUE, waiting for time delay
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
IBase 1 - 99999 1 3000 A Base setting for current
levels
235
Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
7.6 Technical data
Table 120: Pole discordance protection (RPLD, 52PD)
TimeDelayTrip 0.000 - 60.000 0.001 0.300 s Time delay between trip
condition and trip signal
ContSel Off
PD signal from CB
Pole pos aux cont.
- Off - Contact function selec-
tion
CurrSel Off
CB oper monitor
Continuous moni-
tor
- Off - Current function selection
CurrUnsymLevel 0 - 100 1 80 % Unsym magn of lowest
phase current compared
to the highest.
CurrRelLevel 0 - 100 1 10 %IB Current magnitude for
release of the function in
% of IBase
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Operate current (0100% of I
base
1.0% of I
r
Time delay (0.000-60.000) s 0.5% 10 ms
236
Pole discordance protection (RPLD, 52PD) Chapter 6
Current protection
237
About this chapter Chapter 7
Voltage protection
Chapter 7 Voltage protection
About this chapter
This chapter describes voltage related protection functions. The way the functions work, their
setting parameters, function blocks, input and output signals and technical data are included for
each function.
238
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
1 Two step undervoltage protection (PUVM, 27)
1.1 Introduction
Undervoltages can occur in the power system during faults or abnormal conditions. The function
can be used to open circuit breakers to prepare for system restoration at power outages or as
long-time delayed back-up to primary protection.
The function has two voltage steps, each with inverse or definite time delay.
1.2 Principle of operation
The two-step undervoltage protection function (TUV) is used to detect low power system volt-
age. The function has two voltage measuring steps with separate time delays. If one, two or three
phase voltages decrease below the set value, a corresponding start signal is issued. TUV can be
set to start/trip based on "one out of three", "two out of three", or "three out of three" of the mea-
sured phase voltages, being below the set point. If the phase voltage remains below the set value
for a time period corresponding to the chosen time delay, the corresponding trip signal is issued.
To avoid an unwanted trip due to disconnection of the related high voltage equipment, a voltage
controlled blocking of the function is available, i.e. if the voltage is lower than the set blocking
level the function is blocked and no start or trip signal is issued. The time delay characteristic is
individually chosen for each step and can be either definite time delay or inverse time delay.
The voltage related settings are made in percent of the base voltage, which is set in kV,
phase-phase.
The undervoltage protection function measures the phase to earth voltages, if the voltage trans-
former is connected phase to earth to the analogue voltage inputs. The setting of the analogue
inputs are given as primary phase to phase voltage and secondary phase to phase voltage. The
function will operate if the phase to earth voltage gets lover than the set percentage of the phase
to earth voltage corresponding to the set base voltage UBase. This means operation for phase to
earth voltage under:
(Equation 33)
Function block name: TUVx- IEC 60617 graphical symbol:
ANSI number: 27
IEC 61850 logical node name:
PH2PUVM
3U<
(%) ( )
3
U UBase kV <
239
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
If the voltage transformer is connected phase to phase to the analogue input, the setting of the
analogue inputs are given as primary phase to phase voltage and secondary phase to phase volt-
age divided by 3. The function will operate if the phase to phase voltage gets lover than the set
percentage of the phase to phase voltage corresponding to the set base voltage UBase.
1.2.1 Measurement principle
All the three phase to earth voltages are measured continuously, and compared with the set val-
ues, U1< and U2<. The parameters OpMode1 and OpMode2 influence the requirements to ac-
tivate the start outputs. Either "1 out of 3", "2 out of 3" or "3 out of 3" phases have to be lower
than the corresponding set point to issue the corresponding start signal.
To avoid oscillations of the output start signal, a hysteresis has been included.
1.2.2 Time delay
The time delay for the two steps can be either definite time delay (DT) or inverse time delay (ID-
MT). For the inverse time delay three different modes are available; inverse curve A, inverse
curve B, and a programmable inverse curve.
The type A curve is described as:
(Equation 34)
The type B curve is described as:
(Equation 35)
The programmable curve can be created as:
(Equation 36)
k
t
U U
U
=
<

<

2.0
480
0.055
32 0.5
k
t
U U
U

= +
<


<

p
k A
t D
U U
B C
U


= +

<



<

240
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
When the denominator in the expression is equal to zero the time delay will be infinity. There
will be an undesired discontinuity. Therefore a tuning parameter CrvSatn is set to compensate
for this phenomenon. In the voltage interval U< down to U< *(1.0 CrvSatn/100) the used volt-
age will be: U< *(1.0 CrvSatn/100). If the programmable curve is used this parameter must be
calculated so that:
(Equation 37)
The lowest phase voltage is always used for the inverse time delay integration, see figure112.
The details of the different inverse time characteristics are shown in section 3 "Inverse charac-
teristics".
Figure 112: Voltage used for the inverse time characteristic integration
Trip signal issuing requires that the undervoltage condition continues for at least the user set
time delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and by
some special voltage level dependent time curves for the inverse time mode (IDMT). If the start
condition, with respect to the measured voltage ceases during the delay time, and is not fulfilled
again within a user defined reset time (tReset1 and tReset2 for the definite time and tIReset1 and
tIReset2 for the inverse time) the corresponding start output is reset. Here it should be noted that
after leaving the hysteresis area, the start condition must be fulfilled again and it is not sufficient
for the signal to only return back to the hysteresis area. Note that for the undervoltage function
0
100
CrvSatn
B C >
Vol tage
IDMT Vol tage
Ti me
UL1
UL2
UL3
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241
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
the IDMT reset time is constant and does not depend on the voltage fluctuations during the
drop-off period. However, there are three ways to reset the timer, either the timer is reset instan-
taneously, or the timer value is frozen during the reset time, or the timer value is linearly de-
creased during the reset time. See figure113 and figure114.
242
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
Figure 113: Voltage profile not causing a reset of the start signal for step 1, and definite time
delay
Vol tage
Ti me
Hyst eresi s
START
TRIP
U1<
START
TRIP
t1
tReset
1
Ti me
Ti me
Integrat or
t1
Froozen Timer
Linear Decrease
Instantaneous
Reset
Measured
Vol tage
tReset
1
en05000010.vsd
243
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
Figure 114: Voltage profile causing a reset of the start signal for step 1, and definite time delay
1.2.3 Blocking
The undervoltage function can be partially or totally blocked, by binary input signals or by pa-
rameter settings, where:
Voltage
Time
Hysteresis
START
TRIP
START
U1<
START
TRIP
t1
tReset1
Time
Time Integrator
t1
Froozen Timer
Linear Decrease
Instantaneous
Reset
Measured Voltage
tReset1
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244
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
If the measured voltage level decreases below the setting of IntBlkStVal1, either the trip output
of step 1, or both the trip and the start outputs of step 1, are blocked. The characteristic of the
blocking is set by the IntBlkSel1 parameter. This internal blocking can also be set to "off" result-
ing in no voltage based blocking. Corresponding settings and functionality are valid also for step
2.
In case of disconnection of the high voltage component the measured voltage will get very low.
The event will start both the under voltage function and the blocking function, as seen in figure
115. The delay of the blocking function must be set less than the time delay of under voltage
function.
BLOCK: blocks all outputs
BLKTR1: blocks all trip outputs of step 1
BLKST1: blocks all start and trip outputs related to step 1
BLKTR2: blocks all trip outputs of step 2
BLKST2: blocks all start and trip outputs related to step 2
245
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
Figure 115: Blocking function.
1.2.4 Design
The voltage measuring elements continuously measure the phase-to-neutral voltages in all three
phases. Recursive Fourier filters filter the input voltage signals. The phase voltages are individ-
ually compared to the set value, and the lowest phase voltage is used for the inverse time char-
acteristic integration. A special logic is included to achieve the "1 out of 3", "2 out of 3" and "3
out of 3" criteria to fulfill the start condition. The design of the TimeUnderVoltage function is
schematically described in figure116.
Time
U
Normal voltage
U1<
U2<
IntBlkStVal1
IntBlkStVal2
Disconnection
tBlkUV1 <
t1,t1Min
tBlkUV2 <
t2,t2Min
Block step 1
Block step 2
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246
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
Figure 116: Schematic design of the TUV function
en05000012.vsd
START
ST1L1
ST1L2
ST1L3
TR1L1
TR1L2
TR1L3
ST1
TR1
START
ST2L1
ST2L2
ST2L3
TR2L1
TR2L2
TR2L3
ST2
TR2
TRIP
Comparator
UL1 <U1<
Comparator
UL2 <U1<
Comparator
UL3 <U1<
MinVoltSelect
or
Comparator
UL1 <U2<
Comparator
UL2 <U2<
Comparator
UL3 <U2<
MinVoltSelect
or
Start
&
Trip
Output
Logic
Step 1
Start
&
Trip
Output
Logic
Step 2
Phase 3
Phase 2
Phase 1
Phase 3
Phase 2
Phase 1
Time integrator
t2
tReset2
ResetTypeCrv2
Voltage Phase
Selector
OpMode2
1 out of 3
2 outof 3
3 out of 3
Time integrator
t1
tReset1
ResetTypeCrv1
Voltage Phase
Selector
OpMode1
1 out of 3
2 out of 3
3 out of 3
UL1
UL2
UL3
TRIP
TRIP
OR
OR
OR
OR
OR
OR
START
247
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
1.3 Function block
Figure 117: TUV function block
1.4 Input and output signals
Table 121: Input signals for the PH2PUVM_27 (TUV1-) function block
Table 122: Output signals for the PH2PUVM_27 (TUV1-) function block
PH2PUVM
TUV1-
U3P
BLOCK
BLKTR1
BLKST1
BLKTR2
BLKST2
TRIP
TR1
TR1L1
TR1L2
TR1L3
TR2
TR2L1
TR2L2
TR2L3
START
ST1
ST1L1
ST1L2
ST1L3
ST2
ST2L1
ST2L2
ST2L3
en05000330.vsd
Signal Description
U3P Group signal for voltage input
BLOCK Block of function
BLKTR1 Block of operate signal, step 1
BLKST1 Block of step 1
BLKTR2 Block of operate signal, step 2
BLKST2 Block of step 2
Signal Description
TRIP Operate signal
TR1 Operate signal for step 1
TR1L1 Operate signal for phase 1, step 1
TR1L2 Operate signal for phase 2, step 1
TR1L3 Operate signal for phase 3, step 1
TR2 Operate signal for step 2
TR2L1 Operate signal for phase 1, step 2
TR2L2 Operate signal for phase 2, step 2
TR2L3 Operate signal for phase 3, step 2
248
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
1.5 Setting parameters
Table 123: Parameter group settings for the PH2PUVM_27 (TUV1-) function
START Start signal
ST1 Start signal for step1
ST1L1 Start signal for phase 1, step 1
ST1L2 Start signal for phase 2, step 1
ST1L3 Start signal for phase 3, step 1
ST2 Start signal for step 2
ST2L1 Start signal for phase 1, step 2
ST2L2 Start signal for phase 2, step 2
ST2L3 Start signal for phase 3, step 2
Signal Description
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage,
phase-phase in kV
Characterist1 Definite time
Inverse curve A
Inverse curve B
Prog. inv. curve
- Definite time - Operation characteristic
selection, step 1
OpMode1 1 out of 3
2 out of 3
3 out of 3
- 1 out of 3 - Operation Mode, 1 out of
3 / 2 out of 3 / 3 out of 3,
step 1
U1< 1 - 100 1 70 %UB Voltage setting/start val
(DT & IDMT) in % of
UBase, step 1
t1 0.000 - 60.000 0.001 5.000 s Operate time delay in DT
mode, step 1.
tReset1 0.000 - 60.000 0.001 0.025 s Time delay in DT reset
(s), step 1
t1Min 0.000 - 60.000 0.001 5.000 s Minimum operate time in
IDMT mode (s), step 1
ResetTypeCrv1 Instantaneous
Frozen timer
Linearly decreased
- Instantaneous - IDMT mode reset type
selector, step 1
tIReset1 0.000 - 60.000 0.001 0.025 s Time delay in IDMT reset
(s), step 1
k1 0.05 - 1.10 0.01 0.05 - Time multiplier in IDMT
mode, step 1
ACrv1 0.005 - 200.000 0.001 1.000 - Setting A for programma-
ble under voltage IDMT
curve, step 1
249
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
BCrv1 0.50 - 100.00 0.01 1.00 - Setting B for programma-
ble under voltage IDMT
curve, step 1
CCrv1 0.0 - 1.0 0.1 0.0 - Setting C for programma-
ble under voltage IDMT
curve, step 1
DCrv1 0.000 - 60.000 0.001 0.000 - Setting D for programma-
ble under voltage IDMT
curve, step 1
PCrv1 0.000 - 3.000 0.001 1.000 - Setting P for programma-
ble under voltage IDMT
curve, step 1
CrvSat1 0 - 100 1 0 % Tuning param for prog.
under voltage IDMT
curve, step 1
IntBlkSel1 Off
Block of trip
Block all
- Off - Internal (low level) block-
ing mode, step 1
IntBlkStVal1 1 - 100 1 20 %UB Voltage setting for inter-
nal blocking in % of
UBase, step 1
tBlkUV1 0.000 - 60.000 0.001 0.000 s Time delay of internal
(low level) blocking for
step 1
HystAbs1 0.0 - 100.0 0.1 0.5 %UB Absolute hysteresis in %
of UBase, step 1
HystAbsIntBlk1 0.0 - 100.0 0.1 0.5 %UB Abs hysteresis for inter-
nal blocking in % of
UBase, step 1
Characterist2 Definite time
Inverse curve A
Inverse curve B
Prog. inv. curve
- Definite time - Operation characteristic
selection, step 2
OpMode2 1 out of 3
2 out of 3
3 out of 3
- 1 out of 3 - Operation Mode, 1 out of
3 / 2 out of 3 / 3 out of 3,
step 2
U2< 1 - 100 1 50 %UB Voltage setting/start val
(DT & IDMT) in % of
UBase, step 2
t2 0.000 - 60.000 0.001 5.000 s Operate time delay in DT
mode, step 2
tReset2 0.000 - 60.000 0.001 0.025 s Time delay in DT reset
(s), step 2
t2Min 0.000 - 60.000 0.001 5.000 s Minimum operate time in
IDMT mode (s), step 2
ResetTypeCrv2 Instantaneous
Frozen timer
Linearly decreased
- Instantaneous - IDMT mode reset type
selector, step 2
Parameter Range Step Default Unit Description
250
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
tIReset2 0.000 - 60.000 0.001 0.025 s Time delay in IDMT reset
(s), step 2
k2 0.05 - 1.10 0.01 0.05 - Time multiplier in IDMT
mode, step 2
ACrv2 0.005 - 200.000 0.001 1.000 - Setting A for programma-
ble under voltage IDMT
curve, step 2
BCrv2 0.50 - 100.00 0.01 1.00 - Setting B for programma-
ble under voltage IDMT
curve, step 2
CCrv2 0.0 - 1.0 0.1 0.0 - Setting C for programma-
ble under voltage IDMT
curve, step 2
DCrv2 0.000 - 60.000 0.001 0.000 - Setting D for programma-
ble under voltage IDMT
curve, step 2
PCrv2 0.000 - 3.000 0.001 1.000 - Setting P for programma-
ble under voltage IDMT
curve, step 2
CrvSat2 0 - 100 1 0 % Tuning param for prog.
under voltage IDMT
curve, step 2
IntBlkSel2 Off
Block of trip
Block all
- Off - Internal (low level) block-
ing mode, step 2
IntBlkStVal2 1 - 100 1 20 %UB Voltage setting for inter-
nal blocking in % of
UBase, step 2
tBlkUV2 0.000 - 60.000 0.001 0.000 s Time delay of internal
(low level) blocking for
step 2
HystAbs2 0.0 - 100.0 0.1 0.5 %UB Absolute hysteresis in %
of UBase, step 2
HystAbsIntBlk2 0.0 - 100.0 0.1 0.5 %UB Abs hysteresis for inter-
nal blocking in % of
UBase, step 2
Parameter Range Step Default Unit Description
251
Two step undervoltage protection (PUVM, 27) Chapter 7
Voltage protection
1.6 Technical data
Table 124: Two step undervoltage protection (PUVM, 27)
Function Range or value Accuracy
Operate voltage, low and high
step
(1100)% of U
base
1.0% of U
r
Absolute hysteresis (0100)% of U
base
1.0% of U
r
Internal blocking level, low and
high step
(1100)% of U
base
1.0% of U
r
Inverse time characteristics for
low and high step, see table 400
- See table 400
Definite time delays (0.000-60.000) s 0.5% 10 ms
Minimum operate time, inverse
characteristics
(0.00060.000) s 0.5% 10 ms
Operate time, start function 25 ms typically at 2 to 0 x U
set
-
Reset time, start function 25 ms typically at 0 to 2 x U
set
-
Critical impulse time 10 ms typically at 2 to 0 x U
set
-
Impulse margin time 15 ms typically -
252
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
2 Two step overvoltage protection (POVM, 59)
2.1 Introduction
Overvoltages will occur in the power system during abnormal conditions such as sudden power
loss, tap changer regulating failures, open line ends on long lines.
The function can be used as open line end detector, normally then combined with directional re-
active over-power function or as system voltage supervision, normally then giving alarm only
or switching in reactors or switch out capacitor banks to control the voltage.
The function has two voltage steps, each of them with inverse or definite time delayed.
The overvoltage function has an extremely high reset ratio to allow setting close to system ser-
vice voltage.
2.2 Principle of operation
The two-step overvoltage protection function (TOV) is used to detect high power system volt-
age. The function has two steps with separate time delays. If one, two or three phase voltages
increase above the set value, a corresponding start signal is issued. TOV can be set to start/trip
based on "one out of three", "two out of three", or "three out of three" of the measured phase
voltages, being above the set point. If the phase voltage remains above the set value for a time
period corresponding to the chosen time delay, the corresponding trip signal is issued. The time
delay characteristic is individually chosen for the two steps and can be either definite time delay
or inverse time delay.
The voltage related settings are made in percent of the base voltage, which is set in kV,
phase-phase.
The overvoltage protection function measures the phase to earth voltages, if the voltage trans-
former is connected phase to earth to the analogue voltage inputs. The setting of the analogue
inputs are given as primary phase to phase voltage and secondary phase to phase voltage. The
function will operate if the phase to earth voltage gets higher than the set percentage of the phase
to earth voltage corresponding to the set base voltage UBase. This means operation for phase to
earth voltage over
(Equation 38)
Function block name: TOVx- IEC 60617 graphical symbol:
ANSI number: 59
IEC 61850 logical node name:
PH2POVM
3U>
(%) ( )
3
U UBase kV >
253
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
If the voltage transformer is connected phase to phase to the analogue input, the setting of the
analogue inputs are given as primary phase to phase voltage and secondary phase to phase volt-
age divided by 3. The function will operate if the phase to phase voltage gets higher than the
set percentage of the phase to phase voltage corresponding to the set base voltage UBase.
2.2.1 Measurement principle
All the three phase voltages are measured continuously, and compared with the set values, U1>
and U2>. The parameters OpMode1 and OpMode2 influence the requirements to activate the
start outputs. Either "1 out of 3", "2 out of 3" or "3 out of 3" phases have to be higher than the
corresponding set point to issue the corresponding start signal.
To avoid oscillations of the output start signal, a hysteresis has been included.
2.2.2 Time delay
The time delay for the two steps can be either definite time delay (DT) or inverse time delay (ID-
MT). For the inverse time delay four different modes are available; inverse curve A, inverse
curve B, inverse curve C, and a programmable inverse curve.
The type A curve is described as:
(Equation 39)
The type B curve is described as:
(Equation 40)
The type C curve is described as:
(Equation 41)
The programmable curve can be created as:
k
t
U U
U
=
>

>

2.0
480
32 0.5 0.035
k
t
U U
U

=
>


>

3.0
480
32 0.5 0.035
k
t
U U
U

=
>


>

254
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
(Equation 42)
When the denominator in the expression is equal to zero the time delay will be infinity. There
will be an undesired discontinuity. Therefore a tuning parameter CrvSatn is set to compensate
for this phenomenon. In the voltage interval U<down to U<*(1.0 CrvSatn/100) the used volt-
age will be: U<*(1.0 CrvSatn/100). If the programmable curve is used this parameter must be
calculated so that:
(Equation 43)
The highest phase voltage is always used for the inverse time delay integration, see figure118.
The details of the different inverse time characteristics are shown in section 3 "Inverse charac-
teristics".
Figure 118: Voltage used for the inverse time characteristic integration
p
k A
t D
U U
B C
U

= +
>


>

0
100
CrvSatn
B C >
en05000016.vsd
Voltage
IDMT Voltage
Time
UL1
UL2
UL3
255
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
Trip signal issuing requires that the overvoltage condition continues for at least the user set time
delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and by se-
lected voltage level dependent time curves for the inverse time mode (IDMT). If the start con-
dition, with respect to the measured voltage ceases during the delay time, and is not fulfilled
again within a user defined reset time (tReset1 and tReset2 for the definite time and tIReset1 and
tIReset2 for the inverse time) the corresponding start output is reset, after that the defined reset
time has elapsed. Here it should be noted that after leaving the hysteresis area, the start condition
must be fulfilled again and it is not sufficient for the signal to only return back to the hysteresis
area. It is also remarkable that for the overvoltage function the IDMT reset time is constant and
does not depend on the voltage fluctuations during the drop-off period. However, there are three
ways to reset the timer, either the timer is reset instantaneously, or the timer value is frozen dur-
ing the reset time, or the timer value is linearly decreased during the reset time. See figure119
and figure120.
256
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
Figure 119: Voltage profile note causing a reset of the start signal for step 1, and definite time
delay
en05000017.vsd
Voltage
Time
Hysteresis
START
TRIP
U1>
START
TRIP
t1
tReset1
Time
Time Integrator
t1
Froozen Timer
Linear Decrease
Instantaneous
Reset
Measured Voltage
tReset1
257
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
Figure 120: Voltage profile causing a reset of the start signal for step 1, and definite time delay
2.2.3 Blocking
The overvoltage function can be partially or totally blocked, by binary input signals where:
en05000018.vsd
Voltage
Time
Hysteresis
START
TRIP START
U1>
START
TRIP
t1
tReset1
Time
Time Integrator
t1
Froozen Timer
Linear Decrease
Instantaneous
Reset
Measured Voltage
tReset1
258
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
2.2.4 Design
The voltage measuring elements continuously measure the phase-to-neutral voltages in all three
phases. Recursive Fourier filters filter the input voltage signals. The phase voltages are individ-
ually compared to the set value, and the highest phase voltage is used for the inverse time char-
acteristic integration. A special logic is included to achieve the "1 out of 3", "2 out of 3" and "3
out of 3" criteria to fulfill the start condition. The design of the TimeOverVoltage function is
schematically described in figure121.
BLOCK: blocks all outputs
BLKTR1: blocks all trip outputs of step 1
BLKST1: blocks all start and trip outputs related to step 1
BLKTR2: blocks all trip outputs of step 2
BLKST2: blocks all start and trip outputs related to step 2
259
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
Figure 121: Schematic design of the TimeOverVoltage function
START
ST1L1
ST1L2
ST1L3
TR1L1
TR1L2
TR1L3
ST1
TR1
START
ST2L1
ST2L2
ST2L3
TR2L1
TR2L2
TR2L3
ST2
TR2
START
TRIP
en05000013.vsd
Comparator
UL1 >U1>
Comparator
UL2 >U1>
Comparator
UL3 >U1>
MaxVoltSelect
or
Comparator
UL1 >U2>
Comparator
UL2 >U2>
Comparator
UL3 >U2>
MaxVoltSelect
or
Start
&
Trip
Output
Logic
Step 1
Start
&
Trip
Output
Logic
Step 2
Phase 3
Phase 2
Phase 1
Phase 3
Phase 2
Phase 1
Time integrator
t2
tReset2
ResetTypeCrv2
Voltage Phase
Selector
OpMode2
1 out of 3
2 outof 3
3 out of 3
Time integrator
t1
tReset1
ResetTypeCrv1
Voltage Phase
Selector
OpMode1
1 out of 3
2 outof 3
3 out of 3
UL1
UL2
UL3
TRIP
TRIP
OR
OR
OR
OR
OR
OR
260
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
2.3 Function block
Figure 122: TOV function block
2.4 Input and output signals
Table 125: Input signals for the PH2POVM_59 (TOV1-) function block
Table 126: Output signals for the PH2POVM_59 (TOV1-) function block
PH2POVM
TOV1-
U3P
BLOCK
BLKTR1
BLKST1
BLKTR2
BLKST2
TRIP
TR1
TR1L1
TR1L2
TR1L3
TR2
TR2L1
TR2L2
TR2L3
START
ST1
ST1L1
ST1L2
ST1L3
ST2
ST2L1
ST2L2
ST2L3
en05000328.vsd
Signal Description
U3P Group signal for three phase voltage input
BLOCK Block of function
BLKTR1 Block of operate signal, step 1
BLKST1 Block of step 1
BLKTR2 Block of operate signal, step 2
BLKST2 Block of step 2
Signal Description
TRIP Operate signal
TR1 Operate signal for step 1
TR1L1 Operate signal from phase 1, step 1
TR1L2 Operate signal from phase 2, step 1
TR1L3 Operate signal from phase 3, step 1
TR2 Operate signal for step 2
TR2L1 Operate signal from phase 1, step 2
TR2L2 Operate signal from phase 2, step 2
TR2L3 Operate signal from phase 3, step 2
261
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
2.5 Setting parameters
Table 127: Parameter group settings for the PH2POVM_59 (TOV1-) function
START Start signal
ST1 Start signal for step1
ST1L1 Start signal from phase 1, step 1
ST1L2 Start signal from phase 2, step 1
ST1L3 Start signal from phase 3, step 1
ST2 Start signal for step 2
ST2L1 Start signal from phase 1, step 2
ST2L2 Start signal from phase 2, step 2
ST2L3 Start signal from phase 3, step 2
Signal Description
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage,
phase-phase in kV
Characterist1 Definite time
Inverse curve A
Inverse curve B
Inverse curve C
Prog. inv. curve
- Definite time - Operation charcteristic
selection, step 1
OpMode1 1 out of 3
2 out of 3
3 out of 3
- 1 out of 3 - Operation mode, 1 out of
3 / 2 out of 3 / 3 out of 3,
step 1
U1> 1 - 200 1 120 %UB Voltage setting/start val
(DT & IDMT) in % of
UBase, step 1
t1 0.000 - 60.000 0.001 5.000 s Operate time delay in DT
mode, step 1.
tReset1 0.000 - 60.000 0.001 0.025 s Time delay in DT reset
(s), step 1
t1Min 0.000 - 60.000 0.001 5.000 s Minimum operate time in
IDMT mode (s), step 1
ResetTypeCrv1 Instantaneous
Frozen timer
Linearly decreased
- Instantaneous - IDMT mode reset type
selector, step 1
tIReset1 0.000 - 60.000 0.001 0.025 s Time delay in IDMT reset
(s), step 1
k1 0.05 - 1.10 0.01 0.05 - Time multiplier in IDMT
mode, step 1
262
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
ACrv1 0.005 - 200.000 0.001 1.000 - Setting A for programma-
ble over voltage IDMT
curve, step 1
BCrv1 0.50 - 100.00 0.01 1.00 - Setting B for programma-
ble over voltage IDMT
curve, step 1
CCrv1 0.0 - 1.0 0.1 0.0 - Setting C for programma-
ble over voltage IDMT
curve, step 1
DCrv1 0.000 - 60.000 0.001 0.000 - Setting D for programma-
ble over voltage IDMT
curve, step 1
PCrv1 0.000 - 3.000 0.001 1.000 - Setting P for programma-
ble over voltage IDMT
curve, step 1
CrvSat1 0 - 100 1 0 % Tuning param for prog.
over voltage IDMT curve,
step 1
HystAbs1 0.0 - 100.0 0.1 0.5 %UB Absolute hysteresis in %
of UBase, step 1
Characterist2 Definite time
Inverse curve A
Inverse curve B
Inverse curve C
Prog. inv. curve
- Definite time - Operation characteristic
selection, step 2
OpMode2 1 out of 3
2 out of 3
3 out of 3
- 1 out of 3 - Operation mode, 1 out of
3 / 2 out of 3 / 3 out of 3,
step 2
U2> 1 - 200 1 180 %UB Voltage setting/start val
(DT & IDMT) in % of
UBase, step 2
t2 0.000 - 60.000 0.001 5.000 s Operate time delay in DT
mode, step 2
tReset2 0.000 - 60.000 0.001 0.025 s Time delay in DT reset
(s), step 2
t2Min 0.000 - 60.000 0.001 5.000 s Minimum operate time in
IDMT mode (s), step 2
ResetTypeCrv2 Instantaneous
Frozen timer
Linearly decreased
- Instantaneous - IDMT mode reset type
selector, step 2
tIReset2 0.000 - 60.000 0.001 0.025 s Time delay in IDMT reset
(s), step 2
k2 0.05 - 1.10 0.01 0.05 - Time multiplier in IDMT
mode, step 2
ACrv2 0.005 - 200.000 0.001 1.000 - Setting A for programma-
ble over voltage IDMT
curve, step 2
Parameter Range Step Default Unit Description
263
Two step overvoltage protection (POVM, 59) Chapter 7
Voltage protection
2.6 Technical data
Table 128: Two step overvoltage protection (POVM, 59)
BCrv2 0.50 - 100.00 0.01 1.00 - Setting B for programma-
ble over voltage IDMT
curve, step 2
CCrv2 0.0 - 1.0 0.1 0.0 - Setting C for programma-
ble over voltage IDMT
curve, step 2
DCrv2 0.000 - 60.000 0.001 0.000 - Setting D for programma-
ble over voltage IDMT
curve, step 2
PCrv2 0.000 - 3.000 0.001 1.000 - Setting P for programma-
ble over voltage IDMT
curve, step 2
CrvSat2 0 - 100 1 0 % Tuning param for prog.
over voltage IDMT curve,
step 2
HystAbs2 0.0 - 100.0 0.1 0.5 %UB Absolute hysteresis in %
of UBase, step 2
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Operate voltage, low and high
step
(1-200)% of U
base
1.0% of U
r
at U <U
r
1.0% of U at U >Ur
Absolute hysteresis (0100)% of U
base
1.0% of U
r
at U <U
r
1.0% of U at U >U
r
Inverse time characteristics for
low and high step, see table 401
- See table 401
Definite time delays (0.000-60.000) s 0.5% 10 ms
Minimum operate time, Inverse
characteristics
(0.000-60.000) s 0.5% 10 ms
Operate time, start function 25 ms typically at 0 to 2 x U
set
-
Reset time, start function 25 ms typically at 2 to 0 x U
set
-
Critical impulse time 10 ms typically at 0 to 2 x U
set
-
Impulse margin time 15 ms typically -
264
Two step residual overvoltage
protection (POVM, 59N)
Chapter 7
Voltage protection
3 Two step residual overvoltage
protection (POVM, 59N)
3.1 Introduction
Residual voltages will occur in the power system during earth faults.
The function can be configured to calculate the residual voltage from the three phase voltage in-
put transformers or from a single phase voltage input transformer fed from an open delta or neu-
tral point voltage transformer.
The function has two voltage steps, each with inverse or definite time delayed.
3.2 Principle of operation
The two-step residual overvoltage protection function (TRV) is used to detect high single-phase
voltage, such as high residual voltage, also called 3U0. The residual voltage can be measured
directly from a voltage transformer in the neutral of a power transformer or from a three-phase
voltage transformer, where the secondary windings are connected in an open delta. Another pos-
sibility is to measure the three phase voltages and internally in the protection terminal calculate
the corresponding residual voltage and connect this calculated residual voltage to the TRV func-
tion block. The function has two steps with separate time delays. If the single-phase (residual)
voltage remains above the set value for a time period corresponding to the chosen time delay,
the corresponding trip signal is issued. The time delay characteristic is individually chosen for
the two steps and can be either definite time delay or inverse time delay
The voltage related settings are made in percent of the base voltage, which is set in kV,
phase-phase.
3.2.1 Measurement principle
The residual voltage is measured continuously, and compared with the set values, U1> and U2>.
To avoid oscillations of the output start signal, a hysteresis has been included.
3.2.2 Time delay
The time delay for the two steps can be either definite time delay (DT) or inverse time delay (ID-
MT). For the inverse time delay four different modes are available; inverse curve A, inverse
curve B, inverse curve C, and a programmable inverse curve.
The type A curve is described as:
Function block name: TRVx- IEC 60617 graphical symbol:
ANSI number: 59N
IEC 61850 logical node name:
R2POVM
3U0
265
Two step residual overvoltage
protection (POVM, 59N)
Chapter 7
Voltage protection
(Equation 44)
The type B curve is described as:
(Equation 45)
The type C curve is described as:
(Equation 46)
The programmable curve can be created as:
(Equation 47)
When the denominator in the expression is equal to zero the time delay will be infinity. There
will be an undesired discontinuity. Therefore a tuning parameter CrvSatn is set to compensate
for this phenomenon. In the voltage interval U> up to U> *(1.0 +CrvSatn/100) the used voltage
will be: U> *(1.0 +CrvSatn/100). If the programmable curve is used this parameter must be cal-
culated so that:
(Equation 48)
k
t
U U
U
=
>

>

2.0
480
32 0.5 0.035
k
t
U U
U

=
>


>

3.0
480
32 0.5 0.035
k
t
U U
U

=
>


>

p
k A
t D
U U
B C
U

= +
>


>

0
100
CrvSatn
B C >
266
Two step residual overvoltage
protection (POVM, 59N)
Chapter 7
Voltage protection
The details of the different inverse time characteristics are shown in chapter 3 "Inverse charac-
teristics".
Trip signal issuing requires that the residual overvoltage condition continues for at least the user
set time delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and
by some special voltage level dependent time curves for the inverse time mode (IDMT). If the
start condition, with respect to the measured voltage ceases during the delay time, and is not ful-
filled again within a user defined reset time (tReset1 and tReset2 for the definite time and
tIReset1 and tIReset2 for the inverse time) the corresponding start output is reset, after that the
defined reset time has elapsed. Here it should be noted that after leaving the hysteresis area, the
start condition must be fulfilled again and it is not sufficient for the signal to only return back to
the hysteresis area. It is also remarkable that for the overvoltage function the IDMT reset time
is constant and does not depend on the voltage fluctuations during the drop-off period. However,
there are three ways to reset the timer, either the timer is reset instantaneously, or the timer value
is frozen during the reset time, or the timer value is linearly decreased during the reset time. See
figure123 and figure124.
267
Two step residual overvoltage
protection (POVM, 59N)
Chapter 7
Voltage protection
Figure 123: Voltage profile not causing a reset of the start signal for step 1, and definite time
delay
en05000019.vsd
Vol tage
Ti me
Hysteresi s
START
TRIP
U1>
START
TRIP
t1
tReset1
Ti me
Ti me
Integrator
t1
Froozen Timer
Linear Decrease
Instantaneous
Reset
Measured
Vol tage
tReset
1
268
Two step residual overvoltage
protection (POVM, 59N)
Chapter 7
Voltage protection
Figure 124: Voltage profile causing a reset of the start signal for step 1, and definite time delay
3.2.3 Blocking
The residual overvoltage function can be partially or totally blocked, by binary input signals
where:
en05000020.vsd
Voltage
Time
Hysteresis
START
TRIP START
U1>
START
TRIP
t1
tReset1
Time
Time Integrator
t1
Froozen Timer
Linear Decrease
Instantaneous
Reset
Measured Voltage
tReset1
269
Two step residual overvoltage
protection (POVM, 59N)
Chapter 7
Voltage protection
3.2.4 Design
The voltage measuring elements continuously measure the residual voltage. Recursive Fourier
filters filter the input voltage signal. The single input voltage is compared to the set value, and
is also used for the inverse time characteristic integration. The design of the TRV function is
schematically described in figure125.
Figure 125: Schematic design of the TRV function
BLOCK: blocks all outputs
BLKTR1: blocks all trip outputs of step 1
BLKST1: blocks all start and trip outputs related to step 1
BLKTR2: blocks all trip outputs of step 2
BLKST2: blocks all start and trip outputs related to step 2
en05000748.vsd
UN ST1
TR1
ST2
TR2
START
TRIP
Comparator
UN >U1>
Start
&
Trip
Output
Logic
Step 2
Phase 1
Phase 1
Time integrator
t2
tReset2
ResetTypeCrv2
START
Start
&
Trip
Output
Logic
Step 1
Time integrator
t1
tReset1
ResetTypeCrv1
Comparator
UN >U2>
START
TRIP
TRIP
OR
OR
270
Two step residual overvoltage
protection (POVM, 59N)
Chapter 7
Voltage protection
3.3 Function block
Figure 126: TRV function block
3.4 Input and output signals
Table 129: Input signals for the R2POVM_59N (TRV1-) function block
Table 130: Output signals for the R2POVM_59N (TRV1-) function block
R2POVM
TRV1-
U3P
BLOCK
BLKTR1
BLKST1
BLKTR2
BLKST2
TRIP
TR1
TR2
START
ST1
ST2
en05000327.vsd
Signal Description
U3P Group signal for voltage input
BLOCK Block of function
BLKTR1 Block of operate signal, step 1
BLKST1 Block of step 1
BLKTR2 Block of operate signal, step 2
BLKST2 Block of step 2
Signal Description
TRIP Operate signal
TR1 Operate signal for step 1
TR2 Operate signal for step 2
START Start signal
ST1 Start signal for step 1
ST2 Start signal for step 2
271
Two step residual overvoltage
protection (POVM, 59N)
Chapter 7
Voltage protection
3.5 Setting parameters
Table 131: Parameter group settings for the R2POVM_59N (TRV1-) function
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage,
phase-phase in kV
Characterist1 Definite time
Inverse curve A
Inverse curve B
Inverse curve C
Prog. inv. curve
- Definite time - Operation characteristic
selection, step 1
U1> 1 - 200 1 30 %UB Voltage setting/start val
(DT & IDMT), step 1 in %
of UBase
t1 0.000 - 60.000 0.001 5.000 s Operate time delay in DT
mode, step 1.
tReset1 0.000 - 60.000 0.001 0.025 s Time delay in DT reset
(s), step 1
t1Min 0.000 - 60.000 0.001 5.000 s Minimum operate time in
IDMT mode (s), step 1
ResetTypeCrv1 Instantaneous
Frozen timer
Linearly decreased
- Instantaneous - IDMT mode reset type
selector, step 1
tIReset1 0.000 - 60.000 0.001 0.025 s Time delay in IDMT reset
(s), step 1
k1 0.05 - 1.10 0.01 0.05 - Time multiplier in IDMT
mode, step 1
ACrv1 0.005 - 200.000 0.001 1.000 - Setting A for programma-
ble over voltage IDMT
curve, step 1
BCrv1 0.50 - 100.00 0.01 1.00 - Setting B for programma-
ble over voltage IDMT
curve, step 1
CCrv1 0.0 - 1.0 0.1 0.0 - Setting C for programma-
ble over voltage IDMT
curve, step 1
DCrv1 0.000 - 60.000 0.001 0.000 - Setting D for programma-
ble over voltage IDMT
curve, step 1
PCrv1 0.000 - 3.000 0.001 1.000 - Setting P for programma-
ble over voltage IDMT
curve, step 1
CrvSat1 0 - 100 1 0 % Tuning param for prog.
over voltage IDMT curve,
step 1
HystAbs1 0.0 - 100.0 0.1 0.5 %UB Absolute hysteresis in %
of UBase, step 1
272
Two step residual overvoltage
protection (POVM, 59N)
Chapter 7
Voltage protection
Characterist2 Definite time
Inverse curve A
Inverse curve B
Inverse curve C
Prog. inv. curve
- Definite time - Operation characteristic
selection, step 2
U2> 1 - 100 1 45 %UB Voltage setting/start val
(DT & IDMT), step 2 in %
of UBase
t2 0.000 - 60.000 0.001 5.000 s Operate time delay in DT
mode, step 2
tReset2 0.000 - 60.000 0.001 0.025 s Time delay in DT reset
(s), step 2
t2Min 0.000 - 60.000 0.001 5.000 s Minimum operate time in
IDMT mode (s), step 2
ResetTypeCrv2 Instantaneous
Frozen timer
Linearly decreased
- Instantaneous - IDMT mode reset type
selector, step 2
tIReset2 0.000 - 60.000 0.001 0.025 s Time delay in IDMT reset
(s), step 2
k2 0.05 - 1.10 0.01 0.05 - Time multiplier in IDMT
mode, step 2
ACrv2 0.005 - 200.000 0.001 1.000 - Setting A for programma-
ble over voltage IDMT
curve, step 2
BCrv2 0.50 - 100.00 0.01 1.00 - Setting B for programma-
ble over voltage IDMT
curve, step 2
CCrv2 0.0 - 1.0 0.1 0.0 - Setting C for programma-
ble over voltage IDMT
curve, step 2
DCrv2 0.000 - 60.000 0.001 0.000 - Setting D for programma-
ble over voltage IDMT
curve, step 2
PCrv2 0.000 - 3.000 0.001 1.000 - Setting P for programma-
ble over voltage IDMT
curve, step 2
CrvSat2 0 - 100 1 0 % Tuning param for prog.
over voltage IDMT curve,
step 2
HystAbs2 0.0 - 100.0 0.1 0.5 %UB Absolute hysteresis in %
of UBase, step 2
Parameter Range Step Default Unit Description
273
Two step residual overvoltage
protection (POVM, 59N)
Chapter 7
Voltage protection
3.6 Technical data
Table 132: Two step residual overvoltage protection (POVM, 59N)
Function Range or value Accuracy
Operate voltage, low and high
step
(1-200)% of U
base
1.0% of U
r
at U <U
r
1.0% of
U at U >U
r
Absolute hysteresis (0100)% of U
base
1.0% of U
r
at U <U
r
1.0% of U at U >U
r
Inverse time characteristics for
low and high step, see table 402
- See table 402
Definite time setting (0.00060.000) s 0.5% 10 ms
Minimum operate time (0.000-60.000) s 0.5% 10 ms
Operate time, start function 25 ms typically at 0 to 2 x U
set
-
Reset time, start function 25 ms typically at 2 to 0 x U
set
-
Critical impulse time 10 ms typically at 0 to 2 x U
set
-
Impulse margin time 15 ms typically -
274
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
4 Overexcitation protection (PVPH, 24)
4.1 Introduction
When the laminated core of a power transformer is subjected to a magnetic flux density beyond
its design limits, stray flux will flow into non-laminated components not designed to carry flux
and cause eddy currents to flow. The eddy currents can cause excessive heating and severe dam-
age to insulation and adjacent parts in a relatively short time.
4.2 Principle of operation
The importance of overexcitation protection is growing as the power transformers as well as oth-
er power system elements today operate most of the time near their designated limits.
Modern design transformers are more sensitive to overexcitation than earlier types. This is a re-
sult of the more efficient designs and designs which rely on the improvement in the uniformity
of the excitation level of modern systems. Thus, if emergency that includes overexcitation does
occur, transformers may be damaged unless corrective action is promptly taken. Transformer
manufacturers recommend an overexcitation protection as a part of the transformer protection
system.
Overexcitation results from excessive applied voltage, possibly in combination with below-nor-
mal frequency. Such condition may occur when a unit is on load, but are more likely to arise
when it is on open circuit, or at a loss of load occurrence. Transformers directly connected to
generators are in particular danger to experience overexcitation condition. It follows from the
fundamental transformer equation, see equation49, that peak flux density Bmax is directly pro-
portional to induced voltage E, and inversely proportional to frequency f, and turns n.
(Equation 49)
The relative excitation M (relative V/Hz) is therefore according to equation50.
(Equation 50)
Function block name: OEXx- IEC 60617 graphical symbol:
ANSI number: 24
IEC 61850 logical node name:
OEXPVPH
U/f >
E 4.44 f n B
max
A =
M relative
V
Hz
-------


E f
Ur ( ) fr ( )
------------------------ = =
275
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
Disproportional variations in quantities E and f may give rise to core overfluxing. If the core flux
density Bmax increases to a point above saturation level (typically 1.9 Tesla), the flux will no
longer be contained within the core only but will extend into other (non-laminated) parts of the
power transformer and give rise to eddy current circulations. Overexcitation will result in:
overheating of the non-laminated metal parts,
a large increase in magnetizing currents,
an increase in core and winding temperature,
an increase in transformer vibration and noise.
Protection against overexcitation is based on calculation of the relative Volts per Hertz (V / Hz)
ratio. The action of the protection is usually to initiate a reduction of excitation and, if this should
fail, or is not possible, to trip the transformer after a delay which can be from seconds to minutes,
typically 5 - 10 seconds.
Overexcitation protection may be of particular concern on directly connected generator unit
transformers. Directly connected generator-transformers are subjected to a wide range of fre-
quencies during the acceleration and deceleration of the turbine. In such cases, the overexcita-
tion protection may trip the field breaker during a start-up of a machine, by means of the
overexcitation ALARM signal from the transformer terminal. If this is not possible, the power
transformer can be disconnected from the source, after a delay, by the TRIP signal.
The IEC 60076 - 1 standard requires that transformers shall be capable of operating continuously
at 10% above rated voltage at no load, and rated frequency. At no load, the ratio of the actual
generator terminal voltage to the actual frequency should not exceed 1.1 times the ratio of trans-
former rated voltage to the rated frequency on a sustained basis, see equation51.
(Equation 51)
or equivalently, with 1.1 Ur =V/Hz> according to equation52.
(Equation 52)
V/Hz> is an OEX setting parameter. The setting range is 1.0 pu to 1.5 pu. If the user does not
know exactly what to set, then the standard IEC 60076 - 1, section 4.4, the default value V/Hz>
= 1.10 pu shall be used.
In OEX protection function the relative excitation M (relative V/Hz) is expressed according to
equation53.
where:
V/Hz> is the maximum continuously allowed voltage at no load, and rated frequency.
E
f
---- 1.1
Ur
fr
------
E
f
----
V/Hz>
fr
---------------------

276
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
(Equation 53)
It is clear from the above formula that, for an unloaded power transformer, M =1 for any E and
f, where the ratio E / f is equal to Ur / fr. A power transformer is not overexcited as long as the
relative excitation is M V/Hz>, V/Hz> expressed in pu. The relative overexcitation is thus de-
fined as shown in equation54.
(Equation 54)
The overexcitation protection algorithm is fed with an input voltage U which is in general not
the induced voltage E from the fundamental transformer equation. For no load condition, these
two voltages are the same, but for a loaded power transformer the internally induced voltage E
may be lower or higher than the voltage U which is measured and fed to OEX, depending on the
direction of the power flow through the power transformer, the power transformer side where
OEX is applied, and the power transformer leakage reactance of the winding. It is important to
specify on the OEX function block in CAP 531 configuration tool worksheet on which side of
the power transformer OEX is placed
As an example, at a transformer with a 15% short circuit impedance Xsc, the full load, 0.8 power
factor, 105% voltage on the load side, the actual flux level in the transformer core, will not be
significantly different from that at the 110% voltage, no load, rated frequency, provided that the
short circuit impedance X can be equally divided between the primary and the secondary wind-
ing: Xleak =Xleak1 =Xleak2 =Xsc / 2 =0.075 pu..
OEX calculates the internal induced voltage E if Xleak (meaning the leakage reactance of the
winding where OEX is connected) is known to the user. The assumption taken for 2-winding
power transformers that Xleak =Xsc / 2 is unfortunately most often not true. For a 2-winding
power transformer the leakage reactances of the two windings depend on how the windings are
located on the core with respect to each other. In the case of three-winding power transformers
the situation is still more complex. If a user has the knowledge on the leakage reactance, then it
should applied. If a user has no idea about it, Xleak can be set to X
c/2
. The OEX protection will
then take the given measured terminal voltage U, as the induced voltage E.
It is assumed that overexcitation is a symmetrical phenomenon, caused by events such as loss of
load, etc. It will be observed that a high phase-to-earth voltage does not mean overexcitation.
For example, in an unearthed power system, a single-phase-to-earth fault means high voltages
of the healthy two phases to earth, but no overexcitation on any winding. The phase-to-phase
voltages will remain essentially unchanged. The important voltage is the voltage between the
two ends of each winding.
4.2.1 Measured voltage
If one phase-to-phase voltage is available from the side where OEX protection is applied, then
OEX protection function block shall be set to measure this voltage, MeasuredU. The particular
voltage which is used determines the two currents that must be used. If, for example, voltage
Uab is fed to OEX, then currents Ia, and Ib must be applied, etc. From these two input currents,
M relative
V
Hz
-------


E f
Ur fr
-------------- = =
overexcitation M V/Hz> =
277
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
current Iab =Ia - Ib is calculated internally by the OEX protection algorithm. The
phase-to-phase voltage must be higher than 70% of the rated value, otherwise the OEX protec-
tion algorithm is exited without calculating the excitation. ERROR output is set to 1, and the dis-
played value of relative excitation V / Hz shows 0.000.
If three phase-to-earth voltages are available from the side where OEX is connected, then OEX
protection function block shall be set to measure positive sequence voltage. In this case the pos-
itive sequence voltage and the positive sequence current are used by OEX protection. A check
is made within OEX protection if the positive sequence voltage is higher than 70% rated
phase-to-earth voltage; below this value, OEX is exited immediately, and no excitation is calcu-
lated. ERROR output is set to 1, and the displayed value of relative excitation V / Hz shows
0.000.
The frequency value is received from the pre-processing block. The function is in operation for
frequencies within the range of 33-60Hz and of 42-75Hz for 50 and 60 Hz respectively.
OEX protection function can be connected to any power transformer side, inde-
pendent from the power flow.
The side with a possible On-Load-Tap-Changer (OLTC) must not be used.
4.2.2 Operate time of the overexcitation protection.
The operate time of the overexcitation protection is a function of the relative overexcitation. Ba-
sically there are two different delay laws available to choose between:
the so called IEEE law, and
a tailor-made law.
The so called IEEE law approximates a square law and has been chosen based on analysis of the
various transformers overexcitation capability characteristics. They can match well a trans-
former core capability.
The square law is according to equation55.
(Equation 55)
An analog overexcitation relay would have to evaluate the following integral expression, which
means to look for the instant of time t =t
op
according to equation56.
where:
M is excitation, mean value in the interval from t =0 to t =t
op
V/Hz> is maximum continuously allowed voltage at no load, and rated frequency, in pu and
k is time multiplier setting for inverse time functions, see figure 128.
Parameter k (time multiplier setting) selects one delay curve from the family of curves.
top
0.18 k
M V/Hz> ( )
2
---------------------------------------------
0.18 k
overexcitation
2
---------------------------------------- = =
278
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
(Equation 56)
A digital, numerical relay will instead look for the lowest j (i.e. j =n) where it becomes true that:
(Equation 57)
As long as M >V/Hz> (i.e. overexcitation condition), the above sum can only be larger with
time, and if the overexcitation persists, the protected transformer will be tripped at j =n.
Inverse delays as per figure128, can be modified (limited) by two special definite delay settings,
namely tMax and tMin, see figure127.
Figure 127: Restrictions imposed on inverse delays by tMax, and tMin
where:
t is the time interval between two successive executions of overexcitation function
and
M(j) - V/Hz> is the relative excitation at (time j) in excess of the normal (rated) excitation which
is given as Ur/fr.
M(t) V/Hz>
( )
2
t d
0
t
op

0.18 k

t M(j) V/Hz> ( )
2
j k =
n

0.18 k
0 M
max
- V/Hz>
M
max
tMin
V/Hz>
E
max
E (only if f =fr =const)
tMax
inverse delay law
overexcitation
under -
excitation
delay in s
99001067.vsd
Overexcitation M-V/Hz>
Excitation M M=V/Hz>
279
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
A definite maximum time, tMax, can be used to limit the operate time at low degrees of overex-
citation. Inverse delays longer than tMax will not be allowed. In case the inverse delay is longer
than tMax, OEX trips after tMax seconds.
A definite minimum time, tMin, can be used to limit the operate time at high degrees of overex-
citation. In case the inverse delay is shorter than tMin, OEX function trips after tMin seconds.
Also, the inverse delay law is no more valid beyond excitation Mmax. Beyond Mmax (beyond
overexcitation Mmax - V/Hz>), the delay will always be tMin, no matter what overexcitation.
Figure 128: Delays inversely proportional to the square of the overexcitation.
The critical value of excitation Mmax is determined indirectly via OEX protection function set-
ting V/Hz>>. V/Hz>> can be thought of as a no-load-rated-frequency voltage, where the inverse
law should be replaced by a short definite delay, tMin. If, for example, V/Hz>> =1.40 pu, then
Mmax is according to equation58.
1 10
1
10
100
1000
2 40 3 4 5 20 30
k =2
k =3
k =4
k =5
k =6
k =7
k =8
k =9
k =10
k =20
k =60
k =1
OVEREXCITATION IN %
Time (s) IEEE OVEREXCITATION CURVES
en01000373.vsd
(M-Emaxcont)*100)
280
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
(Equation 58)
The Tailor-Made law allows a user to design an arbitrary delay characteristic. In this case the
interval between M =V/Hz>, and M =Mmax is automatically divided into five equal subinter-
vals, with six delays. (settings t1, t2, t3, t4, t5, and t6) as shown in the figure129. These times
should be set so that t1 =>t2 =>t3 =>t4 =>t5 =>t6.
Figure 129: An example of a Tailor-Made delay characteristic
Delays between two consecutive points, for example t3 and t4, are obtained by linear interpola-
tion.
Should it happen that tMax be lower than, for example, delays t1, and t2, the actual delay would
be tMax. Above Mmax, the delay can only be tMin.
4.2.3 Cooling
The overexcitation protection OEX is basically a thermal protection; therefore a cooling process
has been introduced. Exponential cooling process is applied. Parameter Tcool is an OEX setting,
with a default time constant tCooling of 20minutes. This means that if the voltage and frequency
return to their previous normal values (no more overexcitation), the normal temperature is as-
sumed to be reached not before approximately 5times tCooling minutes. If an overexcitation
condition would return before that, the time to trip will be shorter than it would be otherwise.
4.2.4 OEX protection function measurands
A service value data item called Time to trip, and designated on the display by tTRIP is available
in seconds on the local HMI, or monitoring tool. This value is an estimation of the remaining
time to trip if the overexcitation remained on the level it had when the estimation was done. This
information can be useful with small or moderate overexcitations. If the overexcitation is so low
that the valid delay is tMax, then the estimation of the remaining time to trip is done against
tMax.
Mmax
V/Hz>>
( )
f
Ur fr
-------------------------- 1.40 = =
0
E
maxcont
M
max
- E
maxcont
M
max
tMin
tMax
delay in s
Overexcitation M-E
maxcont
Excitation M
under-
excitation
99001068.vsd
281
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
The displayed relative excitation M, designated on the display by V/Hz is calculated from the
expression:
(Equation 59)
If less than V / Hz =V/Hz> (in pu) is shown on the HMI display (or read via SM/RET521), the
power transformer is underexcited. If the value of V/Hz is shown which is equal to V/Hz> (in
pu), it means that the excitation is exactly equal to the power transformer continuous capability.
If a value higher than the value of V/Hz> is shown, the protected power transformer is overex-
cited. For example, if V/Hz =1.100 is shown, while V/Hz> =1.1 pu, then the power transformer
is exactly on its maximum continuous excitation limit.
The third item of the OEX protection service report is the thermal status of the protected power
transformer iron core, designated on the display by ThermalStatus. This gives the thermal status
in % of the trip value which corresponds to 100%. Thermal Status should reach 100% at the
same time, when tTRIP reaches 0 seconds. If the protected power transformer is then for some
reason not switched off, the ThermalStaus shall go over 100%.
If the delay as per IEEE law, or Tailor-made Law, is limited by tMax, and/or TMin, then the
Thermal Status will generally not reach 100% at the same time, when tTRIP reaches 0 seconds.
For example, if, at low degrees of overexcitation, the very long delay is limited by tMax, then
the OEX TRIP output signal will be set to 1 before the Thermal status reaches 100%.
4.2.5 Overexcitation alarm
A separate step, AlarmLevel, is provided for alarming purpose. The voltages are normally set
2%lower and has a definite time delay, tAlarm. This will give the operator an early abnormal
voltages warning.
M relative
V
Hz
-------


E f
Uf fr
-------------- = =
282
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
4.2.6 Logic diagram
Figure 130: A simplified diagram of the OEX protection function
Simplification of the diagram is in the way the IEEE and Tailor-made delays are calculated. The
cooling process is not shown. It is not shown that voltage and frequency are separately checked
against their respective limit values.
4.3 Function block
Figure 131: OEX function block
OEXPVPH
OEX1-
I3P
U3P
BLOCK
RESET
ERROR
TRIP
START
ALARM
en05000329.vsd
283
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
4.4 Input and output signals
Table 133: Input signals for the OEXPVPH (OEX1-) function block
Table 134: Output signals for the OEXPVPH (OEX1-) function block
4.5 Setting parameters
Table 135: Parameter group settings for the OEXPVPH (OEX1-) function
Signal Description
I3P Group signal for current input
U3P Group signal for voltage input
BLOCK External block
RESET Reset operation
Signal Description
ERROR General function error
TRIP Trip from overexcitation function
START Overexcitation above set operate level (instantaneous)
ALARM Overexcitation above set alarm level (delayed)
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
IBase 1 - 99999 1 3000 A Base current (rated
phase current)
UBase 0.05 - 2000.00 0.05 400.00 kV Base voltage (main volt-
age) in kV
MeasuredU Ph-Ph
Pos Seq
- Ph-Ph - Input voltage selection
(pos. seq/one
phase-to-phase)
V/Hz> 100.0 - 180.0 0.1 110.0 %UB/f Operate level of V/Hz at
no load & rated freq in %
of Ubase
V/Hz>> 100.0 - 200.0 0.1 140.0 %UB/f High level of V/Hz above
which tMin is used, in %
of Ubase
XLeak 0.000 - 200.000 0.001 0.000 ohm Winding reactance in pri-
mary ohms
TrPulse 0.000 - 60.000 0.001 0.100 s Length of the pulse for
trip signal (in sec)
tMin 0.000 - 60.000 0.001 7.000 s Minimum trip delay for
V/Hz inverse curve, in
sec
284
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
tMax 0.00 - 9000.00 0.01 1800.00 s Maximum trip delay for
V/Hz inverse curve, in
sec
tCooling 0.10 - 9000.00 0.01 1200.00 s Transformer magnetic
core cooling time con-
stant, in sec
CurveType IEEE
Tailor made
- IEEE - Inverse time curve selec-
tion, IEEE/Tailor made
kForIEEE 1 - 60 1 1 - Time multiplier for IEEE
inverse type curve
t1Tailor 0.00 - 9000.00 0.01 7200.00 s Time delay t1 (longest)
for tailor made curve, in
sec
t2Tailor 0.00 - 9000.00 0.01 3600.00 s Time delay t2 for tailor
made curve, in sec
t3Tailor 0.00 - 9000.00 0.01 1800.00 s Time delay t3 for tailor
made curve, in sec
t4Tailor 0.00 - 9000.00 0.01 900.00 s Time delay t4 for tailor
made curve, in sec
t5Tailor 0.00 - 9000.00 0.01 450.00 s Time delay t5 for tailor
made curve, in sec
t6Tailor 0.00 - 9000.00 0.01 225.00 s Time delay t6 (shortest)
for tailor made curve, in
sec
AlarmLevel 50.0 - 120.0 0.1 100.0 % Alarm operate level as %
of the trip level
tAlarm 0.00 - 9000.00 0.01 5.00 s Alarm time delay, in sec
Parameter Range Step Default Unit Description
285
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
4.6 Technical data
Table 136: Overexcitation protection (PVPH, 24)
Function Range or value Accuracy
Operate value, start (100180)% of (U
base
/f
rated
) 1.0% of U
Operate value, alarm (50120)% of start level 1.0% of U
r
at U U
r
1.0% of U at U >U
r
Operate value, high level (100200)% of (U
base
/f
rated
) 1.0% of U
Curve type IEEE or customer defined
where M=relative (V/Hz) =
(E/f)/(Ur/fr)
Class 5 +40 ms
Minimum time delay for inverse
function
(0.00060.000) s 0.5% 10 ms
Maximum time delay for inverse
function
(0.009000.00) s 0.5% 10 ms
Alarm time delay (0.00060.000) s 0.5% 10 ms
2
(0.18 )
:
( 1)
k
IEEE t
M

286
Overexcitation protection (PVPH, 24) Chapter 7
Voltage protection
287
About this chapter Chapter 8
Frequency protection
Chapter 8 Frequency
protection
About this chapter
This chapter describes the frequency protection functions. The way the functions work, their set-
ting parameters, function blocks, input and output signals and technical data are included for
each function.
288
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
1 Underfrequency protection (PTUF, 81)
1.1 Introduction
Underfrequency occurs as a result of lack of generation in the network.
The function can be used for load shedding systems, remedial action schemes, gas turbine
start-up etc.
The function is provided with an undervoltage blocking. The operation may be based on single
phase, phase-to-phase or positive sequence voltage measurement.
Up to six independent under frequency steps are available.
1.2 Principle of operation
The underfrequency (TUF) function is used to detect low power system frequency. The function
can either have a definite time delay or a voltage magnitude dependent time delay. If the voltage
magnitude dependent time delay is applied the time delay will be longer if the voltage is higher
and shorter if the voltage is lower. If the frequency remains below the set value for a time period
corresponding to the chosen time delay, the corresponding trip signal is issued. To avoid an un-
wanted trip due to uncertain frequency measurement at low voltage magnitude, a voltage con-
trolled blocking of the function is available, i.e. if the voltage is lower than the set blocking
voltage the function is blocked and no start or trip signal is issued.
1.2.1 Measurement principle
The fundamental frequency of the measured input voltage is measured continuously, and com-
pared with the set value, StartFrequency. The frequency function is also dependent on the volt-
age magnitude. If the voltage magnitude decreases the setting IntBlkStVal, the underfrequency
function is blocked, and the output BLKDMAGN is issued. All voltage settings are made in per-
cent of the setting UBase, which should be set as a phase-phase voltage in kV.
To avoid oscillations of the output start signal, a hysteresis has been included, see section3 "In-
verse characteristics".
1.2.2 Time delay
The time delay for the underfrequency function can be either a settable definite time delay or a
voltage magnitude dependent time delay, where the time delay depends on the voltage level; a
high voltage level gives a longer time delay and a low voltage level causes a short time delay.
For the definite time delay, the setting tTrip sets the time delay, see figure 132and figure 133.
Function block name: TUFx-- IEC 60617 graphical symbol:
ANSI number: 81
IEC 61850 logical node name:
SAPTUF
f <
289
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
For the voltage dependent time delay the measured voltage level and the settings UNom, UMin,
Exponent, tMax and tMin set the time delay according to figure 134 and equation 60. The setting
TimerOperation is used to decide what type of time delay to apply. The output STARTDUR,
gives the time elapsed from the issue of the start output, in percent of the total operation time
available in PST.
Trip signal issuing requires that the underfrequency condition continues for at least the user set
time delay. If the start condition, with respect to the measured frequency ceases during the delay
time, and is not fulfilled again within a user defined reset time, tReset, the start output is reset,
after that the defined reset time has elapsed. Here it should be noted that after leaving the hys-
teresis area, the start condition must be fulfilled again and it is not sufficient for the signal to
only return back to the hysteresis area.
On the output of the underfrequency function a 100 ms pulse is issued, after a time delay corre-
sponding to the setting of TimeDlyRestore, when the measured frequency returns to the level
corresponding to the setting RestoreFreq.
290
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
Figure 132: Frequency profile not causing a reset of the start signal
en05000721.vsd
Time
Frequency
Time
Hysteresis
START
TRIP
StartFrequency
START
TRIP
tTRip
tReset
Time Integrator
tTrip
Measured
Frequency
tReset
291
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
Figure 133: Frequency profile causing a reset of the start signal
1.2.3 Voltage dependent time delay
Since the fundamental frequency in a power system is the same all over the system, except some
deviations during power oscillations, another criterion is needed to decide, where to take actions,
based on low frequency. In many applications the voltage level is very suitable, and in most cas-
es is load shedding preferable in areas with low voltage. Therefore, a voltage dependent time
delay has been introduced, to make sure that load shedding, or other actions, take place at the
en05000723.vsd
Frequency
Time
Hysteresis
START
TRIP
START
StartFrequency
START
TRIP
tTrip
tReset
Time
Time Integrator
tTrip
Measured
Frequency
tReset
292
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
right location. At constant voltage, U, the voltage dependent time delay is calculated according
to equation60. At non-constant voltage, the actual time delay is integrated in a similar way as
for the inverse time characteristic for the undervoltage and overvoltage functions.
(Equation 60)
The inverse time characteristics are shown in figure134, for:
where:
t is the voltage dependent time delay (at constant voltage),
U is the measured voltage
Exponent is a setting,
UMin, UNom are voltage settings corresponding to
tMax, tMin are time settings.
UMin =90%
UNom =100%
tMax =1.0 s
tMin =0.0 s
Exponent =0, 1, 2, 3 and 4
( )
Exponent
U UMin
t tMax tMin tMin
UNom UMin

= +




293
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
Figure 134: Voltage dependent inverse time characteristics for the underfrequency function.
The time delay to operate is plotted as a function of the measured voltage, for the
Exponent = 0, 1, 2, 3, 4 respectively.
1.2.4 Blocking
The underfrequency function can be partially or totally blocked, by binary input signals or by
parameter settings, where:
If the measured voltage level decreases below the setting of IntBlkStVal, both the start and the
trip outputs, are blocked.
1.2.5 Design
The frequency measuring element continuously measures the frequency of the positive sequence
voltage and compares it to the setting StartFrequency. The frequency signal is filtered to avoid
transients due to switchings and faults. The time integrator can operate either due to a definite
delay time or to the special voltage dependent delay time. When the frequency has returned back
to the setting of RestoreFreq, the RESTORE output is issued after the time delay TimeDlyRe-
store. The design of the underfrequency function is schematically described in figure135.
90 95 100
0
0.5
1
en05000075.vsd
T
i
m
e
D
l
y
O
p
e
r
a
t
e

[
s
]
U [% of UBase]
Exponenent
0
1
2
3
4
BLOCK: blocks all outputs
BLKTRIP: blocks the TRIP output
BLKREST: blocks the RESTORE output
294
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
Figure 135: Schematic design of the underfrequency function
1.3 Function block
Figure 136: TUF function block
Frequency Comparator
f <StartFrequency
Voltage
START
START
TRIP
Comparator
U <IntBlockLevel
BLOCK
Comparator
f >RestoreFreq
Block
OR
Time integrator
TimerOperation Mode
Selector
TimeDlyOperate
TimeDlyReset
TimeDlyRestore
RESTORE
100 ms
Start
&
Trip
Output
Logic
en05000726.vsd
TRIP
BLKDMAGN
SAPTUF
TUF1-
U3P
BLOCK
BLKTRIP
BLKREST
TRIP
START
RESTORE
BLKDMAGN
en05000326.vsd
295
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
1.4 Input and output signals
Table 137: Input signals for the SAPTUF_81 (TUF1-) function block
Table 138: Output signals for the SAPTUF_81 (TUF1-) function block
1.5 Setting parameters
Table 139: Parameter group settings for the SAPTUF_81 (TUF1-) function
Signal Description
U3P Group signal for voltage input
BLOCK Block of function
BLKTRIP Blocking operate output.
BLKREST Blocking restore output.
Signal Description
TRIP Operate/trip signal for frequency.
START Start/pick-up signal for frequency.
RESTORE Restore signal for load restoring purposes.
BLKDMAGN Blocking indication due to low amplitude.
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
UBase 0.05 - 2000.00 0.05 400.00 kV Base setting for the
phase-phase voltage in
kV.
StartFrequency 35.00 - 75.00 0.01 48.80 Hz Frequency setting/start
value.
IntBlkStVal 0 - 100 1 50 %UB Internal blocking level in
% of UBase.
tTrip 0.000 - 60.000 0.001 0.200 s Operate time delay.
tReset 0.000 - 60.000 0.001 0.000 s Time delay for reset.
TimeDlyRestore 0.000 - 60.000 0.001 0.000 s Restore time delay.
RestoreFreq 45.00 - 65.00 0.01 50.10 Hz Restore frequency level
after operation.
TimerOperation Definite timer
Volt based timer
- Definite timer - Setting for choosing timer
mode.
296
Underfrequency protection (PTUF, 81) Chapter 8
Frequency protection
1.6 Technical data
Table 140: Underfrequency protection (PTUF, 81)
UNom 50 - 150 1 100 %UB Nominal voltage in % of
UBase for voltage based
timer.
UMin 50 - 150 1 90 %UB Lower operation limit in
% of UBase for voltage
based timer.
Exponent 0.0 - 5.0 0.1 1.0 - For calculation of the
curve form for voltage
based timer.
tMax 0.000 - 60.000 0.001 1.000 s Maximum time operation
limit for voltage based
timer.
tMin 0.000 - 60.000 0.001 0.000 s Minimum time operation
limit for voltage based
timer.
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Operate value, start function (35.00-75.00) Hz 2.0 mHz
Operate time, start function 100 ms typically -
Reset time, start function 100 ms typically -
Operate time, definite time function (0.000-60.000)s 0.5% +10 ms
Reset time, definite time function (0.000-60.000)s 0.5% +10 ms
Voltage dependent time delay
U=U
measured
Settings:
UNom=(50-150)% of U
base
UMin=(50-150)% of U
base
Exponent=0.0-5.0
tMax=(0.001-60.000)s
tMin=(0.000-60.000)s
Class 5 +200 ms
( )
Exponent
U UMin
t tMax tMin tMin
UNom UMin

= +




297
Overfrequency protection (PTOF, 81) Chapter 8
Frequency protection
2 Overfrequency protection (PTOF, 81)
2.1 Introduction
Overfrequency will occur at sudden load drops or shunt faults in the power network. In some
cases close to generating part governor problems can also cause overfrequency.
The function can be used for generation shedding, remedial action schemes etc. It can also be
used as a sub-nominal frequency stage initiating load restoring.
The function is provided with an undervoltage blocking. The operation may be based on single
phase, phase-to-phase or positive sequence voltage measurement.
Up to six independent frequency steps are available.
2.2 Principle of operation
The Overfrequency (TOF) function is used to detect high power system frequency. The function
has a settable definite time delay. If the frequency remains above the set value for a time period
corresponding to the chosen time delay, the corresponding trip signal is issued. To avoid an un-
wanted trip due to uncertain frequency measurement at low voltage magnitude, a voltage con-
trolled blocking of the function is available, i.e. if the voltage is lower than the set blocking
voltage the function is blocked and no start or trip signal is issued.
2.2.1 Measurement principle
The fundamental frequency of the positive sequence voltage is measured continuously, and
compared with the set value, StartFrequency. The frequency function is also dependent on the
voltage magnitude. If the voltage magnitude decreases below the setting IntBlkStVal, the over-
frequency function is blocked, and the output BLKDMAGN is issued. All voltage settings are
made in percent of the UBase, which should be set as a phase-phase voltage in kV. To avoid
oscillations of the output start signal, a hysteresis has been included, see section3 "Inverse char-
acteristics".
2.2.2 Time delay
The time delay for the overfrequency function is a settable definite time delay, specified by the
setting tTrip, see figure 137 and figure138. The output STARTDUR, gives the time elapsed
from the issue of the start output, in percent of the total operation time available in PST.
Function block name: TOFx-- IEC 60617 graphical symbol:
ANSI number: 81
IEC 61850 logical node name:
SAPTOF
f >
298
Overfrequency protection (PTOF, 81) Chapter 8
Frequency protection
Trip signal issuing requires that the overfrequency condition continues for at least the user set
time delay. If the start condition, with respect to the measured frequency ceases during the delay
time, and is not fulfilled again within a user defined reset time, tReset, the start output is reset,
after that the defined reset time has elapsed. Here it should be noted that after leaving the hys-
teresis area, the start condition must be fulfilled again and it is not sufficient for the signal to
only return back to the hysteresis area.
299
Overfrequency protection (PTOF, 81) Chapter 8
Frequency protection
Figure 137: Frequency profile not causing a reset of the start signal
Frequency
Time
Hysteresis
START
TRIP
StartFrequency
START
TRIP
tTrip
tReset
Time
Time Integrator
tTrip
Measured
Frequency
tReset
en05000732.vsd
300
Overfrequency protection (PTOF, 81) Chapter 8
Frequency protection
Figure 138: Frequency profile causing a reset of the start signal
2.2.3 Blocking
The overfrequency function can be partially or totally blocked, by binary input signals or by pa-
rameter settings, where:
en05000733.vsd
Frequency
Time
Hysteresis
START
TRIP
START
StartFrequency
START
TRIP
tTrip
tReset
Time
Time Integrator
tTrip
Measured
Frequency
tReset
301
Overfrequency protection (PTOF, 81) Chapter 8
Frequency protection
If the measured voltage level decreases below the setting of IntBlkStVal, both the start and the
trip outputs, are blocked.
2.2.4 Design
The frequency measuring element continuously measures the frequency of the positive sequence
voltage and compares it to the setting StartFrequency. The frequency signal is filtered to avoid
transients due to switchings and faults in the power system. The time integrator operates due to
a definite delay time. The design of the overfrequency function is schematically described in
figure139.
Figure 139: Schematic design of the overfrequency function
TOF-BLOCK: blocks all outputs
TOF-BLKTRIP: blocks the TOF-TRIP output
Voltage
START START
TRIP
Start
&
Trip
Output
Logic
Time integrator
Definite Time Delay
TimeDlyOperate
TimeDlyReset
Comparator
U <IntBlockLevel
BLOCK
en05000735.vsd
Frequency Comparator
f >StartFrequency
TRIP
BLKDMAGN
BLOCK
OR
BLKTRIP
302
Overfrequency protection (PTOF, 81) Chapter 8
Frequency protection
2.3 Function block
Figure 140: TOF function block
2.4 Input and output signals
Table 141: Input signals for the SAPTOF_81 (TOF1-) function block
Table 142: Output signals for the SAPTOF_81 (TOF1-) function block
2.5 Setting parameters
Table 143: Parameter group settings for the SAPTOF_81 (TOF1-) function
SAPTOF
TOF1-
U3P
BLOCK
BLKTRIP
TRIP
START
BLKDMAGN
en05000325.vsd
Signal Description
U3P Group signal for voltage input
BLOCK Block of function
BLKTRIP Blocking operate output.
Signal Description
TRIP Operate/trip signal for frequency.
START Start/pick-up signal for frequency.
BLKDMAGN Blocking indication due to low amplitude.
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
UBase 0.05 - 2000.00 0.05 400.00 kV Base setting for the
phase-phase voltage in
kV.
StartFrequency 35.00 - 75.00 0.01 51.20 Hz Frequency setting/start
value.
IntBlkStVall 0 - 100 1 50 %UB Internal blocking level in
% of UBase.
tTrip 0.000 - 60.000 0.001 0.000 s Operate time delay.
tReset 0.000 - 60.000 0.001 0.000 s Time delay for reset.
303
Overfrequency protection (PTOF, 81) Chapter 8
Frequency protection
2.6 Technical data
Table 144: Overfrequency protection (PTOF, 81)
Function Range or value Accuracy
Operate value, start function (35.00-75.00) Hz 2.0 mHz
Operate time, start function 100 ms typically -
Reset time, start function 100 ms typically -
Operate time, definite time func-
tion
(0.000-60.000)s 0.5% +10 ms
Reset time, definite time function (0.000-60.000)s 0.5% +10 ms
304
Rate-of-change frequency
protection (PFRC, 81)
Chapter 8
Frequency protection
3 Rate-of-change frequency protection (PFRC, 81)
3.1 Introduction
Rate of change of frequency function gives an early indication of a main disturbance in the sys-
tem.
The function can be used for generation shedding, load shedding, remedial action schemes etc.
The function is provided with an undervoltage blocking. The operation may be based on single
phase, phase-to-phase or positive sequence voltage measurement.
Each step can discriminate between positive or negative change of frequency.
Up to six independent rate-of-change frequency steps are available.
3.2 Principle of operation
The rate-of-change of frequency (RCF) function is used to detect fast power system frequency
changes, increase as well as decrease, at an early stage. The function has a settable definite time
delay. If the rate-of-change of frequency remains below the set value, for negative
rate-of-change, for a time period equal to the chosen time delay, the trip signal is issued. If the
rate-of-change of frequency remains above the set value, for positive rate-of-change, for a time
period equal to the chosen time delay, the trip signal is issued. To avoid an unwanted trip due to
uncertain frequency measurement at low voltage magnitude, a voltage controlled blocking of the
function is available, i.e. if the voltage is lower than the set blocking voltage, the function is
blocked and no start or trip signal is issued. If the frequency recovers, after a frequency decrease,
a restore signal is issued.
3.2.1 Measurement principle
The rate-of-change of the fundamental frequency of the selected voltage is measured continu-
ously, and compared with the set value, StartFreqGrad. The rate-of-change of frequency func-
tion is also dependent on the voltage magnitude. If the voltage magnitude decreases below the
setting IntBlockLevel, the rate-of-change of frequency function is blocked, and the output
BLKDMAGN is issued. The sign of the setting StartFreqGrad, controls if the rate-of-change of
frequency function reacts on a positive or on a negative change in frequency. If the
rate-of-change of frequency function is used for decreasing frequency, i.e. the setting Start-
FreqGrad has been given a negative value, and a trip signal has been issued, then a 100 ms pulse
Function block name: RCFx-- IEC 60617 graphical symbol:
ANSI number: 81
IEC 61850 logical node name:
SAPFRC
df/dt
>
<
305
Rate-of-change frequency
protection (PFRC, 81)
Chapter 8
Frequency protection
is issued on the RESTORE output, when the frequency recovers to a value higher than the setting
RestoreFreq. A positive setting of StartFreqGrad, sets the rate-of-change of frequency function
to start and trip for frequency increases.
To avoid oscillations of the output start signal, a hysteresis has been included, see section3 "In-
verse characteristics".
3.2.2 Time delay
The rate-of-change of frequency function has a settable definite time delay, tTrip. The output
STARTDUR, gives the time elapsed from the issue of the start output, in percent of the total op-
eration time.
Trip signal issuing requires that the rate-of-change of frequency condition continues for at least
the user set time delay, tTrip. If the start condition, with respect to the measured frequency ceas-
es during the delay time, and is not fulfilled again within a user defined reset time, tReset, the
start output is reset, after that the defined reset time has elapsed. Here it should be noted that
after leaving the hysteresis area, the start condition must be fulfilled again and it is not sufficient
for the signal to only return back into the hysteresis area, see figure141-144.
The RESTORE output of the rate-of-change of frequency function is set, after a time delay equal
to the setting of tRestore, when the measured frequency has returned to the level corresponding
to RestoreFreq, after an issue of the TRIP output signal. If tRestore is set to 0.000 s the restore
functionality is disabled, and no output will be given. The restore functionality is only active for
lowering frequency conditions and the restore sequence is disabled if a new negative frequency
gradient is detected during the restore period, defined by the settings RestoreFreq and tRestore.
306
Rate-of-change frequency
protection (PFRC, 81)
Chapter 8
Frequency protection
Figure 141: Rate-of-change of frequency profile, set for frequency decrease conditions, not
causing a reset of the start signal
en05000727.vsd
Rate-of-Change
of Frequency
Time
Hysteresis
START
TRIP
StartFreqGrad
START
TRIP
tTrip
tReset
Time
Time Integrator
tTrip
Measured Rate-of-
Change of Frequency
tReset
307
Rate-of-change frequency
protection (PFRC, 81)
Chapter 8
Frequency protection
Figure 142: Frequency profile, set for frequency decrease conditions, causing a reset of the
start signal
en05000728.vsd
Rate-of-Change
of Frequency
Time
Hysteresis
START
TRIP
START
StartFreqGrad
START
TRIP
tTrip
tReset
Time
Time Integrator
tTrip
Measured
Rate-of-Change
of Frequency
tReset
308
Rate-of-change frequency
protection (PFRC, 81)
Chapter 8
Frequency protection
Figure 143: Rate-of-change of frequency profile, set for frequency increase conditions, not
causing a reset of the start signal
en05000729.vsd
Rate-of-Change
of Frequency
Time
Hysteresis
START
TRIP
StartFreqGrad
START
TRIP
tTrip
tReset
Time
Time Integrator
tTrip
Measured Rate-of-
Change of Frequency
tReset
309
Rate-of-change frequency
protection (PFRC, 81)
Chapter 8
Frequency protection
Figure 144: Frequency profile, set for frequency increase conditions, causing a reset of the
start signal
3.2.3 Blocking
The rate-of-change of frequency function can be partially or totally blocked, by binary input sig-
nals or by parameter settings, where:
en05000730.vsd
Rate-of-Change
of Frequency
Time
Hysteresis
START
TRIP
START
StartFreqGrad
START
TRIP
tTrip
tReset
Time
Time Integrator
tTrip
Measured
Rate-of-Change
of Frequency
tReset
310
Rate-of-change frequency
protection (PFRC, 81)
Chapter 8
Frequency protection
If the measured voltage level decreases below the setting of IntBlockLevel, both the start and the
trip outputs, are blocked.
3.2.4 Design
The rate-of-change of frequency measuring element continuously measures the frequency of the
selected voltage and compares it to the setting StartFreqGrad. The frequency signal is filtered
to avoid transients due to power system switchings and faults. The time integrator operates with
a definite delay time. When the frequency has returned back to the setting of RestoreFreq, the
RESTORE output is issued after the time delay tRestore, if the TRIP signal has earlier been is-
sued. The sign of the setting StartFreqGrad is essential, and controls if the function is used for
raising or lowering frequency conditions. The design of the rate-of-change of frequency function
is schematically described in figure145.
Figure 145: Schematic design of the rate-of-change of frequency function
BLOCK: blocks all outputs
BLKTRIP: blocks the TRIP output
BLKREST: blocks the RESTORE output
en05000835.vsd
RESTORE
Voltage
START
START
TRIP
Start
&
Trip
Output
Logic
BLOCK
Frequency
100 ms
Comparator
If
[StartFreqGrad<0
AND
df/dt <StartFreqGrad]
OR
[StartFreqGrad>0
AND
df/dt >StartFreqGrad]
Then
START
Comparator
U <IntBlockLevel
Comparator
f >RestoreFreq
OR
Time integrator
Definite Time Delay
TimeDlyOperate
TimeDlyReset
TimeDlyRestore
BLKDMAGN
Rate-of-Change
of Frequency
BLOCK
BLKTRIP
BLKRESET
311
Rate-of-change frequency
protection (PFRC, 81)
Chapter 8
Frequency protection
3.3 Function block
Figure 146: RCF function block
3.4 Input and output signals
Table 145: Input signals for the SAPFRC_81 (RCF1-) function block
Table 146: Output signals for the SAPFRC_81 (RCF1-) function block
SAPFRC
RCF1-
U3P
BLOCK
BLKTRIP
BLKREST
TRIP
START
RESTORE
BLKDMAGN
en05000322.vsd
Signal Description
U3P Group signal for voltage input
BLOCK Block of function
BLKTRIP Blocking operate output.
BLKREST Blocking restore output.
Signal Description
TRIP Operate/trip signal for frequencyGradient
START Start/pick-up signal for frequencyGradient
RESTORE Restore signal for load restoring purposes.
BLKDMAGN Blocking indication due to low amplitude
312
Rate-of-change frequency
protection (PFRC, 81)
Chapter 8
Frequency protection
3.5 Setting parameters
Table 147: Parameter group settings for the SAPFRC_81 (RCF1-) function
3.6 Technical data
Table 148: Rate-of-change frequency protection (PFRC, 81)
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
UBase 0.05 - 2000.00 0.05 400.00 kV Base setting for the
phase-phase voltage in
kV
StartFreqGrad -10.00 - 10.00 0.01 0.50 Hz/s Frequency gradient start
value. Sign defines direc-
tion.
IntBlockLevel 0 - 100 1 50 %UB Internal blocking level in
% of UBase.
tTrip 0.000 - 60.000 0.001 0.200 s Operate time delay in
pos./neg. frequency gra-
dient mode.
RestoreFreq 45.00 - 65.00 0.01 49.90 Hz Restore frequency if fre-
quency is above fre-
quency value (Hz)
tRestore 0.000 - 60.000 0.001 0.000 s Restore time delay.
tReset 0.000 - 60.000 0.001 0.000 s Time delay for reset.
Function Range or value Accuracy
Operate value, start function (-10.00-10.00) Hz/s 10.0 mHz/s
Operate value, internal blocking
level
(0-100)% of U
base
1.0% of U
r
Operate time, start function 100 ms typically -
313
About this chapter Chapter 9
Multipurpose protection
Chapter 9 Multipurpose
protection
About this chapter
This chapter describes Multipurpose protection and includes the General current and voltage
function. The way the functions work, their setting parameters, function blocks, input and output
signals and technical data are included for each function.
314
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
1 General current and voltage protection (GAPC)
1.1 Introduction
The protection module is recommended as a general backup protection with many possible ap-
plication areas due to its flexible measuring and setting facilities.
The built-in overcurrent protection feature has two settable current levels. Both of them can be
used either with definite time or inverse time characteristic. The overcurrent protection steps can
be made directional with selectable voltage polarizing quantity. Additionally they can be voltage
and/or current controlled/restrained. 2nd harmonic restraining facility is available as well. At too
low polarizing voltage the overcurrent feature can be either blocked, made non directional or or-
dered to use voltage memory in accordance with a parameter setting.
Additionally two overvoltage and two undervoltage steps, either with definite time or inverse
time characteristic, are available within each function.
The general function suits applications with underimpedance and voltage controlled overcurrent
solutions. The general function can also be utilized for generator transformer protection appli-
cations where positive, negative or zero sequence components of current and voltage quantities
is typically required.
Additionally generator applications such as loss of field, inadvertent energizing, stator or rotor
overload, circuit breaker head flash-over and open phase detection are just a few of possible pro-
tection arrangements with these functions.
1.2 Principle of operation
1.2.1 Measured quantities within the function
The function is always connected to three-phase current and three-phase voltage input in the
configuration tool, but it will always measure only one current and one voltage quantity selected
by the end user in the setting tool.
Function block name: GFxx- IEC 60617 graphical symbol:
ANSI number: 46, 51, 67, 51N, 67N, 27, 59, 21,
40
IEC 61850 logical node name: CVGAPC
I< I>
U< U>
315
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
The user can select to measure one of the current quantities shown in table149.
Table 149: Current selection for the GF function
The user can select to measure one of the voltage quantities shown in table150:
Set value for
the parameter
CurrentInput
Comment
1 Phase1 GF function will measure the phase L1 current phasor
2 Phase2 GF function will measure the phase L2 current phasor
3 Phase3 GF function will measure the phase L3 current phasor
4 PosSeq GF function will measure internally calculated positive sequence
current phasor
5 NegSeq GF function will measure internally calculated negative sequence
current phasor
6 3ZeroSeq GF function will measure internally calculated zero sequence current pha-
sor multiplied by factor 3
7 MaxPh GF function will measure current phasor of the phase with
maximummagnitude
8 MinPh GF function will measure current phasor of the phase with
minimummagnitude
9 UnbalancePh GF function will measure magnitude of unbalance current, which is inter-
nally calculated as the algebraic magnitude difference between the current
phasor of the phase with maximum magnitude and current phasor of the
phase with minimum magnitude. Phase angle will be set to 0 all the time
10 Phase1-Phase2 GF function will measure the current phasor internally calculated as the vec-
tor difference between the phase L1 current phasor and phase L2 current
phasor (i.e. I
L1
-I
L2
)
11 Phase2-Phase3 GF function will measure the current phasor internally calculated as the vec-
tor difference between the phase L2 current phasor and phase L3 current
phasor (i.e. I
L2
-I
L3
)
12 Phase3-Phase1 GF function will measure the current phasor internally calculated as the vec-
tor difference between the phase L3 current phasor and phase L1 current
phasor (i.e. I
L3
-I
L1
)
13 MaxPh-Ph GF function will measure ph-ph current phasor with the maximum magni-
tude
14 MinPh-Ph GF function will measure ph-ph current phasor with the minimum magnitude
15 UnbalancePh-Ph GF function will measure magnitude of unbalance current, which is inter-
nally calculated as the algebraic magnitude difference between the ph-ph
current phasor with maximum magnitude and ph-ph current phasor with
minimum magnitude. Phase angle will be set to 0 all the time
316
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
Table 150: Voltage selection for the GF function
It is important to notice that the voltage selection from table150 is always applicable regardless
the actual external VT connections. The three-phase VT inputs can be connected to IED as either
three phase-to-ground voltages U
L1
, U
L2
& U
L3
or three phase-to-phase voltages U
L1L2
, U
L2L3

& U
L3L1
). This information about actual VT connection is entered as a setting parameter for the
pre-processing block, which will then take automatic care about it.
Set value for
the parameter Volt-
ageInput
Comment
1 Phase1 GF function will measure the phase L1 voltage phasor
2 Phase2 GF function will measure the phase L2 voltage phasor
3 Phase3 GF function will measure the phase L3 voltage phasor
4 PosSeq GF function will measure internally calculated positive sequence voltage
phasor
5 -NegSeq GF function will measure internally calculated negative sequence voltage
phasor. This voltage phasor will be intentionally rotated for 180 in order to
enable easier settings for the directional feature when used.
6 -3ZeroSeq GF function will measure internally calculated zero sequence voltage pha-
sor multiplied by factor 3. This voltage phasor will be intentionally rotated for
180 in order to enable easier settings for the directional feature when used.
7 MaxPh GF function will measure voltage phasor of the phase with
maximummagnitude
8 MinPh GF function will measure voltage phasor of the phase with
minimummagnitude
9 UnbalancePh GF function will measure magnitude of unbalance voltage, which is inter-
nally calculated as the algebraic magnitude difference between the voltage
phasor of the phase with maximum magnitude and voltage phasor of the
phase with minimum magnitude. Phase angle will be set to 0 all the time
10 Phase1-Phase2 GF function will measure the voltage phasor internally calculated as the
vector difference between the phase L1 voltage phasor and phase L2 volt-
age phasor (i.e. U
L1
-U
L2
)
11 Phase2-Phase3 GF function will measure the voltage phasor internally calculated as the
vector difference between the phase L2 voltage phasor and phase L3 volt-
age phasor (i.e. U
L2
-U
L3
)
12 Phase3-Phase1 GF function will measure the voltage phasor internally calculated as the
vector difference between the phase L3 voltage phasor and phase L1 volt-
age phasor (i.e. U
L3
-U
L1
)
13 MaxPh-Ph GF function will measure ph-ph voltage phasor with the maximum magni-
tude
14 MinPh-Ph GF function will measure ph-ph voltage phasor with the minimum magni-
tude
15 UnbalancePh-Ph GF function will measure magnitude of unbalance voltage, which is inter-
nally calculated as the algebraic magnitude difference between the ph-ph
voltage phasor with maximum magnitude and ph-ph voltage phasor with
minimum magnitude. Phase angle will be set to 0 all the time
317
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
The user can select one of the current quantities shown in table151 for built-in current restraint
feature:
Table 151: Restraint current selection for the GF function
1.2.2 Base quantities within the function
The base quantities (i.e. 100%) shall be entered as setting parameters for every GF function.
Base current shall be entered as rated phase current of the protected object in primary amperes.
Base voltage shall be entered as rated phase-to-phase voltage of the protected object in primary
kV. Function will itself performer automatic scaling of these base quantities with factor sqrt(3)
(i.e. 1.732) in accordance with selected measured quantities.
1.2.3 Built-in overcurrent protection steps
Two overcurrent protection steps are available. They are absolutely identical and therefore only
one will be explained here.
Overcurrent step simply compares the magnitude of the measured current quantity
(seetable149) with the set pickup level. Non-directional overcurrent step will pickup if the
magnitude of the measured current quantity is bigger than this set level. Reset ratio is settable,
with default value of 0.96. However depending on other enabled built-in features this overcur-
rent pickup might not cause the overcurrent step start signal. Start signal will only come if all of
the enabled built-in features in the overcurrent step are fulfilled at the same time.
Second harmonic feature
The overcurrent protection step can be restrained by a second harmonic component in the mea-
sured current quantity (seetable149). However it shall be noted that this feature is not applica-
ble when one of the following measured currents is selected:
PosSeq (i.e. positive sequence current)
NegSeq (i.e. negative sequence current)
UnbalancePh (i.e. unbalance phase current)
UnbalancePh-Ph (i.e. unbalance ph-ph current)
This feature will simple prevent overcurrent step start if the second-to-first harmonic ratio in the
measured current exceeds the set level.
Set value for
the parameter Restr-
Curr
Comment
1 PosSeq GF function will measure internally calculated positive sequence current
phasor
2 NegSeq GF function will measure internally calculated negative sequence current
phasor
3 3ZeroSeq GF function will measure internally calculated zero sequence current pha-
sor multiplied by factor 3
4 MaxPh GF function will measure current phasor of the phase with maximum magni-
tude
318
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
Directional feature
The overcurrent protection step operation can be can be made dependent on the relevant phase
angle between measured current phasor (seetable149) and measured voltage phasor
(seetable150). In protection terminology it means that the PGPF function can be made direc-
tional by enabling this built-in feature. In that case overcurrent protection step will only operate
if the current flow is in accordance with the set direction (i.e. Forward, which means towards
the protected object, or Reverse, which means from the protected object). For this feature it is of
the outmost importance to understand that the measured voltage phasor (seetable150) and mea-
sured current phasor (seetable149) will be used for directional decision. Therefore it is the sole
responsibility of the end user to select the appropriate current and voltage signals in order to get
a proper directional decision. The PGPF function will NOT do this automatically. It will just
simply use the current and voltage phasors selected by the end user to check for the directional
criteria.
Table152 gives an overview of the typical choices (but not the only possible ones) for these two
quantities for traditional directional relays.
Table 152: Typical current and voltage choices for directional feature
Unbalance current or voltage measurement shall not be used when the directional feature is en-
abled.
Two types of directional measurement principles are available, I & U and IcosPhi&U. The first
principle, referred to as "I & U" in the parameter setting tool, checks that:
the magnitude of the measured current is bigger than the set pick-up level
the phasor of the measured current is within the operating region (defined by the
relay operate angle, ROADir parameter setting; seefigure147).
Set value for
the parameter Cur-
rentInput
Set value for
the parameter Volt-
ageInput
Comment
PosSeq PosSeq Directional positive sequence overcurrent function is
obtained. Typical setting for RCADir is from -45 to -90
depending on the power
NegSeq -NegSeq Directional negative sequence overcurrent function is
obtained. Typical setting for RCADir is from -45 to -90
depending on the power system voltage level (i.e. X/R
ratio)
3ZeroSeq -3ZeroSeq Directional zero sequence overcurrent function is
obtained. Typical setting for RCADir is from
0 to -90 depending on the power system earthing (i.e.
solidly earthed, earthed via resistor, etc.)
Phase1 Phase2-Phase3 Directional overcurrent function for the first phase is
obtained. Typical setting for RCADir is +30 or +45
Phase2 Phase3-Phase1 Directional overcurrent function for the second phase is
obtained. Typical setting for RCADir is +30 or +45
Phase3 Phase1-Phase2 Directional overcurrent function for the third phase is
obtained. Typical setting for RCADir is +30 or +45
319
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
Figure 147: I & U directional operating principle for the GF function
The second principle, referred to as "IcosPhi&U" in the parameter setting tool, checks that:
that the product Icos() is bigger than the set pick-up level, where is angle
between the current phasor and the mta line
that the phasor of the measured current is within the operating region (defined by
the Icos() straight line and the relay operate angle, ROADir parameter setting;
seefigure147).
where:
RCADir is -75
ROADir is 50
U=-3U0
Ipickup
Operate region
I=3Io
mta line
RCADir
ROADir
en05000252.vsd
320
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
Figure 148: GF, IcosPhi&U directional operating principle
Note that it is possible to decide by a parameter setting how the directional feature shall behave
when the magnitude of the measured voltage phasor falls below the pre-set value. User can select
one of the following three options:
Non-directional (i.e. operation allowed for low magnitude of the reference volt-
age)
Block (i.e. operation prevented for low magnitude of the reference voltage)
Memory (i.e. memory voltage shall be used to determine direction of the current)
It shall also be noted that the memory duration is limited in the algorithm to 100ms. After that
time the current direction will be locked to the one determined during memory time and it will
re-set only if the current fails below set pickup level or voltage goes above set voltage memory
limit.
Voltage restraint/control feature
The overcurrent protection step operation can be can be made dependent of a measured voltage
quantity (seetable150). Practically then the pickup level of the overcurrent step is not constant
but instead decreases with the decrease in the magnitude of the measured voltage quantity. Two
different types of dependencies are available:
Voltage restraint overcurrent (when setting parameter VDepMode_OC1=Slope)
where:
RCADir is -75
ROADir is 50
U=-3U0
Operate region
RCADir
ROADir Ipickup
I=3Io
mta line

en05000253.vsd
321
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
Figure 149: Example for OC1 step current pickup level variation as function of measured volt-
age magnitude in Slope mode of operation
Voltage controlled overcurrent (when setting parameter VDepMode_OC1=Step
has value=step)
Figure 150: Example for OC1 step current pickup level variation as function of measured volt-
age magnitude in Step mode of operation
Selected Voltage
Magnitude
OC1 Stage Pickup Level
StartCurr_OC1
VDepFact_OC1 * StartCurr_OC1
UHighLimit_OC1 ULowLimit_OC1
en05000324.vsd
Selected Voltage Magnitude
OC1 Stage Pickup Level
StartCurr_OC1
VDepFact_OC1 * StartCurr_OC1
UHighLimit_OC1
en05000323.vsd
322
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
This feature will simple change the set overcurrent pickup level in accordance with magnitude
variations of the measured voltage. It shall be noted that this feature will as well affect the pickup
current value for calculation of operate times for IDMT curves (i.e. overcurrent with IDMT
curve will operate faster during low voltage conditions).
Current restraint feature
The overcurrent protection step operation can be can be made dependent of a restraining current
quantity (seetable151). Practically then the pickup level of the overcurrent step is not constant
but instead increases with the increase in the magnitude of the restraining current.
Figure 151: Current pickup variation with restraint current magnitude
This feature will simple prevent overcurrent step to start if the magnitude of the measured cur-
rent quantity is smaller than the set percentage of the restrain current magnitude. However this
feature will not affect the pickup current value for calculation of operate times for IDMT curves.
This means that the IDMT curve operate time will not be influenced by the restrain current mag-
nitude.
When set, the start signal will start definite time delay or inverse (i.e. IDMT) time delay in ac-
cordance with the end user setting. If the start signal has value one for longer time than the set
time delay, the overcurrent step will set its trip signal to one. Reset of the start and trip signal
can be instantaneous or time delay in accordance with the end user setting.
1.2.4 Built-in undercurrent protection steps
Two undercurrent protection steps are available. They are absolutely identical and therefore only
one will be explained here. Undercurrent step simply compares the magnitude of the measured
current quantity (seetable149) with the set pickup level. The undercurrent step will pickup and
set its start signal to one if the magnitude of the measured current quantity is smaller than this
set level. The start signal will start definite time delay with set time delay. If the start signal has
IsetHigh
IsetLow
I
Measured
Restraint
atan(RestrCoeff)
en05000255.vsd
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323
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
value one for longer time than the set time delay the undercurrent step will set its trip signal to
one. Reset of the start and trip signal can be instantaneous or time delay in accordance with the
setting.
1.2.5 Built-in overvoltage protection steps
Two overvoltage protection steps are available. They are absolutely identical and therefore only
one will be explained here.
Overvoltage step simply compares the magnitude of the measured voltage quantity
(seetable150) with the set pickup level. The overvoltage step will pickup if the magnitude of
the measured voltage quantity is bigger than this set level. Reset ratio is settable, with default
value of 0.99.
The start signal will start definite time delay or inverse (i.e. IDMT) time delay in accordance
with the end user setting. If the start signal has value one for longer time than the set time delay,
the overvoltage step will set its trip signal to one. Reset of the start and trip signal can be instan-
taneous or time delay in accordance with the end user setting.
1.2.6 Built-in undervoltage protection steps
Two undervoltage protection steps are available. They are absolutely identical and therefore
only one will be explained here.
Undervoltage step simply compares the magnitude of the measured voltage quantity
(seetable150 with the set pickup level. The undervoltage step will pickup if the magnitude of
the measured voltage quantity is smaller than this set level. Reset ratio is settable, with default
value of 1.01.
The start signal will start definite time delay or inverse (i.e. IDMT) time delay in accordance
with the end user setting. If the start signal has value one for longer time than the set time delay,
the undervoltage step will set its trip signal to one. Reset of the start and trip signal can be in-
stantaneous or time delay in accordance with the end user setting.
1.2.7 Logic diagram
The simplified internal logics, for the PGPF function are shown in the following figures.
324
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
Figure 152: Treatment of measured currents within IED for PGPF function
Figure 152 shows how internal treatment of measured currents is done for multipurpose protec-
tion function
The following currents and voltages are inputs to the multipurpose protection function. They
must all be expressed in true power system (primary) Amperes and kilovolts.
1. Instantaneous values (samples) of currents & voltages from one three-phase cur-
rent and one three-phase voltage input.
2. Fundamental frequency phasors from one three-phase current and one
three-phase voltage input calculated by the pre-processing modules.
3. Sequence currents & voltages from one three-phase current and one three-phase
voltage input calculated by the pre-processing modules.
The multipurpose protection function:
1. Selects one current from the three phase input system (see table 153) for internal-
ly measured current.
2. Selects one voltage from the three phase input system (see table 154) for inter-
nally measured voltage.
3. Selects one current from the three phase input system (see table 154) for internal-
ly measured restraint current.
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Current and voltage selection
settings
en05000169.vsd
Selection of which current
and voltage shall be given to
the built-in protection
elements
Restraint current selection
Selection of restraint current
Selected current
Selected voltage
Selected restraint current
325
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
Figure 153: PGPF function main logic diagram for built in protection elements
Logic in figure 153 can be summarized as follows:
UC2
UC1
CURRENT
TRUC1
STUC2
TRUC2
STOC1
BLK2ND
STOC2
TROC2
OV1
STOV1
TROV1
OV2
STOV2
TROV2
UV1
STUV1
TRUV1
UV2
STUV2
TRUV2
Selected current
Selected restraint current
en05000170.vsd
Selected voltage
1
1
UDIRLOW
TROC1
OC1
2
nd
Harmonic
restraint
Current restraint
Directionality
Voltage control /
restraint
OC2
2
nd
Harmonic
restraint
Current restraint
Directionality
Voltage control /
restraint
DIROC2
DIROC1
2
nd
Harmonic
restraint
2
nd
Harmonic
restraint
VOLTAGE
326
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
1. The selected currents and voltage are given to built-in protection elements. Each
protection element and step makes independent decision about status of its
START and TRIP output signals.
2. More detailed internal logic for every protection element is given in the following
four figures
3. Common START and TRIP signals from all built-in protection elements & steps
(internal OR logic) are available from multipurpose function as well.
Figure 154: Simplified internal logic diagram for built-in first overcurrent step i.e. OC1 (step
OC2 has the same internal logic)
1
Second
harmonic check
Selected voltage
X
StartCurr_OC1
a
b
a>b
Voltage
control or
restraint
feature
OC1=On
BLKOC1
Directionality
check
Current
Restraint
Feature
I
measured
>k I
restraint
DIR_OK
Inverse
DEF
DEF time
selected
Inverse
time
selected
OR
Enable
second
harmonic
en05000831.vsd
Selected current
STOC1
TROC1
AND
BLKTROC
1
Selected restrain current
AND
327
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
Figure 155: Simplified internal logic diagram for built-in first undercurrent step i.e. UC1 (step
UC2 has the same internal logic)
Figure 156: Simplified internal logic diagram for built-in first overvoltage step i.e.OV1 (step
OV2 has the same internal logic)
a
b
b>a
Selected current
StartCurr_UC1
Operation_UC1=On
Bin input: BLKUC1
STUC1
en05000750.vsd
TRUC1
Bin input: BLKUC1TR
DEF
AND
AND
a
b
a>b
Selected voltage
StartVolt_OV1
Operation_OV1=On
BLKOV1
Inverse time
selected
en05000751.vsd
Inverse
DEF
DEF time
selected
STOV1
TROV1
AND
BLKTROV1
AND
OR
328
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
Figure 157: Simplified internal logic diagram for built-in first undervoltage step i.e.UV1 (step
UV2 has the same internal logic)
1.3 Function block
Figure 158: GF function block
AND
a
b
b>a
Selected voltage
StartVolt_UV1
Operation_UV1=On
BLKUV1
Inverse time
selected
en05000752.vsd
Inverse
DEF
DEF time
selected
OR
STUV1
TRUV1
AND
BLKTRUV
1
CVGAPC
GF01-
I3P
U3P
BLOCK
BLKOC1
BLKOC1TR
ENMLTOC1
BLKOC2
BLKOC2TR
ENMLTOC2
BLKUC1
BLKUC1TR
BLKUC2
BLKUC2TR
BLKOV1
BLKOV1TR
BLKOV2
BLKOV2TR
BLKUV1
BLKUV1TR
BLKUV2
BLKUV2TR
TRIP
TROC1
TROC2
TRUC1
TRUC2
TROV1
TROV2
TRUV1
TRUV2
START
STOC1
STOC2
STUC1
STUC2
STOV1
STOV2
STUV1
STUV2
BLK2ND
DIROC1
DIROC2
UDIRLOW
CURRENT
ICOSFI
VOLTAGE
UIANGLE
en05000372.vsd
329
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
1.4 Input and output signals
Table 153: Input signals for the CVGAPC (GF01-) function block
Table 154: Output signals for the CVGAPC (GF01-) function block
Signal Description
I3P Group signal for current input
U3P Group signal for voltage input
BLOCK Block of function
BLKOC1 Block of over current function OC1
BLKOC1TR Block of trip for over current function OC1
ENMLTOC1 When activated, the current multiplier is in use for OC1
BLKOC2 Block of over current function OC2
BLKOC2TR Block of trip for over current function OC2
ENMLTOC2 When activated, the current multiplier is in use for OC2
BLKUC1 Block of under current function UC1
BLKUC1TR Block of trip for under current function UC1
BLKUC2 Block of under current function UC2
BLKUC2TR Block of trip for under current function UC2
BLKOV1 Block of over voltage function OV1
BLKOV1TR Block of trip for over voltage function OV1
BLKOV2 Block of over voltage function OV2
BLKOV2TR Block of trip for over voltage function OV2
BLKUV1 Block of under voltage function UV1
BLKUV1TR Block of trip for under voltage function UV1
BLKUV2 Block of under voltage function UV2
BLKUV2TR Block of trip for under voltage function UV2
Signal Description
TRIP General trip signal
TROC1 Trip signal from overcurrent function OC1
TROC2 Trip signal from overcurrent function OC2
TRUC1 Trip signal from undercurrent function UC1
TRUC2 Trip signal from undercurrent function UC2
TROV1 Trip signal from overvoltage function OV1
TROV2 Trip signal from overvoltage function OV2
TRUV1 Trip signal from undervoltage function UV1
TRUV2 Trip signal from undervoltage function UV2
START General start signal
STOC1 Start signal from overcurrent function OC1
STOC2 Start signal from overcurrent function OC2
330
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
STUC1 Start signal from undercurrent function UC1
STUC2 Start signal from undercurrent function UC2
STOV1 Start signal from overvoltage function OV1
STOV2 Start signal from overvoltage function OV2
STUV1 Start signal from undervoltage function UV1
STUV2 Start signal from undervoltage function UV2
BLK2ND Block from second harmonic detection
DIROC1 Directional mode of OC1 (nondir, forward,reverse)
DIROC2 Directional mode of OC2 (nondir, forward,reverse)
UDIRLOW Low voltage for directional polarization
CURRENT Measured current value
ICOSFI Measured current multiplied with cos (Phi)
VOLTAGE Measured voltage value
UIANGLE Angle between voltage and current
Signal Description
331
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
1.5 Setting parameters
Table 155: Parameter group settings for the CVGAPC (GF01-) function
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
CurrentInput phase1
phase2
phase3
PosSeq
NegSeq
3*ZeroSeq
MaxPh
MinPh
UnbalancePh
phase1-phase2
phase2-phase3
phase3-phase1
MaxPh-Ph
MinPh-Ph
UnbalancePh-Ph
- MaxPh - Select current signal
which will be measured
inside function
IBase 1 - 99999 1 3000 A Base Current
VoltageInput phase1
phase2
phase3
PosSeq
-NegSeq
-3*ZeroSeq
MaxPh
MinPh
UnbalancePh
phase1-phase2
phase2-phase3
phase3-phase1
MaxPh-Ph
MinPh-Ph
UnbalancePh-Ph
- MaxPh - Select voltage signal
which will be measured
inside function
UBase 0.05 - 2000.00 0.05 400.00 kV Base Voltage
OperHarmRestr Off
On
- Off - Operation of 2nd har-
monic restrain Off / On
l_2nd/l_fund 10.0 - 50.0 1.0 20.0 % Ratio of second to funda-
mental current harmonic
in %
BlkLevel2nd 10 - 5000 1 5000 %IB Harm analyse disabled
above this current level in
% of Ibase
EnRestrainCurr Off
On
- Off - Enable current restrain
function On / Off
332
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
RestrCurrInput PosSeq
NegSeq
3*ZeroSeq
Max
- PosSeq - Select current signal
which will be used for
curr restrain
RestrCurrCoeff 0.00 - 5.00 0.01 0.00 - Restraining current coef-
ficient
RCADir -180 - 180 1 -75 Deg Relay Characteristic
Angle
ROADir 1 - 90 1 75 Deg Relay Operate Angle
LowVolt_VM 0.0 - 5.0 0.1 0.5 %UB Below this level in % of
Ubase setting ActLowVolt
takes over
Operation_OC1 Off
On
- Off - Operation OC1 Off / On
StartCurr_OC1 2.0 - 5000.0 1.0 120.0 %IB Operate current level for
OC1 in % of Ibase
CurrMult_OC1 1.0 - 10.0 0.1 2.0 - Multiplier for scaling the
current setting value for
OC1
CurveType_OC1 ANSI Ext. inv.
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Programmable
RI type
RD type
- ANSI Def. Time - Selection of time delay
curve type for OC1
tDef_OC1 0.00 - 6000.00 0.01 0.50 s Independent (definitive)
time delay of OC1
k_OC1 0.05 - 999.00 0.01 0.30 - Time multiplier for the
dependent time delay for
OC1
tMin_OC1 0.00 - 6000.00 0.01 0.05 s Minimum operate time for
IEC IDMT curves for OC1
ResCrvType_OC1 Instantaneous
IEC Reset
ANSI reset
- Instantaneous - Selection of reset curve
type for OC1
Parameter Range Step Default Unit Description
333
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
tResetDef_OC1 0.00 - 6000.00 0.01 0.00 s Reset time delay used in
IEC Definite Time curve
OC1
P_OC1 0.0001 - 10.0000 0.0001 0.0200 - Parameter P for cus-
tomer programmable
curve for OC1
A_OC1 0.0000 - 999.0000 0.0001 0.1400 - Parameter A for cus-
tomer programmable
curve for OC1
B_OC1 0.0000 - 99.0000 0.0001 0.0000 - Parameter B for cus-
tomer programmable
curve for OC1
C_OC1 0.0000 - 1.0000 0.0001 1.0000 - Parameter C for cus-
tomer programmable
curve for OC1
PR_OC1 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve for OC1
TR_OC1 0.005 - 600.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve for OC1
CR_OC1 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for OC1
VCntrlMode_OC1 Voltage control
Input control
Volt/Input control
Off
- Off - Control mode for voltage
controlled OC1 function
VDepMode_OC1 Step
Slope
- Step - Voltage dependent mode
OC1 (step, slope)
VDepFact_OC1 0.02 - 5.00 0.01 1.00 - Multiplying factor for I
pickup when OC1 is U
dependent
ULowLimit_OC1 1.0 - 200.0 0.1 50.0 %UB Voltage low limit setting
OC1 in % of Ubase
UHighLimit_OC1 1.0 - 200.0 0.1 100.0 %UB Voltage high limit setting
OC1 in % of Ubase
HarmRestr_OC1 Off
On
- Off - Enable block of OC1 by
2nd harmonic restrain
DirMode_OC1 Non-directional
Forward
Reverse
- Non-directional - Directional mode of OC1
(nondir, forward,reverse)
DirPrinc_OC1 I&U
IcosPhi&U
- I&U - Measuring on IandU or
IcosPhiandU for OC1
ActLowVolt1_VM Non-directional
Block
Memory
- Non-directional - Low voltage level action
for Dir_OC1 (Nodir, Blk,
Mem)
Parameter Range Step Default Unit Description
334
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
Operation_OC2 Off
On
- Off - Operation OC2 Off / On
StartCurr_OC2 2.0 - 5000.0 1.0 120.0 %IB Operate current level for
OC2 in % of Ibase
CurrMult_OC2 1.0 - 10.0 0.1 2.0 - Multiplier for scaling the
current setting value for
OC2
CurveType_OC2 ANSI Ext. inv.
ANSI Very inv.
ANSI Norm. inv.
ANSI Mod. inv.
ANSI Def. Time
L.T.E. inv.
L.T.V. inv.
L.T. inv.
IEC Norm. inv.
IEC Very inv.
IEC inv.
IEC Ext. inv.
IEC S.T. inv.
IEC L.T. inv.
IEC Def. Time
Programmable
RI type
RD type
- ANSI Def. Time - Selection of time delay
curve type for OC2
tDef_OC2 0.00 - 6000.00 0.01 0.50 s Independent (definitive)
time delay of OC2
k_OC2 0.05 - 999.00 0.01 0.30 - Time multiplier for the
dependent time delay for
OC2
tMin_OC2 0.00 - 6000.00 0.01 0.05 s Minimum operate time for
IEC IDMT curves for OC2
ResCrvType_OC2 Instantaneous
IEC Reset
ANSI reset
- Instantaneous - Selection of reset curve
type for OC2
tResetDef_OC2 0.00 - 6000.00 0.01 0.00 s Reset time delay used in
IEC Definite Time curve
OC2
P_OC2 0.0001 - 10.0000 0.0001 0.0200 - Parameter P for cus-
tomer programmable
curve for OC2
A_OC2 0.0000 - 999.0000 0.0001 0.1400 - Parameter A for cus-
tomer programmable
curve for OC2
B_OC2 0.0000 - 99.0000 0.0001 0.0000 - Parameter B for cus-
tomer programmable
curve for OC2
Parameter Range Step Default Unit Description
335
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
C_OC2 0.0000 - 1.0000 0.0001 1.0000 - Parameter C for cus-
tomer programmable
curve for OC2
PR_OC2 0.005 - 3.000 0.001 0.500 - Parameter PR for cus-
tomer programmable
curve for OC2
TR_OC2 0.005 - 600.000 0.001 13.500 - Parameter TR for cus-
tomer programmable
curve for OC2
CR_OC2 0.1 - 10.0 0.1 1.0 - Parameter CR for cus-
tomer programmable
curve for OC2
VCntrlMode_OC2 Voltage control
Input control
Volt/Input control
Off
- Off - Control mode for voltage
controlled OC2 function
VDepMode_OC2 Step
Slope
- Step - Voltage dependent mode
OC2 (step, slope)
VDepFact_OC2 0.02 - 5.00 0.01 1.00 - Multiplying factor for I
pickup when OC2 is U
dependent
ULowLimit_OC2 1.0 - 200.0 0.1 50.0 %UB Voltage low limit setting
OC2 in % of Ubase
UHighLimit_OC2 1.0 - 200.0 0.1 100.0 %UB Voltage high limit setting
OC2 in % of Ubase
HarmRestr_OC2 Off
On
- Off - Enable block of OC2 by
2nd harmonic restrain
DirMode_OC2 Non-directional
Forward
Reverse
- Non-directional - Directional mode of OC2
(nondir, forward,reverse)
DirPrinc_OC2 I&U
IcosPhi&U
- I&U - Measuring on IandU or
IcosPhiandU for OC2
ActLowVolt2_VM Non-directional
Block
Memory
- Non-directional - Low voltage level action
for Dir_OC2 (Nodir, Blk,
Mem)
Operation_UC1 Off
On
- Off - Operation UC1 Off / On
EnBlkLowI_UC1 Off
On
- Off - Enable internal low cur-
rent level blocking for
UC1
BlkLowCurr_UC1 0 - 150 1 20 %IB Internal low current
blocking level for UC1 in
% of Ibase
StartCurr_UC1 2.0 - 150.0 1.0 70.0 %IB Operate undercurrent
level for UC1 in % of
Ibase
Parameter Range Step Default Unit Description
336
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
tDef_UC1 0.00 - 6000.00 0.01 0.50 s Independent (definitive)
time delay of UC1
tResetDef_UC1 0.00 - 6000.00 0.01 0.00 s Reset time delay used in
IEC Definite Time curve
UC1
HarmRestr_UC1 Off
On
- Off - Enable block of UC1 by
2nd harmonic restrain
Operation_UC2 Off
On
- Off - Operation UC2 Off / On
EnBlkLowI_UC2 Off
On
- Off - Enable internal low cur-
rent level blocking for
UC2
BlkLowCurr_UC2 0 - 150 1 20 %IB Internal low current
blocking level for UC2 in
% of Ibase
StartCurr_UC2 2.0 - 150.0 1.0 70.0 %IB Operate undercurrent
level for UC2 in % of
Ibase
tDef_UC2 0.00 - 6000.00 0.01 0.50 s Independent (definitive)
time delay of UC2
tResetDef_UC2 0.00 - 6000.00 0.01 0.00 s Reset time delay used in
IEC Definite Time curve
UC2
HarmRestr_UC2 Off
On
- Off - Enable block of UC2 by
2nd harmonic restrain
Operation_OV1 Off
On
- Off - Operation OV1 Off / On
StartVolt_OV1 2.0 - 200.0 0.1 150.0 %UB Operate voltage level for
OV1 in % of Ubase
CurveType_OV1 Definite time
Inverse curve A
Inverse curve B
Inverse curve C
Prog. inv. curve
- Definite time - Selection of time delay
curve type for OV1
ResCrvType_OV1 Instantaneous
Frozen timer
Linearly decreased
- Instantaneous - Selection of reset curve
type for OV1
tDef_OV1 0.00 - 6000.00 0.01 1.00 s Operate time delay in sec
for definite time use of
OV1
tResetDef_OV1 0.00 - 6000.00 0.01 0.00 s Reset time delay in sec
for definite time use of
OV1
tMin_OV1 0.00 - 6000.00 0.01 0.05 s Minimum operate time for
IDMT curves for OV1
tResetIDMT_OV1 0.00 - 6000.00 0.01 0.00 s Reset time delay in sec
for IDMT curves for OV1
Parameter Range Step Default Unit Description
337
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
k_OV1 0.05 - 999.00 0.01 0.30 - Time multiplier for the
dependent time delay for
OV1
A_OV1 0.0050 - 999.0000 0.0001 0.1400 - Parameter A for cus-
tomer programmable
curve for OV1
B_OV1 0.5000 - 99.0000 0.0001 1.0000 - Parameter B for cus-
tomer programmable
curve for OV1
C_OV1 0.0000 - 1.0000 0.0001 1.0000 - Parameter C for cus-
tomer programmable
curve for OV1
D_OV1 0.000 - 10.000 0.001 0.000 - Parameter D for cus-
tomer programmable
curve for OV1
P_OV1 0.0001 - 10.0000 0.0001 0.0200 - Parameter P for cus-
tomer programmable
curve for OV1
Operation_OV2 Off
On
- Off - Operation UV2 Off / On
StartVolt_OV2 2.0 - 200.0 0.1 150.0 %UB Operate voltage level for
OV2 in % of Ubase
CurveType_OV2 Definite time
Inverse curve A
Inverse curve B
Inverse curve C
Prog. inv. curve
- Definite time - Selection of time delay
curve type for OV2
ResCrvType_OV2 Instantaneous
Frozen timer
Linearly decreased
- Instantaneous - Selection of reset curve
type for OV2
tDef_OV2 0.00 - 6000.00 0.01 1.00 s Operate time delay in sec
for definite time use of
OV2
tResetDef_OV2 0.00 - 6000.00 0.01 0.00 s Reset time delay in sec
for definite time use of
OV2
tMin_OV2 0.00 - 6000.00 0.01 0.05 s Minimum operate time for
IDMT curves for OV2
tResetIDMT_OV2 0.00 - 6000.00 0.01 0.00 s Reset time delay in sec
for IDMT curves for OV2
k_OV2 0.05 - 999.00 0.01 0.30 - Time multiplier for the
dependent time delay for
OV2
A_OV2 0.0050 - 999.0000 0.0001 0.1400 - Parameter A for cus-
tomer programmable
curve for OV2
Parameter Range Step Default Unit Description
338
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
B_OV2 0.5000 - 99.0000 0.0001 1.0000 - Parameter B for cus-
tomer programmable
curve for OV2
C_OV2 0.0000 - 1.0000 0.0001 1.0000 - Parameter C for cus-
tomer programmable
curve for OV2
D_OV2 0.000 - 10.000 0.001 0.000 - Parameter D for cus-
tomer programmable
curve for OV2
P_OV2 0.0001 - 10.0000 0.0001 0.0200 - Parameter P for cus-
tomer programmable
curve for OV2
Operation_UV1 Off
On
- Off - Operation UV1 Off / On
StartVolt_UV1 2.0 - 150.0 0.1 50.0 %UB Operate undervoltage
level for UV1 in % of
Ubase
CurveType_UV1 Definite time
Inverse curve A
Inverse curve B
Prog. inv. curve
- Definite time - Selection of time delay
curve type for UV1
ResCrvType_UV1 Instantaneous
Frozen timer
Linearly decreased
- Instantaneous - Selection of reset curve
type for UV1
tDef_UV1 0.00 - 6000.00 0.01 1.00 s Operate time delay in sec
for definite time use of
UV1
tResetDef_UV1 0.00 - 6000.00 0.01 0.00 s Reset time delay in sec
for definite time use of
UV1
tMin_UV1 0.00 - 6000.00 0.01 0.05 s Minimum operate time for
IDMT curves for UV1
tResetIDMT_UV1 0.00 - 6000.00 0.01 0.00 s Reset time delay in sec
for IDMT curves for UV1
k_UV1 0.05 - 999.00 0.01 0.30 - Time multiplier for the
dependent time delay for
UV1
A_UV1 0.0050 - 999.0000 0.0001 0.1400 - Parameter A for cus-
tomer programmable
curve for UV1
B_UV1 0.5000 - 99.0000 0.0001 1.0000 - Parameter B for cus-
tomer programmable
curve for UV1
C_UV1 0.0000 - 1.0000 0.0001 1.0000 - Parameter C for cus-
tomer programmable
curve for UV1
Parameter Range Step Default Unit Description
339
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
D_UV1 0.000 - 10.000 0.001 0.000 - Parameter D for cus-
tomer programmable
curve for UV1
P_UV1 0.0001 - 10.0000 0.0001 0.0200 - Parameter P for cus-
tomer programmable
curve for UV1
EnBlkLowV_UV1 Off
On
- On - Enable internal low volt-
age level blocking for
UV1
BlkLowVolt_UV1 0.0 - 5.0 0.1 0.5 %UB Internal low voltage
blocking level for UV1 in
% of Ubase
Operation_UV2 Off
On
- Off - Operation UV2 Off / On
StartVolt_UV2 2.0 - 150.0 0.1 50.0 %UB Operate undervoltage
level for UV2 in % of
Ubase
CurveType_UV2 Definite time
Inverse curve A
Inverse curve B
Prog. inv. curve
- Definite time - Selection of time delay
curve type for UV2
ResCrvType_UV2 Instantaneous
Frozen timer
Linearly decreased
- Instantaneous - Selection of reset curve
type for UV2
tDef_UV2 0.00 - 6000.00 0.01 1.00 s Operate time delay in sec
for definite time use of
UV2
tResetDef_UV2 0.00 - 6000.00 0.01 0.00 s Reset time delay in sec
for definite time use of
UV2
tMin_UV2 0.00 - 6000.00 0.01 0.05 s Minimum operate time for
IDMT curves for UV2
tResetIDMT_UV2 0.00 - 6000.00 0.01 0.00 s Reset time delay in sec
for IDMT curves for UV2
k_UV2 0.05 - 999.00 0.01 0.30 - Time multiplier for the
dependent time delay for
UV2
A_UV2 0.0050 - 999.0000 0.0001 0.1400 - Parameter A for cus-
tomer programmable
curve for UV2
B_UV2 0.5000 - 99.0000 0.0001 1.0000 - Parameter B for cus-
tomer programmable
curve for UV2
Parameter Range Step Default Unit Description
340
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
1.6 Technical data
Table 156: General current and voltage protection (GAPC)
C_UV2 0.0000 - 1.0000 0.0001 1.0000 - Parameter C for cus-
tomer programmable
curve for UV2
D_UV2 0.000 - 10.000 0.001 0.000 - Parameter D for cus-
tomer programmable
curve for UV2
P_UV2 0.0001 - 10.0000 0.0001 0.0200 - Parameter P for cus-
tomer programmable
curve for UV2
EnBlkLowV_UV2 Off
On
- On - Enable internal low volt-
age level blocking for
UV2
BlkLowVolt_UV2 0.0 - 5.0 0.1 0.5 %UB Internal low voltage
blocking level for UV2 in
% of Ubase
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Measuring current input phase1, phase2, phase3, Pos-
Seq, NegSeq, 3*ZeroSeq,
MaxPh, MinPh, UnbalancePh,
phase1-phase2,
phase2-phase3,
phase3-phase1, MaxPh-Ph,
MinPh-Ph, UnbalancePh-Ph
-
Base current (1 - 99999) A -
Measuring voltage input phase1, phase2, phase3, Pos-
Seq, -NegSeq, -3*ZeroSeq,
MaxPh, MinPh, UnbalancePh,
phase1-phase2,
phase2-phase3,
phase3-phase1, MaxPh-Ph,
MinPh-Ph, UnbalancePh-Ph
-
Base voltage (0.05 - 2000.00) kV -
Start overcurrent, step 1 and 2 (2 - 5000)% of I
base
1.0% of I
r
for I<I
r
1.0% of I for I>I
r
Start undercurrent, step 1 and 2 (2 - 150)% of I
base
1.0% of I
r
for I<I
r
1.0% of I for I>I
r
Definite time delay (0.00 - 6000.00) s 0.5% 10 ms
Operate time start overcurrent 25 ms typically at 0 to 2 xI
set
-
Reset time start overcurrent 25 ms typically at 2 to 0 xI
set
-
Operate time start undercurrent 25 ms typically at 2 to 0 xI
set
-
Reset time start undercurrent 25 ms typically at 0 to 2 xI
set
-
341
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
See table 398 and table 399 Parameter ranges for customer
defined characteristic no 17:
k: 0.05 - 999.00
A: 0.0000 - 999.0000
B: 0.0000 - 99.0000
C: 0.0000 - 1.0000
P: 0.0001 - 10.0000
PR: 0.005 - 3.000
TR: 0.005 - 600.000
CR: 0.1 - 10.0
See table 398 and table 399
Voltage level where voltage
memory takes over
(0.0 - 5.0)% of U
base
1.0% of U
r
Start overvoltage, step 1 and 2 (2.0 - 200.0)% of U
base
1.0% of U
r
for U<U
r
1.0% of U for U>U
r
Start undervoltage, step 1 and 2 (2.0 - 150.0)% of U
base
1.0% of U
r
for U<U
r
1.0% of U for U>U
r
Operate time, start overvoltage 25 ms typically at 0 to 2 x U
set
-
Reset time, start overvoltage 25 ms typically at 2 to 0 x U
set
-
Operate time start undervoltage 25 ms typically 2 to 0 xU
set
-
Reset time start undervoltage 25 ms typically at 0 to 2 x U
set
-
High and low voltage limit, volt-
age dependent operation
(1.0 - 200.0)% of U
base
1.0% of U
r
for U<U
r
1.0% of U for U>U
r
Directional function Settable: NonDir, forward and
reverse
-
Relay characteristic angle (-180 to +180) degrees 2.0 degrees
Relay operate angle (1 to 90) degrees 2.0 degrees
Reset ratio, overcurrent >95% -
Reset ratio, undercurrent <105% -
Reset ratio, overvoltage >95% -
Reset ratio, undervoltage <105% -
Overcurrent:
Critical impulse time 10 ms typically at 0 to 2 x I
set
-
Impulse margin time 15 ms typically -
Undercurrent:
Critical impulse time 10 ms typically at 2 to 0 x I
set
-
Impulse margin time 15 ms typically -
Overvoltage:
Function Range or value Accuracy
342
General current and voltage
protection (GAPC)
Chapter 9
Multipurpose protection
Critical impulse time 10 ms typically at 0 to 2 xU
set
-
Impulse margin time 15 ms typically -
Undervoltage:
Critical impulse time 10 ms typically at 2 to 0 xU
set
-
Impulse margin time 15 ms typically -
Function Range or value Accuracy
343
About this chapter Chapter 10
Secondary system supervision
Chapter 10 Secondary system
supervision
About this chapter
This chapter describes functions like Current circuit supervision and Fuse failure supervision.
The way the functions work, their setting parameters, function blocks, input and output signals
and technical data are included for each function.
344
Current circuit supervision (RDIF) Chapter 10
Secondary system supervision
1 Current circuit supervision (RDIF)
1.1 Introduction
Open or short circuited current transformer cores can cause unwanted operation of many protec-
tion functions such as differential, earth fault current and negative sequence current functions.
It must be remembered that a blocking of protection functions at an occurring open CT circuit
will mean that the situation will remain and extremely high voltages will stress the secondary
circuit.
The current circuit supervision function compares the residual current from a three phase set of
current transformer cores with the neutral point current on a separate input taken from another
set of cores on the current transformer.
A detection of a difference indicates a fault in the circuit and is used as alarm or to block protec-
tion functions expected to give unwanted tripping.
1.2 Principle of operation
The supervision function compares the absolute value of the vectorial sum of the three phase
currents |Iphase| and the numerical value of the residual current |Iref| from another current
transformer set, see figure159.
The FAIL output will be set to a logical one when the following criteria are fulfilled:
The numerical value of the difference |Iphase| |Iref| is higher than 80% of the
numerical value of the sum |Iphase| +|Iref|.
The numerical value of the current |Iphase| |Iref| is equal to or higher than the
set operate value IMinOp.
No phase current has exceeded Ip>Block during the last 10ms.
The current circuit supervision is enabled by setting Operation = On.
The FAIL output remains activated 100ms after the AND-gate resets when being activated for
more than 20ms. If the FAIL lasts for more than 150ms a ALARM will be issued. In this case
the FAIL and ALARM will remain activated 1s after the AND-gate resets. This prevents un-
wanted resetting of the blocking function when phase current supervision element(s) operate,
e.g. during a fault.
Function block name: CCSx- IEC 60617 graphical symbol:
ANSI number:
IEC 61850 logical node name: CCSRDIF
345
Current circuit supervision (RDIF) Chapter 10
Secondary system supervision
Figure 159: Simplified logic diagram for the current circuit supervision
The operate characteristic is percentage restrained, see figure 160.
346
Current circuit supervision (RDIF) Chapter 10
Secondary system supervision
Figure 160: Operate characteristics
1.3 Function block
Figure 161: CCS function block
1.4 Input and output signals
Table 157: Input signals for the CCSRDIF (CCS1-) function block
Slope =0.8
Slope =1
Operation
area
I
MinOp
99000068.vsd
phase ref
| I | - | I |
phase ref
| I | +| I |
Note!
Due to the formulas for the axis compared, |Iphase | - |I ref | and | I phase | + | I ref | respec-
tively, the slope can not be above 2.
CCSRDIF
CCS1-
I3P
IREF
BLOCK
FAIL
ALARM
en05000389.vsd
Signal Description
I3P Group signal for three phase current input
IREF TBD
BLOCK Block of function
347
Current circuit supervision (RDIF) Chapter 10
Secondary system supervision
Table 158: Output signals for the CCSRDIF (CCS1-) function block
1.5 Setting parameters
Table 159: Parameter group settings for the CCSRDIF (CCS1-) function
1.6 Technical data
Table 160: Current circuit supervision (RDIF)
Signal Description
FAIL Detection of current circuit failure
ALARM Alarm for current circuit failure
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
IBase 1 - 99999 1 3000 A IBase value for current
level detectors
Ip>Block 5 - 500 1 150 %IB Block of the function at
high phase current, in %
of IBase
IMinOp 5 - 200 1 20 %IB Minimum operate cur-
rent differential level in %
of IBase
Function Range or value Accuracy
Operate current (5-200)% of I
r
1.0% of I
r
at I I
r
1.0% of I at I >I
r
Block current (5-500)% of I
r
1.0% of I
r
at I I
r
1.0% of I at I >I
r
348
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
2 Fuse failure supervision (RFUF)
2.1 Introduction
The aim of the fuse failure supervision function (FSD) is to block voltage measuring functions
at failures in the secondary circuits between the voltage transformer and the IED in order to
avoid unwanted operations that otherwise might occur.
The fuse failure supervision function basically has two different algorithms, negative sequence
and zero sequence based algorithm and an additional delta voltage and delta current algorithm.
The negative sequence detection algorithm is recommended for IEDs used in isolated or
high-impedance earthed networks. It is based on the negative-sequence measuring quantities, a
high value of voltage 3U2 without the presence of the negative-sequence current 3I2.
The zero sequence detection algorithm is recommended for IEDs used in directly or low imped-
ance earthed networks. It is based on the zero sequence measuring quantities, a high value of
voltage 3U0 without the presence of the residual current 3I0.
A criterion based on delta current and delta voltage measurements can be added to the fuse fail-
ure supervision function in order to detect a three phase fuse failure, which in practice is more
associated with voltage transformer switching during station operations.
For better adaptation to system requirements, an operation mode setting has been introduced
which makes it possible to select the operating conditions for negative sequence and zero se-
quence based function. The selection of different operation modes makes it possible to choose
different interaction possibilities between the negative sequence and zero sequence based algo-
rithm.
2.2 Principle of operation
2.2.1 Zero sequence
The function can be set in five different modes by setting the parameter OpMode. The zero se-
quence function continuously measure the internal currents and voltages in all three phases and
calculate:
the zero-sequence voltage 3U0
the zero-sequence current 3I0.
The measured signals are compared with their respective set values 3U0< and 3I0>.
Function block name: FSDx- IEC 60617 graphical symbol:
ANSI number:
IEC 61850 logical node name: SDDRFUF
349
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
The function enable the internal signal FuseFailDet if the measured zero sequence voltage is
higher than the set value 3U0>, the measured zero sequence current is below the set value 3I0<
and the operation mode selector OpMode is set toUZsIZs (zero sequence mode). The latched
signal followed by the described criteria will set the output signals BLKU and BLKZ.
If the latched signal is present for more than 5seconds or if any phase voltage is below the set-
ting parameter UPh> at the same time as parameter SealIn = On the latched signal is sealed in.
It is recommended to always set SealIn to On since this will secure that no unwanted operation
of fuse failure will occur at closing command of breaker when the line is already energized from
the other end. The system voltages shall be normal before fuse failure is allowed to be activated
and initiate block of different protection functions.
If the latched signal is set and all three phase voltages are below the setting UPh> the output
signal 3PH will be activated (set to1). Also the output signals BLKU and BLKZ will be active
as well.
The output signal BLKU can also be activated if any phase voltage is below the setting UPh>
for more than 60seconds at the same time as the latch or seal in signal is set for more than
5seconds (that is fuse fail is detected), all phase currents are below the setting IDLD< (operate
level for dead line detection) and the circuit breaker is closed (input CBCLOSED is activated).
This condition covers for fuse failure at open breaker position.
Fuse failure condition is unlatched when the normal voltage conditions are restored
(STUL1N =STUL2N =STUL3N =0).
Fuse failure condition is stored in the non volatile memory in the IED. In the new start-up pro-
cedure the IED checks the 3PH (STORE3PH) value in its non volatile memory and establishes
the corresponding starting conditions.
350
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
Figure 162: Simplified logic diagram for fuse failure supervision function, zero sequence
based
Input and output signals
The output signals 3PH, BLKU and BLKZ can be blocked in the following conditions:
The input BLOCK is activated
The input BLKSP is activated at the same time as any of the internal signals
StartFusefail3Ph, StartFusefailRestr or StartFusefailGen are present
The operation mode selector OpMode is set to Off.
The IED is in TEST status (TEST-ACTIVE is high) and the function has been
blocked from the HMI (BlockFUSE=Yes)
The input BLOCK signal is a general purpose blocking signal of the fuse failure supervision
function. It can be connected to a binary input of the IED in order to receive a block command
from external devices or can be software connected to other internal functions of the IED itself
in order to receive a block command from internal functions. Through OR gate it can be con-
nected to both binary inputs and internal function outputs.
en05000655.vsd
Store in non volatile
(FUSE-STORE3PH)
BLKSP
BLKU
TEST-ACTIVE
AND
TEST
BlockFUSE=Yes
STDUDI
AND
BLKZ
3PH
MCBOP
DISCPOS
AND
AND
t
150 ms
OR
OR t
200 ms
AND
OR t
5 s
AND
STUL3N
STUL2N
STUL1N
OR
AND
AND
OR
OR
STORE3PH
20 ms
OR
1:All voltages
are low
From non
volatile memory
0: All voltages
are high
(Reset Latch)
1:Fuse failure for
more than 5 s
Dead-Line
Block
(Set Latch)
1:Function
Enable
1:Fuse Failure
Detection
STDUDIL1
OR
OR
OR
AND
STDUDIL2
STDUDIL3
IL1>
IL2>
IL3>
AND
OR
- loop
OperationDUDI =On
DLCND
CBCLOSED
BLOCK
OpMode =Off
351
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
The input BLKSP is intended to be connected to the trip output at any of the protection functions
included in the IED. When activated for than 20ms, the operation of the fuse failure is blocked
during a fixed time of 100ms. The aim is to increase the security against unwanted operations
during the opening of the breaker, which might cause unbalance conditions for which the fuse
failure might operate.
The output signal BLKZ will also be blocked if the internal dead line detection is activated. The
block signal has a 200ms drop-off time delay.
The input signal MCBOP is supposed to be connected via a terminal binary input to the N.C.
auxiliary contact of the miniature circuit breaker protecting the VT secondary circuit. The
MCBOP signal sets the output signals BLKU and BLKZ in order to block all the voltage related
functions when the MCB is open. The additional drop-off timer of 150ms prolongs the presence
of MCBOP signal to prevent the unwanted operation of voltage dependent function due to non
simultaneous closing of the main contacts of the miniature circuit breaker.
The input signal DISCPOS is supposed to be connected via a terminal binary input to the N.C.
auxiliary contact of the line disconnector. The DISCPOS signal sets the output signal BLKU in
order to block the voltage related functions when the line disconnector is open. The impedance
protection function is not affected by the position of the line disconnector since there will be no
line currents that can cause maloperation of the distance protection. If DISCPOS=0 it signifies
that the line is connected to the system and when the DISCPOS=1 it signifies that the line is dis-
connected from the system and the block signal BLKU is generated.
The output BLKU can be used for blocking the voltage related measuring functions (undervolt-
age protection, synchro-check etc.) except for the impedance protection.
The function output BLKZ can be used for blocking the impedance protection function.
If the fuse failure condition is detected for more then five seconds and at least one of the phases
has a low phase to earth voltage, then the fuse failure condition is latched: signal BLKU is turned
high, if there is no dead line condition also BLKZ is high; if all the three phases have no voltage
(STUL1N =STUL2N =STUL3N =1) then the output signal 3PH is turned high.
The output signal 3PH is high if the fuse failure condition is detected for 5seconds and all the
three measured voltages are low. The three phase criterion will also set the output BLKU and
BLKZ. The BLKZ will only be activated if not the internal dead line detection is activated at the
same time.
The fuse failure condition is unlatched when the normal voltage conditions are restored
(STUL1N =STUL2N =STUL3N =0).
2.2.2 Negative sequence
The negative sequence operates in the same way as the zero sequence, but it calculates the neg-
ative sequence component of current and voltage i.e.:
the negative sequence current I2
the negative sequence voltage U2
The measured signals are compared with their respective set values 3U2< and 3I2>.
352
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
The signal STZERO is set to1, if the negative sequence measured voltage exceeds its set
value3U2> and if the negative sequence measured current does not exceed its pre-set
value3I2<.
2.2.3 du/dt and di/dt
The current and voltage is continuously measured in all three phases and the following quantities
are calculated:
The change of voltage U/t
The change of current I/t
The calculated delta quantities are compared them with their respective set values DI< and
DU>.
The delta current and delta voltage algorithm, detects a fuse failure if a sufficient negative
change in voltage amplitude without a sufficient change in current amplitude is detected in each
phase separately. This check is performed if the circuit breaker is closed. Information about the
circuit breaker position is brought to the function input CBCLOSED through a binary input of
the IED.
There are two conditions for activating the internal STDU signal and set the latch:
The magnitude of U is higher than the corresponding setting DU> and I is be-
low the setting DI> in any phase at the same time as the circuit breaker is closed
(CBCLOSED =1)
The magnitude U is higher than the setting DU> and the magnitude of I is be-
low the setting DI> in any phase at the same time as the magnitude of the phase
current in the same phase is higher than the setting IPh>.
The first criterion requires that the internal signal STDUDI shall be activated in any phase at the
same time as circuit breaker is closed. Open circuit breaker at one end and energizing the line
from other end onto a fault could lead to wrong start of the fuse failure function at the end with
the open breaker. If this is considering to bee an important disadvantage, connect
theCBCLOSED input to FALSE. In this way only the second criterion can activate the signal
STDUDI.
The second criterion means that detected fuse failure in one phase together with high current for
the same phase will set the latch. The measured phase current is used to reduce the risk of false
fuse failure detection. If the current on the protected line is low, a voltage drop in the system (not
caused by fuse failure) is not by certain followed by current change and a false fuse failure might
occur. To prevent that the phase current criterion is introduced.
If the latch is set and if all measured voltages are low (lower than the settingUph>) the output
3PH will be activated indicating fuse failure in all three phases. The output BLKU and BLKZ
will be activated as well.
If the voltage is low in any phase for more than 5seconds (STUL1N, STUL2N or STUL3N=1),
the STDUDI signal is sealed in.
353
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
Figure 163: Simplified logic diagram for fuse failure supervision function, du/dt based.
2.2.4 Operation modes
The fuse failure supervision function can be switched on or off by the setting parameter Opera-
tion to On or Off.
Negative and zero sequence algorithm
For increased flexibility and adaptation to system requirements, an operation mode selector, Op-
Mode has been introduced to make it possible to select different operating modes for the nega-
tive and zero sequence based algorithm. The different operation modes are:
OpMode =Off; the negative and zero sequence function is switched off
OpMode =UNsINs; Negative sequence is selected
OpMode =UZsIZs; Zero sequence is selected
OpMode =UZsIZs OR UNsINs; Both negative and zero sequence is activated and
working in parallel in an OR-condition
OpMode =UZsIZs AND UNsINs; Both negative and zero sequence is activated
and working in series (AND-condition for operation)
Store in non volatile
(FUSE-STORE3PH)
BLKSP
BLKU
TEST-ACTIVE
AND
TEST
BlockFUSE=Yes
STDUDI
AND
BLKZ
MCBOP
DISCPOS
AND
AND
t
150 ms
OR
OR t
200 ms
AND
OR t
5 s
AND
STUL3N
STUL2N
STUL1N
OR
AND
AND
OR
OR
STORE3PH
20 ms
OR
1:All voltages
are low
From non volatile
memory
0: All voltages are
high (Reset Latch)
1:Fuse failure for
more than 5 s
Dead-Line
Block
(Set Latch)
1:Function
Enable
1:Fuse Failure
Detection
STDUDIL1
OR
OR
OR
STDUDIL2
STDUDIL3
IL1>Iph>
IL2>Iph>
IL3>Iph>
AND
OR
- loop
OperationDUDI =On
DLCND
AND
3PH
AND
AND
en05000656.vsd
CBCLOSED
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Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
OpMode =OptimZsNs; Optimum of negative and zero sequence (the function
that has the highest magnitude of measured negative and zero sequence current
will be activated).
du/dt and di/dt algorithm
The U and I function can be switched on or off by the setting parameter OperationDUDI to
On or Off.
2.2.5 Dead line detection
The function input signal DLCND (see figure162, 163 and 164) is related to the internal dead
line detection function. This signal is activated from the dead line condition function when the
voltage and the current in at least one phase is below their respective setting values. It prevents
the blocking of the impedance protection by a fuse failure detection during dead line condition
(that occurs also during single pole auto-reclosing). The 200ms drop-off timer prolongs the
dead line condition after the line-energization in order to prevent the blocking of the impedance
protection for unequal pole closing.
Figure 164: Simplified logic diagram for dead line detection
a
b
a<b
IPhL1
IPhL2
IPhL3
UPhL1
UPhL2
UPhL3
IDLD<
UDLD<
AND
a
b
a<b
a
b
a<b
a
b
a<b
a
b
a<b
a
b
a<b
AND
AND
OR
DLCND
SIGNAL
AND
en05000654.vsd
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Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
2.3 Function block
Figure 165: FSD function block
2.4 Input and output signals
Table 161: Input signals for the SDDRFUF (FSD1-) function block
Table 162: Output signals for the SDDRFUF (FSD1-) function block
SDDRFUF
FSD1-
BLOCK
I3P
U3P
CBCLOSED
MCBOP
DISCPOS
BLKSP
BLKZ
BLKU
3PH
en05000700.vsd
Signal Description
BLOCK Block of function
I3P Group signal for current input
U3P Group signal for voltage input
CBCLOSED Active when circuit breaker is closed
MCBOP Active when external MCB opens protected voltage circuit
DISCPOS Active when line disconnector is open
BLKSP Blocks operation of function when active
Signal Description
BLKZ Start of current and voltage controlled function
BLKU General start of function
3PH Three-phase start of function
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Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
2.5 Setting parameters
Table 163: Parameter group settings for the SDDRFUF (FSD1-) function
Parameter Range Step Default Unit Description
Operation Off
On
- On - Operation Off / On
IBase 1 - 99999 1 3000 A Base value for current
settings in A
UBase 0.05 - 2000.00 0.05 400.00 kV Base value for voltage
settings in kV
OpMode Off
UNsINs
UZsIZs
UZsIZs OR
UNsINs
UZsIZs AND
UNsINs
OptimZsNs
- UZsIZs - Operating mode selec-
tion
3U0> 1 - 100 1 30 %UB Operate level of residual
overvoltage element in %
of UBase
3I0< 1 - 100 1 10 %IB Operate level of residual
undercurrent element in
% of IBase
3U2> 1 - 100 1 30 %UB Operate level of neg seq
overvoltage element in %
of UBase
3I2< 1 - 100 1 10 %IB Operate level of neg seq
undercurrent element in
% of IBase
OperationDUDI Off
On
- Off - Operation of change
based function Off/On
DU> 1 - 100 1 60 %UB Operate level of change
in phase voltage in % of
UBase
DI< 1 - 100 1 15 %IB Operate level of change
in phase current in % of
IBase
UPh> 1 - 100 1 70 %UB Operate level of phase
voltage in % of UBase
357
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
2.6 Technical data
Table 164: Fuse failure supervision (RFUF)
IPh> 1 - 100 1 10 %IB Operate level of phase
current in % of IBase
SealIn Off
On
- On - Seal in functionality
Off/On
USealln< 1 - 100 1 70 %UB Operate level of seal-in
phase voltage in % of
UBase
IDLD< 1 - 100 1 5 %IB Operate level for open
phase current detection
in % of IBase
UDLD< 1 - 100 1 60 %UB Operate level for open
phase voltage detection
in % of UBase
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Operate voltage, zero sequence (1-100)% of U
base
1.0% of U
r
Operate current, zero sequence (1100)% of I
base
1.0% of I
r
Operate voltage, negative sequence (1100)% of U
base
1.0% of U
r
Operate current, negative sequence (1100)% of I
base
1.0% of I
r
Operate voltage change level (1100)% of U
base
1.0% of U
r
Operate current change level (1100)% of I
base
1.0% of I
r
358
Fuse failure supervision (RFUF) Chapter 10
Secondary system supervision
359
About this chapter Chapter 11
Control
Chapter 11 Control
About this chapter
This chapter describes the control functions. The way the functions work, their setting parame-
ters, function blocks, input and output signals and technical data are included for each function.
360
Synchrocheck and energizing check
(RSYN, 25)
Chapter 11
Control
1 Synchrocheck and energizing check (RSYN, 25)
1.1 Introduction
The synchrocheck function checks that the voltages on both sides of the circuit breaker are in
synchronism, or with at least one side dead to ensure that closing can be done safely.
The function includes a built-in voltage selection scheme for double bus and one- and a half or
ring busbar arrangements.
Manual closing as well as automatic reclosing can be checked by the function and can have dif-
ferent settings, e.g. the allowed frequency difference can be set to allow wider limits for the au-
to-reclose attempt than for the manual closing.
1.2 Principle of operation
1.2.1 Basic functionality
The synchronism check function measures the conditions across the circuit breaker and com-
pares them to set limits. The output is only given when all measured quantities are simultaneous-
ly within their set limits.
The energizing check function measures the bus and line voltages and compares them to both
high and low threshold detectors. The output is only given when the actual measured quantities
match the set conditions.
For single circuit breaker and 1 1/2 circuit breaker arrangements, the SYN function blocks have
the capability to make the necessary voltage selection. For single circuit breaker arrangements,
selection of the correct voltage is made using auxiliary contacts of the bus disconnectors. For 1
1/2 circuit breaker arrangements, correct voltage selection is made using auxiliary contacts of
the bus disconnectors as well as the circuit breakers
The internal logic for each function block as well as the Input and Outputs and the setting pa-
rameters with default setting and setting ranges is described in this document. For application
related information, please refer to the Application manual.
1.2.2 Logic diagrams
The logic diagrams that follow illustrate the main principles of the Synchrocheck function com-
ponents such as Synchronism check, Energizing check and Voltage selection, and are intended
to simplify the understanding of the function.
Function block name: SYNx- IEC 60617 graphical symbol:
ANSI number: 25
IEC 61850 logical node name:
SECRSYN
sc/vc
361
Synchrocheck and energizing check
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Chapter 11
Control
Synchronism check
The voltage difference, frequency difference and phase angle difference values are measured in
the IED centrally and are available for the Synchrocheck function for evaluation. If the bus volt-
age is connected as phase-phase and the line voltage as phase-neutral (or the opposite), this need
to be compensated. This is done with a setting, which scales up the line voltage to a level equal
to the bus voltage.
When the function is set to Operation =On, the measuring will start.
The function will compare the bus and line voltage values with the set values for UHighBusSync
and UHighLineSync.
If both sides are higher than the set values the measured values are compared with the set values
for acceptable frequency, phase angle and voltage difference FreqDiff, PhaseDiff and UDiff. If
a compensation factor is set due to the use of different voltages on the Bus and Line, the factor
is deducted from the line voltage before the comparison of the phase angle values.
The frequency on both sides of the circuit breaker is also measured. The frequencies must not
deviate from the rated frequency more than +/-5Hz. The frequency difference between the bus
frequency and the line frequency is measured and may not exceed the set value.
Two sets of settings for frequency difference and phase angle difference are available and used
for the Manual closing and Auto-Reclose functions respectively as required.
The inputs BLOCK and BLKSYNCH are available for total block of the complete Synchro-
check function and block of the Synchronism check function respectively. TSTAUTSY will al-
low testing of the function where the fulfilled conditions are connected to a separate test output
Two outputs MANSYOK resp. AUTOSYOK are activated when the actual measured conditions
match the set conditions for the respective output. The output signal can be delayed independent-
ly for MANSYOK conditions and for ARSYNOK.
A number of outputs are available as information about fulfilled checking conditions. UOK
shows that the voltages are high, UDIFF, FRDIFFM/A, PHDIFFM/A shows when the voltage
difference, frequency difference and phase angle difference conditions are met.
Energizing check
Voltage values are measured in the IED centrally and are available for evaluation by the Synch-
rocheck function. If the bus voltage is connected as phase-phase and the line voltage as
phase-neutral, (or the opposite) this needs to be compensated. This is done with a setting, which
scales the line voltage to a level equal to the bus voltage.
The function measures voltages on the busbar and the line to verify whether they are live or dead.
This is done by comparing with the set values UHighLineEnerg and ULowLineEnerg for bus re-
spectively line energizing.
The frequency on both sides of the circuit breaker is also measured. The frequencies must not
deviate from the rated frequency more than +/-5Hz. The frequency difference between the bus
frequency and the line frequency is measured and shall not exceed a set value.
362
Synchrocheck and energizing check
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Chapter 11
Control
The Energizing direction can be selected individually for the Manual and the Automatic func-
tions respectively. When the conditions are met the outputs AUTOENOK and MANENOK re-
spectively will be activated if the fuse supervision conditions are fulfilled. The output signal can
be delayed independently for MANENOK conditions and for AUTOENOK.
The inputs BLOCK and BLKENERG are available for total block of the complete Synchrocheck
function resp. block of the Energizing check function. TSTENOK will allow testing of the func-
tion where the fulfilled conditions are connected to a separate test output.
363
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Chapter 11
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Figure 166: Simplified logic diagram for the Synchronism check function
Voltage selection
The voltage selection module including supervision of included voltage transformer fuses for
the different arrangements is a basic part of the Synchrocheck function and determines the pa-
rameters fed to the Synchronism check and Energizing check functions. This includes the selec-
tion of the appropriate Line and Bus voltages and fuse supervision.
en05000790.vsd
OperationSync =On
TSTSYNC
BLKSYNC
BLOCK
SelectedFuseOK
TSTSYNOK
SYNOK
PHDIFFME
FRDIFFME
UDIFFME
PHDIFFM
PHDIFFA
FRDIFFM
FRDIFFA
UOK
UDIFF
OR
t
0-60 s
t
0-60 s
AND
AND
AND
AND
AND
AND
OR
AND
AND
AND
t
50 ms
UHighLineSync
UHighBusSync
UDiff
phaseAngleDifferenceValue
frequencyDifferenceValue
voltageDifferenceValue
1
1
1
1
1
AND
AND
tSync
tSync2
PhaseDiffM
PhaseDiffA
FreqDiffM
FreqDiffA
364
Synchrocheck and energizing check
(RSYN, 25)
Chapter 11
Control
The voltage selection type to be used is set with the parameter CBConfig. The different alterna-
tives are described below.
If NoVoltageSel is set the default voltages used will be ULine1 and UBus1. This is also the case
when external voltage selection is provided. Fuse failure supervision for the used inputs must
also be connected.
The voltage selection function selected voltages and fuse conditions are the Synchronism check
and Energizing check inputs.
For the disconnector positions it is advisable to use (NO) a and (NC) b type contacts to supply
Disconnector Open and Closed positions but it is of course also possible to use an inverter for
one of the positions.
Fuse failure supervision
External fuse-failure signals or signals from a tripped fuse switch/MCB are connected to binary
inputs that are configured to the inputs of the Synchrocheck functions in the terminal. Alterna-
tively the internal signals from fuse failure supervision can be used when available. There are
two alternative connection possibilities. Inputs labelled OK must be connected if the available
contact indicates that the voltage circuit is healthy. Inputs labelled FF must be connected if the
available contact indicates that the voltage circuit is faulty.
The SYN1(2)-UB1/2OK and SYN1(2)-UB1/2FF inputs are related to the busbar voltage and the
SYN1(2)-ULN1/2OK and SYN1(2)-ULN1/2FF inputs are related to the line voltage. Configure
them to the binary inputs or function outputs that indicate the status of the external fuse failure
of the busbar and line voltages. In the event of a fuse failure, the energizing check functions are
blocked. The synchronism check requires full voltage on both sides and will be blocked auto-
matically in the event of fuse failures.
Voltage selection for a single circuit breaker with double busbars
This function uses the binary input from the disconnectors auxiliary contacts
B1QOPEN-B1QCLD for Bus 1, and B2QOPEN-B2QCLD for Bus 2 to select between bus 1 and
bus 2 voltages. If the disconnector connected to bus 2 is closed and the disconnector connected
to bus 1 is opened the bus 2 voltage is used. All other combinations use the bus 1 voltage. The
Outputs B1SEL and B2SEL respectively indicate the selected Bus voltage.
The function also checks the fuse-failure signals for bus 1, bus 2 and line voltage transformers.
Inputs UB1OK-UB1FF supervise the fuse for Bus 1. UB2OK-UB2FF supervises the fuse for
Bus 2 and ULNOK-ULNFF supervises the fuse for the Line voltage transformer. The inputs fail
(FF) or healthy (OK) can alternatively be used dependent on the available signal. If a fuse-failure
is detected in the selected voltage source an output signal USELFAIL is set. This output signal
is true if the selected bus or line voltages have a fuse failure. This output as well as the function
can be blocked with the input signal BLOCK. The function logic diagram is shown in figure 167.
365
Synchrocheck and energizing check
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Chapter 11
Control
Figure 167: Logic diagram for the voltage selection function of a single circuit breaker with
double busbars
Voltage selection for a 1 1/2 circuit breaker arrangement
Note that with 11/2 breaker schemes two Synchrocheck functions must be used in the IED (three
for two IEDs in a complete bay). Below, the scheme for one Bus breaker and the Tie breakers is
described.
This voltage selection function uses the binary inputs from the disconnectors and circuit break-
ers auxiliary contacts to select the right voltage for the Synchrocheck (Synchronism and Ener-
gizing check) function. For the bus circuit breaker one side of the circuit breaker is connected to
the busbar and the other side is connected either to line 1, line 2 or the other busbar depending
on the arrangement.
Inputs LN1QOPEN-LN1QCLD, B1QOPEN-B1QCLD, B2QOPEN-B2QCLD,
LN2QOPEN-LN2QCLD are inputs for the position of the Line disconnectors respectively the
Bus and Tie breakers. The Outputs LN1SEL, LN2SEL and B2SEL will give indication of the
selected Line voltage as a reference to the fixed Bus 1 voltage.
The fuse supervision is connected to ULNOK-ULNFF etc. and with alternative Healthy or Fail-
ing fuse signals depending on what is available for each of fuse (MCB).
AND
AND
AND
bus1Voltage
OR
OR
OR
ULN1FF
ULN1OK
UB1FF
UB1OK
UB2FF
UB2OK
B2QCLD
B2QOPEN
B1QCLD
B1QOPEN
selectedFuseOK
BLOCK
bus2Voltage
busVoltage
AND
1
invalidSelection
B2SEL
B1SEL
AND
AND
AND
USELFAIL
en05000779.vsd
OR
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Synchrocheck and energizing check
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Chapter 11
Control
The tie circuit breaker is connected either to bus 1 or line 1 on one side and the other side is con-
nected either to bus 2 or line 2. Four different output combinations are possible, bus to bus, bus
to line, line to bus and line to line.
The line 1 voltage is selected if the line 1 disconnector is closed.
The bus 1 voltage is selected if the line 1 disconnector is open and the bus 1 cir-
cuit breaker is closed.
The line 2 voltage is selected if the line 2 disconnector is closed.
The bus 2 voltage is selected if the line 2 disconnector is open and the bus 2 Cir-
cuit breaker is closed.
The function also checks the fuse-failure signals for bus 1, bus 2, line 1 and line 2. If a fuse-fail-
ure is detected in the selected voltage an output signal USELFAIL is set. This output signal is
true if the selected bus or line voltages have a fuse failure. This output as well as the function
can be blocked with the input signal BLOCK.The function block diagram for the voltage selec-
tion of a bus circuit breaker is shown in Figure 168: and for the tie circuit breaker in Figure 169:
367
Synchrocheck and energizing check
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Chapter 11
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Figure 168: Simplified logic diagram for the voltage selection function for a bus circuit break-
er in a 1 1/2 breaker arrangement.
AND
AND
OR
OR
ULN1FF
ULN1OK
UB1FF
UB1OK
UB2FF
UB2OK
B1QCLD
B1QOPEN
LN1QCLD
LN1QOPEN
selectedFuseOK
BLOCK
lineVoltage
invalidSelection
LN1SEL
AND
AND
USELFAIL
ULN2FF
ULN2OK
OR
AND
AND
B2QCLD
B2QOPEN
LN2QCLD
LN2QOPEN
AND
AND
LN2SEL
OR
AND
B2SEL
AND
AND
AND
en05000780.vsd
OR
OR
line2Voltage
bus2Voltage
line1Voltage
368
Synchrocheck and energizing check
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Chapter 11
Control
Figure 169: Simplified logic diagram for the voltage selection function for the tie circuit break-
er in 1 1/2 breaker arrangement.
1.3 Function block
The Synchrocheck function block is shown in Figure 170:. Tables describing the inputs, outputs
and setting parameters of this function are presented in the following sections of this document.
Refer to the Application manual for the use of inputs and outputs in your particular applica-
tion.
AND
AND
OR
OR
ULN1FF
ULN1OK
UB1FF
UB1OK
UB2FF
UB2OK
B1QCLD
B1QOPEN
LN1QCLD
LN1QOPEN
selectedFuseOK
BLOCK
line1Voltage
LN1SEL
AND
AND
USELFAIL
ULN2FF
ULN2OK
OR
AND
AND
AND
AND
AND
1
B1SEL
bus1Voltage
busVoltage
AND
AND
AND
B2QCLD
B2QOPEN
LN2QCLD
LN2QOPEN
bus2Voltage
LN2SEL
AND
AND
1
B2SEL
line2Voltage
lineVoltage
invalidSelection OR
en05000781.vsd
OR
OR
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Chapter 11
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Figure 170: SYN function block
1.4 Input and output signals
Table 165: Input signals for the SECRSYN_25 (SYN1-) function block
SECRSYN
SYN1-
U3PBB1
U3PBB2
U3PLN1
U3PLN2
B1QOPEN
B1QCLD
B2QOPEN
B2QCLD
LN1QOPEN
LN1QCLD
LN2QOPEN
LN2QCLD
UB1OK
UB1FF
UB2OK
UB2FF
ULN1OK
ULN1FF
ULN2OK
ULN2FF
TSTENERG
TSTSYNC
BLKENERG
BLKSYNC
BLOCK
B1SEL
B2SEL
LN1SEL
LN2SEL
USELFAIL
AUTOENOK
MANENOK
TSTENOK
MANSYOK
TSTMANSY
UDIFF
FRDIFFM
FRDIFFA
PHDIFFM
PHDIFFA
UOK
AUTOSYOK
TSTAUTSY
en05000702.vsd
Signal Description
U3PBB1 Group signal for voltage input busbar 1
U3PBB2 Group signal for voltage input busbar 2
U3PLN1 Group signal for voltage input line 1
U3PLN2 Group signal for voltage input line 2
B1QOPEN Open status for CB or disconnector connected to bus1
B1QCLD Close status for CB or disconnector connected to bus1
B2QOPEN Open status for CB or disconnector connected to bus2
B2QCLD Close status for CB or disconnector connected to bus2
LN1QOPEN Open status for CB or disconnector connected to line1
LN1QCLD Close status for CB or disconnector connected to line1
LN2QOPEN Open status for CB or disconnector connected to line2
LN2QCLD Close status for CB or disconnector connected to line2
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Chapter 11
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Table 166: Output signals for the SECRSYN_25 (SYN1-) function block
UB1OK Bus1 voltage transformer OK
UB1FF Bus1 voltage transformer fuse failure
UB2OK Bus2 voltage transformer OK
UB2FF Bus2 voltage transformer fuse failure
ULN1OK Line1 voltage transformer OK
ULN1FF Line1 voltage transformer fuse failure
ULN2OK Line2 voltage transformer OK
ULN2FF Line2 voltage transformer fuse failure
TSTENERG Energizing check in test mode
TSTSYNC Synchrocheck in test mode
BLKENERG Energizing check blocked
BLKSYNC Synchrocheck blocked
BLOCK Block of function
Signal Description
B1SEL Bus1 selected
B2SEL Bus2 selected
LN1SEL Line1 selected
LN2SEL Line2 selected
USELFAIL Selected voltage transformer fuse failed
AUTOENOK Automatic energizing check OK
MANENOK Manual energizing check OK
TSTENOK Energizing check OK test output
MANSYOK Manual synchro check OK
TSTMANSY Manual synchro check OK test output
UDIFF Voltage difference out of limit
FRDIFFM Frequency difference out of limit for Manual operation
FRDIFFA Frequency difference out of limit for Auto operation
PHDIFFM Phase angle difference out of limit for Manual Operation
PHDIFFA Phase angle difference out of limit for Auto operation
UOK Voltage amplitudes above set limits
AUTOSYOK Auto synchro check OK
TSTAUTSY Auto synchro check OK test output
Signal Description
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Control
1.5 Setting parameters
Table 167: Parameter group settings for the SECRSYN_25 (SYN1-) function
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off / On
SelPhaseBus1 phase1
phase2
phase3
phase1-phase2
phase2-phase3
phase3-phase1
- phase2 - Select phase for bus1
SelPhaseBus2 phase1
phase2
phase3
phase1-phase2
phase2-phase3
phase3-phase1
- phase2 - Select phase for bus2
SelPhaseLine1 phase1
phase2
phase3
phase1-phase2
phase2-phase3
phase3-phase1
- phase2 - Select phase for line1
SelPhaseLine2 phase1
phase2
phase3
phase1-phase2
phase2-phase3
phase3-phase1
- phase2 - Select phase for line2
CBConfig No voltage sel.
Double bus
1 1/2 bus CB
1 1/2 bus alt. CB
Tie CB
- No voltage sel. - Select CB configuration
UHighBusEnerg 50.0 - 120.0 1.0 80.0 %UB Voltage high limit bus for
energizing check in % of
UBase
UHighLineEnerg 50.0 - 120.0 1.0 80.0 %UB Voltage high limit line for
energizing check in % of
UBase
ULowBusEnerg 10.0 - 80.0 1.0 40.0 %UB Voltage low limit bus for
energizing check in % of
UBase
ULowLineEnerg 10.0 - 80.0 1.0 40.0 %UB Voltage low limit line for
energizing check in % of
UBase
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AutoEnerg Off
DLLB
DBLL
Both
- DLLB - Automatic energizing
check mode
ManEnerg Off
DLLB
DBLL
Both
- DLLB - Manual energizing check
mode
ManEnergDBDL Off
On
- Off - Manual dead bus, dead
line energizing
tAutoEnerg 0.000 - 60.000 0.001 0.100 s Time delay for automatic
energizing check
tManEnerg 0.000 - 60.000 0.001 0.100 s Time delay for manual
energizing check
UMaxEnerg 80.0 - 140.0 1.0 115.0 %UB Maximum voltage for
energizing in % of UBase
UBase 0.001 - 9999.999 0.001 400.000 kV Base voltage in kV
OperationSync Off
On
- On - Operation for synchro-
nism check function
Off/On
PhaseShift -180 - 180 5 0 Deg Phase shift
URatio 0.20 - 5.00 0.01 1.00 - Voltage ratio
UHighBusSync 50.0 - 120.0 1.0 80.0 %UB Voltage high limit bus for
synchrocheck in % of
UBase
UHighLineSync 50.0 - 120.0 1.0 80.0 %UB Voltage high limit line for
synchrocheck in % of
UBase
FreqDiffM 0.003 - 1.000 0.001 0.050 Hz Frequency difference
limit between bus and
line Manual
FreqDiffA 0.003 - 1.000 0.001 0.200 Hz Frequency difference
limit between bus and
line Auto
Parameter Range Step Default Unit Description
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Control
1.6 Technical data
Table 168: Synchrocheck and energizing check (RSYN, 25)
PhaseDiffM 5.0 - 90.0 1.0 25.0 Deg Phase angle difference
limit between bus and
line Manual
PhaseDiffA 5.0 - 90.0 1.0 25.0 Deg Phase angle difference
limit between bus and
line Auto
UDiff 2.0 - 50.0 1.0 15.0 %UB Voltage difference limit
between bus and line in
% of UBase
tSyncM 0.000 - 60.000 0.001 1.000 s Time delay output for
synchrocheck
tSyncA 0.000 - 60.000 0.001 0.100 s Time delay output for
synchrocheck for Auto
operation
Parameter Range Step Default Unit Description
Function Range or value Accuracy
Phase shift,
line
-
bus
(-180 to 180) degrees -
Voltage ratio, U
bus
/U
line
(0.20-5.00)% of U
base
-
Voltage high limit for synchro-
check
(50.0-120.0)% of U
base
1.0% of U
r
at U U
r
1.0% of U at U >U
r
Reset ratio, synchrocheck >95% -
Frequency difference limit
between bus and line
(0.003-1.000) Hz 2.0 mHz
Phase angle difference limit
between bus and line
(5.0-90.0) degrees 2.0 degrees
Voltage difference limit between
bus and line
(2.0-50.0)% of U
base
1.0% of U
r
Time delay output for synchro-
check
(0.000-60.000) s 0.5% 10 ms
Voltage high limit for energizing
check
(50.0-120.0)% of U
base
1.0% of U
r
at U U
r
1.0% of U at U >U
r
Reset ratio, voltage high limit >95% -
Voltage low limit for energizing
check
(10.0-80.0)% of U
base
1.0% of U
r
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Control
Reset ratio, voltage low limit <105% -
Maximum voltage for energizing (80.0-140.0)% of U
base
1.0% of U
r
at U U
r
1.0% of U at U >U
r
Time delay for energizing check (0.000-60.000) s 0.5% 10 ms
Operate time for synchrocheck
function
160 ms typically -
Operate time for energizing func-
tion
80 ms typically -
Function Range or value Accuracy
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2 Apparatus control (APC)
2.1 Introduction
The apparatus control is a function for control and supervision of circuit breakers, disconnectors
and earthing switches within a bay. Permission to operate is given after evaluation of conditions
from other functions such as interlocking, synchrocheck, operator place selection and external
or internal blockings.
2.2 Principle of operation
A bay can handle, for example a power line, a transformer, a reactor, or a capacitor bank. The
different primary apparatuses within the bay can be controlled via the apparatus control function
directly by the operator or indirectly by automatic sequences.
Because a primary apparatus can be allocated to many functions within a Substation Automation
system, the object-oriented approach with a function module that handles the interaction and sta-
tus of each process object ensures consistency in the process information used by higher-level
control functions.
Primary apparatuses such as breakers and disconnectors are controlled and supervised by one
software module (SCSWI) each. Because the number and type of signals connected to a breaker
and a disconnector are almost the same, the same software is used to handle these two types of
apparatuses.
The software module is connected to the physical process in the switchyard via an interface
module by means of a number of digital inputs and outputs. One type of interface module is in-
tended for a circuit breaker (SXCBR) and another type is intended for a disconnector or earthing
switch (SXSWI). Four types of function blocks are available to cover most of the control and
supervision within the bay. These function blocks are interconnected to form a control function
reflecting the switchyard configuration. The total number used depends on the switchyard con-
figuration. These four types are:
Bay control QCBAY
Switch controller SCSWI
Circuit breaker SXCBR
Circuit switch SXSWI
The three latter functions are logical nodes according to IEC 61850. The function blocks Local-
Remote and LocRemControl, to handle the local/remote switch, and the function blocks
QCRSV and RESIN, for the reservation function, also belong to the apparatus control function.
The principles of operation, function block, input and output signals and setting parameters for
all these functions are described below.
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2.3 Bay control (QCBAY)
2.3.1 Introduction
This function is used to handle the selection of the operator place per bay. The bay control func-
tion also provides blocking functions that can be distributed to different apparatuses within the
bay.
2.3.2 Principle of operation
The functionality of the bay control function is not defined in the IEC 6185081 standard,
which means that the function is a vendor specific logical node.
The function sends information about the Permitted Source To Operate (PSTO) and blocking
conditions to other functions within the bay e.g. switch control functions, voltage control func-
tions and measurement functions.
Local panel switch
The local panel switch is a switch that defines the operator place selection. The switch connected
to this function can have three positions remote/local/off. The positions are here defined so that
remote means that operation is allowed from station/remote level and local from the IED level.
The local/remote switch is normally situated on the control/protection IED itself, which means
that the position of the switch and its validity information are connected internally, and not via
I/O boards. When the switch is mounted separately on the IED the signals are connected to the
function via I/O boards.
When the local panel switch is in Off position all commands from remote and local level will be
ignored. If the position for the local/remote switch is not valid the PSTO output will always be
set to faulty state (3), which means no possibility to operate.
To adapt the signals from the local HMI or from an external local/remote switch, the function
blocks LocalRemote and LocRemControl are needed and connected to QCBAY. For more in-
formation, see section 2.4 "Local/Remote switch (LocalRemote, LocRemControl)".
Permitted Source To Operate (PSTO)
The actual state of the operator place is presented by the value of the Permitted Source To Op-
erate, PSTO signal. The PSTO value is evaluated from the local/remote switch position accord-
ing to table169. In addition, there is one configuration parameter that affects the value of the
PSTO signal. If the parameter AllPSTOValid is set and LR-switch position is in Local or Remote
state, the PSTO value is set to 5 (all), i.e. it is permitted to operate from both local and remote
level without any priority. When the external panel switch is in Off position the PSTO value
shows the actual state of switch, i.e. 0. In this case it is not possible to control anything.
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Table 169: PSTO values for different Local panel switch positions
Blockings
The blocking states for position indications and commands are intended to provide the possibil-
ity for the user to make common blockings for the functions configured within a complete bay.
The blocking facilities provided by the bay control function are the following:
Blocking of position indications, BL_UPD. This input will block all inputs relat-
ed to apparatus positions for all configured functions within the bay.
Blocking of commands, BL_CMD. This input will block all commands for all
configured functions within the bay.
Blocking of function, BLOCK, signal from DO (Data Object) Behavior (IEC
6185081). If DO Behavior is set to "blocked" it means that the function is ac-
tive, but no outputs are generated, no reporting, control commands are rejected
and functional and configuration data is visible.
The switching of the Local/Remote switch requires an Control level password. This will be re-
quested at attempt to operate if authority levels has been defined in the IED. Default password
is "abb".
2.3.3 Function block
Figure 171: CB function block
Local panel switch
positions
PSTO value AllPSTOValid
(configuration
parameter)
Possible locations that shall be able
to operate
0 =Off 0 -- Not possible to operate
1 =Local 1 FALSE Local Panel
1 =Local 5 TRUE Local or Remote level without any priority
2 =Remote 2 FALSE Remote level
2 =Remote 5 TRUE Local or Remote level without any priority
3 =Faulty 3 -- Not possible to operate
QCBAY
CB01-
LR_OFF
LR_LOC
LR_REM
LR_VALID
BL_UPD
BL_CMD
PSTO
UPD_BLKD
CMD_BLKD
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2.3.4 Input and output signals
Table 170: Input signals for the QCBAY (CB01-) function block
Table 171: Output signals for the QCBAY (CB01-) function block
2.3.5 Setting parameters
Table 172: General settings for the QCBAY (CB01-) function
2.4 Local/Remote switch (LocalRemote, LocRemControl)
2.4.1 Introduction
The signals from the local LCD HMI or from an external local/remote switch are applied via
function blocks LocalRemote and LocRemControl to the Bay control QCBAY function block.
A parameter in function block LocalRemote is set to choose if the switch signals are coming
from the local LCD HMI or from an external hardware switch connected via binary inputs.
2.4.2 Principle of operation
The function block LocalRemote handles the signals coming from the local/remote switch. The
connections are seen in figure172, where the inputs on function block LocalRemote are con-
nected to binary inputs if an external switch is used. When a local LCD HMI is used, the inputs
are not used and are set to FALSE in the configuration. The outputs from the LocalRemote func-
tion block control the output PSTO (Permitted Source To Operate) on QCBAY.
Signal Description
LR_OFF External Local/Remote switch is in Off position
LR_LOC External Local/Remote switch is in Local position
LR_REM External Local/Remote switch is in Remote position
LR_VALID Data representing the L/R switch position is valid
BL_UPD Steady signal to block the position updates
BL_CMD Steady signal to block the command
Signal Description
PSTO The value for the operator place allocation
UPD_BLKD The update of position is blocked
CMD_BLKD The function is blocked for commands
Parameter Range Step Default Unit Description
AllPSTOValid Priority
No priority
- Priority - The priority of originators
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Figure 172: Configuration for the local/remote handling for a local LCD HMI with two bays
and two screen pages
If the IED contains control functions for several bays, the local/remote position can be different
for the included bays. When the local LCD HMI is used the position of the local/remote switch
can be different depending on which single line diagram screen page that is presented on the lo-
cal HMI. The function block LocRemControl controls the presentation of the LEDs for the lo-
cal/remote position to applicable bay and screen page.
The local-remote switching is under strict password control. This is activated by defining an ad-
ministrator and user with their passwords. Default password i abb. The selected position lo-
cal-remote or local and remote is indicated by LEDs.
QCBAY
CB02-
LR_OFF
LR_LOC
LR_REM
LR_VALID
BL_UPD
BL_CMD
PSTO
UPD_BLKD
CMD_BLKD
LocalRemote
LR02-
CTRLOFF
LOCCTRL
REMCTRL
LHMICTRL
OFF
LOCAL
REMOTE
VALID
LocRemControl
LRC1-
PSTO1
PSTO2
PSTO3
PSTO4
PSTO5
PSTO6
PSTO7
PSTO8
PSTO9
PSTO10
PSTO11
PSTO12
HMICTR1
HMICTR2
HMICTR3
HMICTR4
HMICTR5
HMICTR6
HMICTR7
HMICTR8
HMICTR9
HMICTR10
HMICTR11
HMICTR12
QCBAY
CB01-
LR_OFF
LR_LOC
LR_REM
LR_VALID
BL_UPD
BL_CMD
PSTO
UPD_BLKD
CMD_BLKD
LocalRemote
LR01-
CTRLOFF
LOCCTRL
REMCTRL
LHMICTRL
OFF
LOCAL
REMOTE
VALID
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2.4.3 Function block
Figure 173: LR function block
Figure 174: LRC function block
2.4.4 Input and output signals
Table 173: Input signals for the LocalRemote (LR01-) function block
Table 174: Output signals for the LocalRemote (LR01-) function block
Local Remote
LR01-
CTRLOFF
LOCCTRL
REMCTRL
LHMICTRL
OFF
LOCAL
REMOTE
VALID
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LocRemContr ol
LRC1-
PSTO1
PSTO2
PSTO3
PSTO4
PSTO5
PSTO6
PSTO7
PSTO8
PSTO9
PSTO10
PSTO11
PSTO12
HMICTR1
HMICTR2
HMICTR3
HMICTR4
HMICTR5
HMICTR6
HMICTR7
HMICTR8
HMICTR9
HMICTR10
HMICTR11
HMICTR12
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Signal Description
CTRLOFF Disable control
LOCCTRL Local in control
REMCTRL Remote in control
LHMICTRL LHMI control
Signal Description
OFF Control is disabled
LOCAL Local control is activated
REMOTE Remote control is activated
VALID Outputs are valid
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Table 175: Input signals for the LocRemControl (LRC1-) function block
Table 176: Output signals for the LocRemControl (LRC1-) function block
2.4.5 Setting parameters
Table 177: General settings for the LocalRemote (LR01-) function
Signal Description
PSTO1 PSTO input channel 1
PSTO2 PSTO input channel 2
PSTO3 PSTO input channel 3
PSTO4 PSTO input channel 4
PSTO5 PSTO input channel 5
PSTO6 PSTO input channel 6
PSTO7 PSTO input channel 7
PSTO8 PSTO input channel 8
PSTO9 PSTO input channel 9
PSTO10 PSTO input channel 10
PSTO11 PSTO input channel 11
PSTO12 PSTO input channel 12
Signal Description
HMICTR1 Bitmask output 1 to local remote LHMI input
HMICTR2 Bitmask output 2 to local remote LHMI input
HMICTR3 Bitmask output 3 to local remote LHMI input
HMICTR4 Bitmask output 4 to local remote LHMI input
HMICTR5 Bitmask output 5 to local remote LHMI input
HMICTR6 Bitmask output 6 to local remote LHMI input
HMICTR7 Bitmask output 7 to local remote LHMI input
HMICTR8 Bitmask output 8 to local remote LHMI input
HMICTR9 Bitmask output 9 to local remote LHMI input
HMICTR10 Bitmask output 10 to local remote LHMI input
HMICTR11 Bitmask output 11 to local remote LHMI input
HMICTR12 Bitmask output 12 to local remote LHMI input
Parameter Range Step Default Unit Description
ControlMode Internal LR-switch
External LR-switch
- Internal LR-switch - Control mode for inter-
nal/external LR-switch
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2.5 Switch controller (SCSWI)
2.5.1 Introduction
The Switch controller (SCSWI) initializes and supervises all functions to properly select and op-
erate switching primary apparatuses. The Switch controller may handle and operate on one
three-phase device or three one-phase switching devices.
2.5.2 Principle of operation
The function is provided with verification checks for the select - execute sequence, i.e. checks
the conditions prior each step of the operation. The involved functions for these condition veri-
fications are interlocking, reservation, blockings and synchrocheck.
Command handling
Two types of command models can be used. The two command models are "direct with en-
hanced security" and "SBO (Select-Before-Operate) with enhanced security". Which one of
these two command models that are used is defined by the parameter CtlModel. The meaning
with "direct with enhanced security" model is that no select is required. The meaning with "SBO
with enhanced security" model is that a select is required before execute.
In this function only commands with enhanced security is supported regarding changing of the
position. With enhanced security means that the command sequence is supervised in three steps,
the selection, command evaluation and the supervision of position. Each step ends up with a
pulsed signal to indicate that the respective step in the command sequence is finished. If an error
occurs in one of the steps in the command sequence, the sequence is terminated and the error is
mapped into the enumerated variable "cause" attribute belonging to the pulsed response signal
for the IEC61850 communication. The last cause L_CAUSE can be read from the function block
and used for example at commissioning. The meaning of the cause signals can be found in table
2.
Before an executing command, an evaluation of the position is done. If the parameter PosDe-
pendent is true and the position is in intermediate state or in bad state no executing command is
send. If the parameter is false the execution command is send independent of the position value.
Evaluation of position
In the case when there are three one-phase switches connected to the switch control function, the
switch control will "merge" the position of the three switches to the resulting three-phase posi-
tion. In the case when the position differ between the one-phase switches, following principles
will be applied:
Note!
There is not any relation between the command direction and the actual position. For example,
if the switch is in close position it is possible to execute a close command.
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Apparatus control (APC) Chapter 11
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The time stamp of the output three-phase position from switch control will have the time stamp
of the last changed phase when it goes to end position. When it goes to intermediate position or
bad state, it will get the time stamp of the first changed phase.
In addition, there is also the possibility that one of the one-phase switches will change position
at any time due to a trip. Such situation is here called pole discordance and is supervised by this
function. In case of a pole discordance situation, i.e. the position of the one-phase switches are
not equal for a time longer than the setting tPoleDiscord, an error signal POLEDISC will be set.
In the supervision phase, the switch controller function evaluates the "cause" values from the
switch modules XCBR/XSWI. At error the "cause" value with highest priority is shown.
Blocking principles
The blocking signals are normally coming from the bay control function (QCBAY) and via the
IEC61850 communication from the operator place.
The different blocking possibilities are:
Block/deblock of command. It is used to block command for operation of posi-
tion.
Blocking of function, BLOCK, signal from DO (Data Object) Behavior
(IEC61850). If DO Behavior is set to "blocked" it means that the function is ac-
tive, but no outputs are generated, no reporting, control commands are rejected
and functional and configuration data is visible.
Interaction with synchrocheck and synchronizing functions
The switch controller works in conjunction with the synchrocheck and the synchronizing func-
tion SECRSYN. It is assumed that the synchrocheck function is continuously in operation and
gives the result to the SCSWI. The result from the synchrocheck function is evaluated during the
close execution. If the operator performs an override of the synchrocheck, the evaluation of the
synchrocheck state is omitted. When there is a positive confirmation from the synchrocheck
function, the switch controller SCSWI will send the close signal EXE_CL to the switch function
SXCBR.
All switches in open position: switch control position =open
All switches in close position: switch control position =close
One switch =open, two switches=close
(or inversely):
switch control position =intermediate
Any switch in intermediate position: switch control position =intermediate
Any switch in bad state: switch control position =bad state
Note!
The different block conditions will only affect the operation of this function, i.e. no blocking sig-
nals will be "forwarded" to other functions. The above blocking outputs are stored in a non-vol-
atile memory.
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When there is no positive confirmation from the synchrocheck function, the SCSWI will send a
start signal START_SY to the synchronizing function, which will send the closing command to
the SXCBR when the synchronizing conditions are fulfilled, see figure175. If no synchronizing
function is included, the timer for supervision of the "synchronizing in progress signal" is set to
0, which means no start of the synchronizing function. The SCSWI will then set the attribute
"blocked-by-synchrocheck" in the "cause" signal. See also the time diagram in figure179.
Figure 175: Example of interaction between SCSWI, SECRSYN (synchrocheck and synchroniz-
ing function) and SXCBR function
Time diagrams
The SCSWI function has timers for evaluating different time supervision conditions. These tim-
ers are explained here.
The timer tSelect is used for supervising the time between the select and the execute command
signal, i.e. the time the operator has to perform the command execution after the selection of the
object to operate.
en05000091.vsd
Synchro
Check
OR
SCSWI
SXCBR
CLOSE
SYNC_OK
EXE_CL
Synchronizing
function
.
SY_INPRO
START_SY
CLOSE CB
SECRSYN
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Figure 176: tSelect
The parameter tResResponse is used to set the maximum allowed time to make the reservation,
i.e. the time between reservation request and the feedback reservation granted from all bays in-
volved in the reservation function.
Figure 177: tResResponse
The timer tExecutionFB supervises the time between the execute command and the command
termination, see figure178.
select
tSelect
timer
execute command
t1
t1>tSelect, then long-
operation-time in 'cause'
is set
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select
tResResponse
timer
reservation granted RES_GRT
t1>tResResponse, then
1-of-n-control in 'cause'
is set
t1
reservation request RES_RQ
command termination
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Figure 178: tExecutionFB
The parameter tSynchrocheck is used to define the maximum allowed time between the execute
command and the input SYNC_OK to become true. If SYNC_OK=true at the time the execute
command signal is received, the timer "tSynchrocheck" will not start. The start signal for the
synchronizing is obtained if the synchrocheck conditions are not fulfilled.
execute command
position L1
t1>tExecutionFB, then
long-operation-time in
'cause' is set
open
close
close
open position L3
close
open position L2
t1
tExecutionFB
timer
cmd termination L1
cmd termination L2
cmd termination L3
cmd termination
position open
close
* The cmd termination will be delayed one execution sample.
*
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Figure 179: tSynchroCheck and tSynchronizing
Error handling
Depending on what error that occurs during the command sequence the error signal will be set
with a value. Table178 describes possible values of the "cause" in priority order. The values are
available over the IEC 61850. An output L_CAUSE on the function block indicates the latest
value of the error during the command.
Table 178: Values for " cause" signal in priority order
execute command
SY_INPRO
SYNC_OK
t2>tSynchronizing, then
blocked-by-synchrocheck in
'cause' is set
tSynchrocheck
t1
START_SY
tSynchronizing
t2
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Cause (value) Description
0 no-error
8 blocked-by-mode
22 wrong-CTL-model
4 Invalid-position
10 blocked-by-interlocking
23 blocked-for-command
11 blocked-by-synchrocheck
14 1-of-n-control
30 long-operation-time
35 not-expected-final-position
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2.5.3 Function block
Figure 180: CS function block
2.5.4 Input and output signals
Table 179: Input signals for the SCSWI (CS01-) function block
SCSWI
CS01-
BLOCK
PSTO
L_SEL
L_OPEN
L_CLOSE
AU_OPEN
AU_CLOSE
BL_CMD
RES_GRT
RES_EXT
SY_INPRO
SYNC_OK
EN_OPEN
EN_CLOSE
XPOS1
XPOS2
XPOS3
EXE_OP
EXE_CL
SELECTED
RES_RQ
START_SY
POSITION
OPENPOS
CLOSEPOS
POLEDISC
CMD_BLK
L_CAUSE
XOUT
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Signal Description
BLOCK Block of function
PSTO Operator place selection
L_SEL Select signal from local panel
L_OPEN Open signal from local panel
L_CLOSE Close signal from local panel
AU_OPEN Used for local automation function
AU_CLOSE Used for local automation function
BL_CMD Steady signal for block of the command
RES_GRT Positive acknowledge that all reservations are made
RES_EXT Reservation is made externally
SY_INPRO Synchronizing function in progress
SYNC_OK Closing is permitted at set to true by the synchrocheck
EN_OPEN Enables open operation
EN_CLOSE Enables close operation
XPOS1 Group signal for XCBR input
XPOS2 Group signal for XCBR input
XPOS3 Group signal for XCBR input
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Table 180: Output signals for the SCSWI (CS01-) function block
2.5.5 Setting parameters
Table 181: General settings for the SCSWI (CS01-) function
Signal Description
EXE_OP Execute command for open direction
EXE_CL Execute command for close direction
SELECTED The select conditions are fulfilled
RES_RQ Request signal to the reservation function
START_SY Starts the synchronizing function
POSITION Position indication
OPENPOS Open position indication
CLOSEPOS Closed position indication
POLEDISC The positions for poles L1-L3 are not equal after a set time
CMD_BLK Commands are blocked
L_CAUSE Latest value of the error indication during command
XOUT Execution information to XCBR/XSWI
Parameter Range Step Default Unit Description
CtlModel Dir Norm
SBO Enh (ABB)
Dir Norm (ABB)
SBO Enh
- SBO Enh - Specifies the type for
control model according
to IEC 61850
PosDependent Always permitted
Not perm at 00/11
- Always permitted - Permission to operate
depending on the posi-
tion
tSelect 0.000 - 60.000 0.001 30.000 s Max time between select
and execute signals
tResResponse 0.000 - 60.000 0.001 5.000 s Allowed time from reser-
vation request to reserva-
tion granted
tSynchrocheck 0.00 - 6000.00 0.01 10.00 s Allowed time for synchro-
check to fulfil close condi-
tions
tSynchronizing 0.000 - 60.000 0.001 0.000 s Supervision time to get
the signal synchronizing
in progress
tExecutionFB 0.000 - 60.000 0.001 30.000 s Max time from command
execution to termination
tPoleDiscord 0.000 - 60.000 0.001 2.000 s Allowed time to have dis-
crepancy between the
poles
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2.6 Circuit breaker (SXCBR)
2.6.1 Introduction
The purpose of this function is to provide the actual status of positions and to perform the control
operations, i.e. pass all the commands to primary apparatuses in the form of circuit breakers via
output boards and to supervise the switching operation and position.
2.6.2 Principle of operation
The intended user of this function is other functions such as e.g. Switch controller, protection
functions, autorecloser function or an IEC 61850 client residing in another IED or the operator
place. This switch function executes commands, evaluate block conditions and evaluate differ-
ent time supervision conditions. Only if all conditions indicate a switch operation to be allowed,
the function performs the execution command. In case of erroneous conditions, the function in-
dicates an appropriate "cause" value.
The function has an operation counter for closing and opening commands. The counter value
can be read remotely from the operator place. The value is reset from a binary input or remotely
from the operator place.
Local/Remote switch
One binary input signal LR_SWI is included in this function to indicate the local/remote switch
position from switchyard provided via the I/O board. If this signal is set to TRUE it means that
change of position is allowed only from switchyard level. If the signal is set to FALSE it means
that command from IED or higher level is permitted. When the signal is set to TRUE all com-
mands (for change of position) from internal IED clients are rejected, even trip commands from
protection functions are rejected. The functionality of the local/remote switch is described in
figure181.
Figure 181: Local/Remote switch
Blocking principles
The function includes several blocking principles. The basic principle for all blocking signals is
that they will affect commands from all other clients e.g. operators place, protection functions,
autoreclosure etc.
The blocking possibilities are:
Block/deblock for open command. It is used to block operation for open com-
mand. Note that this block signal also affects the input OPEN for immediate com-
mand.
From I/O switchLR
T
R
U
E
F
A
L
S
E
Local=Operation at
switch yard level
Remote=Operation at
IED or higher level
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Block/deblock for close command. It is used to block operation for close com-
mand. Note that this block signal also affects the input CLOSE for immediate
command.
Update block/deblock of positions. It is used to block the updating of position
values. Other signals related to the position will be reset.
Blocking of function, BLOCK, signal from DO (Data Object) Behavior
(IEC61850). If DO Behavior is set to "blocked" it means that the function is ac-
tive, but no outputs are generated, no reporting, control commands are rejected
and functional and configuration data is visible.
The above blocking outputs are stored in a non-volatile memory.
Substitution
The substitution part in this function is used for manual set of the position for the switch. The
typical use of substitution is that an operator enters a manual value because that the real process
value is erroneous of some reason. The function will then use the manually entered value instead
of the value for positions determined by the process.
Time diagrams
There are two timers for supervising of the execute phase, tStartMove and tIntermediate. tStart-
Move supervises that the primary device starts moving after the execute output pulse is sent. tIn-
termediate defines the maximum allowed time for intermediate position. Figure182 explains
these two timers during the execute phase.
Note!
It is always possible to make a substitution, independently of the position indication and the sta-
tus information of the I/O board. When substitution is enabled, the position values are blocked
for updating and other signals related to the position are reset. The substituted values are stored
in a non-volatile memory.
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Figure 182: The timers tStartMove and tIntermediate
The timers tOpenPulse and tClosePulse are the length of the execute output pulses to be sent to
the primary equipment. Note that the output pulses for open and close command can have dif-
ferent pulse lengths. The pulses can also be set to be adaptive with the configuration parameter
AdaptivePulse. Figure183 shows the principle of the execute output pulse. The adaptively pa-
rameter will have affect on both execute output pulses.
Figure 183: Execute output pulse
EXE_CL
tStartMove timer
OPENPOS
CLOSEPOS
tIntermediate timer
t1
t2
tStartMove
tIntermediate
if t1 >tStartMove then
"switch-not-start-moving"
attribute in 'cause' is set
if t2 >tIntermediate then
"persisting-intermediate-state"
attribute in 'cause' is set
Close pulse duration
AdaptivePulse =TRUE
en05000097.vsd
EXE_CL
CLOSEPOS
EXE_CL
OPENPOS
AdaptivePulse=FALSE
tClosePulse
tClosePulse
AdaptivePulse=TRUE
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If the pulse is set to be adaptive, it is not possible for the pulse to exceed tOpenPulse or
tClosePulse.
The execute output pulses are reset when:
the new expected final position is reached and the configuration parameter Adap-
tivePulse is set to true
the timer tOpenPulse or tClosePulse has elapsed
an error occurs due to the switch does not start moving, i.e. tStartMove has
elapsed.
There is one exception from the first item above. If the primary device is in open position and
an open command is executed or if the primary device is in close position and a close command
is executed. In these cases, with the additional condition that the configuration parameter Adap-
tivePulse is true, the execute output pulse is always activated and resets when tStartMove has
elapsed. If the configuration parameter AdaptivePulse is set to false the execution output re-
mains active until the pulse duration timer has elapsed.
An example of when a primary device is open and an open command is executed is shown in
figure184 .
Figure 184: Open command with open position indication
Note!
If the start position indicates bad state (OPENPOS=1 and CLOSEPOS =1) when a command is
executed the execute output pulse resets only when timer "tOpenPulse" or "tClosePulse" has
elapsed.
EXE_OP
CLOSEPOS
EXE_OP
OPENPOS
AdaptivePulse=FALSE
tOpenPulse
tOpenPulse
AdaptivePulse=TRUE
tStartMove timer
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Error handling
Depending on what error that occurs during the command sequence the error signal will be set
with a value. Table182 describes possible values of the "cause" in priority order. The values are
available over the IEC 61850. An output L_CAUSE on the function block indicates the latest
value of the error during the command.
Table 182: Values for " cause" signal in priority order
2.6.3 Function block
Figure 185: XC function block
Cause (value) Description
0 no-error
8 blocked-by-mode
2 blocked-by-switching-hierarchy
24 blocked-for-open-command
25 blocked-for-close-command
9 blocked-by-process
12 command-already-in-execution
31 switch-not-start-moving
32 persistent-intermediate-state
33 switch-returned-to-initial-position
34 switch-in-bad-state
35 not-expected-final-position
SXCBR
XC01-
BLOCK
LR_SWI
OPEN
CLOSE
BL_OPEN
BL_CLOSE
BL_UPD
POSOPEN
POSCLOSE
TR_OPEN
TR_CLOSE
RS_CNT
XIN
XPOS
EXE_OP
EXE_CL
SUBSTED
OP_BLKD
CL_BLKD
UPD_BLKD
OPENPOS
CLOSEPOS
TR_POS
CNT_VAL
L_CAUSE
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2.6.4 Input and output signals
Table 183: Input signals for the SXCBR (XC01-) function block
Table 184: Output signals for the SXCBR (XC01-) function block
Signal Description
BLOCK Block of function
LR_SWI Local/Remote switch indication from switchyard
OPEN Pulsed signal used to immediately open the switch
CLOSE Pulsed signal used to immediately close the switch
BL_OPEN Signal to block the open command
BL_CLOSE Signal to block the close command
BL_UPD Steady signal for block of the position updating
POSOPEN Signal for open position of apparatus from I/O
POSCLOSE Signal for close position of apparatus from I/O
TR_OPEN Signal for open position of truck from I/O
TR_CLOSE Signal for close position of truck from I/O
RS_CNT Resets the operation counter
XIN Execution information from CSWI
Signal Description
XPOS Group signal for XCBR output
EXE_OP Executes the command for open direction
EXE_CL Executes the command for close direction
SUBSTED Indication that the position is substituted
OP_BLKD Indication that the function is blocked for open commands
CL_BLKD Indication that the function is blocked for close commands
UPD_BLKD The update of position indication is blocked
OPENPOS Apparatus open position
CLOSEPOS Apparatus closed position
TR_POS Truck position indication
CNT_VAL The value of the operation counter
L_CAUSE Latest value of the error indication during command
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2.6.5 Setting parameters
Table 185: General settings for the SXCBR (XC01-) function
2.7 Circuit switch (SXSWI)
2.7.1 Introduction
The purpose of this function is to provide the actual status of positions and to perform the control
operations, i.e. pass all the commands to primary apparatuses in the form of disconnectors or
earthing switches via output boards and to supervise the switching operation and position.
2.7.2 Principle of operation
The intended user of this function is other functions such as e.g. Switch controller, protection
functions, autorecloser function or a 61850 client residing in another IED or the operator place.
This switch function executes commands, evaluate block conditions and evaluate different time
supervision conditions. Only if all conditions indicate a switch operation to be allowed, the func-
tion performs the execution command. In case of erroneous conditions, the function indicates an
appropriate "cause" value.
The function has an operation counter for closing and opening commands. The counter value
can be read remotely from the operator place. The value is reset from a binary input or remotely
from the operator place.
Local/Remote switch
One binary input signal LR_SWI is included in this function to indicate the local/remote switch
position from switchyard provided via the I/O board. If this signal is set to TRUE it means that
change of position is allowed only from switchyard level. If the signal is set to FALSE it means
that command from IED or higher level is permitted. When the signal is set to TRUE all com-
mands (for change of position) from internal IED clients are rejected, even trip commands from
protection functions are rejected. The functionality of the local/remote switch is described in
figure186.
Parameter Range Step Default Unit Description
tStartMove 0.000 - 60.000 0.001 0.100 s Supervision time for the
apparatus to move after a
command
tIntermediate 0.000 - 60.000 0.001 0.150 s Allowed time for interme-
diate position
AdaptivePulse Not adaptive
Adaptive
- Not adaptive - The output resets when a
new correct end position
is reached
tOpenPulse 0.000 - 60.000 0.001 0.200 s Output pulse length for
open command
tClosePulse 0.000 - 60.000 0.001 0.200 s Output pulse length for
close command
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Figure 186: Local/Remote switch
Blocking principles
The function includes several blocking principles. The basic principle for all blocking signals is
that they will affect commands from all other clients e.g. operators place, protection functions,
autoreclosure etc.
The blocking possibilities are:
Block/deblock for open command. It is used to block operation for open com-
mand. Note that this block signal also affects the input OPEN for immediate com-
mand.
Block/deblock for close command. It is used to block operation for close com-
mand. Note that this block signal also affects the input CLOSE for immediate
command.
Update block/deblock of positions. It is used to block the updating of position
values. Other signals related to the position will be reset.
Blocking of function, BLOCK, signal from DO (Data Object) Behavior
(IEC61850). If DO Behavior is set to "blocked" it means that the function is ac-
tive, but no outputs are generated, no reporting, control commands are rejected
and functional and configuration data is visible.
The above blocking outputs are stored in a non-volatile memory.
Substitution
The substitution part in this function is used for manual set of the position for the switch. The
typical use of substitution is that an operator enters a manual value because that the real process
value is erroneous of some reason. The function will then use the manually entered value instead
of the value for positions determined by the process.
From I/O switchLR
T
R
U
E
F
A
L
S
E
Local=Operation at
switch yard level
Remote=Operation at
IED or higher level
en05000096.vsd
Note!
It is always possible to make a substitution, independently of the position indication and the sta-
tus information of the I/O board. When substitution is enabled, the position values are blocked
for updating and other signals related to the position are reset. The substituted values are stored
in a non-volatile memory.
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Control
Time diagrams
There are two timers for supervising of the execute phase, tStartMove and tIntermediate. tStart-
Move supervises that the primary device starts moving after the execute output pulse is sent. tIn-
termediate defines the maximum allowed time for intermediate position. Figure187 explains
these two timers during the execute phase.
Figure 187: The timers tStartMove and tIntermediate
The timers tOpenPulse and tClosePulse are the length of the execute output pulses to be sent to
the primary equipment. Note that the output pulses for open and close command can have dif-
ferent pulse lengths. The pulses can also be set to be adaptive with the configuration parameter
AdaptivePulse. Figure188 shows the principle of the execute output pulse. The adaptively pa-
rameter will have affect on both execute output pulses.
EXE_CL
tStartMove timer
OPENPOS
CLOSEPOS
tIntermediate timer
t1
t2
tStartMove
tIntermediate
if t1 >tStartMove then
"switch-not-start-moving"
attribute in 'cause' is set
if t2 >tIntermediate then
"persisting-intermediate-state"
attribute in 'cause' is set
Close pulse duration
AdaptivePulse =TRUE
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Figure 188: Execute output pulse
If the pulse is set to be adaptive, it is not possible for the pulse to exceed tOpenPulse or
tClosePulse.
The execute output pulses are reset when:
the new expected final position is reached and the configuration parameter Adap-
tivePulse is set to true
the timer tOpenPulse or tClosePulse has elapsed
an error occurs due to the switch does not start moving, i.e. tStartMove has
elapsed.
There is one exception from the first item above. If the primary device is in open position and
an open command is executed or if the primary device is in close position and a close command
is executed. In these cases, with the additional condition that the configuration parameter Adap-
tivePulse is true, the execute output pulse is always activated and resets when tStartMove has
elapsed. If the configuration parameter AdaptivePulse is set to false the execution output re-
mains active until the pulse duration timer has elapsed.
An example when a primary device is open and an open command is executed is shown in
figure189.
EXE_CL
CLOSEPOS
EXE_CL
OPENPOS
AdaptivePulse=FALSE
tClosePulse
tClosePulse
AdaptivePulse=TRUE
en05000098.vsd
Note!
If the start position indicates bad state (OPENPOS=1 and CLOSEPOS =1) when a command is
executed the execute output pulse resets only when timer "tOpenPulse" or "tClosePulse" has
elapsed.
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Figure 189: Open command with open position indication
Error handling
Depending on what error that occurs during the command sequence the error signal will be set
with a value. Table186 describes possible values of the "cause" in priority order. The values are
available over the IEC 61850. An output L_CAUSE on the function block indicates the latest
value of the error during the command.
Table 186: Values for " cause" signal in priority order
Cause (value) Description
0 no-error
8 blocked-by-mode
2 blocked-by-switching-hierarchy
24 blocked-for-open-command
25 blocked-for-close-command
9 blocked-by-process
12 command-already-in-execution
31 switch-not-start-moving
32 persistent-intermediate-state
33 switch-returned-to-initial-position
34 switch-in-bad-state
35 not-expected-final-position
EXE_OP
CLOSEPOS
EXE_OP
OPENPOS
AdaptivePulse=FALSE
tOpenPulse
tOpenPulse
AdaptivePulse=TRUE
tStartMove timer
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2.7.3 Function block
Figure 190: XS function block
2.7.4 Input and output signals
Table 187: Input signals for the SXSWI (XS01-) function block
Table 188: Output signals for the SXSWI (XS01-) function block
SXSWI
XS01-
BLOCK
LR_SWI
OPEN
CLOSE
BL_OPEN
BL_CLOSE
BL_UPD
POSOPEN
POSCLOSE
RS_CNT
XIN
XPOS
EXE_OP
EXE_CL
SUBSTED
OP_BLKD
CL_BLKD
UPD_BLKD
OPENPOS
CLOSEPOS
CNT_VAL
L_CAUSE
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Signal Description
BLOCK Block of function
LR_SWI Local/Remote switch indication from switchyard
OPEN Pulsed signal used to immediately open the switch
CLOSE Pulsed signal used to immediately close the switch
BL_OPEN Signal to block the open command
BL_CLOSE Signal to block the close command
BL_UPD Steady signal for block of the position updating
POSOPEN Signal for open position of apparatus from I/O
POSCLOSE Signal for close position of apparatus from I/O
RS_CNT Resets the operation counter
XIN Execution information from CSWI
Signal Description
XPOS Group signal for XSWI output
EXE_OP Executes the command for open direction
EXE_CL Executes the command for close direction
SUBSTED Indication that the position is substituted
OP_BLKD Indication that the function is blocked for open commands
CL_BLKD Indication that the function is blocked for close commands
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2.7.5 Setting parameters
Table 189: General settings for the SXSWI (XS01-) function
2.8 Bay reserve (QCRSV)
2.8.1 Introduction
The purpose of the reservation function is primarily to transfer interlocking information between
IEDs in a safe way and to prevent double operation in a bay, switchyard part, or complete sub-
station.
2.8.2 Principle of operation
The function block QCRSV handles the reservation. The function starts to operate in two ways.
It starts when there is a request for reservation of the own bay or if there is a request for reser-
vation from another bay. It is only possible to reserve the function if it is not currently reserved.
The signal that can reserve the own bay is the input signal RES_RQx (x=1-8) coming from
switch controller SCWI. The signals for request from another bay are the outputs RE_RQ_B and
V_RE_RQ from function block RESIN. These signals are included in signal EXCH_OUT from
RESIN and are connected to RES_DATA in QCRSV.
UPD_BLKD The update of position indication is blocked
OPENPOS Apparatus open position
CLOSEPOS Apparatus closed position
CNT_VAL The value of the operation counter
L_CAUSE Latest value of the error indication during command
Signal Description
Parameter Range Step Default Unit Description
tStartMove 0.000 - 60.000 0.001 3.000 s Supervision time for the
apparatus to move after a
command
tIntermediate 0.000 - 60.000 0.001 15.000 s Allowed time for interme-
diate position
AdaptivePulse Not adaptive
Adaptive
- Not adaptive - The output resets when a
new correct end position
is reached
tOpenPulse 0.000 - 60.000 0.001 0.200 s Output pulse length for
open command
tClosePulse 0.000 - 60.000 0.001 0.200 s Output pulse length for
close command
SwitchType Load Break
Disconnector
Earthing Switch
HS Earthing
Switch
- Disconnector - Switch Type
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The parameters ParamRequestx (x=1-8) are chosen at reservation of the own bay only (TRUE)
or other bays (FALSE). To reserve the own bay only means that no reservation request
RES_BAYS is created.
Reservation request of own bay
If the reservation request comes from the own bay, the function QCRSV has to know which ap-
paratus the request comes from. This information is available with the input signal RES_RQx
and parameter ParamRequestx (where x=1-8 is the number of the requesting apparatus). In order
to decide if a reservation request of the current bay can be permitted QCRSV has to know wheth-
er the own bay already is reserved by itself or another bay. This information is available in the
output signal RESERVED.
If the RESERVED output is not set, the selection is made with the output RES_GRTx (where
x=1-8 is the number of the requesting apparatus), which is connected to switch controller SC-
SWI. If the bay already is reserved the command sequence will be reset and the SCSWI will set
the attribute '1-of-n-control' in the 'cause' signal.
Reservation of other bays
When the function QCRSV receives a request from an apparatus in the own bay that requires
other bays to be reserved as well, it checks if it already is reserved. If not, it will send a request
to the other bays that are predefined (to be reserved) and wait for their response (acknowledge).
The request of reserving other bays is done by activating the output RES_BAYS.
When it receives acknowledge from the bays via the input RES_DATA, it sets the output
RES_GRTx (where x=1-8 is the number of the requesting apparatus). If not acknowledgement
from all bays is received within a certain time defined in SCSWI (tResResponse), the SCSWI
will reset the reservation and set the attribute '1-of-n-control' in the 'cause' signal.
Reservation request from another bay
When another bay requests for reservation, the input BAY_RES in corresponding function block
RESIN is activated. The signal for reservation request is grouped into the output signal
EXCH_OUT in RESIN, which is connected to input RES_DATA in QCRSV. If the bay is not
reserved, the bay will be reserved and the acknowledgment from output ACK_T_B is sent back
to the requested bay. If the bay already is reserved the reservation is kept and no acknowledg-
ment is sent.
Blocking and overriding of reservation
If the function QCRSV is blocked (input BLK_RES is set to true) the reservation is blocked.
That is, no reservation can be made from the own bay or any other bay. This can be set, for ex-
ample, via a binary input from an external device to prevent operations from another operator
place at the same time.
The reservation function can also be overridden in the own bay with the OVERRIDE input sig-
nal, i.e. reserving the own bay without waiting for the external acknowledge.
Bay with more than eight apparatuses
If only one instance of QCRSV is used for a bay i.e. use of up to eight apparatuses, the input
EXCH_IN must be set to FALSE.
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If there are more than eight apparatuses in the bay there has to be one additional QCRSV. The
both functions QCRSV have to communicate and this is done through the input EXCH_IN and
EXCH_OUT according to figure 10. If more then one QCRSV are used, the execution order is
very important. The execution order must be in the way that the first QCRSV has a lower number
than the next one.
Figure 191: Connection of two QCRSV function blocks
QCRSV
CR01-
EXCH_IN
RES_RQ1
RES_RQ2
RES_RQ3
RES_RQ4
RES_RQ5
RES_RQ6
RES_RQ7
RES_RQ8
BLK_RES
OVERRIDE
RES_DATA
RES_GRT1
RES_GRT2
RES_GRT3
RES_GRT4
RES_GRT5
RES_GRT6
RES_GRT7
RES_GRT8
RES_BAYS
ACK_TO_B
RESERVED
EXCH_OUT
QCRSV
CR02-
EXCH_IN
RES_RQ1
RES_RQ2
RES_RQ3
RES_RQ4
RES_RQ5
RES_RQ6
RES_RQ7
RES_RQ8
BLK_RES
OVERRIDE
RES_DATA
RES_GRT1
RES_GRT2
RES_GRT3
RES_GRT4
RES_GRT5
RES_GRT6
RES_GRT7
RES_GRT8
RES_BAYS
ACK_TO_B
RESERVED
EXCH_OUT
1
1
1
RESERVED
ACK_TO_B
RES_BAYS
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2.8.3 Function block
Figure 192: CR function block
2.8.4 Input and output signals
Table 190: Input signals for the QCRSV (CR01-) function block
Table 191: Output signals for the QCRSV (CR01-) function block
QCRSV
CR01-
EXCH_IN
RES_RQ1
RES_RQ2
RES_RQ3
RES_RQ4
RES_RQ5
RES_RQ6
RES_RQ7
RES_RQ8
BLK_RES
OVERRIDE
RES_DATA
RES_GRT1
RES_GRT2
RES_GRT3
RES_GRT4
RES_GRT5
RES_GRT6
RES_GRT7
RES_GRT8
RES_BAYS
ACK_TO_B
RESERVED
EXCH_OUT
en05000340.vsd
Signal Description
EXCH_IN Used for exchange signals between different BayRes blocks
RES_RQ1 Signal for app. 1 that requests to do a reservation
RES_RQ2 Signal for app. 2 that requests to do a reservation
RES_RQ3 Signal for app. 3 that requests to do a reservation
RES_RQ4 Signal for app. 4 that requests to do a reservation
RES_RQ5 Signal for app. 5 that requests to do a reservation
RES_RQ6 Signal for app. 6 that requests to do a reservation
RES_RQ7 Signal for app. 7 that requests to do a reservation
RES_RQ8 Signal for app. 8 that requests to do a reservation
BLK_RES Reservation is not possible and the output signals are reset
OVERRIDE Signal to override the reservation
RES_DATA Reservation data coming from function block ResIn
Signal Description
RES_GRT1 Reservation is made and the app. 1 is allowed to operate
RES_GRT2 Reservation is made and the app. 2 is allowed to operate
RES_GRT3 Reservation is made and the app. 3 is allowed to operate
RES_GRT4 Reservation is made and the app. 4 is allowed to operate
RES_GRT5 Reservation is made and the app. 5 is allowed to operate
RES_GRT6 Reservation is made and the app. 6 is allowed to operate
RES_GRT7 Reservation is made and the app. 7 is allowed to operate
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2.8.5 Setting parameters
Table 192: General settings for the QCRSV (CR01-) function
2.9 Reservation input (RESIN)
2.9.1 Introduction
The function block RESIN receives the reservation information from other bays. The number of
instances is the same as the number of involved bays (up to 60 instances are available).
RES_GRT8 Reservation is made and the app. 8 is allowed to operate
RES_BAYS Request for reservation of other bays
ACK_TO_B Acknowledge to other bays that this bay is reserved
RESERVED Indicates that the bay is reserved
EXCH_OUT Used for exchange signals between different BayRes blocks
Signal Description
Parameter Range Step Default Unit Description
tCancelRes 0.000 - 60.000 0.001 10.000 s Supervision time for can-
celing the reservation
ParamRequest1 Other bays res.
Only own bay res.
- Only own bay res. - Reservation of the own
bay only, at selection of
apparatus 1
ParamRequest2 Other bays res.
Only own bay res.
- Only own bay res. - Reservation of the own
bay only, at selection of
apparatus 2
ParamRequest3 Other bays res.
Only own bay res.
- Only own bay res. - Reservation of the own
bay only, at selection of
apparatus 3
ParamRequest4 Other bays res.
Only own bay res.
- Only own bay res. - Reservation of the own
bay only, at selection of
apparatus 4
ParamRequest5 Other bays res.
Only own bay res.
- Only own bay res. - Reservation of the own
bay only, at selection of
apparatus 5
ParamRequest6 Other bays res.
Only own bay res.
- Only own bay res. - Reservation of the own
bay only, at selection of
apparatus 6
ParamRequest7 Other bays res.
Only own bay res.
- Only own bay res. - Reservation of the own
bay only, at selection of
apparatus 7
ParamRequest8 Other bays res.
Only own bay res.
- Only own bay res. - Reservation of the own
bay only, at selection of
apparatus 8
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Apparatus control (APC) Chapter 11
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2.9.2 Principle of operation
The reservation input function is based purely on Boolean logic conditions. The logic diagram
in figure193 shows how the output signals are created. The inputs of the function block are con-
nected to a receive function block representing signals transferred over the station bus from an-
other bay.
Figure 193: Logic diagram for RESIN
Figure194 describes the principle of the data exchange between all RESIN modules in the cur-
rent bay. There is one RESIN function block per "other bay" used in the reservation mechanism.
The output signal EXCH_OUT in the last RESIN functions block are connected to the module
QCRSV that handles the reservation function in the own bay. The value to the input EXCH_IN
on the first RESIN module in the chain has the integer value 5. This is provided by the use of
instance number one of the function block RESIN (RE01-), where the input EXCH_IN is set to
#5, but is hidden for the user.
en05000089.vsd
&
1
1
&
1
1
&
1
FutureUse
ACK_F_B
ANY_ACK
VALID_TX
RE_RQ_B
V _RE_RQ
BAY_VAL
BAY_RES
EXCH_IN
INT
BIN
BIN
INT
EXCH_OUT
BAY_ACK
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Apparatus control (APC) Chapter 11
Control
Figure 194: Diagram of the chaining principle for RESIN
2.9.3 Function block
Figure 195: RE function block
2.9.4 Input and output signals
Table 193: Input signals for the RESIN (RE01-) function block
Bay 1
Bay 2
Bay n
QCRSV
RES_DATA
RESIN
RE02-
EXCH_IN
BAY_ACK
BAY_VAL
BAY_RES
ACK_F_B
ANY_ACK
VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
RESIN
RE01-
BAY_ACK
BAY_VAL
BAY_RES
ACK_F_B
ANY_ACK
VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
RESIN
REnn-
EXCH_IN
BAY_ACK
BAY_VAL
BAY_RES
ACK_F_B
ANY_ACK
VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
CR01-
en05000090.vsd
RESIN
RE01-
BAY_ACK
BAY_VAL
BAY_RES
ACK_F_B
ANY_ACK
VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
en05000341.vsd
Signal Description
BAY_ACK Another bay has acknow. the reservation req. from this bay
BAY_VAL The reserv. and acknow. signals from another bay are valid
BAY_RES Request from other bay to reserve this bay
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Apparatus control (APC) Chapter 11
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Table 194: Output signals for the RESIN (RE01-) function block
2.9.5 Setting parameters
Table 195: General settings for the RESIN (RE01-) function
Signal Description
ACK_F_B All other bays have acknow. the reserv. req. from this bay
ANY_ACK Any other bay has acknow. the reserv. req. from this bay
VALID_TX The reserv. and acknow. signals from other bays are valid
RE_RQ_B Request from other bay to reserve this bay
V_RE_RQ Check if the request of reserving this bay is valid
EXCH_OUT Used for exchange signals between different ResIn blocks
Parameter Range Step Default Unit Description
FutureUse Bay in use
Bay future use
- Bay in use - The bay for this ResIn
block is for future use
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Interlocking Chapter 11
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3 Interlocking
3.1 Introduction
The interlocking function blocks the possibility to operate high-voltage switching devices, for
instance when a disconnector is under load, in order to prevent material damage and/or acciden-
tal human injury.
Each control IED has interlocking functions for different switchyard arrangements, each han-
dling the interlocking of one bay. The function is distributed to each control IED and not depen-
dent on any central function. For the station-wide interlocking, the IEDs communicate via the
station bus or by using hard wired binary inputs/outputs.
The interlocking conditions depend on the circuit configuration and status of the installation at
any given time.
3.2 Principle of operation
The interlocking function consists of software modules located in each control IED. The func-
tion is distributed and not dependent on any central function. Communication between modules
in different bays is performed via the station bus.
The reservation function (see section 2 "Apparatus control (APC)") is used to ensure that HV
apparatuses that might affect the interlock are blocked during the time gap, which arises between
position updates. This can be done by means of the communication system, reserving all HV ap-
paratuses that might influence the interlocking condition of the intended operation. The reserva-
tion is maintained until the operation is performed.
After the selection and reservation of an apparatus, the function has complete data on the status
of all apparatuses in the switchyard that are affected by the selection. Other operators cannot in-
terfere with the reserved apparatus or the status of switching devices that may affect it.
The open or closed positions of the HV apparatuses are inputs to software modules distributed
in the control IEDs. Each module contains the interlocking logic for a bay. The interlocking log-
ic in a module is different, depending on the bay function and the switchyard arrangements, that
is, double-breaker or 1 1/2 breaker bays have different modules. Specific interlocking conditions
and connections between standard interlocking modules are performed with an engineering tool.
Bay-level interlocking signals can include the following kind of information:
Positions of HV apparatuses (sometimes per phase)
Valid positions (if evaluated in the control module)
External release (to add special conditions for release)
Line voltage (to block operation of line earthing switch)
Output signals to release the HV apparatus
The interlocking module is connected to the surrounding functions within a bay as shown in fig-
ure 196.
411
Interlocking Chapter 11
Control
Figure 196: Interlocking module on bay level.
Bays communicate via the station bus and can convey information regarding the following:
Unearthed busbars
Busbars connected together
Other bays connected to a busbar
Received data from other bays is valid
Figure 197 illustrates the data exchange principle.
Interlocking
modules in
other bays
Interlocking
module
SCILO SCSWI
Apparatus control
modules
SXCBR
SCILO SCSWI SXSWI
Apparatus control
modules
SCILO SCSWI SXSWI
Apparatus control
modules
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Figure 197: Data exchange between interlocking modules.
When invalid data such as intermediate position, loss of a control terminal, or input board error
are used as conditions for the interlocking condition in a bay, a release for execution of the func-
tion will not be given.
On the station HMI an override function exists, which can be used to bypass the interlocking
function in cases where not all the data required for the condition is valid.
For all interlocking modules these general rules apply:
The interlocking conditions for opening or closing of disconnectors and earthing
switches are always identical.
Earthing switches on the line feeder end, e.g. rapid earthing switches, are normal-
ly interlocked only with reference to the conditions in the bay where they are lo-
cated, not with reference to switches on the other side of the line. So a line voltage
indication may be included into line interlocking modules. If there is no line volt-
age supervision within the bay, then the appropriate inputs must be set to no volt-
age, and the operator must consider this when operating.
Earthing switches can only be operated on isolated sections e.g. without
load/voltage. Circuit breaker contacts cannot be used to isolate a section, i.e. the
status of the circuit breaker is irrelevant as far as the earthing switch operation is
concerned.
Disconnectors cannot break power current or connect different voltage systems.
Disconnectors in series with a circuit breaker can only be operated if the circuit
breaker is open, or if the disconnectors operate in parallel with other closed con-
Disc QB1 and QB2 closed
WA1 not earthed
WA2 not earthed
WA1 and WA2 interconn
Disc QB1 and QB2 closed
WA1 not earthed
WA2 not earthed
WA1 and WA2 interconn
. . .
. .
Station bus
QB1
WA1
WA2
Bay 1 Bay n Bus coupler
WA1 unearthed
WA1 unearthed
WA1 and WA2 interconn
WA1 and WA2 interconn
in other bay
QB2
QA1
QB9
QB1
QB2
QA1
QB9
QB2 QB1
QA1
QC1 QC2
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nections. Other disconnectors can be operated if one side is completely isolated,
or if the disconnectors operate in parallel to other closed connections, or if they
are earthed on both sides.
Circuit breaker closing is only interlocked against running disconnectors in its
bay or additionally in a transformer bay against the disconnectors and earthing
switch on the other side of the transformer, if there is no disconnector between
CB and transformer.
Circuit breaker opening is only interlocked in a bus-coupler bay, if a bus bar
transfer is in progress.
To make the implementation of the interlocking function easier, a number of standardized and
tested software interlocking modules containing logic for the interlocking conditions are avail-
able:
Line for double and transfer busbars, ABC_LINE
Bus for double and transfer busbars, ABC_BC
Transformer bay for double busbars, AB_TRAFO
Bus-section breaker for double busbars, A1A2_BS
Bus-section disconnector for double busbars, A1A2_DC
Busbar earthing switch, BB_ES
Double CB Bay, DB_BUS_A, DB_LINE, DB_BUS_B
1 1/2-CB diameter, BH_LINE_A, BH_CONN, BH_LINE_B
The interlocking conditions can be altered, to meet the customers specific requirements, by add-
ing configurable logic by means of the graphical configuration tool PCM 600. The inputs
Qx_EXy on the interlocking modules are used to add these specific conditions.
The input signals EXDU_xx shall be set to true if there is no transmission error at the transfer
of information from other bays. Required signals with designations ending in TR are intended
for transfer to other bays.
3.3 Logical node for interlocking (SCILO)
3.3.1 Introduction
The function SCILO is used to enable a switching operation if the interlocking conditions per-
mit. The function itself does not provide any interlocking functionality. The interlocking condi-
tions are generated in separate function blocks containing the interlocking logic.
3.3.2 Principle of operation
The function contains logic to enable the open and close commands respectively if the interlock-
ing conditions are fulfilled. That means also, if the switch has a defined end position e.g. open,
then the appropriate enable signal (in this case EN_OPEN) is false. The enable signals
EN_OPEN and EN_CLOSE can be true at the same time only in the intermediate and bad posi-
tion state and if they are enabled by the interlocking function. The position inputs come from the
logical nodes Circuit breaker/switch SXCBR/SXSWI and the enable signals come from the in-
terlocking logic. The outputs are connected to the logical node Switch controller SCSWI. One
instance per switching device is needed.
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Interlocking Chapter 11
Control
Figure 198: SCILO function logic diagram
3.3.3 Function block
Figure 199: CI function block
3.3.4 Input and output signals
Table 196: Input signals for the SCILO (CI01-) function block
Table 197: Output signals for the SCILO (CI01-) function block
OPEN_EN
POSOPEN
POSCLOSE
1
EN_OPEN
EN_CLOSE CLOSE_EN
SCILO
=1
&
>1
>1
&
&
&
en04000525.vsd
SCILO
CI01-
POSOPEN
POSCLOSE
OPEN_EN
CLOSE_EN
EN_OPEN
EN_CLOSE
en05000359.vsd
Signal Description
POSOPEN Open position of switch device
POSCLOSE Closed position of switch device
OPEN_EN Open operation from interlocking logic is enabled
CLOSE_EN Close operation from interlocking logic is enabled
Signal Description
EN_OPEN Open operation at closed or interm. or bad pos. is enabled
EN_CLOSE Close operation at open or interm. or bad pos. is enabled
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Interlocking Chapter 11
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3.4 Interlocking for line bay (ABC_LINE)
3.4.1 Introduction
The interlocking module ABC_LINE is used for a line connected to a double busbar arrange-
ment with a transfer busbar according to figure 200. The module can also be used for a double
busbar arrangement without transfer busbar or a single busbar arrangement with/without transfer
busbar.
Figure 200: Switchyard layout ABC_LINE
QB1 QB2
QC1
QA1
QC2
QB9
QC9
WA1 (A)
WA2 (B)
WA7 (C)
QB7
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3.4.2 Function block
Figure 201: IF function block
ABC_LINE
IF01-
QA1_OP
QA1_CL
QB9_OP
QB9_CL
QB1_OP
QB1_CL
QB2_OP
QB2_CL
QB7_OP
QB7_CL
QC1_OP
QC1_CL
QC2_OP
QC2_CL
QC9_OP
QC9_CL
QC11_OP
QC11_CL
QC21_OP
QC21_CL
QC71_OP
QC71_CL
BB7_D_OP
BC_12_CL
BC_17_OP
BC_17_CL
BC_27_OP
BC_27_CL
VOLT_OFF
VOLT_ON
VP_BB7_D
VP_BC_12
VP_BC_17
VP_BC_27
EXDU_ES
EXDU_BPB
EXDU_BC
QB9_EX1
QB9_EX2
QB1_EX1
QB1_EX2
QB1_EX3
QB2_EX1
QB2_EX2
QB2_EX3
QB7_EX1
QB7_EX2
QB7_EX3
QB7_EX4
QA1CLREL
QA1CLITL
QB9REL
QB9ITL
QB1REL
QB1ITL
QB2REL
QB2ITL
QB7REL
QB7ITL
QC1REL
QC1ITL
QC2REL
QC2ITL
QC9REL
QC9ITL
QB1OPTR
QB1CLTR
QB2OPTR
QB2CLTR
QB7OPTR
QB7CLTR
QB12OPTR
QB12CLTR
VPQB1TR
VPQB2TR
VPQB7TR
VPQB12TR
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Control
3.4.3 Logic diagram
QA1_OP
QB9_OP
QA1_CL
QB9_CL
QB1_CL
QB1_OP
QB2_OP
QB7_CL
QC9_OP
QC2_CL
QB7_OP
QC2_OP
QC1_CL
QC1_OP
QC9_CL
QC21_OP
QC21_CL
QC11_CL
QC11_OP
1
QB9ITL
QB9REL
en04000527.vsd
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
QB2_CL
VPQC21
VPQC11
VPQC9
VPQC2
VPQC1
VPQB7
VPQB2
VPQB1
VPQB9
VPQA1
ABC_LINE
=1
=1
QC71_OP
QC71_CL
VOLT_OFF
VOLT_ON
VPQC71
VPVOLT
& >1
&
VPQA1
VPQC1
VPQC2
VPQC9
QA1_OP
QC1_OP
QC2_OP
QC9_OP
QB9_EX1
VPQC2
VPQC9
QC2_CL
QC9_CL
QB9_EX2
& 1
QA1CLITL
QA1CLREL
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Interlocking Chapter 11
Control
&
&
&
1
QB1REL
QB1ITL
VPQA1
VPQB2
VPQC1
VPQC2
VPQC11
QA1_OP
QB2_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQB2
VP_BC_12
QB2_CL
BC_12_CL
EXDU_BC
QB1_EX2
VPQC1
VPQC11
QC1_CL
QC11_CL
EXDU_ES
QB1EX3
en04000528.vsd
1
419
Interlocking Chapter 11
Control
&
&
&
1
1
QB2REL
QB2ITL
VPQA1
VPQB1
VPQC1
VPQC2
VPQC21
QA1_OP
QB1_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQB1
VP_BC_12
QB1_CL
BC_12_CL
EXDU_BC
QB2_EX2
VPQC1
VPQC21
QC1_CL
QC21_CL
EXDU_ES
QB2_EX3
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Interlocking Chapter 11
Control
&
&
>1
1
VPQC9
VPQC71
VP_BB7_D
VP_BC_17
VP_BC_27
QC9_OP
QC71_OP
EXDU_ES
BB7_D_OP
EXDU_BPB
BC_17_OP
BC_27_OP
EXDU_BC
QB7_EX1
VPQA1
VPQB1
VPQC9
VPQB9
VPQC71
VP_BB7_D
VP_BC_17
QA1_CL
QB1_CL
QC9_OP
QB9_CL
QC71_OP
EXDU_ES
BB7_D_OP
EXDU_BPB
BC_17_CL
EXDU_BC
QB7_EX2
QB7REL
QB7ITL
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Interlocking Chapter 11
Control
VPQA1
VPQC9
VPQB2
VPQB9
VP_BB7_D
VPQC71
VP_BC_27
QB2_CL
EXDU_ES
QA1_CL
QC71_OP
QB9_CL
QC9_OP
BB7_D_OP
BC_27_CL
QB7_EX3
EXDU_BC
VPQC9
EXDU_BPB
VPQC71
QB2_OP
QB1_OP
VPQB9
VPQB2
VPQB1
QB7_EX4
EXDU_ES
QC71_CL
QC9_CL
QB9_OP
VPQB7
QB9_OP
QB7_OP
VPVOLT
VPQB9
VOLT_OFF
&
&
&
&
>1
1
1
QC1ITL
QC1REL
QC2REL
QC2ITL
QC9REL
1
QC9ITL
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Interlocking Chapter 11
Control
3.4.4 Input and output signals
Table 198: Input signals for the ABC_LINE (IF01-) function block
VPQB2
VPQB1
QB2_OP
QB1_OP
1
QB12CLTR
QB12OPTR
en04000532.vsd
>1
&
VPQB12TR
QB7OPTR
QB7CLTR
VPQB7TR
QB7_OP
QB7_CL
VPQB7
VPQB2
QB2_CL
QB2_OP QB2OPTR
QB2CLTR
VPQB2TR
QB1OPTR
QB1CLTR
VPQB1TR
QB1_OP
QB1_CL
VPQB1
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QB9_OP QB9 is in open position
QB9_CL QB9 is in closed position
QB1_OP QB1 is in open position
QB1_CL QB1 is in closed position
QB2_OP QB2 is in open position
QB2_CL QB2 is in closed position
QB7_OP QB7 is in open position
QB7_CL QB7 is in closed position
QC1_OP QC1 is in open position
QC1_CL QC1 is in closed position
QC2_OP QC2 is in open position
QC2_CL QC2 is in closed position
QC9_OP QC9 is in open position
QC9_CL QC9 is in closed position
QC11_OP Earthing switch QC11 on busbar WA1 is in open position
QC11_CL Earthing switch QC11 on busbar WA1 is in closed position
QC21_OP Earthing switch QC21 on busbar WA2 is in open position
QC21_CL Earthing switch QC21 on busbar WA2 is in closed position
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Interlocking Chapter 11
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QC71_OP Earthing switch QC71 on busbar WA7 is in open position
QC71_CL Earthing switch QC71 on busbar WA7 is in closed position
BB7_D_OP Disconnectors on busbar WA7 except in the own bay are open
BC_12_CL A bus coupler connection exists between busbar WA1 and WA2
BC_17_OP No bus coupler connection exists between busbar WA1 and
WA7
BC_17_CL A bus coupler connection exists between busbar WA1 and WA7
BC_27_OP No bus coupler connection exists between busbar WA2 and
WA7
BC_27_CL A bus coupler connection exists between busbar WA2 and WA7
VOLT_OFF There is no voltage on the line and not VT (fuse) failure
VOLT_ON There is voltage on the line or there is a VT (fuse) failure
VP_BB7_D Switch status of the disconnectors on busbar WA7 are valid
VP_BC_12 Status of the bus coupler app. between WA1 and WA2 are valid
VP_BC_17 Status of the bus coupler app. between WA1 and WA7 are valid
VP_BC_27 Status of the bus coupler app. between WA2 and WA7 are valid
EXDU_ES No transm error from any bay containing earthing switches
EXDU_BPB No transm error from any bay with disconnectors on WA7
EXDU_BC No transmission error from any bus coupler bay
QB9_EX1 External condition for apparatus QB9
QB9_EX2 External condition for apparatus QB9
QB1_EX1 External condition for apparatus QB1
QB1_EX2 External condition for apparatus QB1
QB1_EX3 External condition for apparatus QB1
QB2_EX1 External condition for apparatus QB2
QB2_EX2 External condition for apparatus QB2
QB2_EX3 External condition for apparatus QB2
QB7_EX1 External condition for apparatus QB7
QB7_EX2 External condition for apparatus QB7
QB7_EX3 External condition for apparatus QB7
QB7_EX4 External condition for apparatus QB7
Signal Description
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Interlocking Chapter 11
Control
Table 199: Output signals for the ABC_LINE (IF01-) function block
3.5 Interlocking for bus-coupler bay (ABC_BC)
3.5.1 Introduction
The interlocking module ABC_BC is used for a bus-coupler bay connected to a double busbar
arrangement according to figure 202. The module can also be used for a single busbar arrange-
ment with transfer busbar or double busbar arrangement without transfer busbar.
Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB9REL Switching of QB9 is allowed
QB9ITL Switching of QB9 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
QB7REL Switching of QB7 is allowed
QB7ITL Switching of QB7 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QC9REL Switching of QC9 is allowed
QC9ITL Switching of QC9 is forbidden
QB1OPTR QB1 is in open position
QB1CLTR QB1 is in closed position
QB2OPTR QB2 is in open position
QB2CLTR QB2 is in closed position
QB7OPTR QB7 is in open position
QB7CLTR QB7 is in closed position
QB12OPTR QB1 or QB2 or both are in open position
QB12CLTR QB1 and QB2 are not in open position
VPQB1TR Switch status of QB1 is valid (open or closed)
VPQB2TR Switch status of QB2 is valid (open or closed)
VPQB7TR Switch status of QB7 is valid (open or closed)
VPQB12TR Switch status of QB1 and QB2 are valid (open or closed)
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Interlocking Chapter 11
Control
Figure 202: Switchyard layout ABC_BC
QB1 QB2
QC1
QA1
WA1 (A)
WA2 (B)
WA7 (C)
QB7 QB20
QC2
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3.5.2 Function block
Figure 203: IG function block
ABC_BC
IG01-
QA1_OP
QA1_CL
QB1_OP
QB1_CL
QB2_OP
QB2_CL
QB7_OP
QB7_CL
QB20_OP
QB20_CL
QC1_OP
QC1_CL
QC2_OP
QC2_CL
QC11_OP
QC11_CL
QC21_OP
QC21_CL
QC71_OP
QC71_CL
BBTR_OP
BC_12_CL
VP_BBTR
VP_BC_12
EXDU_ES
EXDU_12
EXDU_BC
QA1O_EX1
QA1O_EX2
QA1O_EX3
QB1_EX1
QB1_EX2
QB1_EX3
QB2_EX1
QB2_EX2
QB2_EX3
QB20_EX1
QB20_EX2
QB7_EX1
QB7_EX2
QA1OPREL
QA1OPITL
QA1CLREL
QA1CLITL
QB1REL
QB1ITL
QB2REL
QB2ITL
QB7REL
QB7ITL
QB20REL
QB20ITL
QC1REL
QC1ITL
QC2REL
QC2ITL
QB1OPTR
QB1CLTR
QB220OTR
QB220CTR
QB7OPTR
QB7CLTR
QB12OPTR
QB12CLTR
BC12OPTR
BC12CLTR
BC17OPTR
BC17CLTR
BC27OPTR
BC27CLTR
VPQB1TR
VQB220TR
VPQB7TR
VPQB12TR
VPBC12TR
VPBC17TR
VPBC27TR
en05000350.vsd
427
Interlocking Chapter 11
Control
3.5.3 Logic diagram
QA1_OP
QB1_OP
QA1_CL
QB1_CL
QB20_CL
QB20_OP
QB7_OP
QB2_CL
QC11_OP
QC2_CL
QB2_OP
QC2_OP
QC1_CL
QC1_OP
QC11_CL
QC71_OP
VPQB1
QC71_CL
QB1_OP
QC21_CL
QC21_OP
QA1O_EX1
VPQB2
VPQB1
QA1O_EX3
EXDU_12
BBTR_OP
VP_BBTR
QA1O_EX2
QB20_OP
VPQB20
VPQB7
VPQB20
1
QA1OPITL
QA1OPREL
QA1CLREL
1
QA1CLITL
en04000533.vsd
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
QB7_CL
VPQC71
VPQC21
VPQC11
VPQC2
VPQC1
VPQB2
VPQB7
VPQB20
VPQB1
VPQA1
ABC_BC
&
&
&
>1
&
428
Interlocking Chapter 11
Control
VPQA1
VPQC1
VPQB2
VPQC2
QA1_OP
VPQC11
QB2_OP
QC2_OP
VPQB2
QB1_EX1
QC1_OP
EXDU_ES
QC11_OP
VP_BC_12
EXDU_BC
VPQC1
QB1_EX2
VPQC11
BC_12_CL
QB2_CL
QC1_CL
QB1_EX3
EXDU_ES
QC11_CL
1
QB1ITL
en04000534.vsd
&
&
>1
&
QB1REL
429
Interlocking Chapter 11
Control
VPQA1
VPQC1
VPQB1
VPQC2
QA1_OP
VPQC21
QB1_OP
QC2_OP
VPQB1
QB2_EX1
QC1_OP
EXDU_ES
QC21_OP
VP_BC_12
EXDU_BC
VPQC1
QB2_EX2
VPQC21
BC_12_CL
QB1_CL
QC1_CL
QB2_EX3
EXDU_ES
QC21_CL
1
QB2ITL
en04000535.vsd
&
&
>1
&
QB2REL
430
Interlocking Chapter 11
Control
VPQA1
VPQC1
VPQB20
VPQC2
QA1_OP
VPQC71
QB20_OP
QC2_OP
VPQC2
QB7_EX1
QC1_OP
EXDU_ES
QC71_OP
VPQC71
EXDU_ES
VPQA1
QB7_EX2
VPQB7
QC71_CL
QC2_CL
VPQC1
QB20_EX1
EXDU_ES
QC21_OP
QC2_OP
QC1_OP
QB7_OP
QA1_OP
VPQC21
VPQC2
VPQC2
VPQC21
EXDU_ES
QC21_CL
QC2_CL
QB20_EX2
QB20REL
1
QB20ITL
en04000536.vsd
&
&
>1
&
&
>1
QB7REL
1
QB7ITL
431
Interlocking Chapter 11
Control
VPQB1
VPQB7
VPQB20
VPQB2
QB20_OP
QB1_OP
QB7_OP
QB1_OP
QB2_OP
QB2_OP
VPQB1
QB1_CL
QB20_OP
VPQB2
VPQB20
VPQB1
VPQA1
QB7_OP
VPQB1
QA1_OP
QB1_OP
VPQB1
VPQA1
QB20_OP
QB1_OP
QA1_OP
QB2_OP
VPQB7
VPQA1
QB7_OP
VPQB2
QA1_OP
VPQB7
1
1
QC1ITL
QC1REL
QC2REL
QC2ITL
BC27OPTR
1
en04000537.vsd
&
&
&
QB220OTR
1
QB220CTR
QB1OPTR
QB1CLTR
VPQB1TR
VQB220TR
QB7_OP
QB7_CL
VPQB7
QB7OPTR
QB7CLTR
VPQB7TR
>1
QB1_OP
QB2_OP
1
QB12OPTR
QB12CLTR
& VPQB2
VPQB12TR
>1
1
BC12CLTR
BC12OPTR
&
VPQB20
VPBC12TR
>1
1
BC17CLTR
BC17OPTR
&
VPBC17TR
>1
BC27CLTR
&
VPBC27TR
432
Interlocking Chapter 11
Control
3.5.4 Input and output signals
Table 200: Input signals for the ABC_BC (IG01-) function block
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QB1_OP QB1 is in open position
QB1_CL QB1 is in closed position
QB2_OP QB2 is in open position
QB2_CL QB2 is in closed position
QB7_OP QB7 is in open position
QB7_CL QB7 is in closed position
QB20_OP QB20 is in open position
QB20_CL QB20 is in closed position
QC1_OP QC1 is in open position
QC1_CL QC1 is in closed position
QC2_OP QC2 is in open position
QC2_CL QC2 is in closed position
QC11_OP Earthing switch QC11 on busbar WA1 is in open position
QC11_CL Earthing switch QC11 on busbar WA1 is in closed position
QC21_OP Earthing switch QC21 on busbar WA2 is in open position
QC21_CL Earthing switch QC21 on busbar WA2 is in closed position
QC71_OP Earthing switch QC71 on busbar WA7 is in open position
QC71_CL Earthing switch QC71 on busbar WA7 is in closed position
BBTR_OP No busbar transfer is in progress
BC_12_CL A bus coupler connection exists between busbar WA1 and WA2
VP_BBTR Status are valid for app. involved in the busbar transfer
VP_BC_12 Status of the bus coupler app. between WA1 and WA2 are valid
EXDU_ES No transm error from any bay containing earthing switches
EXDU_12 No transm error from any bay connected to WA1/WA2 busbars
EXDU_BC No transmission error from any other bus coupler bay
QA1O_EX1 External open condition for apparatus QA1
QA1O_EX2 External open condition for apparatus QA1
QA1O_EX3 External open condition for apparatus QA1
QB1_EX1 External condition for apparatus QB1
QB1_EX2 External condition for apparatus QB1
QB1_EX3 External condition for apparatus QB1
QB2_EX1 External condition for apparatus QB2
QB2_EX2 External condition for apparatus QB2
433
Interlocking Chapter 11
Control
Table 201: Output signals for the ABC_BC (IG01-) function block
QB2_EX3 External condition for apparatus QB2
QB20_EX1 External condition for apparatus QB20
QB20_EX2 External condition for apparatus QB20
QB7_EX1 External condition for apparatus QB7
QB7_EX2 External condition for apparatus QB7
Signal Description
QA1OPREL Opening of QA1 is allowed
QA1OPITL Opening of QA1 is forbidden
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
QB7REL Switching of QB7 is allowed
QB7ITL Switching of QB7 is forbidden
QB20REL Switching of QB20 is allowed
QB20ITL Switching of QB20 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QB1OPTR QB1 is in open position
QB1CLTR QB1 is in closed position
QB220OTR QB2 and QB20 are in open position
QB220CTR QB2 or QB20 or both are not in open position
QB7OPTR QB7 is in open position
QB7CLTR QB7 is in closed position
QB12OPTR QB1 or QB2 or both are in open position
QB12CLTR QB1 and QB2 are not in open position
BC12OPTR No connection via the own bus coupler between WA1 and WA2
BC12CLTR Conn. exists via the own bus coupler between WA1 and WA2
BC17OPTR No connection via the own bus coupler between WA1 and WA7
BC17CLTR Conn. exists via the own bus coupler between WA1 and WA7
BC27OPTR No connection via the own bus coupler between WA2 and WA7
BC27CLTR Conn. exists via the own bus coupler between WA2 and WA7
Signal Description
434
Interlocking Chapter 11
Control
3.6 Interlocking for transformer bay (AB_TRAFO)
3.6.1 Introduction
The interlocking module AB_TRAFO is used for a transformer bay connected to a double bus-
bar arrangement according to figure 204. The module is used when there is no disconnector be-
tween circuit breaker and transformer. Otherwise, the module ABC_LINE can be used. This
module can also be used in single busbar arrangements.
Figure 204: Switchyard layout AB_TRAFO
VPQB1TR Switch status of QB1 is valid (open or closed)
VQB220TR Switch status of QB2 and QB20 are valid (open or closed)
VPQB7TR Switch status of QB7 is valid (open or closed)
VPQB12TR Switch status of QB1 and QB2 are valid (open or closed)
VPBC12TR Status of the bus coupler app. between WA1 and WA2 are valid
VPBC17TR Status of the bus coupler app. between WA1 and WA7 are valid
VPBC27TR Status of the bus coupler app. between WA2 and WA7 are valid
Signal Description
QB1 QB2
QC1
QA1
QC2
WA1 (A)
WA2 (B)
QA2
QC3
T
QC4
QB4 QB3
QA2 and QC4 are not
used in this interlocking
AB_TRAFO
en04000515.vsd
435
Interlocking Chapter 11
Control
3.6.2 Function block
Figure 205: IE function block
AB_TRAFO
IE01-
QA1_OP
QA1_CL
QB1_OP
QB1_CL
QB2_OP
QB2_CL
QC1_OP
QC1_CL
QC2_OP
QC2_CL
QB3_OP
QB3_CL
QB4_OP
QB4_CL
QC3_OP
QC3_CL
QC11_OP
QC11_CL
QC21_OP
QC21_CL
BC_12_CL
VP_BC_12
EXDU_ES
EXDU_BC
QA1_EX1
QA1_EX2
QA1_EX3
QB1_EX1
QB1_EX2
QB1_EX3
QB2_EX1
QB2_EX2
QB2_EX3
QA1CLREL
QA1CLITL
QB1REL
QB1ITL
QB2REL
QB2ITL
QC1REL
QC1ITL
QC2REL
QC2ITL
QB1OPTR
QB1CLTR
QB2OPTR
QB2CLTR
QB12OPTR
QB12CLTR
VPQB1TR
VPQB2TR
VPQB12TR
en05000358.vsd
436
Interlocking Chapter 11
Control
3.6.3 Logic diagram
QA1_OP
QB1_OP
QA1_CL
QB1_CL
QB2_CL
QB2_OP
QC1_OP
QC2_CL
QC3_OP
QB4_CL
QC2_OP
QB4_OP
QB3_CL
QB3_OP
QC3_CL
QC21_OP
VPQB1
QC21_CL
VPQB2
QC11_CL
QC11_OP
VPQC1
QC3_CL
QC2_CL
QC1_CL
QA1_EX3
QC3_OP
QA1_EX2
VPQB4
VPQB3
VPQC2
QA1_EX1
1
QA1CLITL
QA1CLREL
en04000538.vsd
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
QC1_CL
VPQC21
VPQC11
VPQC3
VPQB4
VPQB3
VPQC2
VPQC1
VPQB2
VPQB1
VPQA1
AB_TRAFO
&
VPQC3
>1
&
437
Interlocking Chapter 11
Control
VPQA1
VPQC1
VPQB2
VPQC2
VPQC11
VPQC3
QA1_OP
QC1_OP
EXDU_ES
QB2_OP
QC11_OP
QC3_OP
QC2_OP
QB1_EX1
VP_BC_12
BC_12_CL
QC3_OP
QB2_CL
EXDU_BC
VPQC3
VPQB2
VPQC3
VPQC2
VPQC1
QB1_EX2
1
QB1ITL
en04000539.vsd
&
&
>1
&
QB1REL
VPQC11
QC1_CL
QC2_CL
QC3_CL
QC11_CL
EXDU_ES
QB1_EX3
438
Interlocking Chapter 11
Control
VPQA1
VPQC1
VPQB1
VPQC2
VPQC21
VPQC3
QA1_OP
QC1_OP
EXDU_ES
QB1_OP
QC21_OP
QC3_OP
QC2_OP
QB2_EX1
VP_BC_12
BC_12_CL
QC3_OP
QB1_CL
EXDU_BC
VPQC3
VPQB1
VPQC3
VPQC2
VPQC1
QB2_EX2
1
QB2ITL
en04000540.vsd
&
&
>1
&
QB2REL
VPQC21
QC1_CL
QC2_CL
QC3_CL
QC21_CL
EXDU_ES
QB2_EX3
439
Interlocking Chapter 11
Control
3.6.4 Input and output signals
Table 202: Input signals for the AB_TRAFO (IE01-) function block
VPQB1
VPQB3
VPQB2
VPQB4
QB2_OP
QB1_OP
QB3_OP
QB1_OP
QB4_OP
VPQB1
QB1_CL
QB2_OP
VPQB1
1
1
QC1ITL
QC1REL
QC2REL
QC2ITL
en04000541.vsd
&
QB1OPTR
QB1CLTR
VPQB1TR
>1
QB1_OP
QB2_OP
1
QB12OPTR
QB12CLTR
& VPQB2
VPQB12TR
QB2_CL
VPQB2
QB2OPTR
QB2CLTR
VPQB2TR
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QB1_OP QB1 is in open position
QB1_CL QB1 is in closed position
QB2_OP QB2 is in open position
QB2_CL QB2 is in closed position
QC1_OP QC1 is in open position
QC1_CL QC1 is in closed position
QC2_OP QC2 is in open position
QC2_CL QC2 is in closed position
QB3_OP QB3 is in open position
QB3_CL QB3 is in closed position
QB4_OP QB4 is in open position
QB4_CL QB4 is in closed position
QC3_OP QC3 is in open position
QC3_CL QC3 is in closed position
QC11_OP QC11 on busbar WA1 is in open position
440
Interlocking Chapter 11
Control
Table 203: Output signals for the AB_TRAFO (IE01-) function block
QC11_CL QC11 on busbar WA1 is in closed position
QC21_OP QC21 on busbar WA2 is in open position
QC21_CL QC21 on busbar WA2 is in closed position
BC_12_CL A bus coupler connection exists between busbar WA1 and WA2
VP_BC_12 Status of the bus coupler app. between WA1 and WA2 are valid
EXDU_ES No transm error from any bay containing earthing switches
EXDU_BC No transmission error from any bus coupler bay
QA1_EX1 External condition for apparatus QA1
QA1_EX2 External condition for apparatus QA1
QA1_EX3 External condition for apparatus QA1
QB1_EX1 External condition for apparatus QB1
QB1_EX2 External condition for apparatus QB1
QB1_EX3 External condition for apparatus QB1
QB2_EX1 External condition for apparatus QB2
QB2_EX2 External condition for apparatus QB2
QB2_EX3 External condition for apparatus QB2
Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QB1OPTR QB1 is in open position
QB1CLTR QB1 is in closed position
QB2OPTR QB2 is in open position
QB2CLTR QB2 is in closed position
QB12OPTR QB1 or QB2 or both are in open position
QB12CLTR QB1 and QB2 are not in open position
VPQB1TR Switch status of QB1 is valid (open or closed)
VPQB2TR Switch status of QB2 is valid (open or closed)
VPQB12TR Switch status of QB1 and QB2 are valid (open or closed)
Signal Description
441
Interlocking Chapter 11
Control
3.7 Interlocking for bus-section breaker (A1A2_BS)
3.7.1 Introduction
The interlocking module A1A2_BS is used for one bus-section circuit breaker between section
1 and 2 according to figure206. The module can be used for different busbars, which includes
a bus-section circuit breaker.
Figure 206: Switchyard layout A1A2_BS
QA1
WA1 (A1)
QB2
QC4
QB1
QC3
WA2 (A2)
en04000516.vsd
QC2 QC1
A1A2_BS
442
Interlocking Chapter 11
Control
3.7.2 Function block
Figure 207: IH function block
A1A2_BS
IH01-
QA1_OP
QA1_CL
QB1_OP
QB1_CL
QB2_OP
QB2_CL
QC3_OP
QC3_CL
QC4_OP
QC4_CL
S1QC1_OP
S1QC1_CL
S2QC2_OP
S2QC2_CL
BBTR_OP
VP_BBTR
EXDU_12
EXDU_ES
QA1O_EX1
QA1O_EX2
QA1O_EX3
QB1_EX1
QB1_EX2
QB2_EX1
QB2_EX2
QA1OPREL
QA1OPITL
QA1CLREL
QA1CLITL
QB1REL
QB1ITL
QB2REL
QB2ITL
QC3REL
QC3ITL
QC4REL
QC4ITL
S1S2OPTR
S1S2CLTR
QB1OPTR
QB1CLTR
QB2OPTR
QB2CLTR
VPS1S2TR
VPQB1TR
VPQB2TR
en05000348.vsd
443
Interlocking Chapter 11
Control
3.7.3 Logic diagram
QA1_OP
QB1_OP
QA1_CL
QB1_CL
QB2_CL
QB2_OP
QC3_OP
QC4_CL
S2QC2_CL
QC4_OP
S2QC2_OP
S1QC1_CL
S1QC1_OP
1
QA1OPITL
QA1OPREL
en04000542.vsd
=1
=1
=1
=1
=1
=1
=1
QC3_CL
VPS2QC2
VPS1QC1
VPQC4
VPQC3
VPQB2
VPQB1
VPQA1
A1A2_BS
& >1
&
&
VPQB1
QB1_OP
QA1O_EX1
VPQB2
QB2_OP
QA1O_EX2
VP_BBTR
BBTR_OP
EXDU_12
QA1O_EX3
1
QA1CLITL
&
QA1CLREL VPQB1
VPQB2
& >1
&
1
QB1ITL
QB1REL
VPQA1
VPQC3
VPQC4
VPS1QC1
QA1_OP
QC3_OP
QC4_OP
S1QC1_OP
VPQC3
VPS1QC1
QC3_CL
S1QC1_CL
EXDU_ES
EXDU_ES
QB1_EX1
QB1_EX2
444
Interlocking Chapter 11
Control
VPQA1
VPQC4
VPQC3
VPS2QC2
QC3_OP
QA1_OP
QC4_OP
EXDU_ES
VPS2QC2
S2QC2_OP
QB2_EX1
VPQC4
S2QC2_CL
QC4_CL
QB1_OP
QB2_OP
QB1_OP
QA1_OP
QB2_CL
VPQB2
QB2_OP
VPQB1
QB1_CL
QB1_OP
VPQB2
VPQB1
VPQA1
1
QB2ITL
QB2REL
en04000543.vsd
EXDU_ES
QB2_EX2
VPQB1
VPQB2
1
QC3REL
QC3ITL
QB2_OP
>1
1
S1S2CLTR
QB2OPTR
&
&
1
QC4REL
QC4ITL
QB1OPTR
QB1CLTR
VPQB1TR
QB2CLTR
VPQB2TR
& >1
&
S1S2OPTR
VPS1S2TR
445
Interlocking Chapter 11
Control
3.7.4 Input and output signals
Table 204: Input signals for the A1A2_BS (IH01-) function block
Table 205: Output signals for the A1A2_BS (IH01-) function block
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QB1_OP QB1 is in open position
QB1_CL QB1 is in closed position
QB2_OP QB2 is in open position
QB2_CL QB2 is in closed position
QC3_OP QC3 is in open position
QC3_CL QC3 is in closed position
QC4_OP QC4 is in open position
QC4_CL QC4 is in closed position
S1QC1_OP QC1 on bus section 1 is in open position
S1QC1_CL QC1 on bus section 1 is in closed position
S2QC2_OP QC2 on bus section 2 is in open position
S2QC2_CL QC2 on bus section 2 is in closed position
BBTR_OP No busbar transfer is in progress
VP_BBTR Status are valid for app. involved in the busbar transfer
EXDU_12 No transm error from any bay connected to busbar 1 and 2
EXDU_ES No transm error from bays containing earth. sw. QC1 or QC2
QA1O_EX1 External open condition for apparatus QA1
QA1O_EX2 External open condition for apparatus QA1
QA1O_EX3 External open condition for apparatus QA1
QB1_EX1 External condition for apparatus QB1
QB1_EX2 External condition for apparatus QB1
QB2_EX1 External condition for apparatus QB2
QB2_EX2 External condition for apparatus QB2
Signal Description
QA1OPREL Opening of QA1 is allowed
QA1OPITL Opening of QA1 is forbidden
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
446
Interlocking Chapter 11
Control
3.8 Interlocking for bus-section disconnector (A1A2_DC)
3.8.1 Introduction
The interlocking module A1A2_DC is used for one bus-section disconnector between section 1
and 2 according to figure 208. The module can be used for different busbars, which includes a
bus-section disconnector.
Figure 208: Switchyard layout A1A2_DC
QC3REL Switching of QC3 is allowed
QC3ITL Switching of QC3 is forbidden
QC4REL Switching of QC4 is allowed
QC4ITL Switching of QC4 is forbidden
S1S2OPTR No bus section connection between bus section 1 and 2
S1S2CLTR Bus coupler connection between bus section 1 and 2 exists
QB1OPTR QB1 is in open position
QB1CLTR QB1 is in closed position
QB2OPTR QB2 is in open position
QB2CLTR QB2 is in closed position
VPS1S2TR Status of the app. between bus section 1 and 2 are valid
VPQB1TR Switch status of QB1 is valid (open or closed)
VPQB2TR Switch status of QB2 is valid (open or closed)
Signal Description
WA1 (A1) WA2 (A2)
QB
QC1 QC2
A1A2_DC
en04000492.vsd
447
Interlocking Chapter 11
Control
3.8.2 Function block
Figure 209: II function block
A1A2_DC
II01-
QB_OP
QB_CL
S1QC1_OP
S1QC1_CL
S2QC2_OP
S2QC2_CL
S1DC_OP
S2DC_OP
VPS1_DC
VPS2_DC
EXDU_ES
EXDU_BB
QBCL_EX1
QBCL_EX2
QBOP_EX1
QBOP_EX2
QBOP_EX3
QBOPREL
QBOPITL
QBCLREL
QBCLITL
DCOPTR
DCCLTR
VPDCTR
en05000349.vsd
448
Interlocking Chapter 11
Control
3.8.3 Logic diagram
QB_OP
QB_CL
S1QC1_CL
en04000544.vsd
=1
=1
=1
VPQB VPDCTR
DCOPTR
DCCLTR
S1QC1_OP
S2QC2_OP
S2QC2_CL
VPS1QC1
VPS2QC2
& >1
&
&
1
QBOPITL
QBOPREL
VPS1QC1
VPS2QC2
VPS1_DC
S1QC1_OP
S2QC2_OP
S1DC_OP
EXDU_ES
EXDU_BB
QBOP_EX1
VPS1QC1
VPS2QC2
VPS2_DC
S1QC1_OP
S2QC2_OP
S2DC_OP
EXDU_ES
EXDU_BB
QBOP_EX2
VPS1QC1
VPS2QC2
S1QC1_CL
S2QC2_CL
EXDU_ES
QBOP_EX3
A1A2_DC
449
Interlocking Chapter 11
Control
3.8.4 Input and output signals
Table 206: Input signals for the A1A2_DC (II01-) function block
Signal Description
QB_OP QB is in open position
QB_CL QB is in closed position
S1QC1_OP QC1 on bus section 1 is in open position
S1QC1_CL QC1 on bus section 1 is in closed position
S2QC2_OP QC2 on bus section 2 is in open position
S2QC2_CL QC2 on bus section 2 is in closed position
S1DC_OP All disconnectors on bus section 1 are in open position
S2DC_OP All disconnectors on bus section 2 are in open position
VPS1_DC Switch status of disconnectors on bus section 1 are valid
VPS2_DC Switch status of disconnectors on bus section 2 are valid
EXDU_ES No transm error from bays containing earth. sw. QC1 or QC2
EXDU_BB No transm error from bays with disc conn to section 1 and 2
QBCL_EX1 External close condition for section disconnector QB
QBCL_EX2 External close condition for section disconnector QB
QBOP_EX1 External open condition for section disconnector QB
QBOP_EX2 External open condition for section disconnector QB
QBOP_EX3 External open condition for section disconnector QB
450
Interlocking Chapter 11
Control
Table 207: Output signals for the A1A2_DC (II01-) function block
3.9 Interlocking for busbar earthing switch (BB_ES)
3.9.1 Introduction
The interlocking module BB_ES is used for one busbar earthing switch on any busbar parts ac-
cording to figure 210.
Figure 210: Switchyard layout BB_ES
3.9.2 Function block
Figure 211: IJ function block
Signal Description
QBOPREL Opening of QB is allowed
QBOPITL Opening of QB is forbidden
QBCLREL Closing of QB is allowed
QBCLITL Closing of QB is forbidden
DCOPTR The bus section disconnector is in open position
DCCLTR The bus section disconnector is in closed position
VPDCTR Switch status of QB is valid (open or closed)
QC
en04000504.vsd
BB_ES
IJ 01-
QC_OP
QC_CL
BB_DC_OP
VP_BB_DC
EXDU_BB
QCREL
QCITL
BBESOPTR
BBESCLTR
en05000347.vsd
451
Interlocking Chapter 11
Control
3.9.3 Logic diagram
3.9.4 Input and output signals
Table 208: Input signals for the BB_ES (IJ01-) function block
Table 209: Output signals for the BB_ES (IJ01-) function block
3.10 Interlocking for double CB bay (DB)
3.10.1 Introduction
The interlocking modules DB_BUS_A, DB_LINE and DB_BUS_B are used for a line connect-
ed to a double circuit breaker arrangement according to figure 212.
EXDU_BB
en04000546.vsd
VP_BB_DC
BB_DC_OP
1
QCREL
QCITL
&
BBESOPTR
BBESCLTR
QC_OP
QC_CL
BB_ES
Signal Description
QC_OP Busbar earthing switch QC is in open position
QC_CL Busbar earthing switch QC is in closed position
BB_DC_OP All disconnectors on this busbar part are open
VP_BB_DC Status for all disconnectors on this busbar part are valid
EXDU_BB No transm error from bays with disc on this busbar part
Signal Description
QCREL Switching of QC is allowed
QCITL Switching of QC is forbidden
BBESOPTR QC on this busbar part is in open position
BBESCLTR QC on this busbar part is in closed position
452
Interlocking Chapter 11
Control
Figure 212: Switchyard layout double circuit breaker.
Three types of interlocking modules per double circuit breaker bay are defined. DB_LINE is the
connection from the line to the circuit breaker parts that are connected to the busbars.
DB_BUS_A and DB_BUS_B are the connections from the line to the busbars.
WA1 (A)
WA2 (B)
QB1
QC1
QA1
QC2
QC9
QB61
QB9
QB2
QC4
QA2
QC5
QC3
QB62
DB_BUS_B
DB_LINE
DB_BUS_A
en04000518.vsd
453
Interlocking Chapter 11
Control
3.10.2 Function block
Figure 213: IB function block
Figure 214: IA function block
DB_BUS_A
IB01-
QA1_OP
QA1_CL
QB1_OP
QB1_CL
QB61_OP
QB61_CL
QC1_OP
QC1_CL
QC2_OP
QC2_CL
QC3_OP
QC3_CL
QC11_OP
QC11_CL
EXDU_ES
QB61_EX1
QB61_EX2
QB1_EX1
QB1_EX2
QA1CLREL
QA1CLITL
QB61REL
QB61ITL
QB1REL
QB1ITL
QC1REL
QC1ITL
QC2REL
QC2ITL
QB1OPTR
QB1CLTR
VPQB1TR
en05000354.vsd
DB_LINE
IA01-
QA1_OP
QA1_CL
QA2_OP
QA2_CL
QB61_OP
QB61_CL
QC1_OP
QC1_CL
QC2_OP
QC2_CL
QB62_OP
QB62_CL
QC4_OP
QC4_CL
QC5_OP
QC5_CL
QB9_OP
QB9_CL
QC3_OP
QC3_CL
QC9_OP
QC9_CL
VOLT_OFF
VOLT_ON
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
QB9REL
QB9ITL
QC3REL
QC3ITL
QC9REL
QC9ITL
en05000356.vsd
454
Interlocking Chapter 11
Control
Figure 215: IC function block
DB_BUS_B
IC01-
QA2_OP
QA2_CL
QB2_OP
QB2_CL
QB62_OP
QB62_CL
QC4_OP
QC4_CL
QC5_OP
QC5_CL
QC3_OP
QC3_CL
QC21_OP
QC21_CL
EXDU_ES
QB62_EX1
QB62_EX2
QB2_EX1
QB2_EX2
QA2CLREL
QA2CLITL
QB62REL
QB62ITL
QB2REL
QB2ITL
QC4REL
QC4ITL
QC5REL
QC5ITL
QB2OPTR
QB2CLTR
VPQB2TR
en05000355.vsd
455
Interlocking Chapter 11
Control
3.10.3 Logic diagrams
QA1_OP
QB61_OP
QA1_CL
QB61_CL
QB1_CL
QB1_OP
QC1_OP
QC2_CL
QC11_CL
QC2_OP
QC11_OP
QC3_CL
QC3_OP
en04000547.vsd
=1
=1
=1
=1
=1
=1
=1
QC1_CL
VPQC11
VPQC3
VPQC2
VPQC1
VPQB1
VPQB61
VPQA1
DB_BUS_A
VPQB61
1
QA1CLITL
&
& >1
&
1
QB1ITL
QB1REL
VPQA1
VPQC1
VPQC2
VPQC11
QA1_OP
QC1_OP
QC2_OP
QC11_OP
VPQC1
VPQC11
QC1_CL
QC11_CL
EXDU_ES
EXDU_ES
QB1_EX1
QB1_EX2
QA1CLREL
1
QB61ITL
QB61REL
VPQA1
VPQC1
VPQC2
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QC2_CL
QC3_CL
QB61_EX2
QB61_EX1
VPQC2
VPQC3
& >1
&
VPQB1
456
Interlocking Chapter 11
Control
QB61_OP
en04000548.vsd
VPQB61
VPQB1
1
QC1REL
QC1ITL
QB1_OP
QB1_OP
QB1_CL
&
1
QC2REL
QC2ITL
VPQB1
QB1OPTR
QB1CLTR
VPQB1TR
457
Interlocking Chapter 11
Control
QA1_OP
QA2_OP
QA1_CL
QA2_CL
QB61_CL
QB61_OP
QC1_OP
QC2_CL
QC5_OP
QC4_CL
QC2_OP
QC4_OP
QB62_CL
QB62_OP
QC5_CL
QC3_OP
QC3_CL
QB9_CL
QB9_OP
1
QB9ITL
QB9REL
en04000549.vsd
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
QC1_CL
VPQC3
VPQB9
VPQC5
VPQC4
VPQB62
VPQC2
VPQC1
VPQB61
VPQA2
VPQA1
DB_LINE
=1
=1
QC9_OP
QC9_CL
VOLT_OFF
VOLT_ON
VPQC9
VPVOLT
& >1
&
VPQA1
VPQA2
VPQC1
VPQC2
VPQC3
VPQC4
VPQC5
VPQC9
QA1_OP
QA2_OP
QC1_OP
QC2_OP
QC3_OP
QC4_OP
QC5_OP
QC9_OP
QB9_EX1
458
Interlocking Chapter 11
Control
en04000550.vsd
& >1
VPQA1
VPQC1
VPQC2
VPQC3
VPQC9
VPQB62
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QC9_OP
QB62_OP
QB9_EX2
VPQA2
VPQB61
VPQC3
VPQC4
&
VPQC5
VPQC9
QA2_OP
QB61_OP
QC3_OP
QC4_OP
QC5_OP
QC9_OP
QB9_EX3
&
VPQC3
VPQC9
VPQB61
VPQB62
QC3_OP
QC9_OP
QB61_OP
QB62_OP
QB9_EX4
&
VPQC3
VPQC9
QC3_CL
QC9_CL
QB9_EX5
459
Interlocking Chapter 11
Control
1
QC3ITL
QC3REL
en04000551.vsd
VPQB62
VPQB9
QB61_OP
QB62_OP
QB9_OP
VPQB9
VPVOLT
QB9_OP
VOLT_OFF
&
&
VPQB61
1
QC9ITL
QC9REL
460
Interlocking Chapter 11
Control
QA2_OP
QB62_OP
QA2_CL
QB62_CL
QB2_CL
QB2_OP
QC4_OP
QC5_CL
QC21_CL
QC5_OP
QC21_OP
QC3_CL
QC3_OP
en04000552.vsd
=1
=1
=1
=1
=1
=1
=1
QC4_CL
VPQC21
VPQC3
VPQC5
VPQC4
VPQB2
VPQB62
VPQA2
DB_BUS_B
VPQB62
1
QA2CLITL
&
& >1
&
1
QB2ITL
QB2REL
VPQA2
VPQC4
VPQC5
VPQC21
QA2_OP
QC4_OP
QC5_OP
QC21_OP
VPQC4
VPQC21
QC4_CL
QC21_CL
EXDU_ES
EXDU_ES
QB2_EX1
QB2_EX2
QA2CLREL
1
QB62ITL
QB62REL
VPQA2
VPQC4
VPQC5
VPQC3
QA2_OP
QC4_OP
QC5_OP
QC3_OP
QC5_CL
QC3_CL
QB62_EX2
QB62_EX1
VPQC5
VPQC3
& >1
&
VPQB2
461
Interlocking Chapter 11
Control
3.10.4 Input and output signals
Table 210: Input signals for the DB_BUS_A (IB01-) function block
QB62_OP
en04000553.vsd
VPQB62
VPQB2
1
QC4REL
QC4ITL
QB2_OP
QB2_OP
QB2_CL
&
1
QC5REL
QC5ITL
VPQB2
QB2OPTR
QB2CLTR
VPQB2TR
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QB1_OP QB1 is in open position
QB1_CL QB1 is in closed position
QB61_OP QB61 is in open position
QB61_CL QB61 is in closed position
QC1_OP QC1 is in open position
QC1_CL QC1 is in closed position
QC2_OP QC2 is in open position
QC2_CL QC2 is in closed position
QC3_OP QC3 is in open position
QC3_CL QC3 is in closed position
QC11_OP Earthing switch QC11 on busbar WA1 is in open position
QC11_CL Earthing switch QC11 on busbar WA1 is in closed position
EXDU_ES No transm error from bay containing earthing switch QC11
QB61_EX1 External condition for apparatus QB61
QB61_EX2 External condition for apparatus QB61
QB1_EX1 External condition for apparatus QB1
QB1_EX2 External condition for apparatus QB1
462
Interlocking Chapter 11
Control
Table 211: Output signals for the DB_BUS_A (IB01-) function block
Table 212: Input signals for the DB_LINE (IA01-) function block
Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB61REL Switching of QB61 is allowed
QB61ITL Switching of QB61 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QB1OPTR QB1 is in open position
QB1CLTR QB1 is in closed position
VPQB1TR Switch status of QB1 is valid (open or closed)
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QA2_OP QA2 is in open position
QA2_CL QA2 is in closed position
QB61_OP QB61 is in open position
QB61_CL QB61 is in closed position
QC1_OP QC1 is in open position
QC1_CL QC1 is in closed position
QC2_OP QC2 is in open position
QC2_CL QC2 is in closed position
QB62_OP QB62 is in open position
QB62_CL QB62 is in closed position
QC4_OP QC4 is in open position
QC4_CL QC4 is in closed position
QC5_OP QC5 is in open position
QC5_CL QC5 is in closed position
QB9_OP QB9 is in open position
QB9_CL QB9 is in closed position
QC3_OP QC3 is in open position
QC3_CL QC3 is in closed position
QC9_OP QC9 is in open position
463
Interlocking Chapter 11
Control
Table 213: Output signals for the DB_LINE (IA01-) function block
Table 214: Input signals for the DB_BUS_B (IC01-) function block
QC9_CL QC9 is in closed position
VOLT_OFF There is no voltage on the line and not VT (fuse) failure
VOLT_ON There is voltage on the line or there is a VT (fuse) failure
QB9_EX1 External condition for apparatus QB9
QB9_EX2 External condition for apparatus QB9
QB9_EX3 External condition for apparatus QB9
QB9_EX4 External condition for apparatus QB9
QB9_EX5 External condition for apparatus QB9
Signal Description
QB9REL Switching of QB9 is allowed
QB9ITL Switching of QB9 is forbidden
QC3REL Switching of QC3 is allowed
QC3ITL Switching of QC3 is forbidden
QC9REL Switching of QC9 is allowed
QC9ITL Switching of QC9 is forbidden
Signal Description
QA2_OP QA2 is in open position
QA2_CL QA2 is in closed position
QB2_OP QB2 is in open position
QB2_CL QB2 is in closed position
QB62_OP QB62 is in open position
QB62_CL QB62 is in closed position
QC4_OP QC4 is in open position
QC4_CL QC4 is in closed position
QC5_OP QC5 is in open position
QC5_CL QC5 is in closed position
QC3_OP QC3 is in open position
QC3_CL QC3 is in closed position
QC21_OP Earthing switch QC21 on busbar WA2 is in open position
QC21_CL Earthing switch QC21 on busbar WA2 is in closed position
Signal Description
464
Interlocking Chapter 11
Control
Table 215: Output signals for the DB_BUS_B (IC01-) function block
3.11 Interlocking for 1 1/2 CB diameter (BH)
3.11.1 Introduction
The interlocking modules BH_LINE_A, BH_CONN and BH_LINE_B are used for lines con-
nected to a breaker-and-a-half diameter according to figure 216.
EXDU_ES No transm error from bay containing earthing switch QC21
QB62_EX1 External condition for apparatus QB62
QB62_EX2 External condition for apparatus QB62
QB2_EX1 External condition for apparatus QB2
QB2_EX2 External condition for apparatus QB2
Signal Description
QA2CLREL Closing of QA2 is allowed
QA2CLITL Closing of QA2 is forbidden
QB62REL Switching of QB62 is allowed
QB62ITL Switching of QB62 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
QC4REL Switching of QC4 is allowed
QC4ITL Switching of QC4 is forbidden
QC5REL Switching of QC5 is allowed
QC5ITL Switching of QC5 is forbidden
QB2OPTR QB2 is in open position
QB2CLTR QB2 is in closed position
VPQB2TR Switch status of QB2 is valid (open or closed)
Signal Description
465
Interlocking Chapter 11
Control
Figure 216: Switchyard layout breaker-and-a-half
Three types of interlocking modules per diameter are defined. BH_LINE_A and BH_LINE_B
are the connections from a line to a busbar. BH_CONN is the connection between the two lines
of the diameter in the breaker and a half switchyard layout.
WA1 (A)
WA2 (B)
QB1
QC1
QA1
QC2
QC9
QB6
QB9
QB2
QC1
QA1
QC2
QC3
QB6
QC3
QB62 QB61 QA1
QC1 QC2
QC9
QB9
BH_LINE_A BH_LINE_B
BH_CONN
en04000513.vsd
466
Interlocking Chapter 11
Control
3.11.2 Function blocks
Figure 217: IL function block
BH_LINE_A
IL01-
QA1_OP
QA1_CL
QB6_OP
QB6_CL
QB1_OP
QB1_CL
QC1_OP
QC1_CL
QC2_OP
QC2_CL
QC3_OP
QC3_CL
QB9_OP
QB9_CL
QC9_OP
QC9_CL
CQA1_OP
CQA1_CL
CQB61_OP
CQB61_CL
CQC1_OP
CQC1_CL
CQC2_OP
CQC2_CL
QC11_OP
QC11_CL
VOLT_OFF
VOLT_ON
EXDU_ES
QB6_EX1
QB6_EX2
QB1_EX1
QB1_EX2
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
QB9_EX6
QB9_EX7
QA1CLREL
QA1CLITL
QB6REL
QB6ITL
QB1REL
QB1ITL
QC1REL
QC1ITL
QC2REL
QC2ITL
QC3REL
QC3ITL
QB9REL
QB9ITL
QC9REL
QC9ITL
QB1OPTR
QB1CLTR
VPQB1TR
en05000352.vsd
467
Interlocking Chapter 11
Control
Figure 218: IM function block
BH_LINE_B
IM01-
QA1_OP
QA1_CL
QB6_OP
QB6_CL
QB2_OP
QB2_CL
QC1_OP
QC1_CL
QC2_OP
QC2_CL
QC3_OP
QC3_CL
QB9_OP
QB9_CL
QC9_OP
QC9_CL
CQA1_OP
CQA1_CL
CQB62_OP
CQB62_CL
CQC1_OP
CQC1_CL
CQC2_OP
CQC2_CL
QC21_OP
QC21_CL
VOLT_OFF
VOLT_ON
EXDU_ES
QB6_EX1
QB6_EX2
QB2_EX1
QB2_EX2
QB9_EX1
QB9_EX2
QB9_EX3
QB9_EX4
QB9_EX5
QB9_EX6
QB9_EX7
QA1CLREL
QA1CLITL
QB6REL
QB6ITL
QB2REL
QB2ITL
QC1REL
QC1ITL
QC2REL
QC2ITL
QC3REL
QC3ITL
QB9REL
QB9ITL
QC9REL
QC9ITL
QB2OPTR
QB2CLTR
VPQB2TR
en05000353.vsd
468
Interlocking Chapter 11
Control
Figure 219: IK function block
BH_CONN
IK01-
QA1_OP
QA1_CL
QB61_OP
QB61_CL
QB62_OP
QB62_CL
QC1_OP
QC1_CL
QC2_OP
QC2_CL
1QC3_OP
1QC3_CL
2QC3_OP
2QC3_CL
QB61_EX1
QB61_EX2
QB62_EX1
QB62_EX2
QA1CLREL
QA1CLITL
QB61REL
QB61ITL
QB62REL
QB62ITL
QC1REL
QC1ITL
QC2REL
QC2ITL
en05000351.vsd
469
Interlocking Chapter 11
Control
3.11.3 Logic diagrams
QA1_OP
QB1_OP
QA1_CL
QB1_CL
QB6_CL
QB6_OP
QC9_OP
QB9_CL
QC3_OP
QC2_CL
QB9_OP
QC2_OP
QC1_CL
QC1_OP
QC3_CL
CQC1_OP
CQC1_CL
CQA1_CL
CQA1_OP
1
QB6ITL
QB6REL
en04000554.vsd
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
QC9_CL
VPCQC1
VPCQA1
VPQC3
VPQC2
VPQC1
VPQB9
VPQC9
VPQB6
VPQB1
VPQA1
BH_LINE_A
=1
=1
CQC2_OP
CQC2_CL
CQB61_OP
VPCQC2
VPCQB61
& >1
VPQA1
VPQC1
VPQC2
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QB6_EX1
VPQC2
VPQC3
QC2_CL
QC3_CL
QB6_EX2
=1
=1
QC11_CL
VOLT_OFF
VPQC11
VPVOLT
QC11_OP
CQB61_CL
VOLT_ON
1
QA1CLITL
QA1CLREL
&
VPQB1
VPQB6
VPQB9
&
470
Interlocking Chapter 11
Control
VPQA1
VPQB6
VPQC9
QB9_EX2
QB6_OP
QB9_EX1
VPCQC2
VPCQC1
VPCQB61
VPQC3
VPQC2
VPQC1
QA1_OP
1
QB9ITL
QB9REL
en04000555.vsd
&
VPCQA1
>1
&
& >1
&
1
QB1ITL
QB1REL
1
QC1ITL
QC1REL
&
1
QC2ITL
QC2REL
&
1
QC3ITL
QC3REL
>1
QC1_OP
QC2_OP
QB9_EX3
VPQA1
VPQC1
VPQC2
VPQC11
QA1_OP
QC1_OP
QC2_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQC1
VPQC11
QC1_CL
QC11_CL
EXDU_ES
QB1_EX2
VPQB1
VPQB6
QB1_OP
QB6_OP
VPQB6
VPQB9
VPCQB61
QB6_OP
QB9_OP
CQB61_OP
471
Interlocking Chapter 11
Control
QB9_EX4
CQB61_OP
CQA1_OP
en04000556.vsd
&
>1
1
QC9ITL
QC9REL
&
CQC1_OP
CQC2_OP
QB9_EX5
VPQB9
VPVOLT
QB9_OP
VOLT_OFF
&
QC9_OP
QC3_OP
QB9_EX6
VPQC9
VPQC3
QC9_CL
QC3_CL
QB9_EX7
&
QB1OPTR
QB1CLTR
VPQB1TR
QB1_OP
QB1_CL
VPQB1
>1
472
Interlocking Chapter 11
Control
QA1_OP
QB2_OP
QA1_CL
QB2_CL
QB6_CL
QB6_OP
QC9_OP
QB9_CL
QC3_OP
QC2_CL
QB9_OP
QC2_OP
QC1_CL
QC1_OP
QC3_CL
CQC1_OP
CQC1_CL
CQA1_CL
CQA1_OP
1
QB6ITL
QB6REL
en04000557.vsd
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
QC9_CL
VPCQC1
VPCQA1
VPQC3
VPQC2
VPQC1
VPQB9
VPQC9
VPQB6
VPQB2
VPQA1
BH_LINE_B
=1
=1
CQC2_OP
CQC2_CL
CQB62_OP
VPCQC2
VPCQB62
& >1
VPQA1
VPQC1
VPQC2
VPQC3
QA1_OP
QC1_OP
QC2_OP
QC3_OP
QB6_EX1
VPQC2
VPQC3
QC2_CL
QC3_CL
QB6_EX2
=1
=1
QC21_CL
VOLT_OFF
VPQC21
VPVOLT
QC21_OP
CQB62_CL
VOLT_ON
1
QA1CLITL
QA1CLREL
&
VPQB2
VPQB6
VPQB9
&
473
Interlocking Chapter 11
Control
VPQA1
VPQB6
VPQC9
QB9_EX2
QB6_OP
QB9_EX1
VPCQC2
VPCQC1
VPCQB62
VPQC3
VPQC2
VPQC1
QA1_OP
1
QB9ITL
QB9REL
en04000558.vsd
&
VPCQA1
>1
&
& >1
&
1
QB2ITL
QB2REL
1
QC1ITL
QC1REL
&
1
QC2ITL
QC2REL
&
1
QC3ITL
QC3REL
>1
QC1_OP
QC2_OP
QB9_EX3
VPQA1
VPQC1
VPQC2
VPQC21
QA1_OP
QC1_OP
QC2_OP
QC21_OP
EXDU_ES
QB2_EX1
VPQC1
VPQC21
QC1_CL
QC21_CL
EXDU_ES
QB2_EX2
VPQB2
VPQB6
QB2_OP
QB6_OP
VPQB6
VPQB9
VPCQB62
QB6_OP
QB9_OP
CQB62_OP
474
Interlocking Chapter 11
Control
QB9_EX4
CQB62_OP
CQA1_OP
en04000559.vsd
&
>1
1
QC9ITL
QC9REL
&
CQC1_OP
CQC2_OP
QB9_EX5
VPQB9
VPVOLT
QB9_OP
VOLT_OFF
&
QC9_OP
QC3_OP
QB9_EX6
VPQC9
VPQC3
QC9_CL
QC3_CL
QB9_EX7
&
QB2OPTR
QB2CLTR
VPQB2TR
QB2_OP
QB2_CL
VPQB2
>1
475
Interlocking Chapter 11
Control
QA1_OP
QB61_OP
QA1_CL
QB61_CL
QB62_CL
QB62_OP
QC1_OP
QC2_CL
2QC3_CL
QC2_OP
2QC3_OP
1QC3_CL
1QC3_OP
en04000560.vsd
=1
=1
=1
=1
=1
=1
=1
QC1_CL
VP2QC3
VP1QC3
VPQC2
VPQC1
VPQB62
VPQB61
VPQA1
BH_CONN
VPQB61
1
QA1CLITL
&
1
QB62ITL
QB62REL
VPQA1
VPQC1
VPQC2
VP2QC3
QA1_OP
QC1_OP
QC2_OP
2QC3_OP
QC2_CL
2QC3_CL
QB62_EX2
QB62_EX1
VPQC2
VP2QC3
QA1CLREL
1
QB61ITL
QB61REL
VPQA1
VPQC1
VPQC2
VP1QC3
QA1_OP
QC1_OP
QC2_OP
1QC3_OP
QC1_CL
1QC3_CL
QB61_EX2
QB61_EX1
VPQC1
VP1QC3
& >1
&
VPQB62
& >1
&
&
1
QC1ITL
QC1REL
1
QC2ITL
QC2REL
VPQB61
VPQB62
QB61_OP
QB62_OP
476
Interlocking Chapter 11
Control
3.11.4 Input and output signals
Table 216: Input signals for the BH_LINE_A (IL01-) function block
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QB6_OP QB6 is in open position
QB6_CL QB6 is in close position
QB1_OP QB1 is in open position
QB1_CL QB1 is in closed position
QC1_OP QC1 is in open position
QC1_CL QC1 is in closed position
QC2_OP QC2 is in open position
QC2_CL QC2 is in closed position
QC3_OP QC3 is in open position
QC3_CL QC3 is in closed position
QB9_OP QB9 is in open position
QB9_CL QB9 is in closed position
QC9_OP QC9 is in open position
QC9_CL QC9 is in closed position
CQA1_OP QA1 in module BH_CONN is in open position
CQA1_CL QA1 in module BH_CONN is in closed position
CQB61_OP QB61 in module BH_CONN is in open position
CQB61_CL QB61 in module BH_CONN is in closed position
CQC1_OP QC1 in module BH_CONN is in open position
CQC1_CL QC1 in module BH_CONN is in closed position
CQC2_OP QC2 in module BH_CONN is in open position
CQC2_CL QC2 in module BH_CONN is in closed position
QC11_OP Earthing switch QC11 on busbar WA1 is in open position
QC11_CL Earthing switch QC11 on busbar WA1 is in closed position
VOLT_OFF There is no voltage on line and not VT (fuse) failure
VOLT_ON There is voltage on the line or there is a VT (fuse) failure
EXDU_ES No transm error from bay containing earthing switch QC11
QB6_EX1 External condition for apparatus QB6
QB6_EX2 External condition for apparatus QB6
QB1_EX1 External condition for apparatus QB1
QB1_EX2 External condition for apparatus QB1
QB9_EX1 External condition for apparatus QB9
QB9_EX2 External condition for apparatus QB9
477
Interlocking Chapter 11
Control
Table 217: Output signals for the BH_LINE_A (IL01-) function block
Table 218: Input signals for the BH_LINE_B (IM01-) function block
QB9_EX3 External condition for apparatus QB9
QB9_EX4 External condition for apparatus QB9
QB9_EX5 External condition for apparatus QB9
QB9_EX6 External condition for apparatus QB9
QB9_EX7 External condition for apparatus QB9
Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB6REL Switching of QB6 is allowed
QB6ITL Switching of QB6 is forbidden
QB1REL Switching of QB1 is allowed
QB1ITL Switching of QB1 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QC3REL Switching of QC3 is allowed
QC3ITL Switching of QC3 is forbidden
QB9REL Switching of QB9 is allowed
QB9ITL Switching of QB9 is forbidden
QC9REL Switching of QC9 is allowed
QC9ITL Switching of QC9 is forbidden
QB1OPTR QB1 is in open position
QB1CLTR QB1 is in closed position
VPQB1TR Switch status of QB1 is valid (open or closed)
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QB6_OP QB6 is in open position
QB6_CL QB6 is in close position
QB2_OP QB2 is in open position
QB2_CL QB2 is in closed position
QC1_OP QC1 is in open position
Signal Description
478
Interlocking Chapter 11
Control
QC1_CL QC1 is in closed position
QC2_OP QC2 is in open position
QC2_CL QC2 is in closed position
QC3_OP QC3 is in open position
QC3_CL QC3 is in closed position
QB9_OP QB9 is in open position
QB9_CL QB9 is in closed position
QC9_OP QC9 is in open position
QC9_CL QC9 is in closed position
CQA1_OP QA1 in module BH_CONN is in open position
CQA1_CL QA1 in module BH_CONN is in closed position
CQB62_OP QB62 in module BH_CONN is in open position
CQB62_CL QB62 in module BH_CONN is in closed position
CQC1_OP QC1 in module BH_CONN is in open position
CQC1_CL QC1 in module BH_CONN is in closed position
CQC2_OP QC2 in module BH_CONN is in open position
CQC2_CL QC2 in module BH_CONN is in closed position
QC21_OP Earthing switch QC21 on busbar WA2 is in open position
QC21_CL Earthing switch QC21 on busbar WA2 is in closed position
VOLT_OFF There is no voltage on line and not VT (fuse) failure
VOLT_ON There is voltage on the line or there is a VT (fuse) failure
EXDU_ES No transm error from bay containing earthing switch QC21
QB6_EX1 External condition for apparatus QB6
QB6_EX2 External condition for apparatus QB6
QB2_EX1 External condition for apparatus QB2
QB2_EX2 External condition for apparatus QB2
QB9_EX1 External condition for apparatus QB9
QB9_EX2 External condition for apparatus QB9
QB9_EX3 External condition for apparatus QB9
QB9_EX4 External condition for apparatus QB9
QB9_EX5 External condition for apparatus QB9
QB9_EX6 External condition for apparatus QB9
QB9_EX7 External condition for apparatus QB9
Signal Description
479
Interlocking Chapter 11
Control
Table 219: Output signals for the BH_LINE_B (IM01-) function block
Table 220: Input signals for the BH_CONN (IK01-) function block
Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB6REL Switching of QB6 is allowed
QB6ITL Switching of QB6 is forbidden
QB2REL Switching of QB2 is allowed
QB2ITL Switching of QB2 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
QC3REL Switching of QC3 is allowed
QC3ITL Switching of QC3 is forbidden
QB9REL Switching of QB9 is allowed
QB9ITL Switching of QB9 is forbidden
QC9REL Switching of QC9 is allowed
QC9ITL Switching of QC9 is forbidden
QB2OPTR QB2 is in open position
QB2CLTR QB2 is in closed position
VPQB2TR Switch status of QB2 is valid (open or closed)
Signal Description
QA1_OP QA1 is in open position
QA1_CL QA1 is in closed position
QB61_OP QB61 is in open position
QB61_CL QB61 is in closed position
QB62_OP QB62 is in open position
QB62_CL QB62 is in closed position
QC1_OP QC1 is in open position
QC1_CL QC1 is in closed position
QC2_OP QC2 is in open position
QC2_CL QC2 is in closed position
1QC3_OP QC3 on line 1 is in open position
1QC3_CL QC3 on line 1 is in closed position
2QC3_OP QC3 on line 2 is in open position
480
Interlocking Chapter 11
Control
Table 221: Output signals for the BH_CONN (IK01-) function block
2QC3_CL QC3 on line 2 is in closed position
QB61_EX1 External condition for apparatus QB61
QB61_EX2 External condition for apparatus QB61
QB62_EX1 External condition for apparatus QB62
QB62_EX2 External condition for apparatus QB62
Signal Description
QA1CLREL Closing of QA1 is allowed
QA1CLITL Closing of QA1 is forbidden
QB61REL Switching of QB61 is allowed
QB61ITL Switching of QB61 is forbidden
QB62REL Switching of QB62 is allowed
QB62ITL Switching of QB62 is forbidden
QC1REL Switching of QC1 is allowed
QC1ITL Switching of QC1 is forbidden
QC2REL Switching of QC2 is allowed
QC2ITL Switching of QC2 is forbidden
Signal Description
481
Logic rotating switch for function selection
and LHMI presentation (GGIO)
Chapter 11
Control
4 Logic rotating switch for function selection
and LHMI presentation (GGIO)
4.1 Introduction
The Logic rotating switch for function selection and LHMI presentation (LSR, or the selector
switch function block, as it is also known) is used within the CAP tool in order to get a selector
switch functionality similar with the one provided by a hardware selector switch. Hardware se-
lector switches are used extensively by utilities, in order to have different functions operating on
pre-set values. Hardware switches are however sources for maintenance issues, lower system re-
liability and extended purchase portfolio. The virtual selector switches eliminate all these prob-
lems.
4.2 Principle of operation
The selector switch can be operated either from the control menu on the Local HMI or with logic
prepared in the configuration.
The LSR has two operating inputs UP and DOWN. When a signal is received on the UP input,
the block will activate the output next to the present activated output, in ascending order (if the
present activated output is 3 for example and one operates the UP input, then the output 4 will
be activated). When a signal is received on the DOWN input, the block will activate the output
next to the present activated output, in descending order (if the present activated output is 3
for example and one operates the DOWN input, then the output 2 will be activated). Depending
on the output settings the output signals can be steady or pulsed. In case of steady signals, in case
of UP or DOWN operation, the previously active output will be deactivated. Also, depending on
the settings one can have a time delay between the UP or DOWN activation signal positive front
and the output activation.
Repeated down or up when end position has been reached will give repeated pulses on the se-
lected step. This can e.g. be used to have multiple activations on two position switches.
One can block the function operation, by activating the BLOCK input. In this case, the present
position will be kept and further operation will be blocked. The operator place (local or remote)
is specified through the PSTO input.
The LSR function block has also an integer value output, that generates the actual position num-
ber. The positions names are fully settable by the user.
482
Logic rotating switch for function selection
and LHMI presentation (GGIO)
Chapter 11
Control
4.3 Function block
Figure 220: LRS1 function block, example for LRS1-LRS6
4.4 Input and output signals
Table 222: Input signals for the SSGGIO (LRS1-) function block
SSGGIO
LRS1-
BLOCK
PSTO
UP
DOWN
SWPOS01
SWPOS02
SWPOS03
SWPOS04
SWPOS05
SWPOS06
SWPOS07
SWPOS08
SWPOS09
SWPOS10
SWPOS11
SWPOS12
SWPOS13
SWPOS14
SWPOS15
SWPOS16
SWPOS17
SWPOS18
SWPOS19
SWPOS20
SWPOS21
SWPOS22
SWPOS23
SWPOS24
SWPOS25
SWPOS26
SWPOS27
SWPOS28
SWPOS29
SWPOS30
SWPOS31
SWPOS32
SWPOSN
en05000658.vsd
NAME01
NAME02
NAME03
NAME04
NAME05
NAME06
NAME07
NAME08
NAME09
NAME10
NAME11
NAME12
NAME13
NAME14
NAME15
NAME16
NAME17
NAME18
NAME19
NAME20
NAME21
NAME22
NAME23
NAME24
NAME25
NAME26
NAME27
NAME28
NAME29
NAME30
NAME31
NAME32
Signal Description
BLOCK Block of function.
PSTO Operator place selection.
UP Binary "UP" command
DOWN Binary "DOWN" command
483
Logic rotating switch for function selection
and LHMI presentation (GGIO)
Chapter 11
Control
Table 223: Output signals for the SSGGIO (LRS1-) function block
Signal Description
SWPOS01 Selector switch position 1
SWPOS02 Selector switch position 2
SWPOS03 Selector switch position 3
SWPOS04 Selector switch position 4
SWPOS05 Selector switch position 5
SWPOS06 Selector switch position 6
SWPOS07 Selector switch position 7
SWPOS08 Selector switch position 8
SWPOS09 Selector switch position 9
SWPOS10 Selector switch position 10
SWPOS11 Selector switch position 11
SWPOS12 Selector switch position 12
SWPOS13 Selector switch position 13
SWPOS14 Selector switch position 14
SWPOS15 Selector switch position 15
SWPOS16 Selector switch position 16
SWPOS17 Selector switch position 17
SWPOS18 Selector switch position 18
SWPOS19 Selector switch position 19
SWPOS20 Selector switch position 20
SWPOS21 Selector switch position 21
SWPOS22 Selector switch position 22
SWPOS23 Selector switch position 23
SWPOS24 Selector switch position 24
SWPOS25 Selector switch position 25
SWPOS26 Selector switch position 26
SWPOS27 Selector switch position 27
SWPOS28 Selector switch position 28
SWPOS29 Selector switch position 29
SWPOS30 Selector switch position 30
SWPOS31 Selector switch position 31
SWPOS32 Selector switch position 32
SWPOSN Switch position (integer).
NAME01 User define string for position 1
NAME02 User define string for position 2
NAME03 User define string for position 3
NAME04 User define string for position 4
NAME05 User define string for position 5
484
Logic rotating switch for function selection
and LHMI presentation (GGIO)
Chapter 11
Control
4.5 Setting parameters
Table 224: General settings for the SSGGIO (LRS1-) function
NAME06 User define string for position 6
NAME07 User define string for position 7
NAME08 User define string for position 8
NAME09 User define string for position 9
NAME10 User define string for position 10
NAME11 User define string for position 11
NAME12 User define string for position 12
NAME13 User define string for position 13
NAME14 User define string for position 14
NAME15 User define string for position 15
NAME16 User define string for position 16
NAME17 User define string for position 17
NAME18 User define string for position 18
NAME19 User define string for position 19
NAME20 User define string for position 20
NAME21 User define string for position 21
NAME22 User define string for position 22
NAME23 User define string for position 23
NAME24 User define string for position 24
NAME25 User define string for position 25
NAME26 User define string for position 26
NAME27 User define string for position 27
NAME28 User define string for position 28
NAME29 User define string for position 29
NAME30 User define string for position 30
NAME31 User define string for position 31
NAME32 User define string for position 32
Signal Description
Parameter Range Step Default Unit Description
StopAtExtremes Disabled
Enabled
- Disabled - Stop when min or max
position is reached
485
Logic rotating switch for function selection
and LHMI presentation (GGIO)
Chapter 11
Control
Table 225: Parameter group settings for the SSGGIO (LRS1-) function
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off/On
NrPos 2 - 32 1 32 - Number of positions in
the switch
OutType Pulsed
Steady
- Steady - Output type, steady (=1)
or pulse (=0)
tPulse 0.000 - 60.000 0.001 0.200 s Operate pulse duration,
in [s]
tDelay 0.000 - 60000.000 0.010 0.000 s Time delay on the output,
in [s]
486
Logic rotating switch for function selection
and LHMI presentation (GGIO)
Chapter 11
Control
487
About this chapter Chapter 12
Logic
Chapter 12 Logic
About this chapter
This chapter describes primarily tripping and trip logic functions. The way the functions work,
their setting parameters, function blocks, input and output signals and technical data are included
for each function.
488
Tripping logic (PTRC, 94) Chapter 12
Logic
1 Tripping logic (PTRC, 94)
1.1 Introduction
A function block for protection tripping is provided for each circuit breaker involved in the trip-
ping of the fault. It provides the pulse prolongation to ensure a trip pulse of sufficient length, as
well as all functionality necessary for correct co-operation with autoreclosing functions.
The trip function block includes functionality for evolving faults and breaker lock-out.
1.2 Principle of operation
The duration of a trip output signal from the TRPx function is settable (tTripMin). The pulse
length should be long enough to secure the breaker opening.
For three-pole tripping, TRPx function has a single input (TRIN) through which all trip output
signals from the protection functions within the IED, or from external protection functions via
one or more of the IEDs binary inputs, are routed. It has a single trip output (TRIP) for connec-
tion to one or more of the IEDs binary outputs, as well as to other functions within the IED re-
quiring this signal.
Figure 221: Simplified logic diagram for three phase trip
The TRPx function for single- and two-pole tripping has additional phase segregated inputs for
this, as well as inputs for faulted phase selection. The latter inputs enable single- and two-pole
tripping for those functions which do not have their own phase selection capability, and there-
Function block name: TRPx- IEC 60617 graphical symbol:
ANSI number: 94
IEC 61850 logical node name:
SMPPTRC
I->O
AND
BLOCK
TRIN
Operation Mode =On
OR
t
tTripMin TRIP
en05000789.vsd
Program =3Ph
489
Tripping logic (PTRC, 94) Chapter 12
Logic
fore which have just a single trip output and not phase segregated trip outputs for routing through
the phase segregated trip inputs of the expanded TRPx function. Examples of such protection
functions are the residual overcurrent protections. The expanded TRPx function has two inputs
for these functions, one for impedance tripping (e.g. carrier-aided tripping commands from the
scheme communication logic), and one for earth fault tripping (e.g. tripping output from a resid-
ual overcurrent protection). Additional logic secures a three-pole final trip command for these
protection functions in the absence of the required phase selection signals.
The expanded TRPx function has three trip outputs TRL1, TRL2, TRL3 (besides the trip output
TRIP), one per phase, for connection to one or more of the IEDs binary outputs, as well as to
other functions within the IED requiring these signals. There are also separate output signals in-
dicating single pole, two pole or three pole trip. These signals are important for cooperation with
the auto-reclosing function.
The expanded TRPx function is equipped with logic which secures correct operation for evolv-
ing faults as well as for reclosing on to persistent faults. A special input is also provided which
disables single- and two-pole tripping, forcing all tripping to be three-pole.
In multi-breaker arrangements, one TRPx function block is used for each breaker. This can be
the case if single pole tripping and auto-reclosing is used.
The breaker close lockout function can be activated from an external trip signal from another
protection function via input (SETLKOUT) or internally at a three pole trip, if desired.
It is possible to lockout seal in the tripping output signals or use blocking of closing only the
choice is by setting TripLockout.
1.2.1 Logic diagram
Figure 222: Three-phase front logic simplified logic diagram
en05000517.vsd
TRINL1
TRINL2
TRINL3
1PTRZ
1PTREF
TRIN
OR
OR
OR
Program =3ph
AND
RSTTRIP - cont.
490
Tripping logic (PTRC, 94) Chapter 12
Logic
Figure 223: Phase segregated front logic
491
Tripping logic (PTRC, 94) Chapter 12
Logic
Figure 224: Additional logic for the 1ph/3ph operating mode
492
Tripping logic (PTRC, 94) Chapter 12
Logic
Figure 225: Additional logic for the 1ph/2ph/3ph operating mode
493
Tripping logic (PTRC, 94) Chapter 12
Logic
Figure 226: Final tripping circuits
1.3 Function block
Figure 227: TRP function block
SMPPTRC
TRP1-
BLOCK
BLKLKOUT
TRIN
TRINL1
TRINL2
TRINL3
PSL1
PSL2
PSL3
1PTRZ
1PTREF
P3PTR
SETLKOUT
RSTLKOUT
TRIP
TRL1
TRL2
TRL3
TR1P
TR2P
TR3P
CLLKOUT
en05000707.vsd
494
Tripping logic (PTRC, 94) Chapter 12
Logic
1.4 Input and output signals
Table 226: Input signals for the SMPPTRC_94 (TRP1-) function block
Table 227: Output signals for the SMPPTRC_94 (TRP1-) function block
Signal Description
BLOCK Block of function
BLKLKOUT Blocks circuit breaker lockout output (CLLKOUT)
TRIN Trip all phases
TRINL1 Trip phase 1
TRINL2 Trip phase 2
TRINL3 Trip phase 3
PSL1 Functional input for phase selection in phase L1
PSL2 Functional input for phase selection in phase L2
PSL3 Functional input for phase selection in phase L3
1PTRZ Zone Trip with a separate phase selection
1PTREF Single phase DEF Trip for separate phase selection
P3PTR Prepare all tripping to be three-phase
SETLKOUT Input for setting the circuit breaker lockout function
RSTLKOUT Input for resetting the circuit breaker lockout function
Signal Description
TRIP General trip output signal
TRL1 Trip signal from phase L1
TRL2 Trip signal from phase L2
TRL3 Trip signal from phase L3
TR1P Tripping single-pole
TR2P Tripping two-pole
TR3P Tripping three-pole
CLLKOUT Circuit breaker lockout output (set until reset)
495
Tripping logic (PTRC, 94) Chapter 12
Logic
1.5 Setting parameters
Table 228: Parameter group settings for the SMPPTRC_94 (TRP1-) function
1.6 Technical data
Table 229: Tripping logic (PTRC, 94)
Parameter Range Step Default Unit Description
Operation Off
On
- On - Operation Off / On
Program 3 phase
1ph/3ph
1ph/2ph/3ph
- 1ph/3ph - Three ph; single or three
ph; single, two or three
ph trip
TripLockout Off
On
- Off - On: activate output
(CLLKOUT) and trip
latch, Off: only outp
AutoLock Off
On
- Off - On: lockout from input
(SETLKOUT) and trip,
Off: only inp
tTripMin 0.000 - 60.000 0.001 0.150 s Minimum duration of trip
output signal
Function Range or value Accuracy
Trip action 3-ph, 1/3-ph, 1/2/3-ph -
Minimum trip pulse length (0.000-60.000) s 0.5% 10 ms
Timers (0.000-60.000) s 0.5% 10 ms
496
Trip matrix logic (GGIO, 94X) Chapter 12
Logic
2 Trip matrix logic (GGIO, 94X)
2.1 Introduction
Twelve trip matrix logic blocks are included in the IED. The function blocks are used in the con-
figuration of the IED to route trip signals and/or other logical output signals to the different out-
put relays.
The matrix and the physical outputs will be seen in the PCM600 engineering tool and this allows
the user to adapt the signals to the physical tripping outputs according to the specific application
needs.
2.2 Principle of operation
Tripping matrix logic block is provided with 32 input signals and 3 output signals. The function
block incorporates internal logic OR gates in order to provide the necessary grouping of con-
nected input signals (e.g. for tripping and alarming purposes) to the three output signals from the
function block.
Internal built-in OR logic is made in accordance with the following three rules:
1. when any one of first 16 inputs signals (i.e. INPUT1 to INPUT16) has logical val-
ue 1 (i.e. TRUE) the first output signal (i.e. OUTPUT1) will get logical value 1
(i.e. TRUE). Additional time delays can be introduced for OUTPUT1 via setting
parameters "PulseTime1", "OnDelayTime1" & "OffDelayTime1".
2. when any one of second 16 inputs signals (i.e. INPUT17 to INPUT32) has logical
value 1 (i.e. TRUE) the second output signal (i.e. OUTPUT2) will get logical val-
ue 1 (i.e. TRUE). Additional time delays can be introduced for OUTPUT2 via
setting parameters "PulseTime2", "OnDelayTime2" & "OffDelayTime2"
3. when any one of all 32 input signals (i.e. INPUT1 to INPUT32) has logical value
1 (i.e. TRUE) the third output signal (i.e. OUTPUT3) will get logical value 1 (i.e.
TRUE). Additional time delays can be introduced for OUTPUT3 via setting pa-
rameters "PulseTime3", "OnDelayTime3" & "OffDelayTime3".
Detailed logical diagram is shown in see figure 228
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Trip matrix logic (GGIO, 94X) Chapter 12
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Figure 228: Tripping Matrix Internal Logic.
Output signals from this function block are typically connected to other logic blocks or directly
to output contacts from the IED. When used for direct tripping of the circuit breaker(s) the pulse
time delay on that output signal shall be set to approximately 0,150s in order to obtain satisfac-
tory minimum duration of the trip pulse to the circuit breaker trip coils.
Twelve such function blocks are available in the IED.
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Trip matrix logic (GGIO, 94X) Chapter 12
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2.3 Function block
Figure 229: TR function block
2.4 Input and output signals
Table 230: Input signals for the TRMGGIO (TR01-) function block
TRMGGIO
TR01-
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
INPUT17
INPUT18
INPUT19
INPUT20
INPUT21
INPUT22
INPUT23
INPUT24
INPUT25
INPUT26
INPUT27
INPUT28
INPUT29
INPUT30
INPUT31
INPUT32
OUTPUT1
OUTPUT2
OUTPUT3
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Signal Description
INPUT1 Binary input 1
INPUT2 Binary input 2
INPUT3 Binary input 3
INPUT4 Binary input 4
INPUT5 Binary input 5
INPUT6 Binary input 6
INPUT7 Binary input 7
INPUT8 Binary input 8
INPUT9 Binary input 9
INPUT10 Binary input 10
INPUT11 Binary input 11
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Trip matrix logic (GGIO, 94X) Chapter 12
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Table 231: Output signals for the TRMGGIO (TR01-) function block
INPUT12 Binary input 12
INPUT13 Binary input 13
INPUT14 Binary input 14
INPUT15 Binary input 15
INPUT16 Binary input 16
INPUT17 Binary input 17
INPUT18 Binary input 18
INPUT19 Binary input 19
INPUT20 Binary input 20
INPUT21 Binary input 21
INPUT22 Binary input 22
INPUT23 Binary input 23
INPUT24 Binary input 24
INPUT25 Binary input 25
INPUT26 Binary input 26
INPUT27 Binary input 27
INPUT28 Binary input 28
INPUT29 Binary input 29
INPUT30 Binary input 30
INPUT31 Binary input 31
INPUT32 Binary input 32
Signal Description
OUTPUT1 Binary output 1
OUTPUT2 Binary output 2
OUTPUT3 Binary output 3
Signal Description
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Trip matrix logic (GGIO, 94X) Chapter 12
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2.5 Setting parameters
Table 232: Parameter group settings for the TRMGGIO (TR01-) function
Parameter Range Step Default Unit Description
Operation Off
On
- On - Operation Off / On
PulseTime1 0.000 - 60.000 0.001 0.000 s Output pulse time for out-
put 1
OnDelayTime1 0.000 - 60.000 0.001 0.000 s Output on delay time for
output 1
OffDelayTime1 0.000 - 60.000 0.001 0.000 s Output off delay time for
output 1
PulseTime2 0.000 - 60.000 0.001 0.000 s Output pulse time for out-
put 2
OnDelayTime2 0.000 - 60.000 0.001 0.000 s Output on delay time for
output 2
OffDelayTime2 0.000 - 60.000 0.001 0.000 s Output off delay time for
output 2
PulseTime3 0.000 - 60.000 0.001 0.000 s Output pulse time for out-
put 3
OnDelayTime3 0.000 - 60.000 0.001 0.000 s Output on delay time for
output 3
OffDelayTime3 0.000 - 60.000 0.001 0.000 s Output off delay time for
output 3
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Configurable logic blocks (LLD) Chapter 12
Logic
3 Configurable logic blocks (LLD)
3.1 Introduction
A high number of logic blocks and timers are available for user to adapt the configuration to the
specific application needs.
3.2 Inverter function block (INV)
Figure 230: INV function block
Table 233: Input signals for the INV (I001-) function block
Table 234: Output signals for the INV (I001-) function block
3.3 OR function block (OR)
The OR function is used to form general combinatory expressions with boolean variables. The
OR function block has six inputs and two outputs. One of the outputs is inverted.
Figure 231: OR function block
Signal Description
INPUT Input
Signal Description
OUT Output
INV
I001-
INPUT OUT
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OR
O001-
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
OUT
NOUT
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Configurable logic blocks (LLD) Chapter 12
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Table 235: Input signals for the OR (O001-) function block
Table 236: Output signals for the OR (O001-) function block
3.4 AND function block (AND)
The AND function is used to form general combinatory expressions with boolean variables.The
AND function block has four inputs and two outputs. One of the inputs and one of the outputs
are inverted.
Figure 232: AND function block
Table 237: Input signals for the AND (A001-) function block
Table 238: Output signals for the AND (A001-) function block
Signal Description
INPUT1 Input 1 to OR gate
INPUT2 Input 2 to OR gate
INPUT3 Input 3 to OR gate
INPUT4 Input 4 to OR gate
INPUT5 Input 5 to OR gate
INPUT6 Input 6 to OR gate
Signal Description
OUT Output from OR gate
NOUT Inverted output from OR gate
Signal Description
INPUT1 Input 1
INPUT2 Input 2
INPUT3 Input 3
INPUT4N Input 4 inverted
Signal Description
OUT Output
NOUT Output inverted
AND
A001-
INPUT1
INPUT2
INPUT3
INPUT4N
OUT
NOUT
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Configurable logic blocks (LLD) Chapter 12
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3.5 Timer function block (Timer)
The function block TIMER has drop-out and pick-up delayed outputs related to the input signal.
The timer has a settable time delay (parameter T).
Figure 233: TM function block
Table 239: Input signals for the Timer (TM01-) function block
Table 240: Output signals for the Timer (TM01-) function block
Table 241: General settings for the Timer (TM01-) function
3.6 Pulse timer function block (PULSE)
The pulse function can be used, for example, for pulse extensions or limiting of operation of out-
puts. The pulse timer TP has a settable length.
Figure 234: PULSE function block
Table 242: Input signals for the Pulse (TP01-) function block
Signal Description
INPUT Input to timer
Signal Description
ON Output from timer , pick-up delayed
OFF Output from timer, drop-out delayed
Parameter Range Step Default Unit Description
T 0.000 - 90000.000 0.001 0.000 s Time delay of function
Timer
TM01-
INPUT
T
ON
OFF
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Signal Description
INPUT Input to pulse timer
Pulse
TP01-
INPUT OUT
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Configurable logic blocks (LLD) Chapter 12
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Table 243: Output signals for the Pulse (TP01-) function block
Table 244: General settings for the Pulse (TP01-) function
3.7 Exclusive OR function block (XOR)
The exclusive OR function XOR is used to generate combinatory expressions with boolean vari-
ables. The function block XOR has two inputs and two outputs. One of the outputs is inverted.
The output signal is 1 if the input signals are different and 0 if they are equal.
Figure 235: XOR function block
Table 245: Input signals for the XOR (XO01-) function block
Table 246: Output signals for the XOR (XO01-) function block
3.8 Set-reset with memory function block (SRM)
The Set-Reset function SRM is a flip-flop with memory that can set or reset an output from two
inputs respectively. Each SRM function block has two outputs, where one is inverted. The mem-
ory setting controls if the flip-flop after a power interruption will return the state it had before or
if it will be reset.
Signal Description
OUT Output from pulse timer
Parameter Range Step Default Unit Description
T 0.000 - 90000.000 0.001 0.010 s Time delay of function
Signal Description
INPUT1 Input 1 to XOR gate
INPUT2 Input 2 to XOR gate
Signal Description
OUT Output from XOR gate
NOUT Inverted output from XOR gate
XOR
XO01-
INPUT1
INPUT2
OUT
NOUT
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Configurable logic blocks (LLD) Chapter 12
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Figure 236: SM function block
Table 247: Input signals for the SRM (SM01-) function block
Table 248: Output signals for the SRM (SM01-) function block
Table 249: Parameter group settings for the SRM (SM01-) function
3.9 Controllable gate function block (GT)
The GT function block is used for controlling if a signal should be able to pass from the input to
the output or not depending on a setting.
Figure 237: GT function block
Table 250: Input signals for the GT (GT01-) function block
Signal Description
SET Set input
RESET Reset input
Signal Description
OUT Output
NOUT Output inverted
Parameter Range Step Default Unit Description
Memory Off
On
- Off - Operating mode of the
memory function
SRM
SM01-
SET
RESET
OUT
NOUT
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Signal Description
INPUT Input to gate
GT
GT01-
INPUT OUT
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Table 251: Output signals for the GT (GT01-) function block
Table 252: Parameter group settings for the GT (GT01-) function
3.10 Settable timer function block (TS)
The function block TS timer has outputs for delayed input signal at drop-out and at pick-up. The
timer has a settable time delay. It also has an Operation setting On, Off that controls the opera-
tion of the timer.
Figure 238: TS function block
Table 253: Input signals for the TimerSet (TS01-) function block
Table 254: Output signals for the TimerSet (TS01-) function block
Table 255: Parameter group settings for the TimerSet (TS01-) function
Signal Description
OUT Output from gate
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off/On
Signal Description
INPUT Input to timer
Signal Description
ON Output from timer, pick-up delayed
OFF Output from timer, drop-out delayed
Parameter Range Step Default Unit Description
Operation Off
On
- Off - Operation Off/On
t 0.000 - 90000.000 0.001 0.000 s Delay for settable timer n
TimerSet
TS01-
INPUT ON
OFF
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Configurable logic blocks (LLD) Chapter 12
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3.11 Technical data
Table 256: Configurable logic blocks
Logic block Quantity with update rate Range or value Accuracy
fast medium normal
LogicAND 60 60 160 - -
LogicOR 60 60 160 - -
LogicXOR 10 10 20 - -
LogicInverter 30 30 80 - -
LogicSRMemory 10 10 20 - -
LogicGate 10 10 20 - -
LogicTimer 10 10 20 (0.00090000.00
0) s
0.5% 10 ms
LogicPulseTimer 10 10 20 (0.00090000.00
0) s
0.5% 10 ms
LogicTimerSet 10 10 20 (0.00090000.00
0) s
0.5% 10 ms
LogicLoopDelay 10 10 20 (0.00090000.00
0) s
0.5% 10 ms
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Fixed signal function block (FIXD) Chapter 12
Logic
4 Fixed signal function block (FIXD)
4.1 Introduction
The fixed signals function block generates a number of pre-set (fixed) signals that can be used
in the configuration of a terminal, either for forcing the unused inputs in the other function
blocks to a certain level/value, or for creating a certain logic.
4.2 Principle of operation
There are eight outputs from the FIXD function block: OFF is a boolean signal, fixed to OFF
(boolean 0) value; ON is a boolean signal, fixed to ON (boolean 1) value; INTZERO is an inte-
ger number, fixed to integer value 0; INTONE is an integer number, fixed to integer value 1;
REALZERO is a floating point real number, fixed to 0.0 value; STRNULL is a string, fixed to
an empty string (null) value; ZEROSMPL is a 32-bit integer, fixed to 0 value; GRP_OFF is a
32-bit integer, fixed to 0 value; The function does not allow any settings and therefore its not
present in PCM600. For examples on how to use each type of output in the configuration, please
read the Application Manual.
4.3 Function block
Figure 239: FIXD function block
4.4 Input and output signals
Table 257: Output signals for the FixedSignals (FIXD-) function block
FixedSignals
FIXD-
OFF
ON
INTZERO
INTONE
REALZERO
STRNULL
ZEROSMPL
GRP_OFF
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Signal Description
OFF Boolean signal fixed off
ON Boolean signal fixed on
INTZERO Integer signal fixed zero
INTONE Integer signal fixed one
REALZERO Real signal fixed zero
STRNULL String signal with no characters
ZEROSMPL Channel id for zero sample
GRP_OFF Group signal fixed off
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Fixed signal function block (FIXD) Chapter 12
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4.5 Setting parameters
The function does not have any parameters available in Local HMI or Protection and Control
IED Manager (PCM600)
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Fixed signal function block (FIXD) Chapter 12
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About this chapter Chapter 13
Monitoring
Chapter 13 Monitoring
About this chapter
This chapter describes the functions that handle measurements, events and disturbances. The
way the functions work, their setting parameters, function blocks, input and output signals, and
technical data are included for each function.
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Measurements (MMXU, MSQI) Chapter 13
Monitoring
1 Measurements (MMXU, MSQI)
1.1 Introduction
Measurement functions is used for power system measurement, supervision and reporting to the
local HMI, monitoring tool within PCM600 or to station level (i.e. IEC61850). The possibility
to continuously monitor measured values of active power, reactive power, currents, voltages,
frequency, power factor etc. is vital for efficient production, transmission and distribution of
electrical energy. It provides to the system operator fast and easy overview of the present status
Function block name: SVRx- IEC 60617 graphical symbol:
ANSI number:
IEC 61850 logical node name:
CVMMXU
Function block name: CPxx IEC 60617 graphical symbol:
ANSI number:
IEC 61850 logical node name:
CMMXU
Function block name: VPx- IEC 60617 graphical symbol:
ANSI number:
IEC 61850 logical node name:
VMMXU
Function block name: CSQx IEC 60617 graphical symbol:
ANSI number:
IEC 61850 logical node name:
CMSQI
Function block name: VSQx IEC 60617 graphical symbol:
ANSI number:
IEC 61850 logical node name:
VMSQI
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Measurements (MMXU, MSQI) Chapter 13
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of the power system. Additionally it can be used during testing and commissioning of protection
and control IEDs in order to verify proper operation and connection of instrument transformers
(i.e. CTs & VTs). During normal service by periodic comparison of the measured value from the
IED with other independent meters the proper operation of the IED analog measurement chain
can be verified. Finally it can be used to verify proper direction orientation for distance or direc-
tional overcurrent protection function.
All measured values can be supervised with four settable limits, i.e. low-low limit, low limit,
high limit and high-high limit. A zero clamping reduction is also supported, i.e the measured val-
ue below a settable limit is forced to zero which reduces the impact of noise in the inputs.
Dead-band supervision can be used to report measured signal value to station level when change
in measured value is above set threshold limit or time integral of all changes since the last time
value updating exceeds the threshold limit. Measure value can also be based on periodic report-
ing.
The measuring function, SVR, provides the following power system quantities:
P, Q and S: three phase active, reactive and apparent power
PF: power factor
U: phase-to-phase voltage magnitude
I: phase current magnitude
F: power system frequency
The measuring functions CP and VP provides physical quantities:
I: phase currents (magnitude and angle)
U: phase-phase voltages (magnitude and angle)
It is possible to calibrate the measuring function above to get class 0.5 presentation. This is ac-
complished by angle and amplitude compensation at 5, 30 and 100% of rated current and volt-
age.
The measuring functions CSQ and VSQ provides sequential quantities:
I: sequence currents (positive, zero, negative sequence, magnitude and angle)
U: sequence voltages (positive, zero and negative sequence, magnitude and an-
gle).
The SVR function calculates three-phase power quantities by using fundamental frequency pha-
sors (i.e. DFT values) of the measured current and voltage signals. The measured power quan-
tities are available either as instantaneously calculated quantities or averaged values over a
period of time (i.e. low pass filtered) depending on the selected settings.
The IED can be provided with up to 3SVR-, 10CP-, 5VP-, 3CSQ- and 3VSQ-measurement
functions.
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Measurements (MMXU, MSQI) Chapter 13
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1.2 Principle of operation
1.2.1 Measurement supervision
The protection, control, and monitoring IEDs have functionality to measure and further process
information for currents and voltages obtained from the pre-processing blocks. The number of
processed alternate measuring quantities depends on the type of IED and built-in options.
The information on measured quantities is available for the user at different locations:
Locally by means of the local HMI
Remotely using the monitoring tool within PCM600 or over the station bus (IEC
61850-8)
Internally by connecting the analog output signals to the Disturbance Report
function
Phase angle reference
All phase angles are presented in relation to a defined reference channel. The parameter
PhaseAngleRef defines the reference, see section 1.
Zero point clamping
Measured value below zero point clamping limit is forced to zero. This allows the noise in the
input signal to be ignored. The zero point clamping limit is a general setting (XZeroDb where X
equals S, P, Q, PF, U, I, F, IL1-3, UL12-31, I1, I2, 3I0, U1, U2 or 3U0).). Observe that this mea-
surement supervision zero point clamping might be overridden by the zero point clamping used
for the service values within SVR.
Continuous monitoring of the measured quantity
Users can continuously monitor the measured quantity available in each function block by
means of four built-in operating thresholds, see figure240. The monitoring has two different
modes of operating:
Overfunction, when the measured current exceeds the High limit (XHiLim) or
High-high limit (XHiHiLim) pre-set values
Underfunction, when the measured current decreases under the Low limit
(XLowLim) or Low-low limit (XLowLowLim) pre-set values.
X_RANGE is illustrated in figure240.
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Measurements (MMXU, MSQI) Chapter 13
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Figure 240: Presentation of operating limits
Each analog output has one corresponding supervision level output (X_RANGE). The output
signal is an integer in the interval 0-4 (0: Normal, 1: High limit exceeded, 3: High-high limit ex-
ceeded, 2: below Low limit and 4: below Low-low limit). The output may be connected to a
measurement expander block (XP) to get measurement supervision as binary signals.
The logical value of the functional output signals changes according to figure240.
The user can set the hysteresis (XLimHyst), which determines the difference between the oper-
ating and reset value at each operating point, in wide range for each measuring channel separate-
ly. The hysteresis is common for all operating values within one channel.
Actual value of the measured quantity
The actual value of the measured quantity is available locally and remotely. The measurement
is continuous for each measured separately, but the reporting of the value to the higher levels
depends on the selected reporting mode. The following basic reporting modes are available:
Cyclic reporting (Cyclic)
Amplitude dead-band supervision (Dead band)
Integral dead-band supervision (Int deadband)
Cyclic reporting
The cyclic reporting of measured value is performed according to chosen setting (XRepTyp).
The measuring channel reports the value independent of amplitude or integral dead-band report-
ing.
en05000657.vsd
X_RANGE=1
X_RANGE =3
X_RANGE=0
Hysteresis
High-high limit
High limit
Low limit
Low-low limit
X_RANGE=2
X_RANGE=4
Y
t
X_RANGE=0
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Measurements (MMXU, MSQI) Chapter 13
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Figure 241: Periodic reporting
Amplitude dead-band supervision
If a measuring value is changed, compared to the last reported value, and the change is larger
than the Y predefined limits that are set by user (XZeroDb), then the measuring channel re-
ports the new value to a higher level, if this is detected by a new measured value. This limits the
information flow to a minimum necessary. Figure242 shows an example with the amplitude
dead-band supervision. The picture is simplified: the process is not continuous but the values are
evaluated with a time interval of one execution cycle from each other.
en05000500.vsd
V
a
l
u
e

1
Y
t
V
a
l
u
e

2
V
a
l
u
e

3
V
a
l
u
e

4
Value Reported
(1st)
Value Reported
V
a
l
u
e

5
Value Reported
Y1
Y2
Y5
Value Reported Value Reported
Y3
Y4
(*)Set value for t: XDbRepInt
t (*) t (*) t (*) t (*)
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Measurements (MMXU, MSQI) Chapter 13
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Figure 242: Amplitude dead-band supervision reporting
After the new value is reported, the Y limits for dead-band are automatically set around it.
The new value is reported only if the measured quantity changes more than defined by the Y
set limits.
Integral dead-band reporting
The measured value is reported if the time integral of all changes exceeds the pre-set limit
(XZeroDb), figure243, where an example of reporting with integral dead-band supervision is
shown. The picture is simplified: the process is not continuous but the values are evaluated with
a time interval of one execution cycle from each other.
The last value reported, Y1 in figure243 serves as a basic value for further measurement. A dif-
ference is calculated between the last reported and the newly measured value and is multiplied
by the time increment (discrete integral). The absolute values of these integral values are added
until the pre-set value is exceeded. This occurs with the value Y2 that is reported and set as a
new base for the following measurements (as well as for the values Y3, Y4 and Y5).
The integral dead-band supervision is particularly suitable for monitoring signals with small
variations that can last for relatively long periods.
99000529.vsd
Y
t
Value Reported
(1st)
Value Reported
Value Reported
Y1
Y2
Y3
Y
Y
Y
Y
Y
Y
Value Reported
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Measurements (MMXU, MSQI) Chapter 13
Monitoring
Figure 243: Reporting with integral dead-band supervision
1.2.2 Service values (MMXU, SVR)
Mode of operation
The measurement function must be connected to three-phase current and three-phase voltage in-
put in the configuration tool (group signals), but it is capable to measure and calculate above
mentioned quantities in nine different ways depending on the available VT inputs connected to
the IED. The end user can freely select by a parameter setting, which one of the nine available
measuring modes shall be used within the function. Available options are summarized in the fol-
lowing table:
99000530.vsd
Y
t