EET480W

Retrofit Voltage Regulator
for the 2A042 electrical generator

Luke Smith
lsmit034@odu.edu
EET480W
December 10, 2007
Abstract
A common 5KW military generator, aailable on t!e sur"lus
mar#et, uses a 1$%0s circuit design to regulate its out"ut oltage.
&!is e'isting design uses a sim"le transistor circuit to ac!iee
"ro"ortional, integral and di((erential control. &!e design is
marginally ade)uate and is a common "oint o( (ailure in t!e
generator system. *sing a micro"rocessor+based design, a retro(it
regulator module can be built to e'ceed t!e original design in bot!
(unction and (eatures.
1
Table of Contents
ntro!uction
,"erational -asics 3
"iscussion
Design .undamentals 4
/icro"rocessor 0election %
D1 2o3er 0u""ly 7
4/0 Detection 5
Analog to Digital 1onersion 10
26D 1ontrol in .irm3are 11
2W/ o( (ield Winding 15
4ecirculated 2o3er 2roblem 15
1ommunications 1$
2er(ormance tuning 22
Conclusion
1ommercial 7iability 25
0ummary 2%
4e(erences 27
A""endi' A 8 0c!ematics 25
A""endi' - 8 0ystem res"onses 31
A""endi' 1 8 .irm3are listing 42
A""endi' D 8 Data 0!eets %1
2
ntro!uction
#$erational basics
&!e generator system uses an 9aircra(t+style: gasoline engine made by ;ercules as its "rime moer. &!e
engine is a t3o+cylinder, air+cooled 42 cubic inc! design. &!e ignition system uses a magneto. 0"eed
regulation is accom"lis!ed mec!anically 3it! a centri(ugal goernor connected to t!e t!rottle. &!e system
is mec!anically tuned to maintain a constant 3%00 42/. &!is "articular engine model is "o"ular in ultra+
lig!t aircra(t designs because o( its lig!t 3eig!t and durability.
&!e A1 generator "ortion o( t!e system uses a 9brus!less: design. &!is is accom"lis!ed t!roug! t!e use
an alternator arrangement t!at uses a stationary 9e'citer: (ield 3inding and rotating armature on t!e main
rotor. &!e 3+"!ase armature 3inding o( t!is alternator is connected to a 3+"!ase bridge recti(ier mounted
directly on t!e rotor. &!e diodes t!at ma#e u" t!e recti(ier use t!e rotor structure as a !eat sin#. &!e D1
out"ut o( t!is alternator is used on t!e same rotor to drie t!e main (ield 3inding o( t!e A1 generator. &!e
3+"!ase A1 out"ut (orm t!e system is ta#en (rom t!e t!ree se"arate main stator 3indings. &!e system
3or#s li#e a sort o( am"li(ier 3it! a small D1 in"ut, (i'ed+s"eed mec!anical in"ut and large A1 out"ut.
&!e adantage o( t!is brus!less design is its reduced maintenance relatie to a brus! and sli"+rings design.
&!e D1 in"ut current t!roug! t!e e'citer (ield 3as obsered to be on t!e order o( 250mA 3!en t!e
system 3as running 3it! a nominal load. 6n t!e original design, t!e (ield current is su""lied by a linear,
transistor+based regulator circuit. &!is circuit deries bot! its "o3er and system out"ut re(erence (rom one
o( t!e t!ree system out"ut "!ases. ,biously, t!is arrangement assumes t!at t!e 3+"!ase load 3ill be
relatiely balanced since only one o( t!e t!ree out"ut "!ases is used as a oltage re(erence.
0ystem out"ut regulation is accom"lis!ed t!roug! a closed loo" bet3een t!e main out"ut and t!e e'citer
(ield in"ut 3it! t!e regulator circuit in t!e middle as a negatie gain element. 6n t!e original design, one o(
t!e t!ree "!ases is broug!t t!roug! a "o3er trans(ormer <3it! multi"le secondary 3indings= and a signal
trans(ormer into t!e circuit (or "o3er and re(erence res"ectiely. &!e A1 system is !ard+3ired in a 9>:
3
con(iguration. &!e center o( t!e 9>: is connected to t!e c!assis and t!e regulator?s ground. &!e "o3er
trans(ormer?s main secondary 3inding is connected to a (ull+3ae bridge recti(ier and (ilter ca"acitor to
(orm t!e D1 su""ly rail (or driing t!e e'citer (ield. &!e t3o ot!er secondary 3indings are eac! !al(+3ae
recti(ied <3it! res"ect to ground= and t!en ca"acitor+(iltered to (orm bi+"olar D1 rails (or t!e am"li(ier
section o( t!e circuit.
&!e circuit <see .igure D in A""endi' A= im"lements a control system 3it! (i'ed terms. &!e set"oint is
controlled by a ariable resistor on t!e (ront "anel. &!e original design su((ers (rom t!e (ollo3ing
s!ortcomings t!at can be oercome 3it! an u"dated design t!at incor"orates a micro"rocessor@
Ao user+accessible tuning mec!anism
;ig! 3aste+!eat to dissi"ate
2ea#+based detection met!od
4e)uires seeral olts su""ly be(ore startu"
"iscussion
Retrofit !esign fun!amentals
&o com"letely re"licate t!e (unction, and con(orm to t!e 6B, 3iring o( t!e original regulator, t!ere 3ere
seeral non+negotiables to base t!e retro(it design around.
A1 oltage su""ly and re(erence are "resented to t!e module as a 3ire "air com"rised o( one
out"ut "!ase and neutral.
&!e e'citer (ield !as an inductance o( about 3.4 ; and a D1 resistance i( o( 50 C. &!e 3inding is
isolated (rom t!e c!assis and bot! ends are "resented to t!e regulator module.
&!e set"oint is controlled on t!e (ront "anel by a ariable resistor t!at is "resented to t!e regulator
module as a "air o( 3ires.
.unctionally, t!e regulator acts as a negatie gain element on t!e di((erence bet3een set"oint and system
out"ut. 0"eci(ically, it recti(ies and (ilters t!e A1 3ae(orm and re+cycles t!e correct amount o( t!at
energy to t!e e'citer (ield as D1.
4
%igure &' %unctional (lock "iagram of com$lete generator s)stem
0eeral #ey "oints can be obsered in t!e system design. .irst, eeryt!ing inside t!e circle is "!ysically on
t!e rotor and com"letely (ree to s"in inside t!e t3o stators. D'citer in"ut and system out"ut are induced
t!roug! t!e air+ga"s. 0econd, t!ere is no battery or "ermanent magnet in t!e design.
6m"lementation o( t!e regulator bloc# 3as accom"lis!ed t!roug! !ard3are and (irm3are. -elo3 is a
(unctional diagram o( t!e circuit. &!e "arts inside t!e red outline are a combination o( (irm3are and built+in
"eri"!erals o( t!e micro"rocessor.
5
%igure 2' %unctional block !iagram of retrofit regulator
*icro$rocessor selection
0eeral o( t!e subsystems illustrated in t!e system bloc# diagram are aailable as built+in "eri"!erals on
modern, lo3+cost micro"rocessors. &!ese "eri"!eral (eatures 3ere signi(icant in t!e micro"rocessor
selection. &!ese 3ere@ Analog to digital conersion, *A4&, 2W/ out"ut and su((icient memory to
im"lement a !ig!+resolution <32+bit= mat! suite. &!e "rocessor c!osen 3as /icroc!i"?s 2611%.55. &!e
2611%.55 !as 10+bit AD1, 10+bit 2W/ module and a *A4& t!at can be easily inter(aced to an 40232
line drierBreceier. An im"ortant "rocessor (eature t!at 3as not obious until 3ell into t!e testing "rocess,
3as non+olatile data memory (or storing con(iguration ariables <2,6,D and set"oint= at run+time. &!is
"rocessor !as 25% bytes o( built+in DD24,/.
%
%igure +' (lock !iagram of the ,C&-%88 $rocessor
"C ,o.er su$$lies
2o3er (or t!e circuit is deried (rom t!e A1 in"ut to t!e regulator. &!ere are t!ree se"arate subsystems
t!at need to be "o3ered inde"endently. &!ey are@ Eogic <5 olts=, D'citer drie <F24 olts= and 40232
isolation <5 olts=. &!e 24 olt su""ly is siGed to delier current to t!e e'citer (ield. &!e (ield 3inding !as a
resistance o( 50 C, so a 93ide+o"en: e'citer drie scenario <at 24 olts= 3ould yield a current o( 450mA.
&!ere(ore, t!e selected trans(ormer 3as rated (or 24 olts out"ut at 12 7A (or %0 !ertG. &!e trans(ormer?s
secondary 3as (ull+3ae recti(ied and (iltered 3it! an electrolytic ca"acitor to ground. &!e ca"acitance
alue o( 3300u. 3as some3!at arbitrary. 1ircuit board s"ace and oltage rating 3ere t!e #ey (actors in
alue selection. &!e su""ly rail sat at about 33 olts D1 3!en t!ere 3as no load <e'citer drie= a""lied
7
3it! 120 olts on t!e A1 in"ut. &!e 5 olt su""ly (or logic is ta#en (rom t!is rail t!roug! an E/7505
linear oltage regulator in a &,+220 "ac#age. An issue t!at 3as not obious until e'"erimentation began
3as t!at t!e sa(e in"ut oltage to t!e E/7505 is limited to 3% olts. &!e generator system?s A1 out"ut !as
t!e "otential to go all t!e 3ay u" to about 150 olts A1 3!en t!e e'citer drie is at 100H and t!e system is
unloaded. *nder t!ese out"ut conditions, t!e D1 rail 3ould rise to 3ell beyond t!e E/7505?s ma'imum
in"ut oltage and it 3ould be burned out. &!e 3or#+around !ere 3as to "ut a 33 olt, 1 3att Gener diode as
a s!unt to ground
3
at t!e in"ut o( t!e E/7505 and a small series resistance to t!e D1 su""ly rail. &!e
resistance alue 3as c!osen to limit t!e current s!unted t!roug! t!e Gener to 30 mA 3!en t!e D1 rail is 40
olts. &!e 40232 isolation circuit also re)uired a 5 olt su""ly 3it! an isolated ground. &!is 3as
accom"lis!ed 3it! a se"arate trans(ormer connected to t!e system A1. &!e secondary 3as recti(ied,
(iltered and regulated 3it! an E/7505. 0ince t!is su""ly 3as only 5 olts, and 3as only used to drie
o"tical isolators and a /a'im /AI232 61, t!e trans(ormer only needed to delier a (raction o( 1 7A. &!e
5 olt re)uirement also allo3ed (or a "o3er trans(ormer 3!ose secondary oltage could be 3ell belo3 t!e
danger+Gone (or burning out t!e regulator. 1onse)uently, t!e Gener diode oltage limiting arrangement 3as
not re)uired on t!is regulator?s in"ut.
R*S !etection
6n t!e interest o( sim"licity, an o((+t!e+s!el( 4/0 to D1 conerter 61 3as incor"orated into t!e design.
&!e Einear tec!nology E&11$%5 3as c!osen (or its lo3 cost and ease o( use. &!e conerter uses a Delta+
0igma AD1 internally to mat!ematically arrie at t!e in"ut signal?s 4/0 e)uialent as a 9D1: out"ut
leel. &!e term D1 is used loosely !ere. -ecause 4/0 detection does actually inole an aeraging
o"eration oer some (inite time interal, a time+constant must be im"lemented 3it! an e'ternal ca"acitor
on t!e out"ut o( t!e conerter. &!e trade+o(( in t!e selection o( t!is ca"acitor?s alue is bet3een (ast
res"onse and ri""le in t!e D1 out"ut. &o arrie at an out"ut 3it! no ri""le 3ould re)uire a time+constant
many times t!at o( t!e line cycle "eriod. &!e "roblem 3it! t!is long time+constant is t!at t!e regulator
3ould be in!erently less sensitie to sudden c!anges in t!e system?s out"ut. 6n e((ect, t!e system+3ide
deriatie res"onse term 3ould be arti(icially !ig!. &!e solution to t!is 3as to s!orten t!e conerter?s time+
constant and "!ase+loc# t!e sam"ling o( t!e 4/0 conerter?s out"ut to t!e A1 out"ut o( t!e mac!ine. &!is
5
3ay, t!ere 3as actually signi(icant ri""le in t!e D1, but t!e same relatie "oint in t!e ri""le cycle 3ould be
sam"led eac! time. &!e sam"ling o( t!e 4/0 conerter is done once "er cycle o( t!e A1 out"ut <ideally
%0;G=.
0ince t!e AD1 sam"le is ta#en only one time "er line+cycle, t!ere are am"le cloc# cycles bet3een eac!
sam"le (or numeric "rocessing. &!is is 3!ere t!e adantage "roided by t!e 4/0 to D1 conerter is
realiGed. 6n order to "er(orm accurate 4/0 detection in (irm3are, t!e !ig! sam"le rate and associated
numeric "rocessing <including a s)uare+root= 3ould stretc! or e'ceed t!e resources o( a lo3+cost 5+bit
microcontroller. &!e Einear &ec!nology 4/0 conerter?s internal AD1 sam"le rate is 2/;G.
Dollar (or dollar, t!e better inestment in !ard3are 3as in t!e conerter instead o( a more adanced
micro"rocessor. &!e design o( t!e 4/0 conerter allo3s (or dual or single su""ly o"eration. &!e use o(
dual su""ly rails allo3s t!e in"ut signal to be symmetrical around 0 olts. W!ile dual su""ly o"eration
yields more "recise results, it adds more circuit com"le'ity t!an 3as deemed necessary (or t!e "ur"ose o(
t!is "roJect. W!en a single su""ly is used, t!e A1 in"ut signal must be o((set (rom 0 olts so t!at it stays
3it!in t!e bounds o( t!e su""ly oltage. &!e conerter !as di((erential in"uts. ,ne o( t!e in"ut met!ods
t!at Einear recommends (or single+su""ly o"eration is to ca"acitor+cou"le t!e A1 signal to one in"ut 3!ile
biasing t!e ot!er to !al(+su""ly.
%igure 4' Schematic !iagram of in$ut section
$
A small "o3er trans(ormer 3as used as "art o( t!e in"ut to t!e 4/0 conerter. 0ee &1 in t!e aboe
sc!ematic <(igure 4=. &!e secondary o( t!e trans(ormer 3as ground+re(erenced on one end 3!ile t!e ot!er
end (ed a resistor oltage diider. &!e trans(ormer turns ratio and resistor diider ratio 3ere c!osen
<t!roug! trial and error= as to net an A1 3ae(orm 3it! a "ea# alue 3it!in t!e s"eci(ied range o( t!e
4/0 conerter?s in"ut 3!ic! is 2 olts "ea#+to+"ea#. 0"eci(ically, t!e alues 3ere c!ose to yield 50H o(
t!at range 3it! a 120 olt 4/0 in"ut.
&!e line oltage detection trans(ormer <&1= is also used as t!e "!ase re(erence (or t!e A1 line. 0ince one
end o( t!e secondary is ground+re(erenced, a sim"le series resistor 3as connected (rom t!e 9!ig!: end o(
t!e secondary <t!e node labeled 91: in t!e aboe sc!ematic= to an in"ut "ort "in on t!e micro+controller.
&!e resistance alue 3as c!osen to limit t!e "ea# current t!roug! t!e in"ut?s internal clam"ing diodes to
about 1mA. &!e resulting 3ae(orm seen by t!e in"ut "in is a s)uare+3ae 3!ose "!ase relations!i" 3it!
t!e A1 line is (i'ed. &!e e'act "!ase angle o( t!e logic+leel 3ae(orm 3it! res"ect to t!e A1 line is
insigni(icant. As long as t!e "!ase relations!i" is (i'ed, t!e AD1 sam"le 3ill occur at a consistent "oint in
t!e ri""le "resent in t!e 4/0 conerter?s out"ut.
&!e out"ut o( t!e 4/0 conerter is am"li(ied 3it! a ,"+Am" (ollo3er con(iguration 3it! a gain o( 5. &!e
am"li(ier?s gain alue o( 5 3as establis!ed t!roug! e'"erimentation to yield an out"ut o( 50H 7dd scale
3!en t!e 4/0 conerter sa3 an in"ut o( 120 olts. &!is 50H met!odology 3as some3!at arbitrary, but
c!osen to aoid )uantiGation errors 3!ile retaining some dynamic !eadroom. &!e ,"+Am" also "roides
bu((ering bet3een t!e 4/0 conerter and t!e analog to digital conerter. &!e 4/0 conerter?s out"ut
resistance is about 12K C, and t!e AD1 in"ut re)uires a source o( less t!an 10K C
Analog to "igital con/ersion
&!e built+in AD1 in t!e 2611%.55 is a 10+bit successie+a""ro'imation ty"e conerter. &!e am"li(ied
out"ut o( t!e 4/0 conerter is connected to t!e "rocessorKs 9AA0: analog in"ut. An e'ternal oltage
re(erence is used (or t!e AD1 module. &!e re(erence oltage comes (rom a linear 3.3 olt regulator o(( t!e
10
5 olt logic rail. 6t 3as obsered t!at t!e 5 olt logic rail contributed noticeable noise to t!e data. 6n
addition, t!e 3.3 olt re(erence sered to 9am"li(y: t!e signal 3it! res"ect to t!e 5 olt re(erence.
&!e sam"ling "rocess is initiated by t!e 94-0: interru"t eent. &!e "ort -.0 "in is 3!ere t!e A1 line
"!ase re(erence is connected. &!e 9conersion com"lete: interru"t serice t!en stores t!e resulting 10+bit
alue and raises a (lag bit to signal t!e (oreground code o( a ne3 sam"le to "rocess. A "roblem obsered
early in t!e design "rocess 3as noise in t!e in"ut sam"les. &!e am"litude o( t!e noise 3as on t!e order o(
LB+ 1H o( t!e in"ut signal. 7arious (iltering met!ods 3ere e'"erimented 3it! on t!e in"ut analog signal
and none a""eared to !ae an e((ect on t!e noise. A se"arate re(erence 3as also incor"orated under t!e
assum"tion t!at t!e logic 7dd rail 3as contributing t!e noise. *ltimately, t!e noise 3as acce"ted as
unaoidable. 6n retros"ect, it !ad a maJor im"act on t!e "er(ormance o( t!e system.
," control in firm.are
2ro"ortional, 6ntegral and Di((erential control are im"lemented in (irm3are t!roug! a sim"le, brute+(orce
a""roac!. All "rocess ariables are im"lemented as 1% or 32 bit signed integers. 4outines (or multi+byte
mat! 3ere do3nloaded (rom htt$011...'s2list'com1techref1microchi$1math1+2bmath3$h'htm. ,nce t!e
mat! routines 3ere tested and eri(ied to 3or#, t!ey 3ere le(t alone and treated as 9blac#+bo'es:.
Darly in t!e design and e'"erimentation "rocess, t!e 26D terms 3ere calculated on eery sam"le <line
cycle=. ;o3eer, a(ter t!e res"onse time o( t!e 3!ole generator system 3as ta#en into account <see t!e
section belo3 on 92W/ o( 6nductie (ield 3inding:=, t!e decision 3as made to use t!e aerage o( seeral
sam"les at a time (or 26D in"ut. A desirable bi+"roduct o( t!e aeraging sc!eme 3as a lo3+"ass (iltering
e((ect t!at tends to reduce noise in t!e in"ut signal. A system o( ariable bloc# siGe (or t!e aeraging 3as
im"lemented in (irm3are. ,n eery AD1 sam"le, its alue is added to a running sum and a sam"le counter
is incremented. W!en t!e sam"le count reac!es t!e desired bloc# siGe, t!e sum is diided by t!e count. &!e
resulting aerage is "assed to t!e 26D "rocess. A(ter trying arious siGes, a bloc# siGe o( si' 3as used. &!e
11
number si' is not com"letely arbitrary. 0i' line cycles at %0 ;G is 100 m0. &!at time constant is roug!ly
1B5 o( t!e mac!ine?s res"onse time to a (ull+scale "ositie c!ange in e'citation current
2
.
At t!e "oint o( eac! ne3 bloc# aerage, t!e 2, 6 and D alues are calculated, (actored by t!e control
constants and added toget!er. &!e resulting alue is t!en scaled bac# to (it in a 10+bit range. &!is scaling is
necessary because t!e internal mat! is done in signed, 32+bit to ma'imiGe dynamic range and minimiGe
)uantiGation errors in t!e intermediate calculation ste"s. &!e resulting alue is t!en limited to "reset
minimum and ma'imum alues and 3ritten to t!e 2W/ subsystem?s control ariable. &!e minimum drie
leel 3as establis!ed to "reent t!e system out"ut oltage (rom dro""ing all t!e 3ay to 0 and causing a
"rocessor reset. &!e ma'imum is 1023 8 based on t!e 10+bit resolution o( t!e 2W/ subsystem.
&!e 26D "rocess is based on error bet3een "resent set"oint and "resent in"ut aerage. &!e error alue is
calculated by subtracting t!e "resent sam"le aerage (rom t!e set"oint. &!e "ro"ortional, or 92:, alue is
calculated by multi"lying t!is error by t!e K" constant. &!e integral, or 96:, alue is based on a running
sum o( all errors. &!is running sum is multi"lied by t!e Ki to (ind 6. &!e delta+t o( t!e integration is treated
as one time+unit and t!ere(ore t!e multi"ly o"eration is omitted (rom t!e calculation. An interesting t!ing to
note !ere is t!at t!is running sum is t!e sum o( all errors since boot+u". &!is 3ould be e)uialent to an ,"+
Am" integrator 3it! no "arallel resistance in t!e (eedbac# "at!. &!e di((erential alue is (ound by
calculating t!e deriatie o( error 3it! res"ect to time. &!is is done by diiding t!e di((erence in errors
<last + "resent= by t!e c!ange in time <delta+t=. Ei#e t!e case o( t!e integration mentioned aboe, t!e diide
o"eration is only im"lied and not im"lemented. 0ince t!e sam"le rate is (i'ed, t!e sam"le "eriod can be
treated as one time+unit and t!e triial diide+by+one o"eration can be s#i""ed. &!e t!ree control constants
K", Ki and Kd are im"lemented as double+byte unsigned integers. A sim"li(ied bloc# diagram o( t!e 26D
cycle (ollo3s.
12
%igure 4' ,rocess flo. of ," calculation
4esearc! into t!e subJect o( closed+loo" control systems 8 s"eci(ically digitally sam"led 26D
im"lementations, con(irmed a "!enomenon obsered during e'"erimentation. &!e "roblem is generally
re(erred to as 9integrator 3indu":. 6t occurs 3!en t!e actuation mec!anism reac!es a saturation "oint
3!ere additional in"ut no longer "roduces greater "rocess res"onse.
2
6n t!is scenario, t!e integral 3ould
increase 3it!out bound during t!e saturation condition. &!is accumulated error !as to be eentually 9"aid+
o((: 3it! an e)ual and o""osite errorBtime area on t!e ot!er side o( t!e set"oint. &!e system res"onse to t!is
13
saturation can be 3ild rail+to+rail oscillation. A solution suggested by 0ila, Datta and -!attac!aryya
1
3as
to sus"end t!e accumulation o( errors 3!eneer t!e mani"ulated ariable !as (orced t!e system into
saturation. &!is 9anti+3indu": (eature 3as im"lemented in t!e (irm3are t!roug! t!e use a 9saturation: (lag.
At t!e "oint in t!e code 3!ere t!e mani"ulated ariable is u"dated 3it! t!e latest calculation result, a
bounds+c!ec# is "er(ormed. 6( eit!er bound <minimum or ma'imum= is e'ceeded, t!e (lag 3ill be set and
remain until an in+bounds alue is 3ritten to t!e mani"ulated ariable. &!e integration "rocess ta#es t!is
(lag into account during summation. &!e u""er bound is sim"ly t!e 100H duty+cycle limit o( t!e 2W/
subsystem. 6n t!is "articular system, t!e "lant?s res"onse can slig!tly e'ceed t!e regulator?s 100H duty+
cycle actuation o( t!e e'citer (ield. A !ig!er D1 su""ly oltage in t!e regulator could ac!iee more
res"onse (rom t!e "lant, but t!e alue c!osen 3as based on obseration o( t!e original regulator?s design.
&!e lo3er bound alue is a (unction o( reliability rat!er t!an saturation aoidance. &!e actual lo3+end
saturation occurs at Gero e'citer drie. &!e arti(icial bound o( 2.$H e'citer drie 3as establis!ed to "reent
t!e e'citation "rocess (rom c!o#ing itsel( into a colla"se during user tuning.
&!e sel(+c!o#ing tendency 3as actually a signi(icant c!allenge during early tuning attem"ts. W!en t!e
e'citer drie out"ut 3as allo3ed to dro" all t!e 3ay to 0H, t!e regulator?s A1 in"ut 3ould dro" too lo3
and cause a "rocessor reset. &!is 3ould cause t!e control terms to be reloaded (rom DD24,/. &!is
(rustrating cycle is 3!at ins"ired t!e inclusion o( t!e 9*"time: (eature <mentioned belo3 in t!e
communication section=. 6nterru"t+based time+#ee"ing 3as im"lemented in t!e (irm3are to maintain a 1%+
bit count o( t!e number o( seconds since boot+u". &!is alue 3as t!en included in t!e data res"onse to a
94D2,4& 0>0&D/ /D&4610: )uery (rom t!e 21 so(t3are. *"dating t!e 9u"time: metric on t!e 21
screen t!en gae t!e tuner an indication 3!en t!e regulator !ad c!o#ed+o(( its o3n su""ly and re+initialiGed
to "reiously saed control terms.
6m"lementation o( 26D control on t!is system is similar to controls (ound in automotie cruise controls. 6n
a cruise control, t!e mani"ulated ariable <t!rottle= can only assume "ositie alues. A negatie t!rottle
"osition 3ould be e)uialent to bra#e a""lication. 0ince cruise control systems do not a""ly t!e bra#es as
"art o( t!eir out"ut, t!e in!erent losses in t!e system are relied u"on to ac!iee a negatie "rocess
14
correction. 6n a car, t!e losses 3ould be 3ind resistance and drie+train (riction. &!e generator system !as
t!e same ty"e o( "ositie+only mani"ulated ariable. &!e e'citer (lu' can not be made any lo3er t!an Gero
in res"onse to a negatie error. 6ntuitiely, t!is leads to a system 3!ose negatie error res"onse could be
signi(icantly less aggressie t!an its "ositie res"onse. &!e automotie analog 3ould be t!e (ull+t!rottle
res"onse to an incline to maintain s"eed and a subse)uent oer+s"eed res"onse on t!e decline. &!is issue
3ould become eident 3!en t!e generator system !ad a sudden decrease in load or decrease in set"oint.
,W* of in!ucti/e fiel! .in!ing
,ne o( t!e motiating adantages o( t!is design is reduced !eat dissi"ation in t!e main "ass element
<transistor= (or t!e e'citer (ield. Alt!oug! energy e((iciency is generally a 3ort!y ideal, t!e gains or losses
to !eat in t!e regulator circuit are insigni(icant to t!e system as a 3!ole. &!e reduced !eat dissi"ation is a
signi(icant adantage in terms o( re)uired !eatsin# area. &!e (ield 3inding !as a D1 resistance o( 50 C.
-ecause o( t!is resistance, t!ere 3ill al3ays be losses in t!e 3inding itsel( <96
2
4 losses:=. &!e loss t!at 3e
can actually control is in t!e "ass element.
6n a linear D1+e'cited (ield system, t!e range o( "ossible (ield current alues must be siGed in suc! a 3ay
t!at t!e typical alue is mid+scale in order to allo3 (or t!e best dynamic range. &!e in!erent "roblem !ere
is t!at t!is mid+range current alue is also t!e !ig!est range o( !eat+loss in t!e "ass element. ,biously, t!e
t3o e'treme cases o( no current and ma'imum current 3ould bot! "roduce no loss and minimum "ass+
element loss res"ectiely.
Assuming t!e ty"ical <3orst+case= scenario@ &o ac!iee t!e !al(+scale alue o( (ield current, t!e "ass
element !as to "resent t!e same e)uialent resistance alue as t!e 3inding itsel(. 6n t!is scenario, t!e 24
7olt su""ly is dro""ed across an e)uialent load o( 100 C. &!e current t!roug! t!is 9diider: is 240mA
<24 7 B 100 C= and t!ere(ore t!e !eat loss is about 3 3atts <.24 am" M 12 olts= in eac! !al( o( t!e diider +
3 3atts in t!e 3inding and 3 3atts in t!e transistor. &!ree 3atts becomes a signi(icant !eatsin#ing
c!allenge in a !ig! ambient+tem"erature enironment li#e t!e inside o( a generator?s control "anel. &!is
(act is eident by obsering t!e amount o( metal inoled in t!e original regulator module.
15
%igure -' #riginal regulator mo!ule
&o ca"italiGe on t!e t3o best+case (ield current scenarios <no current and ma'imum current=, 2ulse Widt!
/odulation <2W/= 3as used 3it! an .D& c!osen (or its lo3 9on: <or saturation= resistance, and (ast
s3itc!ing s"eed. &!e 6nternational 4ecti(ier 6.4540 3as c!osen (or t!ese attributes and its common
aailability. &!e 9on: resistance o( t!e 540 is ty"ically a (raction o( 1 C <see data s!eet in A""endi' D=.
-ecause o( t!is lo3 resistance, t!e !eatsin# re)uirements go (rom a signi(icant design c!allenge <in t!e
linear system= to triial. &!e 261 micro"rocessor !as a built+in 2W/ mec!anism 3it! a 10+bit resolution.
&!is sub+system greatly sim"li(ies t!e tas# o( so(t3are 2W/. ;o3eer, it 3as )uic#ly (ound t!at driing a
large .D& <and inductie load= directly (rom t!e "ort "in o( t!e micro"rocessor yielded disa""ointing
results. &!e large gate ca"acitance o( t!e .D& caused so(t s3itc!ing transitions. &!is "rom"ted t!e
inclusion o( an .D& gate drier into t!e design. &!e &e'as 6nstruments &202514 deice 3as c!osen as an
inter(ace bet3een t!e micro"rocessor and t!e .D&.
1%
&!e inductance o( t!e e'citer (ield 3inding sered as a lo3+"ass (ilter to smoot! out t!e s3itc!ing
3ae(orm. A small <.1N.= ceramic ca"acitor 3as added in "arallel to t!e (ield 3inding to su""ress transient
noise (rom t!e s3itc!ing. &!e large alue o( inductance in t!e (ield 3inding also introduced a lo3+"ass
e((ect to t!e 3!ole system?s dynamic res"onse to load c!anges and e'citer current c!anges. 6n order to
)uanti(y t!is e((ect, t!e actual alue o( t!e (ield?s inductance 3as measured. &!e met!od (or measurement
3as to connect a #no3n resistance <1000 C= in series 3it! t!e (ield 3inding and a""ly a ariable (re)uency
sine 3ae to t!e series combination 3it! a signal generator. &!e (re)uency at 3!ic! t!e A1 oltage dro"
3as e)ually s"lit bet3een 4 and E elements 3as (ound. &!is 3as done by slo3ly s3ee"ing t!e signal
generator?s (re)uency 3!ile obsering t!e oltages across t!e series elements 3it! a oltmeter. &!e
(re)uency 3!ere t!e 3inding oltage e)ualed t!e resistor oltage 3as 47 !ertG. At 47 !ertG, t!e magnitude
o( t!e inductie reactance 3as 1000 C. -y soling t!e e)uation (or inductie reactance magnitude (or IE,
t!e alue o( E 3as (ound to be 3.4 !.
1000 C 3as c!osen because it 3as many times t!e alue o( t!e 3inding resistance o( 50 C. &!is 3ay, t!e
relatiely small 3inding resistance could be ignored 3it!out a signi(icant e((ect on t!e result. &!e 3.4 !
3inding 3it! its 50 C o( distributed 3ire resistance also "roduces a lo3+"ass (ilter e((ect o( an un3anted
nature. &!is e((ect seres to retard t!e reaction time to a sudden load c!ange. &!e time constant o( 3.4 ! B
50 C is %5m0. Assuming a load 3as "resented to t!e system t!at necessitated a 100H c!ange in (ield
current <(rom 0 to (ull scale=, t!e 3inding 3ould ta#e about 5 time+constants <325m0= to reac! t!e ne3
current alue. Oust as in t!e case o( 4/0 conerter?s aeraging, t!is (ilter e((ect also acts to limit t!e
system?s res"onse s"eed. &!e e'citer (ield 3inding and drie circuit 3ere modeled in /ultisim in order to
)uanti(y t!e res"onse time o( t!e e'citer (ield. &!e 2W/ subsystem 3as an un(oreseen source o(
)uantiGation error. Wit! t!e main D1 rail oltage near 24 olts, t!e duty cycle re)uired to delier 2.1 #W at
17
120 olts 3as only about 10H. &!is lo3+utiliGation o( t!e 2W/ resolution e((ectiely reduced its
resolution to about 7+bits. A design assum"tion 3as t!at t!e !ig! D1 rail oltage 3ould be re)uired (or
e'citation at mac!ine oer+load conditions. ,t!er3ise, t!e rail oltage 3ould !ae been designed lo3er.
Re3circulate! $o.er startu$ $roblem an! fiel! flashing
,n obseration o( t!e system layout in .igure 1, e'citation startu" is clearly a "roblem. 0ince t!e system
uses its o3n A1 output to ultimately drie its input, it is not in!erently sel( starting. 6n an automotie
system by contrast, t!e battery is t!e source o( t!e alternator (ield current. 6n t!is military design, t!e
system does not com"letely rely on a battery (or anyt!ing. Alt!oug! t!e system !as a 24 olt battery on+
board (or t!e starter motor, it does not use it (or ignition or (ield e'citation. &!e a""arent rationale !ere is to
!ae a mac!ine t!at could be started by !and 3it! a "ull cord and used 3it! no battery in e'treme
<battle(ield= circumstances.
&!e original design actually relies on residual magnetic "olariGation in t!e e'citer?s core. &y"ically, t!ere
is enoug! residual (ield (or t!e sel(+e'citation to start. &!e system does !ae a mec!anism (or a""lying t!e
system?s battery <t!roug! a "air o( resistors= to t!e e'citer (ield manually i( t!e residual (ield is insu((icient.
&!is (eature is called 9.ield .las!:. 6t is a momentary s3itc! be!ind t!e control "anel.
&!e original analog regulator circuit 3as set u" to begin o"eration (rom minimal in"ut su""ly oltage and
9s"ool u": 3it! t!e rest o( t!e system. &!is 3as accom"lis!ed t!roug! t!e absence o( 9real: <by modern
standards= D1 oltage regulators on t!e circuitKs "ositie and negatie rails. &!e internal D1 regulation
3as done 3it! Gener s!unt diodes to ground and series resistors to limit t!e rails to t!eir ma'imum alues
o( $.17olts. &!e beauty o( t!is D1 regulation sc!eme is t!at t!ere is no 9dro"out: as t!ere is 3it! modern
61 oltage regulators li#e t!e E/7505. At t!e time o( t!e original circuit design, t!e Gener s!unt met!od
3as "robably t!e only "ractical regulation met!od (or circuits o( t!is nature. &!e analog circuit t!ere(ore
!ad a relatiely !ig! start oltage t!at 3as "robably on t!e order o( seeral diode+dro"s.
15
A design c!allenge (or t!e micro"rocessor+based system 3as t!e re)uirement o( (ull, stable "o3er be(ore
starting. -y using a digital element in t!e e'citation loo", t!e minimum start oltage 3ent (rom seeral
diode dro"s to about 5 olts <5 olts logic rail "lus t!e regulator?s 9dro"out: oltage=. Ao3 t!e system 3as
een less li#ely to sel( star t!an t!e original analog circuit.

A sim"le 3or#+around to t!is dilemma is a relay by"ass in t!e "o3er section o( t!e circuit. A normally+
closed relay 3as connected across t!e out"ut .D&. Dssentially, t!e relay by"ass across t!e .D& nets a 100H
drie o( t!e e'citer (ield. &!e relay?s coil is energiGed <remoing t!e by"ass= by t!e 24 olt rail 3!en t!e
system is u" and running. &!e e((ect is to run t!e e'citation 93ide+o"en: 3it! t!e total aailable current
until t!e micro"rocessor can ta#e oer. &!is is actually a subtle im"roement oer t!e original analog
design. 6nstead o( re)uiring <at t!e ery least= t!e t3o diode+dro"s in t!e Darlington "air o( t!e analog
design?s "ass element, t!e relay solution !as no minimum re)uired startu" oltage. &!e result 3ould be a
system t!at can sel(+start (rom a 3ea#er residual e'citer (ield. ,( course, in eit!er design <original or
retro(it=, t!ere are still t!e t3o diode dro"s associated 3it! t!e bridge recti(ier t!at (eeds t!e 24 olt rail.
Communication an! control har!.are1firm.are1soft.are
Due to t!e "otential com"le'ity o( tuning and monitoring t!e system, a mec!anism o( remote
communication and control 3as im"lemented. &!is inter(ace also ta#es t!e "lace o( t!e set"oint
"otentiometer on t!e control "anel. &!e occasion to tune and con(igure t!e regulation "arameters 3ould not
"resent itsel( o(ten enoug! to 3arrant built+in user inter(ace. Also, t!e e'treme o"erational conditions
<ibration, !eat and dust= 3ould "resent "articularly di((icult design c!allenges (or E1D and button user
inter(ace.
&!e mec!anism c!osen uses legacy 40232 as its "!ysical layer and a custom command structure to
control and )uery t!e regulator. A sim"le 7isual -asic a""lication 3as 3ritten (or a 21 to sere as t!e user
inter(ace to t!e system. &!is allo3s t!e user to be "!ysically distant (rom t!e running mac!ine. 6t also
allo3s (or user inter(ace (eatures t!at could not easily be im"lemented in an on+board E1D and button
1$
inter(ace. ,ne o( t!ese (eatures, (or e'am"le, is a set o( scrolling gra"!s re"resenting t!e mac!ine?s out"ut
oltage, (re)uency and e'citer drie leel oer t!e "ast seeral minutes. &!is ty"e o( gra"!ical
re"resentation ma#es (or (ast and obJectie setting o( t!e 26D terms.
&!e main disadantage o( 40232 as a "!ysical communication layer is t!e (act t!at it is unbalanced and
relies on t!e 21?s c!assis ground as !al( o( t!e signal "at!. 6n t!e ty"ical tuning scenario, a user 3ould
"o3er t!eir 21 (rom t!e building and t!e generator 3ould be running com"letely isolated (rom t!e
building?s ground system. &!e "roblem 3it! suc! a "otential c!assis oltage di((erential is a ground current
t!roug! t!e communication cabling. &!is could result in signal corru"tion, e)ui"ment damage and
electrical s!oc# to t!e user. A balanced isolated medium li#e Dt!ernet 3ould certainly oercome t!is issue,
but t!e added com"le'ity in t!e u""er communication layers 3ould be 3ell beyond t!e sco"e o( t!is
"roJect.
&o oercome t!e limitations o( 40232 3!ile maintaining its bene(its, o"tical and trans(ormer isolation
3ere em"loyed to se"arate t!e regulator?s ground (rom t!e 21?s ground.
5
0ee (igure 7 belo3. &!e o"tical
isolator c!osen 3as t!e E6&D+,A E&7527. &!e isolation and line drier circuit is on a se"arate circuit
board t!at connects to t!e regulator t!roug! a %+"in !eader. &!e line drierBreceier c!osen 3as t!e /a'im
/AI232A (or its robustness and ease o( use.
%igure 5' #$to3solate! serial interface boar!
20
&!e serial "ort is set to a relatiely lo3 bit rate o( $%00b"s to ma'imiGe noise immunity and cable lengt!.
&!e communication sc!eme t!at ma#es u" t!e second layer o( t!e "rotocol is a (ramed arrangement
<similar to an Dt!ernet (rame in (unction=. &!e (rame is based on a 7+bit data 3ord. Any 3ord 3it! its 5
t!
bit set is a (raming 3ord 3!ose lo3er 7 bits ma#e u" t!e destination address (or t!e (rame. 6n t!is
a""lication, t!ere is obiously only one destination on t!e communication bus. ;o3eer, t!e "rotocol
allo3s (or e'"ansion (or ot!er modular control deices to s!are t!e same bus. Dery byte a(ter t!e
(ramingBaddress byte !as a s"eci(ic "ur"ose. &!e (rame is a (i'ed lengt! and uses an E41 as t!e last byte to
allo3 (or error detection. &!e regulator sim"ly discards t!e (rame i( t!e E41 byte does not matc! t!e
running e'clusie+,4 o( all t!e bytes in t!e (rame. &!ere is no 9A1KBAA1K: res"onse (rom t!e regulator
bac# to t!e !ost 21. &!e basic (unction o( t!e communication "rotocol is to delier commands to t!e
regulator (or e'ecution. &!e second byte o( t!e (rame is a command number. &!e t!ird, (ourt! and (i(t!
bytes are command arguments. A t!ree+byte argument structure 3as deised in order to communicate all
t!ree 26D terms in a single (rame. A(ter e'"erimentation, it 3as concluded t!at a 7+bit dynamic range 3as
insu((icient (or t!e 26D terms. &!e "rotocol 3as c!anged to communicate t!e 2,6 and D terms in se"arate
(rames as 14+bit alues. &!e "rocessing o( receied bytes is done under interru"t 3it! a state+mac!ine li#e
met!od.
&!e recei"t o( a byte 3!ose /0- is set causes a state reset bac# to t!e beginning+o(+(rame state. Dery
subse)uent byte is !eld in memory locations as t!e state ariable is incremented. W!en t!e state dictates
t!at t!e last (rame byte is e'"ected, and a byte is receied, t!e E41 is calculated and c!ec#ed. Assuming a
alid E41, t!e interru"t+drien data recei"t "rocess raises a (lag bit to signal t!e (oreground t!at a alid
(rame is sitting in memory and ready (or e'ecution. &!e bac#ground recei"t "rocess 3ill not oer3rite a
receied (rame i( t!at (lag bit is still set.
&!e (oreground code loo" is constantly c!ec#ing (or t!e "resence o( (rames to e'ecute. 6n t!e case 3!ere
a "arameter is sent, t!e (oreground code 3rites t!at "arameter into t!e a""ro"riate location and clears t!e
(lag to indicate t!at t!e (rame !as been "rocessed. 6n t!e case 3!ere t!ere is a res"onse re)uired to a (rame,
t!e (oreground code loads t!e res"onse data into a so(t3are transmit bu((er and clears t!e (lag.
21
&!e data transmit "rocess is also !andled by t!e (oreground code. ,n eery main+loo" iteration, one o( t!e
tas#s is to "oll t!e status o( t!e *A4& transmit s!i(t+register. 6( t!e register is em"ty, and t!ere are )ueued
bytes in t!e so(t3are bu((er, t!e ne't bu((er byte is loaded and t!e t!e bu((er inde' is decremented. 6n
general, t!ere is not!ing in t!e code t!at 3ill blindly loc# 3aiting (or an eent. &!e (irm3are could be
considered a 9multi+tas#ing: system. &!e one caeat to t!is design rule is in t!e case read or 3riting to
DD24,/. /icroc!i" recommends t!at all interru"ts be disabled during t!ese o"erations. DD24,/ is
accessed on boot+u" to retriee control "arameters and on command (rom t!e 21 to 9Write 4unning
con(iguration to A7/:.
&!e return "at! (or t!e data <(rom regulator to 21= does not use a (raming+byte sc!eme. &!e entire 5 bits
are used to communicate data. &!e rationale is t!at t!e 21, being t!e bus master, is al3ays in control o( t!e
state o( communications on t!e bus and is able to inter"ret incoming data conte'tually. .or e'am"le, i( t!e
21 issues a command t!at re)uires a 2+byte res"onse, t!e ne't t3o bytes receied are assumed to be a
res"onse to t!e last command. *sing t!e (ull 5+bits o( t!e return data "at! sim"li(ies t!e (irm3are side o(
t!e communication "rotocol.
0ince t!e "rotocol is based on a 7 bit 3ord, any command needing to communicate an argument alue
larger t!an 127 must brea# u" t!e argument alue into se"arate 7+bit 3ords. 0ee (igure 5 belo3 (or a
diagram (or t!e (rame layout. 0ome commands are one+3ay, 3!ile ot!ers dictate a res"onse (rom t!e
regulator. &!e 94D2,4& 0>0&D/ /D&4610: command 3ill be ans3ered by t!e regulator 3it! a series
o( bytes re"resenting t!e "resent system oltage, e'citer drie leel, line "eriod and system u"time. &!e
90D& 0D&2,6A&: command, on t!e ot!er !and, does not re)uire a res"onse bac# (rom t!e regulator.
22
Comman!
Letter
6ame Argument
%ormat
Res$onse
back to ,C
Comment
A 0D& 0D&2,6A& Double+byte Aone
- 0D& D467D ED7DE Double+byte Aone Diagnostic 8
disables 26D control
1 0D& 2 PA6A Double+byte Aone
D 0D& 6 PA6A Double+byte Aone
D 0D& D PA6A Double+byte Aone
. 4D2,4& 4*AA6AP 1,A.6P Aone 0et"oint, K",Ki and Kd as double+byte
3ords
P 4D2,4& *2&6/D Aone 0econds since boot as a double+byte 3ord
; 4D2,4& 0>0&D/ /D&4610 Aone 0ystem A1 out"ut, Eine 2eriod, e'citer
drie and u"time
as double+byte 3ords
6 W46&D 4*AA6AP 1,A.6P
&, DD24,/
Aone Aone 0et"oint, 2,6,D and
ag bloc#
O 4D+DAA-ED 26D 24,1D00
1,A&4,E
Aone Aone 4estore normal
control a(ter
diagnostic.
%igure 8' Comman! list for the communications $rotocol
Circuit (oar! la)out Consi!erations
A(ter t!e !and+built "rototy"e 3as com"letely tested and t!e circuit design !ad stabiliGed, a "rinted circuit
board 3as laid+out using 21AD. &!e "rimary consideration in t!e layout 3as to #ee" t!e !ig! current "at!s
isolated (rom t!e oltage detection section. &race 3idt!s 3ere siGed (or t!e e'"ected current.
4
0econdary,
t!e goal 3as to #ee" t!e layout small and dense (or mec!anical stability in a !ig! ibration enironment.
&!e decision 3as made early on to #ee" t!e trans(ormers o(( t!e circuit board (or t!is reason also. 21-+
mounted trans(ormers 3it! t!eir signi(icant mass 3ould (atigue t!eir traces and solder Joints 3!en
subJected to ibration. 2rinting o( t!e board 3as done by a 1anadian com"any called Alberta Printed
Circuits. &!ey o((er a (ast, lo3+cost "rototy"e board "rinting serice. &!e serice included .0%2: .44
material, t3o+sided "rinting and no solder mas#s or sil#screen.
,erformance testing an! tuning
6n t!e conte't o( tuning, it is 3ort! "ointing out !ere !o3 in!erently unstable t!is sel(+e'citing generator
con(iguration is. W!en t!e regulation mec!anism 3as con(igured sim"ly as a recti(ierB(ilter, t!e system
out"ut (eeding its o3n in"ut 3ould )uic#ly reac! (ull+scale saturation. Qero to (ull+scale runa3ay 3as
23
obsered to ta#e about t3o seconds under no+load conditions. &!is con(iguration is analogous to an
am"li(ier 3it! "ositie (eedbac#. 4una3ay (eedbac# is e'actly 3!at is !a""ening <intentionally= during t!e
brie( startu" "eriod 3!en t!e by"ass relay is still engaged across t!e "ass+element in t!e e'citer drie
circuit. ,ne 3ay to tame t!is instability 3ould be to regulate <limit= t!e main D1 su""ly rail t!at (eeds t!e
e'citer drie circuit so t!at t!e "ositie (eedbac# is limited in !ard3are in addition to (irm3are. ;o3eer,
rail regulation 3ould !ae to be done is suc! a 3ay as to aoid dro"+out or t!e system could not sel(+start.
Additionally, regulation o( t!e main D1 rail 3ould ca" t!e ma'imum e'citer drie leel at an arbitrary
leel. A more e'otic a""roac! to t!e "ositie (eedbac# "roblem 3ould be to numerically account (or t!e
dynamic D1 rail oltage as "art o( t!e control "rocess. 0ince t!e rail is relatie to t!e same ground as t!e
AD1?s negatie re(erence and its source im"edance is "ractically Gero, it can be resistor+diided do3n to
t!e range o( t!e AD1?s in"ut. -asically, t!e strategy 3ould be to diide t!e mani"ulated ariable by a
(actor o( t!e D1 rail oltage be(ore a""lying it to t!e e'citer drie. A rise in rail+oltage 3ould cause a
scale+bac# o( t!e regulator?s a""lication o( t!at oltage to t!e e'citer. &!is ty"e o( arrangement 3ould
amount to a negatie (eedbac# loo" inside t!e regulator.

A resistie test load 3as constructed o( lig!t bulbs and distributed eenly across t!e t!ree system "!ases.
&!e total load 3attage 3as 2.1 #W at 120 olts. &!is 3as 42H o( t!e mac!ine?s rated load. A lig!t bulb is
not a "er(ectly (air test+load because o( its large "ositie tem"erature coe((icient, but it is a real+3orld load.
&!e bulbs used 3ere obsered to !ae about a 1%+(old increase in resistance 3!en going (rom o(( to on.
&!is 3as (ound by com"aring t!e measured cold resistance and t!e calculated resistance (rom t!e
3attageBoltage rating. &!e system !as a 3+"ole circuit brea#er built in to allo3 clean a""lication or
remoal o( t!e load (rom all "!ases at once.
6n order to establis! a base+line (or com"arison o( t!e original circuit to t!e ne3 design, t!e digital circuit
3as connected to 9listen+in: on t!e original. &!is 3as done by connecting t!e generator?s A1 out"ut to t!e
digital circuit and using t!e 21 so(t3are to "lot t!e res"onse to t!e dummy+load a""lication and remoal.
&!is only reealed t!e "rocess res"onse, and not t!e internal drie leel o( t!e original circuit. 0ee
a""endi' - (or a side+by+side com"arison o( t!e t3o regulators res"onding to t!e same load conditions.
24
,bseration o( t!e original circuit?s res"onse to sudden load c!anges indicated t!at its regulation o( t!e
system 3as slig!tly sti((er t!an t!e best tuning o( t!e retro(it could delier. &!e di((erence 3as only slig!t.
Wit! "ro"er tuning, t!e retro(it could "robably out+"er(orm t!e original. Additionally, t!e original circuit
and t!e retro(it 3ere only tested at one load <42H o( rated=.
&!e trial+and+error tuning met!od described by 0toec#er 3as used.
2
&!e met!od uses t!e obsered
ma'imum stable "ro"ortional gain as a starting "oint and t!en adds t!e ot!er terms. A""endi' - contains a
series o( screen+s!ots o( t!e 21 so(t3are "lotting t!e "rocess res"onse to load c!anges under arious tuning
scenarios. &!e conclusion dra3n (rom t!e arious tuning attem"ts is t!at t!e in!erent "ositie (eedbac#
"roblem mentioned aboe and t!e noise "resent in t!e in"ut data 3ould !ae to be oercome be(ore any
disci"lined tuning met!od 3ould yield satis(actory results.
Conclusions
Commercial $ro!uct /iabilit)
,ne o( t!e goals (or t!is "roJect 3as to consider t!e (easibility o( t!is design as a commercial "roduct.
0eeral assum"tions !ae to be made in order to attem"t 3eig!ing t!e (easibility. 6n order to bring t!e
design to commercial readiness, signi(icant (urt!er re(inement o( all as"ects 3ould be re)uired. A
conseratie estimate is 125 more !ours in deelo"ment 3ould be re)uired. Arbitrarily assigning a alue o(
R50 "er !our to t!e remaining deelo"ment 3or# 3ould net a re)uired inestment o( R10,000 in t!e
"roduct. .or t!e sa#e i( 4,6 calculation, R10,000 is t!e amount to be recou"ed.
&!e total cost o( com"onents (rom a one+sto" endor li#e Digi+Key <assuming 100 unit "roduction runs=
is about R40. Assuming a circuit board cost o( R5, assembly labor cost o( R20 and R10 in a mec!anical
!ousing, t!e total !ard cost "er unit 3ould be R75. Alt!oug! an e'act e)uialent 3as not (ound, a casual
surey o( t!e mar#et (or general+"ur"ose retro(it generator regulators suggested t!at suc! a deice 3ould
retail around R300. &!e ideal "ro(it o( R225 "er unit 3ould reac! t!e brea#+een "oint (or t!e R10,000
inestment at 45 units sold.
25
&!ere is no 3ay to #no3 e'actly !o3 many o( t!ese mac!ines are still in use today. 6t is een less clear
!o3 many o( t!em need a re"lacement regulator. 6t 3ould be !ard to (ind an inestor to s"onsor suc! an
uncertain return on t!e inestment.
&!e end result 3as a re"lacement circuit 3it! interesting 9bells and 3!istles:, but (unctionally e)uialent
to t!e original. &!e added (eatures come at a cost. &!e most obious cost is robustness. &!is design
re"laces a ery sim"le analog circuit 3it! a (airly com"le' digital one. &!e addition o( sensitie digital
com"onents <and more o( t!em= !as t!e "otential to net a design t!at is more ulnerable to o"erational
stresses o( !eat and ibration and e'treme stresses li#e a near lig!tning stri#e.
&!e conce"ts o( 4/0 detection, 2W/, isolated serial communication, numeric 26D control and closed+
loo" mac!ine (eedbac# 3ere all incor"orated. W!ile t!is 3as a 3ort!3!ile academic e'ercise, t!is circuit?s
"ractical a""lication is ery limited.
2%
References
&7 Sil/a8 9uillermo :'8 S',' (hattachar))a8 an! Aniru!!ha "atta' ," Controllers for time3
!ela) s)stems' &st' ;SA0 (irkhauser8 20040 &-3&8
27 Stoecker8 Wilbert %'' *icrocom$uter control of thermal an! mechanical s)stems' &st'
6e. <ork0 Van 6ostran! Reinhol!8 &=8=0 4&=3424
+7 (uchsbaum8 Walter >'' (uchsbaum?s Com$lete han!book of $ractical electronic
reference !ata' 2n!' Engle.oo! Cliffs8 6:0 ,rentice3>all8 &=5+0 4=5
47 Clark8 Ra)mon! >'' ,rinte! circuit engineering 3 o$timi@ing for manufacturabilit)' &st'
6e. <ork0 Van 6ostran! Reinhol!8 &=8=0 228
47 *alone)8 Timoth) :' *o!ern in!ustrial electronics' +r!' Engle.oo! Cliffs8 6:0 ,rentice3
>all8 &==-0 +--3+50
27
A$$en!i2 A A Schematics an! gra$hs
%igure A' *ain circuit
25
%igure (' EBui/alent circuit for multisim simulation of the ,W* !ri/e circuit'
%igure C' *ultisim CTransient Anal)sisD simulation of ,W* e2citer !ri/e circuit' Time scale is first
400mS of o$eration starting from no magneti@ation' Simulate! ,W* !ri/e le/el is 40E' S.itch rate is
20F>@'
2$
Q1
IRF540
L1
3.4H
V1
24V
0
0
V2
0V12V
25usec50usec
0
3
R1
52
C1
10nF
R2
10
4
D1
1N4004GP
6
1
2
%igure "' #riginal Regulator
30
A""endi' - 8 0ystem dynamic res"onses
%igure A' #riginal regulator?s s)stem res$onse to a 2'& kW loa! change Gcenter of timeline7
%igure (' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H&8 H08 "H0
31
%igure C' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H28 H08 "H0
%igure "' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+8 H08 "H0
32
%igure E' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H48 H08 "H0
%igure %' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H48 H08 "H0
33
%igure 9' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H-8 H08 "H0
%igure >' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H58 H08 "H0
34
%igure ' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H88 H08 "H0
%igure :' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'0&8 "H0
35
%igure F' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'028 "H0
%igure L' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'0+8 "H0
3%
%igure *' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'048 "H0
%igure 6' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'048 "H0
37
%igure #' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'0-8 "H0
%igure ,' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'058 "H0
35
%igure I' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'088 "H0
%igure R' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'0=8 "H0
3$
%igure S' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'&8 "H0
%igure T' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'&8 "H0'2
40
%igure ;' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'&8 "H0'4
%igure V' S)stem res$onse to a 2'& kW loa! change Gcenter of timeline7 ,H+'48 H0'&8 "H0'-
41
A$$en!i2 C A %irm.are co!e listing
S Eu#e 0mit! <lsmit034@odu.edu=
S 12B10B2007
S regulator o( t!e 2A042 </D2+017A= generator
S DD&450W "roJect (irm3are
E60& 2T1%.55
Uinclude "1%.55.inc
Sserial receie state de(initions
receieVidleT0
3aitingV(orVcommandT1
3aitingV(orVarg0T2
3aitingV(orVarg1T3
3aitingV(orVarg2T4
3aitingV(orVlrcT5
Sserial t' state
transmitVidleT0
sendingVdataT1
SmainV(lags bit de(initions
DIDV1,//AADT!?01?
0A/2EDT!?02?
1,A&4,EVDAA-EDT!?03?
/7V0A&*4A&6,AT!?04?
SDD24,/ memory de(initions
DDVset"ointV!T0
DDVset"ointVlT1
DDV#"V!T2
DDV#"VlT3
DDV#iV!T4
DDV#iVlT5
DDV#dV!T%
DDV#dVlT7
1-E,1K 0I20
mainVstate S20
mainV(lags
tem"1
tem"2
/&D/2
/1,*A&
D1,*A&
4DPA0 Slsb
4DPA1
4DPA2
4DPA3 Smsb
4DP-0 Slsb
4DP-1
4DP-2
4DP-3 Smsb
4DP10 Slsb
4DP11
4DP12
4DP13 Smsb
4DPD0 Slsb
4DPD1
4DPD2
4DPD3 Smsb
A11*/0 Slsb
A11*/1
A11*/2
A11*/3 Smsb
receieVstate
transmitVstate
inVbyte
address
42
command S3(
arg0
arg1
arg2
lrc
sam"leVcount
u"timeV!
u"timeVl
sam"leV!
sam"leVl
4/0Vno3V!
4/0Vno3Vl
set"ointV!
set"ointVl
lineV"eriodV!
lineV"eriodVl
#"V! Scontrol (actor (or "ro"ortional
#"Vl S50
#iV! Scontrol (actor (or integral
#iVl
#dV! Scontrol (actor (or di((erential
#dVl S
2W/V! Scurrent W"roccessW out"ut leel
2W/Vl
t'Vbu((Vinde'
t'Vbu((V0
t'Vbu((V1
t'Vbu((V2 S5a
t'Vbu((V3
t'Vbu((V4
t'Vbu((V5
t'Vbu((V%
t'Vbu((V7
t'Vbu((V5 S%0
t'Vbu((V$
!istVinde'
errorVsum0
errorVsum1
errorVsum2
errorVsum3
lastVerror0
lastVerror1
lastVerror2
lastVerror3 S%a
timerVa
DAD1
1-E,1K 0I7D
bgVWVtem"
bgV0&A&*0Vtem"
bgV21EA&;Vtem"
DAD1
,4P 0'00
4D0D& P,&, 0&A4&
,4P 0'04
67D1& call intVserice
4D&.6D
,4P 0I0.
0&A4& goto init
STTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT
TTTTTT
intVserice mo3( bgVWVtem"
s3a"( 0&A&*0,W
mo3( bgV0&A&*0Vtem"
mo( 21EA&;,3 Ssae 21EA&;
mo3( bgV21EA&;Vtem"
bc( 0&A&*0, 420
43
intV4-0 bt(ss 6A&1,A,1 Ssee i( interu"t source is -0 rising edge
goto intVtimer0
bc( 6A&1,A,1
S4-0 !as Just gone !ig!
bs( 2,4&-,1
bs( AD1,A0,2
no"
no"
bc( 2,4&-,1
bc( 2641,AD6.
/,7. &/41;, W S 4ead !ig! byte
/,7W. lineV"eriodV!
/,7. &/41E, W S 4ead lo3 byte
/,7W. lineV"eriodVl
/,7. &/41;, W S 4ead !ig! byte
0*-W. lineV"eriodV!, W S 0ub 1st read 3it! 2nd read
-&.01 0&A&*0, Q S 6s result T 0
P,&, intV4-0.10 S Pood 1%+bit read
/,7. &/41;, W S 4ead !ig! byte
/,7W. lineV"eriodV!
/,7. &/41E, W S 4ead lo3 byte
/,7W. lineV"eriodVl
intV4-0.10 clr( &/41E
clr( &/41;
intV4-0.end
Stimer0 interru"t serice
intVtimer0 bt(ss 6A&1,A,&/406. Ssee i( interu"t source is Wtimer 0W
goto intVadcVdone
bc( 6A&1,A,&/406.
mol3 d?157?
mo3( &/40
dec(sG timerVa,(
goto intVtimer0.end
mol3 d?$$?
mo3( timerVa
inc( u"timeVl,(
bt(sc 0&A&*0,Q
inc( u"timeV!,(
intVtimer0.end
SAD1 done serice
intVadcVdone bt(ss 2641,AD6. Ssee i( interu"t source is WAD1 doneW
goto intVusartVrec.10
bc( 2641,AD6.
bc( 0&A&*0,421
bs( 0&A&*0,420
mo( AD4D0E,W
bc( 0&A&*0,420
mo3( sam"leVl
mo( AD4D0;,W
mo3( sam"leV!
bs( mainV(lags,0A/2ED
intVadcVdone.end
S *0A4& receie interu"t serice
intVusartVrec.10 bt(ss 2641,416.
goto intVsericeVend
bc( 2641,416.
mo( 414DP,W
mo3( inVbyte
bt(ss inVbyte,7
Smsb is set
44
bc( inVbyte,7
mo( address,W
'or3( inVbyte,W
bt(ss 0&A&*0,Q
goto intVsericeVend
S t!is re)uest is (or me
mol3 3aitingV(orVcommand
mo3( receieVstate
mo( inVbyte,W
mo3( lrc
goto intVsericeVend
intVusartVrec.15 mol3 receieVidle
sub3( receieVstate,W
bt(sc 0&A&*0,Q
goto intVsericeVend
mol3 3aitingV(orVcommand
bt(sc 0&A&*0,Q
mol3 3aitingV(orVarg0
bt(sc 0&A&*0,Q
bt(sc 0&A&*0,Q
bt(sc 0&A&*0,Q
mol3 3aitingV(orVlrc
bt(sc 0&A&*0,Q
intVusartVrec.20 St!is byte is t!e command
mo( inVbyte,W
mo3( command
'or3( lrc,.
mo3( receieVstate
goto intVsericeVend
intVusartVrec.30 St!is byte is t!e arg0
mo( inVbyte,W
mo3( arg0
'or3( lrc,.
mo3( receieVstate
goto intVsericeVend
mo( inVbyte,W
mo3( arg1
'or3( lrc,.
mo3( receieVstate
goto intVsericeVend
mo( inVbyte,W
mo3( arg2
'or3( lrc,.
mol3 3aitingV(orVlrc
45
mo3( receieVstate
goto intVsericeVend
intVusartVrec.40 St!is byte is t!e lrc
mo( inVbyte,W
'or3( lrc,.
bt(ss 0&A&*0,Q
Sgood lrc
bs( mainV(lags,DIDV1,//AAD
intVusartVrec.43 bs( 2,4&-,7 Sbad E41
no"
bc( 2,4&-,7
intVusartVrec.45 mol3 receieVidle
mo3( receieVstate
intVsericeVend mo( bgV21EA&;Vtem",W Srestore 21EA&;
mo3( 21EA&;
s3a"( bgV0&A&*0Vtem",W
mo3( 0&A&*0
s3a"( bgVWVtem",.
s3a"( bgVWVtem",W
4D&*4A
S++++++++++++++++++++++++++++++++++++++++++ /A6A ++++++++++++++++++++++++++++++++++++++++
main 1E4WD&
bt(ss mainV(lags,DIDV1,//AAD
goto mainV100
mol3 a?A?
sub3( command,W
bt(ss 0&A&*0,Q
goto mainV10
S set set"oint alue
rl( arg0,(
clrc
rr( arg1,(
rr( arg0,(
mo( arg0,3
mo3( set"ointVl
mo( arg1,3
mo3( set"ointV!
clr( errorVsum0 Sreset t!e integration sum
clr( errorVsum1
clr( errorVsum2
clr( errorVsum3
bc( mainV(lags,DIDV1,//AAD
goto mainV100
mainV10 mol3 a?-?
sub3( command,W
bt(ss 0&A&*0,Q
goto mainV20
S set 2W/ alue
bc( mainV(lags,1,A&4,EVDAA-ED
Sturn o(( t!e 26D "rocess because 3e are manually setting t!e out"ut Sduty cycle (or diagnostic reasons
rl( arg0,(
clrc
rr( arg1,(
rr( arg0,( S!ig!Blo3 no3 re+assembled as 14+bit
mo( arg1,3
mo3( 2W/V!
mo( arg0,3
mo3( 2W/Vl
call setV2W/
4%
goto mainV100
mainV20 mol3 a?1?
sub3( command,W
bt(ss 0&A&*0,Q
goto mainV30
S set K" alue
rl( arg0,(
clrc
rr( arg1,(
mo( arg1,3
mo3( #"V!
mo( arg0,3
mo3( #"Vl
goto mainV100
mainV30 mol3 a?D?
sub3( command,W
bt(ss 0&A&*0,Q
goto mainV40
S set Ki alue
rl( arg0,(
clrc
rr( arg1,(
mo( arg1,3
mo3( #iV!
mo( arg0,3
mo3( #iVl
goto mainV100
mainV40 mol3 a?D?
sub3( command,W
bt(ss 0&A&*0,Q
goto mainV50
S set Kd alue
rl( arg0,(
clrc
rr( arg1,(
mo( arg1,3
mo3( #dV!
mo( arg0,3
mo3( #dVl
goto mainV100
mainV50 mol3 a?.?
sub3( command,W
bt(ss 0&A&*0,Q
goto mainV%0
S re"ort running con(ig
mo( t'Vbu((Vinde',(
bt(ss 0&A&*0,Q
goto mainV55
mo( set"ointVl,3
mo3( t'Vbu((V7
mo( set"ointV!,3
mo3( t'Vbu((V%
mo( #"Vl,3
mo3( t'Vbu((V5
mo( #"V!,3
mo3( t'Vbu((V4
mo( #iVl,3
mo3( t'Vbu((V3
mo( #iV!,3
mo3( t'Vbu((V2
47
mo( #dVl,3
mo3( t'Vbu((V1
mo( #dV!,3
mo3( t'Vbu((V0
mol3 d?7?
mo3( t'Vbu((Vinde'
mol3 sendingVdata
mo3( transmitVstate
mainV55 bc( mainV(lags,DIDV1,//AAD
goto mainV100
mainV%0 mol3 a?P?
sub3( command,W
bt(ss 0&A&*0,Q
goto mainV70
S re"ort u"time <seconds since boot=
mo( t'Vbu((Vinde',(
bt(ss 0&A&*0,Q
goto mainV%5
mo( errorVsum0,3
mo3( t'Vbu((V3
mo( errorVsum1,3
mo3( t'Vbu((V2
mo( errorVsum2,3
mo3( t'Vbu((V1
mo( errorVsum3,3
mo3( t'Vbu((V0
mol3 d?3?
mo3( t'Vbu((Vinde'
mol3 sendingVdata
mo3( transmitVstate
mainV%5 bc( mainV(lags,DIDV1,//AAD
goto mainV100
mainV70 mol3 a?;?
sub3( command,W
bt(ss 0&A&*0,Q
goto mainV50
S re"ort all stats <4/0 no3, line "eriod, drie, u"time=
mo( t'Vbu((Vinde',(
bt(ss 0&A&*0,Q
goto mainV75
mo( 4/0Vno3Vl,3
mo3( t'Vbu((V7
mo( 4/0Vno3V!,3
mo3( t'Vbu((V%
mo( lineV"eriodVl,3
mo3( t'Vbu((V5
mo( lineV"eriodV!,3
mo3( t'Vbu((V4
mo( 2W/Vl,3
mo3( t'Vbu((V3
mo( 2W/V!,3
mo3( t'Vbu((V2
mo( u"timeVl,3
mo3( t'Vbu((V1
mo( u"timeV!,3
mo3( t'Vbu((V0
mol3 d?7?
mo3( t'Vbu((Vinde'
mol3 sendingVdata
mo3( transmitVstate
mainV75 bc( mainV(lags,DIDV1,//AAD
goto mainV100
mainV50 mol3 a?6?
sub3( command,W
bt(ss 0&A&*0,Q
goto mainV$0
S 3rite running con(ig <26D constants and set"oint= to A7 memory
45
mo( set"ointV!,W
bs( 0&A&*0,421
mo3( DDDA&A
mol3 DDVset"ointV!
call 3riteVDD
mo( set"ointVl,W
bs( 0&A&*0,421
mo3( DDDA&A
mol3 DDVset"ointVl
call 3riteVDD
mo( #"Vl,W
bs( 0&A&*0,421
mo3( DDDA&A
mol3 DDV#"Vl
call 3riteVDD
mo( #"V!,W
bs( 0&A&*0,421
mo3( DDDA&A
mol3 DDV#"V!
call 3riteVDD
mo( #iVl,W
bs( 0&A&*0,421
mo3( DDDA&A
mol3 DDV#iVl
call 3riteVDD
mo( #iV!,W
bs( 0&A&*0,421
mo3( DDDA&A
mol3 DDV#iV!
call 3riteVDD
mo( #dVl,W
bs( 0&A&*0,421
mo3( DDDA&A
mol3 DDV#dVl
call 3riteVDD
mo( #dV!,W
bs( 0&A&*0,421
mo3( DDDA&A
mol3 DDV#dV!
call 3riteVDD
goto mainV100
mainV$0 mol3 a?O?
sub3( command,W
bt(ss 0&A&*0,Q
goto mainV100
S re+enable 26D "rocess and clear integral sum
clr( errorVsum0
clr( errorVsum1
clr( errorVsum2
clr( errorVsum3
bs( mainV(lags,1,A&4,EVDAA-ED
goto mainV100
S++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
S deal 3it! serial t' bu((er
mainV100 mo( transmitVstate,3
subl3 transmitVidle
bt(ss 0&A&*0,Q
goto mainV110
Stransmit idle state
goto mainV200
mainV110 mo( transmitVstate,3
subl3 sendingVdata
bt(ss 0&A&*0,Q
goto mainV120
4$
Ssending bu((er contents state
bt(ss 2641,&I6.
goto mainV200
mainV111 mol3 t'Vbu((V0
add3( t'Vbu((Vinde',3
mo3( .04
mo( 6AD.,3
mo3( &I4DP
mo( t'Vbu((Vinde',(
bt(ss 0&A&*0,Q
goto mainV112
mol3 transmitVidle
mo3( transmitVstate
goto mainV200
mainV112 dec( t'Vbu((Vinde',(
mainV120
Ssome ot!er t' state
mainV200 bt(ss mainV(lags,0A/2ED
goto mainV300
S add latest sam"le into sum (or later aeraging
call clrb
mo( sam"leVl,3
mo3( 4DP-0
mo( sam"leV!,3
mo3( 4DP-1
call moaccuma
call add32
call moaaccum
bc( mainV(lags,0A/2ED
dec(sG sam"leVcount,(
goto mainV300
Send o( sam"le grou" + diide by sam"le count to (ind aerage
SA still contains sum
call clrb
mol3 d?%?
mo3( 4DP-0
call di32
call round
mo( 4DPA0,3
mo3( 4/0Vno3Vl
mo( 4DPA1,3
mo3( 4/0Vno3V!
mol3 d?%? Sre+initialiGe sam"le aeraging ars
mo3( sam"leVcount
mainV220 bs( 2,4&-,4
Ss#i" (urt!er calcs and out"ut i( control is not enabled <(or diagnostics=
bt(ss mainV(lags,1,A&4,EVDAA-ED
goto mainV300
Scalculate "resent error
call clra
mo( set"ointVl,3
mo3( 4DPA0
mo( set"ointV!,3
mo3( 4DPA1
call clrb
mo( 4/0Vno3Vl,3
mo3( 4DP-0
mo( 4/0Vno3V!,3
mo3( 4DP-1
call sub32
call moad Sco"y "resent error into D (or later use
Smulti"ly t!e "resent error by K" <"ro"ortional gain= and store to Accumulator A
call clrb
mo( #"Vl,3
mo3( 4DP-0
mo( #"V!,3
mo3( 4DP-1
call mult32 SA no3 !olds DMK"
50
call moaaccum Sco"y DMK" into accumulator A
Sadd t!is latest error into errorsum and (actor to get 6 term
call modb Sget "resent error (rom storage into -
call clra
mo( errorVsum0,3
mo3( 4DPA0
mo( errorVsum1,3
mo3( 4DPA1
mo( errorVsum2,3
mo3( 4DPA2
mo( errorVsum3,3
mo3( 4DPA3
Stest (or out"ut satuation (lag and s#i" t!e integration o( "resent error
S i( set + !is is t!e integral anti+3indu" mec!anism
bt(sc mainV(lags,/7V0A&*4A&6,A
goto mainV230
call add32 Sadd r"esent error into integral sum
mo( 4DPA0,3
mo3( errorVsum0
mo( 4DPA1,3
mo3( errorVsum1
mo( 4DPA2,3
mo3( errorVsum2
mo( 4DPA3,3
mo3( errorVsum3
mainV230 call clrb
mo( #iVl,3 Smulti"ly error !istory integral by Ki
mo3( 4DP-0
mo( #iV!,3
mo3( 4DP-1
call mult32 SA no3 !olds 6
call moaccumb
call add32
call moaaccum Saccumulator no3 !olds 2L6
Scalc diriitie <last error+t!is error=
mo( lastVerror0,3 S "ut t!e last error in A
mo3( 4DPA0
mo( lastVerror1,3
mo3( 4DPA1
mo( lastVerror2,3
mo3( 4DPA2
mo( lastVerror3,3
mo3( 4DPA3
mo( 4DPD0,3 S"ut t!e "resent error in -
mo3( 4DP-0
mo( 4DPD1,3
mo3( 4DP-1
mo( 4DPD2,3
mo3( 4DP-2
mo( 4DPD3,3
mo3( 4DP-3
call sub32 S subtract last+"resent
call clrb
mo( #dVl,3
mo3( 4DP-0
mo( #dV!,3
mo3( 4DP-1
call mult32 SA no3 !olds <last+no3=MKd
call moaccumb
call add32
call clraccum Sclear accumulator (or sam"le+aeraging
S store "resent error (or diriitie calc on ne't cycle
mo( 4DPD0,3
mo3( lastVerror0
mo( 4DPD1,3
mo3( lastVerror1
51
mo( 4DPD2,3
mo3( lastVerror2
mo( 4DPD3,3
mo3( lastVerror3
Sscale 26D result bac# by 1000
call clrb
mol3 !?e5?
mo3( 4DP-0
mol3 !?03?
mo3( 4DP-1
call di32
call round
call moad Sstore 26D result in D (or sae #ee"ing
SA no3 !olds (inal signed 26D result + limit it to !ig!Blo3 bounds and a""ly it to t!e out"ut
call clrb
mol3 !?((?
mo3( 4DP-0
mol3 !?03?
mo3( 4DP-1
call scm"32
bt(sc 0&A&*0,1
goto mainV250
S26D (inal result is greater t!an 1023 + limit it
bs( mainV(lags,/7V0A&*4A&6,A
mol3 !?((?
mo3( 2W/Vl
mol3 !?03?
mo3( 2W/V!
call setV2W/
goto mainV400
mainV250 S26D result is 1023 or less <maybe negatie=
call moda Srecoer 26D result (rom storage
call clrb
mol3 d?30? S%H o( 1023
mo3( 4DP-0
call scm"32
bt(ss 0&A&*0,1
goto mainV250
S resulting 2W/ is too small + limit to minimum <15H=
bs( mainV(lags,/7V0A&*4A&6,A
clr( 2W/V!
mol3 d?30?
mo3( 2W/Vl
call setV2W/
goto mainV400
mainV250 S 26D result is 3it!in usabale range + a""ly to 2W/ module
bc( mainV(lags,/7V0A&*4A&6,A
call moda Srecoer 26D result (rom storage
mo( 4DPA0,3
mo3( 2W/Vl
mo( 4DPA1,3
mo3( 2W/V!
call setV2W/
mainV300
mainV400 bc( 2,4&-,4
goto main
STTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT
init 1E4. 2,4&A
1E4. 2,4&-
-0. 0&A&*0, 420
S++++++++++++++!ig! ban# registers
/,7EW b?00001101?
/,7W. &460A
52
/,7EW b?00000101?
/,7W. &460-
/,7EW -?11000111?
/,7W. ,2&6,AV4DP
/,7EW b?11110000?
/,7W. AD1,A1
/,7EW b?00001101?
/,7W. AA0DE
/,7EW -?01100000?
/,7W. 26D1
/,7EW !?..?
/,7W. 242
/,7EW -?00100100?
/,7W. &I0&A
/,7EW d?%4? Sbaud rate generator constant (or $%00 b"s @ 10m!G cloc#
/,7W. 02-4P
S++++++++++++++!ig! ban# registers
-1. 0&A&*0, 420
/,7EW -?10010000?
/,7W. 410&A
/,7EW -?11110000?
/,7W. 6A&1,A
/,7EW -?00000111?
/,7W. 1/1,A S 1/1,AT7 set com"erators o((
/,7EW b?10000001?
/,7W. AD1,A0
/,7EW b?00001100?
/,7W. 11211,A
/,7EW b?00000000?
/,7W. 11241E
/,7EW b?00010101?
/,7W. &11,A
/,7EW b?00000100?
/,7W. &21,A
clr( mainV(lags
clr( receieVstate
clr( transmitVstate
clr( t'Vbu((Vinde'
bs( mainV(lags,1,A&4,EVDAA-ED
mol3 d?1?
mo3( address
S "ull 26D and set"oint (rom A7 memory
mol3 DDVset"ointV!
call readVDD
mo3( set"ointV!
mol3 DDVset"ointVl
call readVDD
mo3( set"ointVl
mol3 DDV#"V!
call readVDD
mo3( #"V!
mol3 DDV#"Vl
call readVDD
mo3( #"Vl
mol3 DDV#iV!
call readVDD
mo3( #iV!
mol3 DDV#iVl
call readVDD
mo3( #iVl
mol3 DDV#dV!
call readVDD
mo3( #dV!
mol3 DDV#dVl
call readVDD
mo3( #dVl
bc( 0&A&*0,642
mol3 d?%?
53
mo3( sam"leVcount
call clraccum
clr( errorVsum0
clr( errorVsum1
clr( errorVsum2
clr( errorVsum3
clr( lastVerror0
clr( lastVerror1
clr( lastVerror2
clr( lastVerror3
clr( u"timeV!
clr( u"timeVl
goto main
S+++++++++++++++++++++++++++++++++++++++++++++++++
setV2W/ mo( 2W/V!,3
mo3( tem"2
mo( 2W/Vl,3
mo3( tem"1
bc( 11211,A,4
bc( 11211,A,5
rr( tem"2,(
rr( tem"1,(
bt(sc 0&A&*0,1
bs( 11211,A,4
rr( tem"2,(
rr( tem"1,(
bt(sc 0&A&*0,1
bs( 11211,A,5
mo( tem"1,3
mo3( 11241E
return
Ssigned, 32bit com"are <A,-=
scm"32 call sub32
bt(ss 4DPA3,7 Sc!ec# sign bit
goto scm"32.10
Sresult o( A+- is negatie. AX-
bs( 0&A&*0,1
bc( 0&A&*0,Q
goto scm"32.end
scm"32.10SA+- is 0 or "ositie
mo( 4DPA0,( Stest byte0 (or 0
bt(ss 0&A&*0,Q
goto scm"32.20
bt(ss 0&A&*0,Q
goto scm"32.20
bt(ss 0&A&*0,Q
goto scm"32.20
bt(ss 0&A&*0,Q
goto scm"32.20
S all 4 bytes o( t!e A+- result are 0. AT-
bs( 0&A&*0,1
bs( 0&A&*0,Q
goto scm"32.end
scm"32.20S one o( t!e 4 bytes 3as non+0. AY-
bc( 0&A&*0,1
bc( 0&A&*0,Q
scm"32.end return
SMMM 32 -6& 06PADD 0*&4A1& MMM
S4DPA + 4DP- +Y 4DPA
54
S4eturn carry set i( oer(lo3
sub32 call negateb SAegate 4DP-
s#"nc
return S,er(lo3
SMMM 32 -6& 06PADD ADD MMM
S4DPA L 4DP- +Y 4DPA
add32 mo( 4DPA3,3 S1om"are signs
'or3( 4DP-3,3
mo3( /&D/2
call addba SAdd 4DP- to 4DPA
clrc S1!ec# signs
mo( 4DP-3,3 S6( signs are same
'or3( 4DPA3,3 Sso must result sign
bt(ss /&D/2,7 Selse oer(lo3
addl3 0'50
return
SMMM 32 -6& 06PADD /*E&62E> MMM
S4DPA M 4DP- +Y 4DPA
mult32 clr( /&D/2 S4eset sign (lag
call absa S/a#e 4DPA "ositie
s#"c
call absb S/a#e 4DP- "ositie
s#"nc
return S,er(lo3
call moac S/oe 4DPA to 4DP1
call clra S1lear "roduct
mol3 D?31? SEoo" counter
mo3( /1,*A&
muloo" call slac S0!i(t le(t "roduct and multi"licand
rl( 4DP13,3 S&est /0- o( multi"licand
s#"nc S6( multi"licand bit is a 1 t!en
call addba Sadd multi"lier to "roduct
s#"c S1!ec# (or oer(lo3
rl( 4DPA3,3
s#"nc
return
dec(sG /1,*A&,( SAe't
goto muloo"
bt(sc /&D/2,0 S1!ec# result sign
call negatea SAegatie
return
SMMM 32 -6& 06PADD D676DD MMM
S4DPA B 4DP- +Y 4DPA
S4emainder in 4DP1
S4eturn carry set i( oer(lo3 or diision by Gero
di32 clr( /&D/2 S4eset sign (lag
mo( 4DP-0,3 S&ra" diision by Gero
ior3( 4DP-1,3
ior3( 4DP-2,3
ior3( 4DP-3,3
subl3 0
s#"c
call absa S/a#e diidend <4DPA= "ositie
s#"c
call absb S/a#e diisor <4DP-= "ositie
s#"nc
return S,er(lo3
clr( 4DP10 S1lear remainder
clr( 4DP11
clr( 4DP12
clr( 4DP13
call slac S2urge sign bit
mol3 D?31? SEoo" counter
mo3( /1,*A&
dloo" call slac S0!i(t diidend <4DPA= msb into remainder <4DP1=
55
mo( 4DP-3,3 S&est i( remainder <4DP1= YT diisor <4DP-=
sub3( 4DP13,3
s#"G
goto dtstgt
mo( 4DP-2,3
sub3( 4DP12,3
s#"G
goto dtstgt
mo( 4DP-1,3
sub3( 4DP11,3
s#"G
goto dtstgt
mo( 4DP-0,3
sub3( 4DP10,3
dtstgt s#"c S1arry set i( remainder YT diisor
goto dremlt
mo( 4DP-0,3 S0ubtract diisor <4DP-= (rom remainder <4DP1=
sub3( 4DP10,(
mo( 4DP-1,3
s#"c
inc(sG 4DP-1,3
sub3( 4DP11,(
mo( 4DP-2,3
s#"c
inc(sG 4DP-2,3
sub3( 4DP12,(
mo( 4DP-3,3
s#"c
inc(sG 4DP-3,3
sub3( 4DP13,(
clrc
bs( 4DPA0,0 S0et )uotient bit
dremlt dec(sG /1,*A&,( SAe't
goto dloo"
bt(sc /&D/2,0 S1!ec# result sign
call negatea SAegatie
return
SMMM 4,*AD 4D0*E& ,. D67606,A &, ADA4D0& 6A&DPD4 MMM
round clr( /&D/2 S4eset sign (lag
call absa S/a#e "ositie
clrc
call slc S/ulti"ly remainder by 2
mo( 4DP-3,3 S&est i( remainder <4DP1= YT diisor <4DP-=
sub3( 4DP13,3
s#"G
goto rtstgt
mo( 4DP-2,3
sub3( 4DP12,3
s#"G
goto dtstgt
mo( 4DP-1,3
sub3( 4DP11,3
s#"G
goto rtstgt
mo( 4DP-0,3
sub3( 4DP10,3
rtstgt s#"c S1arry set i( remainder YT diisor
goto rremlt
inc(sG 4DPA0,( SAdd 1 to )uotient
goto rremlt
inc(sG 4DPA1,(
goto rremlt
inc(sG 4DPA2,(
goto rremlt
inc( 4DPA3,(
s#"nG
return S,er(lo3,return carry set
5%
rremlt bt(sc /&D/2,0 S4estore sign
call negatea
return
SAdd 4DP- to 4DPA <*nsigned=
S*sed by add, multi"ly,
addba mo( 4DP-0,3 SAdd lo byte
add3( 4DPA0,(
mo( 4DP-1,3 SAdd mid+lo byte
s#"nc SAo carryVin, so Just add
inc(sG 4DP-1,3 SAdd carryVin to 4DP-
add3( 4DPA1,( SAdd and "ro"agate carryVout
mo( 4DP-2,3 SAdd mid+!i byte
s#"nc
inc(sG 4DP-2,3
add3( 4DPA2,(
mo( 4DP-3,3 SAdd !i byte
s#"nc
inc(sG 4DP-3,3
add3( 4DPA3,(
return
negateb mo( 4DP-3,3 S0ae sign in 3
andl3 0'50
com( 4DP-0,( S2?s com"lement
com( 4DP-1,(
com( 4DP-2,(
com( 4DP-3,(
inc(sG 4DP-0,(
goto negb1
inc(sG 4DP-1,(
goto negb1
inc(sG 4DP-2,(
goto negb1
inc( 4DP-3,(
negb1 inc( /&D/2,( S(li" sign (lag
add3( 4DP-3,3 S4eturn carry set i( +2147453%45
return
S1!ec# sign o( 4DPA and conert negatie to "ositie
S*sed by multi"ly, diide, bin2dec, round
absa rl( 4DPA3,3
s#"c
return S2ositie
SAegate 4DPA
S*sed by absa, multi"ly, diide, bin2dec, dec2bin, round
negatea mo( 4DPA3,3 S0ae sign in 3
andl3 0'50
com( 4DPA0,( S2?s com"lement
com( 4DPA1,(
com( 4DPA2,(
com( 4DPA3,(
inc(sG 4DPA0,(
goto nega1
inc(sG 4DPA1,(
goto nega1
inc(sG 4DPA2,(
goto nega1
inc( 4DPA3,(
nega1 inc( /&D/2,( S(li" sign (lag
add3( 4DPA3,3 S4eturn carry set i( +2147453%45
return
S1!ec# sign o( 4DP- and conert negatie to "ositie
S*sed by multi"ly, diide
absb rl( 4DP-3,3
s#"c
return S2ositie
57
S0!i(t le(t 4DPA and 4DP1
S*sed by multi"ly, diide, round
slac rl( 4DPA0,(
rl( 4DPA1,(
rl( 4DPA2,(
rl( 4DPA3,(
slc rl( 4DP10,(
rl( 4DP11,(
rl( 4DP12,(
rl( 4DP13,(
return
S/oe 4DPA to 4DP1
S*sed by multi"ly, s)rt
moac mo( 4DPA0,3
mo3( 4DP10
mo( 4DPA1,3
mo3( 4DP11
mo( 4DPA2,3
mo3( 4DP12
mo( 4DPA3,3
mo3( 4DP13
return
S1lear 4DP-
clrb clr( 4DP-0
clr( 4DP-1
clr( 4DP-2
clr( 4DP-3
return
S1lear 4DP- and 4DPA
S*sed by s)rt
clrba clr( 4DP-0
clr( 4DP-1
clr( 4DP-2
clr( 4DP-3
S1lear 4DPA
S*sed by multi"ly, s)rt
clra clr( 4DPA0
clr( 4DPA1
clr( 4DPA2
clr( 4DPA3
return
S/oe 4DPA to 4DPD
moad mo( 4DPA0,3
mo3( 4DPD0
mo( 4DPA1,3
mo3( 4DPD1
mo( 4DPA2,3
mo3( 4DPD2
mo( 4DPA3,3
mo3( 4DPD3
return
S/oe 4DPD to 4DPA
moda mo( 4DPD0,3
mo3( 4DPA0
mo( 4DPD1,3
mo3( 4DPA1
mo( 4DPD2,3
mo3( 4DPA2
mo( 4DPD3,3
mo3( 4DPA3
return
S/oe 4DPD to 4DP-
55
modb mo( 4DPD0,3
mo3( 4DP-0
mo( 4DPD1,3
mo3( 4DP-1
mo( 4DPD2,3
mo3( 4DP-2
mo( 4DPD3,3
mo3( 4DP-3
return
S/oe 4DPA to A11*/
moaaccum mo( 4DPA0,3
mo3( A11*/0
mo( 4DPA1,3
mo3( A11*/1
mo( 4DPA2,3
mo3( A11*/2
mo( 4DPA3,3
mo3( A11*/3
return
S/oe A11*/ to 4DPA
moaccuma mo( A11*/0,3
mo3( 4DPA0
mo( A11*/1,3
mo3( 4DPA1
mo( A11*/2,3
mo3( 4DPA2
mo( A11*/3,3
mo3( 4DPA3
return
S/oe A11*/ to 4DP-
moaccumb mo( A11*/0,3
mo3( 4DP-0
mo( A11*/1,3
mo3( 4DP-1
mo( A11*/2,3
mo3( 4DP-2
mo( A11*/3,3
mo3( 4DP-3
return
clraccum clr( A11*/0
clr( A11*/1
clr( A11*/2
clr( A11*/3
return
Scall 3it! DD aadress <0+255= in W, and data "re+loaded in DDdata
S 3ill disable interu"ts and loc# until 3rite com"lete
3riteVDD bc( 6A&1,A,P6D
bc( 0&A&*0,420
bs( 0&A&*0,421
mo3( DDAD4
bs( 0&A&*0,420
bc( DD1,A1,DD2PD
bs( DD1,A1,W4DA
mol3 !?55?
mo3( DD1,A2
mol3 !?AA?
mo3( DD1,A2
bs( DD1,A1,W4
3riteVDD.10 bt(sc DD1,A1,W4
goto 3riteVDD.10
bc( DD1,A1,W4DA
bc( 0&A&*0,420
bc( 0&A&*0,421
bs( 6A&1,A,P6D
return
5$
Scall 3it! address <0+255= in W
S returns DD data alue in W
readVDD bc( 0&A&*0,420
bs( 0&A&*0,421
mo3( DDAD4
bs( 0&A&*0,420
bc( DD1,A1,DD2PD
bs( DD1,A1,4D
bc( 0&A&*0,420
mo( DDDA&A,W
bc( 0&A&*0,420
bc( 0&A&*0,421
return
end
%0
A$$en!i2 " A "ata Sheets
%1
1
LTC1968
1968f
Precision Wide Bandwidth,
RMS-to-DC Converter
High Linearity:
0.02% Linearity Allows Simple System Calibration
Wide Input Bandwidth:

Bandwidth to 1% Additional Gain Error: 500kHz
Bandwidth to 0.1% Additional Gain Error: 150kHz
3dB Bandwidth Independent of Input Voltage
Amplitude
No-Hassle Simplicity:
True RMS-DC Conversion with Only One External
Capacitor
Delta Sigma Conversion Technology
Ultralow Shutdown Current:

0.1A
Flexible Inputs:
Differential or Single Ended
Rail-to-Rail Common Mode Voltage Range
Up to 1V
PEAK
Differential Voltage
Flexible Output:
Rail-to-Rail Output
Separate Output Reference Pin Allows Level Shifting
Small Size:
Space Saving 8-Pin MSOP Package
True RMS Digital Multimeters and Panel Meters
True RMS AC + DC Measurements

DESCRIPTIO
U
FEATURES
APPLICATIO S
U
The LTC
1968 is a true RMS-to-DC converter that uses an

innovative delta-sigma computational technique. The ben-
efits of the LTC1968 proprietary architecture, when com-
pared to conventional log-antilog RMS-to-DC converters,
are higher linearity and accuracy, bandwidth independent
of amplitude and improved temperature behavior.
The LTC1968 operates with single-ended or differential in-
put signals and accurately supports crest factors up to 4.
Common mode input range is rail-to-rail. Differential in-
put range is 1V
PEAK
, and offers unprecedented linearity. The
LTC1968 allows hassle-free system calibration at any in-
put voltage.
The LTC1968 has a rail-to-rail output with a separate out-
put reference pin providing flexible level shifting; it oper-
ates on a single power supply from 4.5V to 5.5V. A low power
shutdown mode reduces supply current to 0.1A.
The LTC1968 is packaged in the space-saving MSOP pack-
age, which is ideal for portable applications.
Single Supply RMS-to-DC Converter
C
AVE
10F
V
OUT
+
1968 TA01
4.5V TO 5.5V
OUTPUT
DIFFERENTIAL
INPUT
LTC1968
V
+
0.1F
OPT. AC
COUPLING
EN GND
OUT RTN
IN1
IN2
TYPICAL APPLICATIO
U
V
IN
(mV AC
RMS
)
0
1.0
L
I
N
E
A
R
I
T
Y

E
R
R
O
R

(
V
O
U
T

m
V

D
C

V
I
N

m
V

A
C
R
M
S
)
0.8
0.6
0.4
0.2
0
0.2
100 200 300 400
1968 TA01b
500
LTC1968,
60Hz SINEWAVE
CONVENTIONAL
LOG/ANTILOG
Linearity Performance
, LTC and LT are registered trademarks of Linear Technology Corporation.
Protected under U.S. Patent Numbers 6,359,576, 6,362,677 and 6,516,291
2
LTC1968
1968f
Supply Voltage
V
+
to GND............................................................. 6V
Input Currents (Note 2) ..................................... 10mA
Output Current (Note 3) ..................................... 10mA
ENABLE Voltage ......................................... 0.3V to 6V
OUT RTN Voltage........................................ 0.3V to V
+
Operating Temperature Range (Note 4)
LTC1968C/LTC1968I ......................... 40C to 85C
Specified Temperature Range (Note 5)
LTC1968C/LTC1968I ......................... 40C to 85C
Maximum Junction Temperature ......................... 150C
Storage Temperature Range ................ 65C to 150C
Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART
NUMBER
LTC1968CMS8
LTC1968IMS8
T
JMAX
= 150C,
JA
= 220C/ W
ABSOLUTE AXI U RATI GS
WW WU
PACKAGE/ORDER I FOR ATIO
U U W
(Note 1)
MS8 PART MARKING
LTAFG
The denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= 25C. V
+
= 5V, V
OUTRTN
= 2.5V, C
AVE
= 10F, V
IN
= 200mV
RMS
, V
ENABLE
= 0.5V
unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The temperature grade (I or C) is indicated on the shipping container.
1
2
3
4
GND
IN1
IN2
NC
8
7
6
5
ENABLE
V
+
OUT RTN
V
OUT
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Conversion Accuracy
G
ERR
Low Frequency Gain Error 50Hz to 20kHz Input (Notes 6, 7) 0.1 0.3 %
0.4 %
V
OOS
Output Offset Voltage (Notes 6, 7) 0.2 0.75 mV
V
OOS
/T Output Offset Voltage Drift (Note 11) 2 10 V/C
LIN
ERR
Linearity Error 50mV to 350mV (Notes 7, 8) 0.02 0.15 %
PSRRG Power Supply Rejection (Note 9) 0.02 0.20 %/V
0.25 %/V
V
IOS
Input Offset Voltage (Notes 6, 7, 10) 0.4 1.5 mV
V
IOS
/T Input Offset Voltage Drift (Note 11) 2 10 V/C
Additional Error vs Crest Factor (CF)
CF = 3 60Hz Fundamental, 200mV
RMS
0.2 mV
CF = 5 60Hz Fundamental, 200mV
RMS
5 mV
Input Characteristics
V
IMAX
Maximum Peak Input Swing Accuracy = 1% (Note 14) 1 1.05 V
I
VR
Input Voltage Range 0 V
+
V
Z
IN
Input Impedance Average, Differential (Note 12) 1.2 M
Average, Common Mode (Note 12) 100 M
CMRRI Input Common Mode Rejection (Note 13) 50 400 V/V
V
IMIN
Minimum RMS Input 5 mV
PSRRI Power Supply Rejection (Note 9) 250 700 V/V
3
LTC1968
1968f
The denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= 25C. V
+
= 5V, V
OUTRTN
= 2.5V, C
AVE
= 10F, V
IN
= 200mV
RMS
, V
ENABLE
= 0.5V
unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The inputs (IN1, IN2) are protected by shunt diodes to GND and
V
+
. If the inputs are driven beyond the rails, the current should be limited
to less than 10mA.
Note 3: The LTC1968 output (V
OUT
) is high impedance and can be
overdriven, either sinking or sourcing current, to the limits stated.
Note 4: The LTC1968C/LTC1968I are guaranteed functional over the
operating temperature range of 40C to 85C.
Note 5: The LTC1968C is guaranteed to meet specified performance from
0C to 70C. The LTC1968C is designed, characterized and expected to
meet specified performance from 40C to 85C but is not tested nor QA
sampled at these temperatures. The LTC1968I is guaranteed to meet
specified performance from 40C to 85C.
Note 6: High speed automatic testing cannot be performed with
C
AVE
= 10F. The LTC1968 is 100% tested with C
AVE
= 47nF.
Note 7: The LTC1968 is 100% tested with DC and 10kHz input signals.
Measurements with DC inputs from 50mV to 350mV are used to calculate
the four parameters: G
ERR
, V
OOS
, V
IOS
and linearity error. Correlation tests
have shown that the performance limits can be guaranteed with the
additional testing being performed to guarantee proper operation of all
internal circuitry.
Note 8: The LTC1968 is inherently very linear. Unlike older log/antilog
circuits, its behavior is the same with DC and AC inputs, and DC inputs are
used for high speed testing.
Note 9: The power supply rejections of the LTC1968 are measured with
DC inputs from 50mV to 350mV. The change in accuracy from V
+
= 4.5V
to V
+
= 5.5V is divided by 1V.
Note 10: Previous generation RMS-to-DC converters required nonlinear
input stages as well as a nonlinear core. Some parts specify a DC reversal
error, combining the effects of input nonlinearity and input offset voltage.
The LTC1968 behavior is simpler to characterize and the input offset
voltage is the only significant source of DC reversal error.
Note 11: Guaranteed by design.
Note 12: The LTC1968 is a switched capacitor device and the input/output
impedance is an average impedance over many clock cycles. The input
impedance will not necessarily lead to an attenuation of the input signal
measured. Refer to the Applications Information section titled Input
Impedance for more information.
Note 13: The common mode rejection ratios of the LTC1968 are measured
with DC inputs from 50mV to 350mV. The input CMRR is defined as the
change in V
IOS
measured with the input common mode voltage at 0V and
V
+
, divided by V
+
. The output CMRR is defined as the change in V
OOS
measured with OUT RTN = 0V and OUT RTN = V
+
350mV divided by
V
+
350mV.
Note 14: The LTC1968 input and output voltage swings are limited by
internal clipping. However, its topology is relatively tolerant of
momentary internal clipping.
Note 15: The LTC1968 exploits oversampling and noise shaping to reduce
the quantization noise of internal 1-bit analog-to-digital conversions. At
higher input frequencies, increasingly large portions of this noise are
aliased down to DC. Because the noise is shifted in frequency, it becomes
a low frequency rumble and is only filtered at the expense of increasingly
long settling times. The LTC1968 is inherently wideband, but the output
accuracy is degraded by this aliased noise.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Characteristics
OVR Output Voltage Range 0 V
+
V
Z
OUT
Output Impedance (Note 12) 10 12.5 16 k
CMRRO Output Common Mode Rejection (Note 13) 50 250 V/V
V
OMAX
Maximum Differential Output Swing Accuracy = 1%, DC Input (Note 14) 1.0 1.05 V
0.9 V
PSRRO Power Supply Rejection (Note 9) 250 1000 V/V
Frequency Response
f
1P
1% Additional Gain Error (Note 15) 500 kHz
f
3dB
3dB Frequency (Note 15) 15 MHz
Power Supplies
V
+
Supply Voltage 4.5 5.5 V
I
S
Supply Current IN1 = 20mV, IN2 = 0V 2.3 2.7 mA
IN1 = 200mV, IN2 = 0V 2.4 mA
Shutdown Characteristics
I
SS
Supply Current V
ENABLE
= 4.5V 0.1 10 A
I
IH
ENABLE Pin Current High V
ENABLE
= 4.5V 1 0.1 A
I
IL
ENABLE Pin Current Low V
ENABLE
= 0.5V 3 0.5 0.1 A
V
TH
ENABLE Threshold Voltage 2.1 V
V
HYS
ENABLE Threshold Hysteresis 0.1 V
5-1
Semiconductor
Features
25A and 28A, 80V and 100V
r
DS(ON)
= 0.077 and 0.100
Single Pulse Avalanche Energy Rated
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Related Literature
- TB334 Guidelines for Soldering Surface Mount
Components to PC Boards
Description
These are N-Channel enhancement mode silicon gate
power eld effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specied level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching conver-
tors, motor drivers, relay drivers, and drivers for high power
bipolar switching transistors requiring high speed and low
gate drive power. These types can be operated directly from
integrated circuits.
Formerly developmental type TA17421.
Symbol
Packaging
JEDEC TO-220AB JEDEC TO-262AA
JEDEC TO-263AB
Ordering Information
PART NUMBER PACKAGE BRAND
IRF540 TO-220AB IRF540
RF1S540 TO-262AA RF1S540
RF1S540SM TO-263AB RF1S540SM
NOTE: When ordering, use the entire part number. Add the sufx 9A to
obtain the TO-263AB variant in the tape and reel, i.e., RF1S540SM9A.
G
D
S
GATE
DRAIN (FLANGE)
SOURCE
DRAIN
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN
(FLANGE)
GATE
SOURCE
November 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures.
Copyright Harris Corporation 1997
File Number 2309.3
IRF540, IRF541, IRF542,
IRF543, RF1S540, RF1S540SM
25A and 28A, 80V and 100V, 0.077 and 0.100 Ohm,
N-Channel Power MOSFETs
5-2
Absolute Maximum Ratings T
C
= 25
o
C, Unless Otherwise Specied
IRF540, RF1S540,
RF1S540SM IRF541 IRF542 IRF543 UNITS
Drain to Source Breakdown Voltage (Note 1). . . . . . . . . .V
DS
100 80 100 80 V
Drain to Gate Voltage (R
GS
= 20k) (Note 1) . . . . . . . V
DGR
100 80 100 80 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
28
20
28
20
25
17
25
17
A
A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . I
DM
110 110 100 100 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
20 20 20 20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . P
D
150 150 150 150 W
Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 W/
o
C
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . E
AS
230 230 230 230 mJ
Operating and Storage Temperature . . . . . . . . . . . . T
J,
T
STG
-55 to 175 -55 to 175 -55 to 175 -55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . T
pkg
300
260
300
260
300
260
300
260
o
C
o
C
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.
NOTE:
1. T
J
= 25
o
C to T
J
= 150
o
C.
Electrical Specications T
C
= 25
o
C, Unless Otherwise Specied
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250A, V
GS
= 0V (Figure 10)
IRF540, IRF542,
RF1S540, RF1S540SM
100 - - V
IRF541, IRF543 80 - - V
Gate to Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250A 2 - 4 V
Zero Gate Voltage Drain Current I
DSS
V
DS
= Rated BV
DSS
, V
GS
= 0V - - 25 A
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V
T
J
= 150
o
C
- - 250 A
On-State Drain Current (Note 2) I
D(ON)
V
DS
> I
D(ON)
x r
DS(ON) MAX
, V
GS
= 10V
(Figure 7)
IRF540, IRF541,
RF1S540, RF1S540SM
28 - - A
IRF542, IRF543 25 - - A
Gate to Source Leakage Current I
GSS
V
GS
= 20V - - 100 nA
Drain to Source On Resistance (Note 2) r
DS(ON)
I
D
= 17A, V
GS
= 10V (Figures 8, 9)
IRF540, IRF541,
RF1S540, RF1S540SM
- 0.060 0.077
IRF542, IRF543 - 0.080 0.100
Forward Transconductance (Note 2) g
fs
V
DS
50V, I
D
= 17A (Figure 12) 8.7 13 - S
Turn-On Delay Time t
d(ON)
V
DD
= 50V
,
I
D
28A, R
G
9.1, R
L
= 1.7
(Figures 17, 18) MOSFET Switching Times are
Essentially Independent of Operating
Temperature
- 15 23 ns
Rise Time t
r
- 70 110 ns
Turn-Off Delay Time t
d(OFF)
- 40 60 ns
Fall Time t
f
- 50 75 ns
Total Gate Charge
(Gate to Source + Gate to Drain)
Q
g(TOT)
V
GS
= 10V, I
D
= 28A, V
DS
= 0.8 x Rated
BV
DSS
, I
g(REF)
= 1.5mA (Figures 14, 19, 20)
Gate Charge is Essentially Independent of Op-
erating Temperature
- 38 59 nC
Gate to Source Charge Q
gs
- 8 - nC
Gate to Drain Miller Charge Q
gd
- 21 - nC
IRF540, IRF541, IRF542, IRF543, RF1S540, RF1S540SM
5-3
Input Capacitance C
ISS
V
DS
= 25V, V
GS
= 0V, f = 1MHz
(Figure 11)
- 1450 - pF
Output Capacitance C
OSS
- 550 - pF
Reverse Transfer Capacitance C
RSS
- 100 - pF
Internal Drain Inductance L
D
Measured From the
Contact Screw on Tab
To Center of Die
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
- 3.5 - nH
Measured From the
Drain Lead, 6mm
(0.25in) from Package to
Center of Die
- 4.5 - nH
Internal Source Inductance L
S
Measured From the
Source Lead, 6mm
(0.25in) From Header to
Source Bonding Pad
- 7.5 - nH
Thermal Resistance Junction to Case R
JC
- - 1
o
C/W
Thermal Resistance
Junction to Ambient
R
JA
Free Air Operation - - 80
o
C/W
R
JA
RF1S540SM Mounted on FR-4 Board with
Minimum Mounting Pad
- - 62
o
C/W
Source to Drain Diode Specications
Continuous Source to Drain Current I
SD
Modified MOSFET Sym-
bol Showing the Integral
Reverse
P-N Junction Diode
- - 28 A
Pulse Source to Drain Current
(Note 3)
I
SDM
- - 110 A
Source to Drain Diode Voltage (Note 2) V
SD
T
J
= 25
o
C, I
SD
= 27A, V
GS
= 0V (Figure 13) - - 2.5 V
Reverse Recovery Time t
rr
T
J
= 25
o
C, I
SD
= 28A, dI
SD
/dt = 100A/s 70 150 300 ns
Reverse Recovery Charge Q
RR
T
J
= 25
o
C, I
SD
= 28A, dI
SD
/dt = 100A/s 0.44 1.0 1.9 C
NOTES:
2. Pulse test: pulse width 300s, duty cycle 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. V
DD
= 25V, starting T
J
= 25
o
C, L = 440H, R
G
= 25, peak I
AS
= 28A. (Figures 15, 16).
Electrical Specications T
C
= 25
o
C, Unless Otherwise Specied (Continued)
L
S
L
D
G
D
S
G
D
S
5-4
Typical Performance Curves Unless Otherwise Specied
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
T
C
, CASE TEMPERATURE (
o
C)
25 50 75 100 125 150 175 0
P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N

M
U
L
T
I
P
L
I
E
R
0
0.2
0.4
0.6
0.8
1.0
1.2
12
6
0
25 50 75 100 125 150
24
I
D
,

D
R
A
I
N

C
U
R
R
E
N
T

(
A
)
T
C
, CASE TEMPERATURE (
o
C)
30
175
18
IRF542, IRF543
IRF540, IRF541
RF1S540, RF1S540SM
t
1
, RECTANGULAR PULSE DURATION (s)
10
Z
J
C
,
T
R
A
N
S
I
E
N
T
10
-3
10
-2
10
-1
1
1
10
-5
10
-4
10
0.01
0.1
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
+ T
C
P
DM
t
1
t
2
0.1
0.02
0.2
0.5
0.01
0.05
SINGLE PULSE
T
H
E
R
M
A
L

I
M
P
E
D
A
N
C
E

(
o
C
/
W
)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10
1
10
1
I
D
,

D
R
A
I
N

C
U
R
R
E
N
T

(
A
)
100
100
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
T
J
= MAX RATED
SINGLE PULSE
IRF540, 1, RF1S540, SM
IRF542, 3
IRF542, 3
IRF541, 3
DC
100s
10s
1ms
I
R
F
5
4
0
,

2
R
F
1
S
5
4
0
,

S
M 10ms
IRF540, 1, RF1S540, SM
T
C
= 25
o
C
V
DS
I
D
,

D
R
A
I
N

C
U
R
R
E
N
T

(
A
)
0
0 12 24 36 48
10
20
30
40
50
60
V
GS
= 7V
V
GS
= 5V
V
GS
= 4V
80s PULSE TEST
V
GS
= 10V
V
GS
= 8V
V
GS
= 6V
5-5
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Typical Performance Curves Unless Otherwise Specied (Continued)
0
10
0 1.0 2.0 3.0 5.0
20
30
I
D
,

D
R
A
I
N

C
U
R
R
E
N
T

(
A
)
V
DS
V
GS
= 6V
V
GS
= 10V
40
4.0
V
GS
= 4V
V
GS
= 7V
V
GS
= 5V
50
V
GS
= 8V
80s PULSE TEST
0 4 6 8 10 2
0.1
1
10
I
D
(
O
N
)
,

O
N
-
S
T
A
T
E

D
R
A
I
N

C
U
R
R
E
N
T

(
A
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
100
25
o
C 175
o
C
V
DS
50V 80s PULSE TEST
DUTY CYCLE = 0.5% MAX
0
0.4
0.6
0.8
25 50 75 100
r
D
S
(
O
N
)
,

D
R
A
I
N

T
O

S
O
U
R
C
E
I
D
, DRAIN CURRENT (A)
125
1.0
0
0.2
V
GS
= 10V
V
GS
= 20V
80s PULSE DURATION
O
N

R
E
S
I
S
T
A
N
C
E

(
)
N
O
R
M
A
L
I
Z
E
D

D
R
A
I
N

T
O

S
O
U
R
C
E
3.0
1.8
1.2
0.6
0.0
-60 -40 -20 0 20 40 60
T
J
, JUNCTION TEMPERATURE (
o
C)
100 120 140 160 180
2.4
80
V
GS
= 10V, I
D
= 28A
O
N

R
E
S
I
S
T
A
N
C
E
1.25
1.05
0.95
0.85
0.75
-60 -40 -20 0 20 40 60
T
J
, JUNCTION TEMPERATURE (
o
C)
N
O
R
M
A
L
I
Z
E
D

D
R
A
I
N

T
O

S
O
U
R
C
E
B
R
E
A
K
D
O
W
N

V
O
L
T
A
G
E
100 120 140 160 180
1.15
80
I
D
= 250A
3000
600
0
1
10 100
C
,

C
A
P
A
C
I
T
A
N
C
E

(
p
F
)
1800
V
DS
2400
1200
C
ISS
C
OSS
C
RSS
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
C
DS
+ C
GD
V
GS
= 0V, f = 1MHz
5-6
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves Unless Otherwise Specied (Continued)
25
o
C
I
D
, DRAIN CURRENT (A)
g
f
s
,

T
R
A
N
S
C
O
N
D
U
C
T
A
N
C
E

(
S
)
0
0 10 20 30 40
4
8
12
16
20
50
175
o
C
V
DS
50V, 80s PULSE TEST
0 1.2 1.8 2.4 3.0 0.6
1
10
100
I
S
D
,

S
O
U
R
C
E

T
O

D
R
A
I
N

C
U
R
R
E
N
T

(
A
)
V
SD
, SOURCE TO DRAIN VOLTAGE (V)
1000
25
o
C
175
o
C
Q
g
, TOTAL GATE CHARGE (nC)
V
G
S
,

G
A
T
E

T
O

S
O
U
R
C
E

V
O
L
T
A
G
E

(
V
)
0
0 12 24 36 48
4
8
12
16
20
60
I
D
= 28A
V
DS
= 50V
V
DS
= 80V
V
DS
= 20V
5-7
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
V
GS
R
L
R
G
DUT
+
-
V
DD
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50% 50%
10%
PULSE WIDTH
V
GS
0
0
0.3F
12V
BATTERY
50k
V
DS
S
DUT
D
G
I
g(REF)
0
(ISOLATED
V
DS
0.2F
CURRENT
REGULATOR
I
D
CURRENT
SAMPLING
I
G
CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT
Q
g(TOT)
Q
gd
Q
gs
V
DS
0
V
GS
V
DD
I
G(REF)
0

EET480W

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EET480W

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Retrofit Voltage Regulator

for the 2A042 electrical generator

Wide Input Bandwidth:

Ultralow Shutdown Current:

True RMS Digital Multimeters and Panel Meters

True RMS AC + DC Measurements

1968 is a true RMS-to-DC converter that uses an

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