Intro Avr

Sistemas Microprocesados IEE633
Microcontroladores AVR
MSc. Jorge Luis Rosero B.
Escuela Politecnica Nacional
Facultad de Ingeniera Electrica y Electr onica
12 de Agosto del 2013
jorge.rosero@epn.edu.ec
Telf: 098-600-3675
Ocina: QE-211
Asesora: Lun-Mier-Jue-Vie 14:00 a 15:00
MSc. Jorge Luis Rosero B. Sistemas Microprocesados IEE633 12 de Agosto del 2013 1 / 17
Taller # 2
1
Que es un Microprocesador y un Microcontrolador?
2
Dibuje:
Ciclo Von Neumann.
Arquitectura Von Neumann.
Arquitectura Harvard.
Estructura interna de un Microprocesador y un Microcontrolador.
3
Construya un arreglo de:
768 16
5K 16
1742 16
En base a las siguientes memorias.
256 8
512 16
1K 8
2K 16
4K 8
Familia AVR (1)
Atmel AVR Microcontrollers
Enabling unlimited possibilities
Atmel AVR Microcontrollers
Atmel
AVR
8- and 32-bit microcontrollers deliver a unique combination of performance, power efficiency, and design
flexibility. Optimized to speed time to market, they are based on the industrys most code-efficient architecture for C and
assembly programming. No other microcontrollers deliver more computing performance with better power efficiency.
Industry-leading development tools and design support let you go to market faster, and once you are there, the large AVR
family lets you reuse your knowledge when improving your products and expanding to new markets - easily and cost-
effectively.
Develop easily and quickly
Atmel AVR Studio
5 is the integrated development environment for developing and debugging AVR applications. AVR Studio
5 provides a seamless and easy-to-use environment to write, build, and debug your C/C++ and assembly code. A wide
range of starter kits, reference designs, and evaluation kits are offered across the range of AVR microcontrollers. Debuggers,
programmers and compiler are offered directly from Atmel and support all AVR microcontrollers. AVR Software Framework is
provided free of charge and provides drivers for all peripherals, example code, driver documentation and reference applications
that will kick-start your AVR project with industry proven code.
Atmel AVR UC3 32-bit Microcontrollers
The Atmel AVR UC3 32-bit takes efficiency to a new level, going beyond high
performance and low power consumption. Native fixed point DSP support,
dual port SRAM, multi layer data bus, peripheral DMA controller, peripheral
event system and intelligent peripherals takes performance and power
consumption to the next step.
The peripheral DMA controller and multi-layer high-speed bus architecture
make the AVR UC3 microcontrollers ideal for high throughput applications.
tinyAVR AVR UC3 AVR XMEGA megaAVR
6-pins
0.5KB Flash
144-pins
512KB Flash
250+ Devices
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Familia AVR (2)
Empaquetados Standar (1)
www.statschippac.com
www.statschippac.com
Diagrama de Bloques Microcontrolador AVR
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8011OAVR07/10
ATmega164P/324P/644P
2. Overview
The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega164P/324P/644P achieves throughputs approaching 1 MIPS per MHz allowing the sys-
tem designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
CPU
GND
VCC
RESET
Power
Supervision
POR / BOD &
RESET
Watchdog
Oscillator
Watchdog
Timer
Oscillator
Circuits /
Clock
Generation
XTAL1
XTAL2
PORT A (8)
PORT D (8)
PD7..0
PORT C (8)
PC5..0
TWI
SPI EEPROM
JTAG/OCD
16 bit T/C 1
8 bit T/C 2
8 bit T/C 0
SRAM FLASH
USART 0
Internal
Bandgap reference
Analog
Comparator
A/D
Converter
PA7..0
PORT B (8)
PB7..0
USART 1
TOSC1/PC6 TOSC2/PC7
Arquitectura del CPU AVR
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8011OAVR07/10
4. AVR CPU Core
4.1 Overview
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 4-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
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Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
Pipeling (1)
ECE7660 Pipeline.5
Fall 2005
Sequential Laundry
Sequential laundry takes 6 hours for 4 loads
If they learned pipelining, how long would laundry take?
A
B
C
D
30 40 20 30 40 20 30 40 20 30 40 20
6 PM 7 8 9 10 11 Midnight
T
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Time
ECE7660 Pipeline.6
Fall 2005
Pipelined Laundry: Start work ASAP
Pipelined laundry takes 3.5 hours for 4 loads
A
B
C
D
T
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k
O
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Time
30 40 40 40 40
20
Pipeling (2)
ECE7660 Pipeline.5
Fall 2005
Sequential Laundry
Sequential laundry takes 6 hours for 4 loads
If they learned pipelining, how long would laundry take?
A
B
C
D
30 40 20 30 40 20 30 40 20 30 40 20
T
a
s
k
O
r
d
e
r
Time
ECE7660 Pipeline.6
Fall 2005
Pipelined Laundry: Start work ASAP
Pipelined laundry takes 3.5 hours for 4 loads
A
B
C
D
T
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k
O
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r
Time
30 40 40 40 40
20
Pipeling (3)
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8011OAVR07/10
Figure 4-5. The Parallel Instruction Fetches and Instruction Executions
Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 4-6. Single Cycle ALU Operation
4.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section Memory Program-
ming on page 293 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in Interrupts on page 61. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to Interrupts on page 61 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see Memory Programming on page 293.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
Operacion de la ALU
15
8011OAVR07/10
Figure 4-5. The Parallel Instruction Fetches and Instruction Executions
Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 4-6. Single Cycle ALU Operation
4.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section Memory Program-
ming on page 293 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in Interrupts on page 61. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to Interrupts on page 61 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see Memory Programming on page 293.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
Memoria de Programa (Flash)
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8011OAVR07/10
Figure 5-1. Program Memory Map
5.3 SRAM Data Memory
Figure 5-2 shows how the ATmega164P/324P/644P SRAM Memory is organized.
The ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can
be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For
the Extended I/O space from $060 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
The first 4,352 Data Memory locations address both the Register File, the I/O Memory,
Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register
file, the next 64 location the standard I/O Memory, then 160 locations of Extended I/O memory
and the next 4,096 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file,
registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
Application Flash Section
Boot Flash Section
Program Memory
0x1FFF
0x0000
Memoria de Datos (SRAM)
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8011OAVR07/10
The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the
1024/2048/4096 bytes of internal data SRAM in the ATmega164P/324P/644P are all accessible
through all these addressing modes. The Register File is described in General Purpose Regis-
ter File on page 12.
Figure 5-2. Data Memory Map for ATmega164P/324P/644P.
5.3.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU
cycles as described in Figure 5-3.
Figure 5-3. On-chip Data SRAM Access Cycles
32 Registers
64 I/O Registers
Internal SRAM
(1024/2048/4096 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x04FF/0x08FF/0x10FF
0x0060 - 0x00FF
Data Memory
160 Ext I/O Reg.
0x0100
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
R
e
a
d
W
r
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t
e
CPU
Memory Access Instruction Next Instruction
Registros de Prop osito General
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8011OAVR07/10
4.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
Tarea 4
Estudiar el Captulo 2 del Libro:
The AVR Microcontroller and Embedded System, Muhammad Ali
Mazidi, Sarmad Naimi, Sepehr Naimi, Prentice Hall, 2010.
Estudiar el AVR Instruction Set (Paginas: 1-9)

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