Вы находитесь на странице: 1из 3

1.

C
2. C
3. a)
an

b
tw


Convert by ad
a) A D fli
b) A T flip
c) A T flip
Complete the
) Complete t
nd asynchro

) Complete t
wo flip-flops
[So
dding extern
p-flop to a J
p-flop to a D
p-flop to a D
e following ti
the following
nous ClrN(c
the timing d
s are differen
Digital
ASS
olve all odd-
nal logic gate
J -K flip-flop
D flip-flop.
D flip-flop w
iming diagra
g timing dia
clear) and Pr
iagram for th
nt
SystemDesig
IGNMENT#5
-numbered
es:
.
with clock en
am for the J -
agram for a J
reN(pre-set)
he following
gn

problems]
able.
-K flip-flop a

J -K flip-flop
inputs.

g circuit. No
arrangement
with a fallin
ote that the C
t:
ng-edge trigg
Ck inputs on

ger
the
DigitalSystemDesign
ASSIGNMENT#5
4. Design a 4 bit universal shift register using MUXs and DFFs which can do the following
operations:
a) Right shift.
b) Left shift
c) Circular right shift
d) Circular left shift
5. Design a synchronous counter which goes through the following sequence of states using
D flip-flops.
11 10 01 00 11 10 01 00
6. Design a synchronous 3-bit Up/Down counter having Gray code sequence.
7. Construct a J ohnson counter for ten timing signals.
8. You are asked to build a digital lock which opens ONLY with the combination 0111.
Design a synchronous digital system that the electronic system of this lock would
comprise, using:
a) D flip-flops
b) J -K flip-flops
Which implementation requires lesser combinational logic? What are the advantages of
using each type of flip-flop? Which flip-flop, in your opinion, would be used more
(generally) in real-life for such design and why? (Note: Assume that the stream of bits at
the input is read-in MSB first, i.e., 0 comes first here.)
9. An AB latch operates as follows: If A =0 and B =0, the latch state is Q =0; if either A =
1 or B =1 (but not both), the latch output does not change; and when both A =1 and B =
1, the latch state is Q =1.
a) Construct the state table and derive the characteristic equation for this AB latch.
b) Derive a circuit for the AB latch that has four two-input NAND gates and two
inverters.
c) In your circuit of Part (b), are there any transitions between input combinations
that might cause unreliable operation? Verify your answer.
d) In your circuit of Part (b), is there a gate output that provides the signal Q?
Verify your answer.
10. A latch can be constructed from an OR gate, an AND gate, and an inverter connected as
follows:

a) W
st
b) C
la
c) C


What restricti
tate conditio
Construct a n
atch.
Complete the

ion must be
ons)?
next-state tab
e following ti
Digital
ASS
placed on R
ble and deriv
iming diagra
SystemDesig
IGNMENT#5

R and H so th
ve the charac
am for the la

gn

hat P will alw


cteristic (nex
atch.
ways equal Q
xt-state) equa
Q (under ste
ation for the
eady-