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Training Module IC Compiler
Lab-1: Milkyway Data preparation and IC Compiler Basic flow


In this training module, we will focus mainly on setting the environment (setting the required
libraries) and complete basic flow from gate level netlist (as input) to Routing.
For this training module:
Create a directory structure as follows: (Optional - You can create your own
structure)
o ICC_Lab1
Source
Scripts
Work
Reports
Download the attached ref.zip folder from forums, then copy the zip folder (Dont
unzip before copying in to the account) to your account and place it in the directory
structure you created. (Inside ICC_Lab1)
Then go to the directory and unzip the ref.zip folder. (command - unzip ref.zip)
Then copy the setup file, place it in the work folder and copy the netlist file and place
it in the source folder.
Invoke IC Compiler in GUI mode icc_shell -gui




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Step: 1
Setup of logical libraries:
IC compiler requires logical libraries which contain timing and functionality information
about all standard cells. In additional they can provide timing information for hard macros
such as PLLs, RAMs, etc. These libraries can be set in two ways:
1. We can set these libraries before invoking the IC Compiler using the setup file -
.synopsys_dc.setup. (Note: You should use the same logical libraries which you used
during the synthesis phase.)
2. Also, we can set these libraries after invoking the IC Compiler using the IC Compiler
GUI mode as shown below:
Go to: File -> Setup -> Application Setup
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Note: As we set the logical libraries in the setup file, the IC Compiler loaded all these
libraries while it is invoking.
Step: 2
Setup of Milkyway Library:
The physical library information is stored in the Milkyway design library. If you have not
already created a Milkyway library for your design (by using another tool that uses
Milkyway), you need to create one by using the IC Compiler tool. If you already have a
Milkyway design library, you must open it before working on your design.

Go to: File -> create library



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IC Compiler uses Milkyway reference libraries and technology (.tf) files to provide physical
library information. The Milkyway reference libraries contain physical information about the
standard cells and macro cells in your technology library. In addition, these reference
libraries define the placement unit tile. The technology files provide technology-specific
information such as the names and characteristics (physical and electrical) for each metal
layer.

Step: 3
Setting TLUPlus Files:
TLUPlus is a binary table format that stores the RC coefficients. IC Compiler uses TLUPlus
to improve preroute and postroute timing correlation. The TLUPlus models enable accurate
RC extraction results by including the effects of width, space, density, and temperature on the
resistance coefficients. To use TLUPlus, you must specify a map file that matches names in
the technology file with names in the Interconnect Technology Format (ITF) file. You must
also specify the maximum TLUPlus model files. IC Compiler stores the names and locations
of these files in Milkyway, but it does not store the TLUPlus information found in those files.
For each session you work on your design, you must specify the TLUPlus files that you need
to use for that session.

Milkyway library path
where all your
designs get saved
Name of the library
where all your
physical design work
get stored.
Setting the technology file Setting the reference
libraries FRAM
Views
Make sure to open
the library, before
going to the next
step.
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Go to: File -> Set TLU+









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Step: 4
Importing the design Reading the synthesized netlist
Go to: File -> Import Designs



You can set any
name; it is the
name of the cell by
which your design
gets saved.
Module name of
your top design
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Design view from ICC after importing the design into ICC:


Step: 5
Creating the floorplan
Go to: Floorplan -> Create Floorplan



After importing the design, all the standard cells in the
synthesized netlist will get replaced with associated
FRAM views which will be available in the reference
library.
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Design View from ICC after creating the floorplan.




Core Area Standard Cells
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Step: 5.1
Deriving PG Connections: Go to: Preroute -> Derive PG Connection





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Step: 5.2
Floorplan Creating rectangular rings
Go to: Preroute -> Create Rings


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Design View from ICC after creating the rectangular rings for Power & Ground connections.


Step: 5.3
VDD Ring (Green M4
layer)
VSS Ring (Blue M5
layer)
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Creating Power straps: Go to: Preroute -> Create Power Straps




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Design view from ICC after creating the power straps.





Both the straps get connected from
the rectangular rings accordingly.
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Step: 6
Pre-routing the standard cells: Go to: Preroute -> Preroute standard cells




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Step 7:
Placement: Go to: Placement -> Core placement and Optimization


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Design view from ICC after Placement:


Step: 8:
Clock Tree Synthesis: Go to: Clock -> Core CTS and Optimization


All the standard cells will get placed
inside the core area after placement.
One can check for congestion reports at
this stage to make sure that all the cells
are placed properly so that there is no
routing, also for efficient routing.
One can also check whether the number
of power straps created is enough or not.
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Design View from ICC after CTS:

Clock Port
Clock Tree In
Green colour
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Step: 9
Routing: Go to: Route -> Core Routing and Optimization


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Design view from ICC after routing:


Lab tasks:

Setup logical libraries
Create Milkyway database
Read the given mapped .ddc file
Create floorplan
Power Ground net connection
Create rectangular rings
Create power/ground straps
Preroute standard cells
Placement and Optimization
Clock tree synthesis
Routing

Once routing is done, all the cells
will get routed. After routing, one
can generate routed netlist in
Verilog format which can be used
for many checks functional
verification, DFT coverage, etc.