ADDWF f, d, a

ADDWFC f, d, a
ANDWF f, d, a
CLRF f, a
COMF f, d, a
CPFSEQ f, a
CPFSGT f, a
CPFSLT f, a
DECF f, d, a
DECFSZ f, d, a
DCFSNZ f, d, a
INCF f, d, a
INCFSZ f, d, a
INFSNZ f, d, a
IORWF f, d, a
MOVF f, d, a
MOVFF fs, fd
MOVWF f, a
MULWF f, a
NEGF f, a
RLCF f, d, a
RLNCF f, d, a
RRCF f, d, a
RRNCF f, d, a
SETF f, a
SUBFWB f, d, a
SUBWF f, d, a
SUBWFB f, d, a
SWAPF f, d, a
TSTFSZ f, a
XORWF f, d, a
BCF f, b, a
BSF f, b, a
BTFSC f, b, a
BTFSS f, b, a
BTG f, d, a
BC n
BN n
BNC n
BNN n
BNOV n
BNZ n
BOV n
BRA n
BZ n
CALL n, s
CLRWDT
DAW
GOTO n
NOP
NOP
POP
PUSH
RCALL n
RESET
RETFIE s
RETLW k
RETURN s
SLEEP
ADDLW k
ANDLW k
IORLW k
LFSR f, k
MOVLB k
MOVLW k
MULLW k
RETLW k
SUBLW k
XORLW k
TBLRD*
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
8-bit literal k and the result is placed in
W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write to W
Example: ADDLW 15h
Before Instruction
W = 10h
After Instruction
W = 25h
ADDWF ADD W to f
Syntax: ADDWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0010 01da ffff ffff
Description: Add W to register f. If d is 0, the
result is stored in W. If d is 1, the
result is stored back in register f
(default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: ADDWF REG, 0, 0
Before Instruction
W = 17h
REG = 0C2h
After Instruction
W = 0D9h
REG = 0C2h
Note: All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
PIC18F2455/2550/4455/4550
DS39632C-page 314 Preliminary 2006 Microchip Technology Inc.
ADDWFC ADD W and Carry bit to f
Syntax: ADDWFC f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) + (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0010 00da ffff ffff
Description: Add W, the Carry flag and data memory
location f. If d is 0, the result is
placed in W. If d is 1, the result is
placed in data memory location f.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: ADDWFC REG, 0, 1
Before Instruction
Carry bit = 1
REG = 02h
W = 4Dh
After Instruction
Carry bit = 0
REG = 02h
W = 50h
ANDLW AND Literal with W
Syntax: ANDLW k
Operands: 0 k 255
Operation: (W) .AND. k W
Status Affected: N, Z
Encoding: 0000 1011 kkkk kkkk
Description: The contents of W are ANDed with the
8-bit literal k. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
k
Process
Data
Write to W
Example: ANDLW 05Fh
Before Instruction
W = A3h
After Instruction
W = 03h
2006 Microchip Technology Inc. Preliminary DS39632C-page 315
PIC18F2455/2550/4455/4550
ANDWF AND W with f
Syntax: ANDWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .AND. (f) dest
Status Affected: N, Z
Encoding: 0001 01da ffff ffff
Description: The contents of W are ANDed with
register f. If d is 0, the result is stored
in W. If d is 1, the result is stored back
in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: ANDWF REG, 0, 0
Before Instruction
W = 17h
REG = C2h
After Instruction
W = 02h
REG = C2h
BC Branch if Carry
Syntax: BC n
Operands: -128 n 127
Operation: if Carry bit is 1
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0010 nnnn nnnn
Description: If the Carry bit is 1, then the program
will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BC 5
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 1;
PC = address (HERE + 12)
If Carry = 0;
PC = address (HERE + 2)
PIC18F2455/2550/4455/4550
DS39632C-page 316 Preliminary 2006 Microchip Technology Inc.
BCF Bit Clear f
Syntax: BCF f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 0 f<b>
Status Affected: None
Encoding: 1001 bbba ffff ffff
Description: Bit b in register f is cleared.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: BCF FLAG_REG, 7, 0
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
BN Branch if Negative
Syntax: BN n
Operands: -128 n 127
Operation: if Negative bit is 1
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0110 nnnn nnnn
Description: If the Negative bit is 1, then the
program will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 1;
PC = address (Jump)
If Negative = 0;
PC = address (HERE + 2)
2006 Microchip Technology Inc. Preliminary DS39632C-page 317
PIC18F2455/2550/4455/4550
BNC Branch if Not Carry
Syntax: BNC n
Operands: -128 n 127
Operation: if Carry bit is 0
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0011 nnnn nnnn
Description: If the Carry bit is 0, then the program
will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BNC Jump
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 0;
PC = address (Jump)
If Carry = 1;
PC = address (HERE + 2)
BNN Branch if Not Negative
Syntax: BNN n
Operands: -128 n 127
Operation: if Negative bit is 0
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0111 nnnn nnnn
Description: If the Negative bit is 0, then the
program will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BNN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 0;
PC = address (Jump)
If Negative = 1;
PC = address (HERE + 2)
PIC18F2455/2550/4455/4550
DS39632C-page 318 Preliminary 2006 Microchip Technology Inc.
BNOV Branch if Not Overflow
Syntax: BNOV n
Operands: -128 n 127
Operation: if Overflow bit is 0
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0101 nnnn nnnn
Description: If the Overflow bit is 0, then the
program will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BNOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 0;
PC = address (Jump)
If Overflow = 1;
PC = address (HERE + 2)
BNZ Branch if Not Zero
Syntax: BNZ n
Operands: -128 n 127
Operation: if Zero bit is 0
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0001 nnnn nnnn
Description: If the Zero bit is 0, then the program
will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BNZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 0;
PC = address (Jump)
If Zero = 1;
PC = address (HERE + 2)
2006 Microchip Technology Inc. Preliminary DS39632C-page 319
PIC18F2455/2550/4455/4550
BRA Unconditional Branch
Syntax: BRA n
Operands: -1024 n 1023
Operation: (PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 0nnn nnnn nnnn
Description: Add the 2s complement number 2n to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: HERE BRA Jump
Before Instruction
PC = address (HERE)
After Instruction
PC = address (Jump)
BSF Bit Set f
Syntax: BSF f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 1 f<b>
Status Affected: None
Encoding: 1000 bbba ffff ffff
Description: Bit b in register f is set.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah
PIC18F2455/2550/4455/4550
DS39632C-page 320 Preliminary 2006 Microchip Technology Inc.
BTFSC Bit Test File, Skip if Clear
Syntax: BTFSC f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: skip if (f<b>) = 0
Status Affected: None
Encoding: 1011 bbba ffff ffff
Description: If bit b in register f is 0, then the next
instruction is skipped. If bit b is 0, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If a is 0, the Access Bank is selected. If
a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f 95 (5Fh).
See Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (TRUE)
If FLAG<1> = 1;
PC = address (FALSE)
BTFSS Bit Test File, Skip if Set
Syntax: BTFSS f, b {,a}
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: skip if (f<b>) = 1
Status Affected: None
Encoding: 1010 bbba ffff ffff
Description: If bit b in register f is 1, then the next
instruction is skipped. If bit b is 1, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If a is 0, the Access Bank is selected. If
a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh).
See Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (FALSE)
If FLAG<1> = 1;
PC = address (TRUE)
2006 Microchip Technology Inc. Preliminary DS39632C-page 321
PIC18F2455/2550/4455/4550
BTG Bit Toggle f
Syntax: BTG f, b {,a}
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: (f<b>) f<b>
Status Affected: None
Encoding: 0111 bbba ffff ffff
Description: Bit b in data memory location f is
inverted.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: BTG PORTC, 4, 0
Before Instruction:
PORTC = 0111 0101 [75h]
After Instruction:
PORTC = 0110 0101 [65h]
BOV Branch if Overflow
Syntax: BOV n
Operands: -128 n 127
Operation: if Overflow bit is 1
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0100 nnnn nnnn
Description: If the Overflow bit is 1, then the
program will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 1;
PC = address (Jump)
If Overflow = 0;
PC = address (HERE + 2)
PIC18F2455/2550/4455/4550
DS39632C-page 322 Preliminary 2006 Microchip Technology Inc.
BZ Branch if Zero
Syntax: BZ n
Operands: -128 n 127
Operation: if Zero bit is 1
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0000 nnnn nnnn
Description: If the Zero bit is 1, then the program
will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 1;
PC = address (Jump)
If Zero = 0;
PC = address (HERE + 2)
CALL Subroutine Call
Syntax: CALL k {,s}
Operands: 0 k 1048575
s [0,1]
Operation: (PC) + 4 TOS,
k PC<20:1>,
if s = 1
(W) WS,
(STATUS) STATUSS,
(BSR) BSRS
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If s = 1, the W, STATUS and
BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If s = 0, no
update occurs (default). Then, the
20-bit value k is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
k<7:0>,
Push PC to
stack
Read literal
k<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: HERE CALL THERE,1
Before Instruction
PC = address (HERE)
After Instruction
PC = address (THERE)
TOS = address (HERE + 4)
WS = W
BSRS = BSR
STATUSS = STATUS
2006 Microchip Technology Inc. Preliminary DS39632C-page 323
PIC18F2455/2550/4455/4550
CLRF Clear f
Syntax: CLRF f {,a}
Operands: 0 f 255
a [0,1]
Operation: 000h f,
1 Z
Status Affected: Z
Encoding: 0110 101a ffff ffff
Description: Clears the contents of the specified
register.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: CLRF FLAG_REG,1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h
CLRWDT Clear Watchdog Timer
Syntax: CLRWDT
Operands: None
Operation: 000h WDT,
000h WDT postscaler,
1 TO,
1 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
No
operation
Example: CLRWDT
Before Instruction
WDT Counter = ?
After Instruction
WDT Counter = 00h
WDT Postscaler = 0
TO = 1
PD = 1
PIC18F2455/2550/4455/4550
DS39632C-page 324 Preliminary 2006 Microchip Technology Inc.
COMF Complement f
Syntax: COMF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) dest
Status Affected: N, Z
Encoding: 0001 11da ffff ffff
Description: The contents of register f are
complemented. If d is 0, the result is
stored in W. If d is 1, the result is
stored back in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: COMF REG, 0, 0
Before Instruction
REG = 13h
After Instruction
REG = 13h
W = ECh
CPFSEQ Compare f with W, Skip if f = W
Syntax: CPFSEQ f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 001a ffff ffff
Description: Compares the contents of data memory
location f to the contents of W by
performing an unsigned subtraction.
If f = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSEQ REG, 0
NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
W = ?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG W;
PC = Address (NEQUAL)
2006 Microchip Technology Inc. Preliminary DS39632C-page 325
PIC18F2455/2550/4455/4550
CPFSGT Compare f with W, Skip if f > W
Syntax: CPFSGT f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) (W),
skip if (f) > (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 010a ffff ffff
Description: Compares the contents of data memory
location f to the contents of the W by
performing an unsigned subtraction.
If the contents of f are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC = Address (HERE)
W = ?
After Instruction
If REG > W;
PC = Address (GREATER)
If REG W;
PC = Address (NGREATER)
CPFSLT Compare f with W, Skip if f < W
Syntax: CPFSLT f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
location f to the contents of W by
performing an unsigned subtraction.
If the contents of f are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSLT REG, 1
NLESS :
LESS :
Before Instruction
PC = Address (HERE)
W = ?
After Instruction
If REG < W;
PC = Address (LESS)
If REG W;
PC = Address (NLESS)
PIC18F2455/2550/4455/4550
DS39632C-page 326 Preliminary 2006 Microchip Technology Inc.
DAW Decimal Adjust W Register
Syntax: DAW
Operands: None
Operation: If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6 W<3:0>;
else
(W<3:0>) W<3:0>
If [W<7:4> + DC > 9] or [C = 1] then
(W<7:4>) + 6 + DC W<7:4>;
else
(W<7:4>) + DC W<7:4>
Status Affected: C
Encoding: 0000 0000 0000 0111
Description: DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register W
Process
Data
Write
W
Example 1: DAW
Before Instruction
W = A5h
C = 0
DC = 0
After Instruction
W = 05h
C = 1
DC = 0
Example 2:
Before Instruction
W = CEh
C = 0
DC = 0
After Instruction
W = 34h
C = 1
DC = 0
DECF Decrement f
Syntax: DECF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0000 01da ffff ffff
Description: Decrement register f. If d is 0, the
result is stored in W. If d is 1, the
result is stored back in register f
(default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: DECF CNT, 1, 0
Before Instruction
CNT = 01h
Z = 0
After Instruction
CNT = 00h
Z = 1
2006 Microchip Technology Inc. Preliminary DS39632C-page 327
PIC18F2455/2550/4455/4550
DECFSZ Decrement f, Skip if 0
Syntax: DECFSZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0010 11da ffff ffff
Description: The contents of register f are
decremented. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f (default).
If the result is 0, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP
CONTINUE
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT 1
If CNT = 0;
PC = Address (CONTINUE)
If CNT 0;
PC = Address (HERE + 2)
DCFSNZ Decrement f, Skip if Not 0
Syntax: DCFSNZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 11da ffff ffff
Description: The contents of register f are
decremented. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f (default).
If the result is not 0, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE DCFSNZ TEMP, 1, 0
ZERO :
NZERO :
Before Instruction
TEMP = ?
After Instruction
TEMP = TEMP 1,
If TEMP = 0;
PC = Address (ZERO)
If TEMP 0;
PC = Address (NZERO)
PIC18F2455/2550/4455/4550
DS39632C-page 328 Preliminary 2006 Microchip Technology Inc.
GOTO Unconditional Branch
Syntax: GOTO k
Operands: 0 k 1048575
Operation: k PC<20:1>
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: GOTO allows an unconditional branch
anywhere within the entire
2-Mbyte memory range. The 20-bit
value k is loaded into PC<20:1>. GOTO
is always a two-cycle instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
k<7:0>,
No
operation
Read literal
k<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: GOTO THERE
After Instruction
PC = Address (THERE)
INCF Increment f
Syntax: INCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0010 10da ffff ffff
Description: The contents of register f are
incremented. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: INCF CNT, 1, 0
Before Instruction
CNT = FFh
Z = 0
C = ?
DC = ?
After Instruction
CNT = 00h
Z = 1
C = 1
DC = 1
2006 Microchip Technology Inc. Preliminary DS39632C-page 329
PIC18F2455/2550/4455/4550
INCFSZ Increment f, Skip if 0
Syntax: INCFSZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0011 11da ffff ffff
Description: The contents of register f are
incremented. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f. (default)
If the result is 0, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE INCFSZ CNT, 1, 0
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT + 1
If CNT = 0;
PC = Address (ZERO)
If CNT 0;
PC = Address (NZERO)
INFSNZ Increment f, Skip if Not 0
Syntax: INFSNZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 10da ffff ffff
Description: The contents of register f are
incremented. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f (default).
If the result is not 0, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE INFSNZ REG, 1, 0
ZERO
NZERO
Before Instruction
PC = Address (HERE)
After Instruction
REG = REG + 1
If REG 0;
PC = Address (NZERO)
If REG = 0;
PC = Address (ZERO)
PIC18F2455/2550/4455/4550
DS39632C-page 330 Preliminary 2006 Microchip Technology Inc.
IORLW Inclusive OR Literal with W
Syntax: IORLW k
Operands: 0 k 255
Operation: (W) .OR. k W
Status Affected: N, Z
Encoding: 0000 1001 kkkk kkkk
Description: The contents of W are ORed with the
eight-bit literal k. The result is placed in
W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write to W
Example: IORLW 35h
Before Instruction
W = 9Ah
After Instruction
W = BFh
IORWF Inclusive OR W with f
Syntax: IORWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .OR. (f) dest
Status Affected: N, Z
Encoding: 0001 00da ffff ffff
Description: Inclusive OR W with register f. If d is
0, the result is placed in W. If d is 1,
the result is placed back in register f
(default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: IORWF RESULT, 0, 1
Before Instruction
RESULT = 13h
W = 91h
After Instruction
RESULT = 13h
W = 93h
2006 Microchip Technology Inc. Preliminary DS39632C-page 331
PIC18F2455/2550/4455/4550
LFSR Load FSR
Syntax: LFSR f, k
Operands: 0 f 2
0 k 4095
Operation: k FSRf
Status Affected: None
Encoding: 1110
1111
1110
0
00ff
k7kkk
k11kkk
kkkk
Description: The 12-bit literal k is loaded into the
File Select Register pointed to by f.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
k MSB
Process
Data
Write
literal k MSB
to FSRfH
Decode Read literal
k LSB
Process
Data
Write literal k
to FSRfL
Example: LFSR 2, 3ABh
After Instruction
FSR2H = 03h
FSR2L = ABh
MOVF Move f
Syntax: MOVF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: f dest
Status Affected: N, Z
Encoding: 0101 00da ffff ffff
Description: The contents of register f are moved to
a destination dependent upon the
status of d. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f (default).
Location f can be anywhere in the
256-byte bank.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write W
Example: MOVF REG, 0, 0
Before Instruction
REG = 22h
W = FFh
After Instruction
REG = 22h
W = 22h
PIC18F2455/2550/4455/4550
DS39632C-page 332 Preliminary 2006 Microchip Technology Inc.
MOVFF Move f to f
Syntax: MOVFF fs,fd
Operands: 0 fs 4095
0 fd 4095
Operation: (fs) fd
Status Affected: None
Encoding:
1st word (source)
2nd word (destin.)
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Description: The contents of source register fs are
moved to destination register fd.
Location of source fs can be anywhere
in the 4096-byte data space (000h to
FFFh) and location of destination fd
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
(src)
Process
Data
No
operation
Decode No
operation
No dummy
read
No
operation
Write
register f
(dest)
Example: MOVFF REG1, REG2
Before Instruction
REG1 = 33h
REG2 = 11h
After Instruction
REG1 = 33h
REG2 = 33h
MOVLB Move Literal to Low Nibble in BSR
Syntax: MOVLW k
Operands: 0 k 255
Operation: k BSR
Status Affected: None
Encoding: 0000 0001 kkkk kkkk
Description: The eight-bit literal k is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains 0
regardless of the value of k7:k4.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write literal
k to BSR
Example: MOVLB 5
Before Instruction
BSR Register = 02h
After Instruction
BSR Register = 05h
2006 Microchip Technology Inc. Preliminary DS39632C-page 333
PIC18F2455/2550/4455/4550
MOVLW Move Literal to W
Syntax: MOVLW k
Operands: 0 k 255
Operation: k W
Status Affected: None
Encoding: 0000 1110 kkkk kkkk
Description: The eight-bit literal k is loaded into W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write to W
Example: MOVLW 5Ah
After Instruction
W = 5Ah
MOVWF Move W to f
Syntax: MOVWF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (W) f
Status Affected: None
Encoding: 0110 111a ffff ffff
Description: Move data from W to register f.
Location f can be anywhere in the
256-byte bank.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: MOVWF REG, 0
Before Instruction
W = 4Fh
REG = FFh
After Instruction
W = 4Fh
REG = 4Fh
PIC18F2455/2550/4455/4550
DS39632C-page 334 Preliminary 2006 Microchip Technology Inc.
MULLW Multiply Literal with W
Syntax: MULLW k
Operands: 0 k 255
Operation: (W) x k PRODH:PRODL
Status Affected: None
Encoding: 0000 1101 kkkk kkkk
Description: An unsigned multiplication is carried
out between the contents of W and the
8-bit literal k. The 16-bit result is
placed in PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A zero result
is possible but not detected.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write
registers
PRODH:
PRODL
Example: MULLW 0C4h
Before Instruction
W = E2h
PRODH = ?
PRODL = ?
After Instruction
W = E2h
PRODH = ADh
PRODL = 08h
MULWF Multiply W with f
Syntax: MULWF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (W) x (f) PRODH:PRODL
Status Affected: None
Encoding: 0000 001a ffff ffff
Description: An unsigned multiplication is carried
out between the contents of W and the
register file location f. The 16-bit
result is stored in the PRODH:PRODL
register pair. PRODH contains the
high byte. Both W and f are
unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A zero
result is possible but not detected.
If a is 0, the Access Bank is
selected. If a is 1, the BSR is used
to select the GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 26.2.3
Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
registers
PRODH:
PRODL
Example: MULWF REG, 1
Before Instruction
W = C4h
REG = B5h
PRODH = ?
PRODL = ?
After Instruction
W = C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h
2006 Microchip Technology Inc. Preliminary DS39632C-page 335
PIC18F2455/2550/4455/4550
NEGF Negate f
Syntax: NEGF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) + 1 f
Status Affected: N, OV, C, DC, Z
Encoding: 0110 110a ffff ffff
Description: Location f is negated using twos
complement. The result is placed in the
data memory location f.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: NEGF REG, 1
Before Instruction
REG = 0011 1010 [3Ah]
After Instruction
REG = 1100 0110 [C6h]
NOP No Operation
Syntax: NOP
Operands: None
Operation: No operation
Status Affected: None
Encoding: 0000
1111
0
xxxx
0
xxxx
0
xxxx
Description: No operation.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
Example:
None.
PIC18F2455/2550/4455/4550
DS39632C-page 336 Preliminary 2006 Microchip Technology Inc.
POP Pop Top of Return Stack
Syntax: POP
Operands: None
Operation: (TOS) bit bucket
Status Affected: None
Encoding: 0000 0000 0000 0110
Description: The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Pop TOS
value
No
operation
Example: POP
GOTO NEW
Before Instruction
TOS = 0031A2h
Stack (1 level down) = 014332h
After Instruction
TOS = 014332h
PC = NEW
PUSH Push Top of Return Stack
Syntax: PUSH
Operands: None
Operation: (PC + 2) TOS
Status Affected: None
Encoding: 0000 0000 0000 0101
Description: The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Push PC + 2
onto return
stack
No
operation
No
operation
Example: PUSH
Before Instruction
TOS = 345Ah
PC = 0124h
After Instruction
PC = 0126h
TOS = 0126h
Stack (1 level down) = 345Ah
2006 Microchip Technology Inc. Preliminary DS39632C-page 337
PIC18F2455/2550/4455/4550
RCALL Relative Call
Syntax: RCALL n
Operands: -1024 n 1023
Operation: (PC) + 2 TOS,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 1nnn nnnn nnnn
Description: Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2s complement
number 2n to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
n
Push PC to
stack
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: HERE RCALL Jump
Before Instruction
PC = Address (HERE)
After Instruction
PC = Address (Jump)
TOS = Address (HERE + 2)
RESET Reset
Syntax: RESET
Operands: None
Operation: Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected: All
Encoding: 0000 0000 1111 1111
Description: This instruction provides a way to
execute a MCLR Reset in software.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Start
Reset
No
operation
No
operation
Example: RESET
After Instruction
Registers = Reset Value
Flags* = Reset Value
PIC18F2455/2550/4455/4550
DS39632C-page 338 Preliminary 2006 Microchip Technology Inc.
RETFIE Return from Interrupt
Syntax: RETFIE {s}
Operands: s [0,1]
Operation: (TOS) PC,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected: GIE/GIEH, PEIE/GIEL.
Encoding: 0000 0000 0001 000s
Description: Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If s = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers, W,
STATUS and BSR. If s = 0, no update
of these registers occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
Pop PC from
stack
Set GIEH or
GIEL
No
operation
No
operation
No
operation
No
operation
Example: RETFIE 1
After Interrupt
PC = TOS
W = WS
BSR = BSRS
STATUS = STATUSS
GIE/GIEH, PEIE/GIEL = 1
RETLW Return Literal to W
Syntax: RETLW k
Operands: 0 k 255
Operation: k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 1100 kkkk kkkk
Description: W is loaded with the eight-bit literal k.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Pop PC from
stack, Write
to W
No
operation
No
operation
No
operation
No
operation
Example:
CALL TABLE ; W contains table
; offset value
; W now has
; table value
:
TABLE
ADDWF PCL ; W = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
W = 07h
After Instruction
W = value of kn
2006 Microchip Technology Inc. Preliminary DS39632C-page 339
PIC18F2455/2550/4455/4550
RETURN Return from Subroutine
Syntax: RETURN {s}
Operands: s [0,1]
Operation: (TOS) PC,
if s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 0000 0001 001s
Description: Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
s= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers, W, STATUS and BSR. If
s = 0, no update of these registers
occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
Pop PC
from stack
No
operation
No
operation
No
operation
No
operation
Example: RETURN
After Instruction:
PC = TOS
RLCF Rotate Left f through Carry
Syntax: RLCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n + 1>,
(f<7>) C,
(C) dest<0>
Status Affected: C, N, Z
Encoding: 0011 01da ffff ffff
Description: The contents of register f are rotated
one bit to the left through the Carry
flag. If d is 0, the result is placed in
W. If d is 1, the result is stored back
in register f (default).
If a is 0, the Access Bank is
selected. If a is 1, the BSR is used to
select the GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 26.2.3
Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: RLCF REG, 0, 0
Before Instruction
REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 1100 1100
C = 1
C register f
PIC18F2455/2550/4455/4550
DS39632C-page 340 Preliminary 2006 Microchip Technology Inc.
RLNCF Rotate Left f (No Carry)
Syntax: RLNCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n + 1>,
(f<7>) dest<0>
Status Affected: N, Z
Encoding: 0100 01da ffff ffff
Description: The contents of register f are rotated
one bit to the left. If d is 0, the result
is placed in W. If d is 1, the result is
stored back in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: RLNCF REG, 1, 0
Before Instruction
REG = 1010 1011
After Instruction
REG = 0101 0111
register f
RRCF Rotate Right f through Carry
Syntax: RRCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n 1>,
(f<0>) C,
(C) dest<7>
Status Affected: C, N, Z
Encoding: 0011 00da ffff ffff
Description: The contents of register f are rotated
one bit to the right through the Carry
flag. If d is 0, the result is placed in W.
If d is 1, the result is placed back in
register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: RRCF REG, 0, 0
Before Instruction
REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0
C register f
2006 Microchip Technology Inc. Preliminary DS39632C-page 341
PIC18F2455/2550/4455/4550
RRNCF Rotate Right f (No Carry)
Syntax: RRNCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n 1>,
(f<0>) dest<7>
Status Affected: N, Z
Encoding: 0100 00da ffff ffff
Description: The contents of register f are rotated
one bit to the right. If d is 0, the result
is placed in W. If d is 1, the result is
placed back in register f (default).
If a is 0, the Access Bank will be
selected, overriding the BSR value. If a
is 1, then the bank will be selected as
per the BSR value (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example 1: RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2: RRNCF REG, 0, 0
Before Instruction
W = ?
REG = 1101 0111
After Instruction
W = 1110 1011
REG = 1101 0111
register f
SETF Set f
Syntax: SETF f {,a}
Operands: 0 f 255
a [0,1]
Operation: FFh f
Status Affected: None
Encoding: 0110 100a ffff ffff
Description: The contents of the specified register
are set to FFh.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: SETF REG,1
Before Instruction
REG = 5Ah
After Instruction
REG = FFh
PIC18F2455/2550/4455/4550
DS39632C-page 342 Preliminary 2006 Microchip Technology Inc.
SLEEP Enter Sleep mode
Syntax: SLEEP
Operands: None
Operation: 00h WDT,
0 WDT postscaler,
1 TO,
0 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0011
Description: The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
Go to
Sleep
Example: SLEEP
Before Instruction
TO = ?
PD = ?
After Instruction
TO = 1
PD = 0
If WDT causes wake-up, this bit is cleared.
SUBFWB Subtract f from W with Borrow
Syntax: SUBFWB f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) (f) (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 01da ffff ffff
Description: Subtract register f and Carry flag
(borrow) from W (2s complement
method). If d is 0, the result is stored
in W. If d is 1, the result is stored in
register f (default).
If a is 0, the Access Bank is
selected. If a is 1, the BSR is used
to select the GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 26.2.3
Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example 1: SUBFWB REG, 1, 0
Before Instruction
REG = 3
W = 2
C = 1
After Instruction
REG = FF
W = 2
C = 0
Z = 0
N = 1 ; result is negative
Example 2: SUBFWB REG, 0, 0
Before Instruction
REG = 2
W = 5
C = 1
After Instruction
REG = 2
W = 3
C = 1
Z = 0
N = 0 ; result is positive
Example 3: SUBFWB REG, 1, 0
Before Instruction
REG = 1
W = 2
C = 0
After Instruction
REG = 0
W = 2
C = 1
Z = 1 ; result is zero
N = 0
2006 Microchip Technology Inc. Preliminary DS39632C-page 343
PIC18F2455/2550/4455/4550
SUBLW Subtract W from Literal
Syntax: SUBLW k
Operands: 0 k 255
Operation: k (W) W
Status Affected: N, OV, C, DC, Z
Encoding: 0000 1000 kkkk kkkk
Description W is subtracted from the eight-bit
literal k. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write to W
Example 1: SUBLW 02h
Before Instruction
W = 01h
C = ?
After Instruction
W = 01h
C = 1 ; result is positive
Z = 0
N = 0
Example 2: SUBLW 02h
Before Instruction
W = 02h
C = ?
After Instruction
W = 00h
C = 1 ; result is zero
Z = 1
N = 0
Example 3: SUBLW 02h
Before Instruction
W = 03h
C = ?
After Instruction
W = FFh ; (2s complement)
C = 0 ; result is negative
Z = 0
N = 1
SUBWF Subtract W from f
Syntax: SUBWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) (W) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 11da ffff ffff
Description: Subtract W from register f (2s
complement method). If d is 0, the
result is stored in W. If d is 1, the
result is stored back in register f
(default).
If a is 0, the Access Bank is
selected. If a is 1, the BSR is used
to select the GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 26.2.3
Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example 1: SUBWF REG, 1, 0
Before Instruction
REG = 3
W = 2
C = ?
After Instruction
REG = 1
W = 2
C = 1 ; result is positive
Z = 0
N = 0
Example 2: SUBWF REG, 0, 0
Before Instruction
REG = 2
W = 2
C = ?
After Instruction
REG = 2
W = 0
C = 1 ; result is zero
Z = 1
N = 0
Example 3: SUBWF REG, 1, 0
Before Instruction
REG = 1
W = 2
C = ?
After Instruction
REG = FFh ;(2s complement)
W = 2
C = 0 ; result is negative
Z = 0
N = 1
PIC18F2455/2550/4455/4550
DS39632C-page 344 Preliminary 2006 Microchip Technology Inc.
SUBWFB Subtract W from f with Borrow
Syntax: SUBWFB f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) (W) (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 10da ffff ffff
Description: Subtract W and the Carry flag (borrow)
from register f (2s complement
method). If d is 0, the result is stored
in W. If d is 1, the result is stored back
in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example 1: SUBWFB REG, 1, 0
Before Instruction
REG = 19h (0001 1001)
W = 0Dh (0000 1101)
C = 1
After Instruction
REG = 0Ch (0000 1011)
W = 0Dh (0000 1101)
C = 1
Z = 0
N = 0 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 1Bh (0001 1011)
W = 1Ah (0001 1010)
C = 0
After Instruction
REG = 1Bh (0001 1011)
W = 00h
C = 1
Z = 1 ; result is zero
N = 0
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 03h (0000 0011)
W = 0Eh (0000 1101)
C = 1
After Instruction
REG = F5h (1111 0100)
; *2s comp+
W = 0Eh (0000 1101)
C = 0
Z = 0
N = 1 ; result is negative
SWAPF Swap f
Syntax: SWAPF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Affected: None
Encoding: 0011 10da ffff ffff
Description: The upper and lower nibbles of register
f are exchanged. If d is 0, the result
is placed in W. If d is 1, the result is
placed in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: SWAPF REG, 1, 0
Before Instruction
REG = 53h
After Instruction
REG = 35h
2006 Microchip Technology Inc. Preliminary DS39632C-page 345
PIC18F2455/2550/4455/4550
TBLRD Table Read
Syntax: TBLRD ( *; *+; *-; +*)
Operands: None
Operation: if TBLRD *
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR No Change;
if TBLRD *+
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPTR;
if TBLRD *-
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) 1 TBLPTR;
if TBLRD +*
(TBLPTR) + 1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT
Status Affected: None
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLRD instruction can modify the value
of TBLPTR as follows:
no change
post-increment
post-decrement
pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
operation
No operation
(Write
TABLAT)
TBLRD Table Read (Continued)
Example 1: TBLRD *+ ;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
MEMORY (00A356h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 00A357h
Example 2: TBLRD +* ;
Before Instruction
TABLAT = AAh
TBLPTR = 01A357h
MEMORY (01A357h) = 12h
MEMORY (01A358h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 01A358h
PIC18F2455/2550/4455/4550
DS39632C-page 346 Preliminary 2006 Microchip Technology Inc.
TBLWT Table Write
Syntax: TBLWT ( *; *+; *-; +*)
Operands: None
Operation: if TBLWT*
(TABLAT) Holding Register;
TBLPTR No Change;
if TBLWT*+
(TABLAT) Holding Register;
(TBLPTR) + 1 TBLPTR;
if TBLWT*-
(TABLAT) Holding Register;
(TBLPTR) 1 TBLPTR;
if TBLWT+*
(TBLPTR) + 1 TBLPTR;
(TABLAT) Holding Register
Status Affected: None
Encoding: 0000 0000 0000 11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction uses the 3 LSBs of TBLPTR
to determine which of the
8 holding registers the TABLAT is written to.
The holding registers are used to
program the contents of Program
Memory (P.M.). (Refer to Section 6.0
Flash Program Memory for additional
details on programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range. The LSb of
the TBLPTR selects which byte of the
program memory location to access.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
no change
post-increment
post-decrement
pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
No
operation
No
operation
(Read
TABLAT)
No
operation
No
operation
(Write to
Holding
Register)
TBLWT Table Write (Continued)
Example 1: TBLWT *+;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
HOLDING REGISTER
(00A356h) = FFh
After Instructions (table write completion)
TABLAT = 55h
TBLPTR = 00A357h
HOLDING REGISTER
(00A356h) = 55h
Example 2: TBLWT +*;
Before Instruction
TABLAT = 34h
TBLPTR = 01389Ah
HOLDING REGISTER
(01389Ah) = FFh
HOLDING REGISTER
(01389Bh) = FFh
After Instruction (table write completion)
TABLAT = 34h
TBLPTR = 01389Bh
HOLDING REGISTER
(01389Ah) = FFh
HOLDING REGISTER
(01389Bh) = 34h
2006 Microchip Technology Inc. Preliminary DS39632C-page 347
PIC18F2455/2550/4455/4550
TSTFSZ Test f, Skip if 0
Syntax: TSTFSZ f {,a}
Operands: 0 f 255
a [0,1]
Operation: skip if f = 0
Status Affected: None
Encoding: 0110 011a ffff ffff
Description: If f = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE TSTFSZ CNT, 1
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
If CNT = 00h,
PC = Address (ZERO)
If CNT 00h,
PC = Address (NZERO)
XORLW Exclusive OR Literal with W
Syntax: XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W
Status Affected: N, Z
Encoding: 0000 1010 kkkk kkkk
Description: The contents of W are XORed with
the 8-bit literal k. The result is placed
in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write to W
Example: XORLW 0AFh
Before Instruction
W = B5h
After Instruction
W = 1Ah
PIC18F2455/2550/4455/4550
DS39632C-page 348 Preliminary 2006 Microchip Technology Inc.
XORWF Exclusive OR W with f
Syntax: XORWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .XOR. (f) dest
Status Affected: N, Z
Encoding: 0001 10da ffff ffff
Description: Exclusive OR the contents of W with
register f. If d is 0, the result is stored
in W. If d is 1, the result is stored back
in the register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: XORWF REG, 1, 0
Before Instruction
REG = AFh
W = B5h
After Instruction
REG = 1Ah
W = B5h
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
Return with literal in WREG
Return from Subroutine
Go into Standby mode
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
to FSR(f) 1st word
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
Table Read
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
ADDLW ADD Literal to W
Syntax: ADDLW k
Operands: 0 k 255
Operation: (W) + k W
Status Affected: N, OV, C, DC, Z
Encoding: 0000 1111 kkkk kkkk
Description: The contents of W are added to the
8-bit literal k and the result is placed in
W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write to W
Example: ADDLW 15h
Before Instruction
W = 10h
After Instruction
W = 25h
ADDWF ADD W to f
Syntax: ADDWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0010 01da ffff ffff
Description: Add W to register f. If d is 0, the
result is stored in W. If d is 1, the
result is stored back in register f
(default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: ADDWF REG, 0, 0
Before Instruction
W = 17h
REG = 0C2h
After Instruction
W = 0D9h
REG = 0C2h
Note: All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
PIC18F2455/2550/4455/4550
DS39632C-page 314 Preliminary 2006 Microchip Technology Inc.
ADDWFC ADD W and Carry bit to f
Syntax: ADDWFC f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) + (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0010 00da ffff ffff
Description: Add W, the Carry flag and data memory
location f. If d is 0, the result is
placed in W. If d is 1, the result is
placed in data memory location f.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: ADDWFC REG, 0, 1
Before Instruction
Carry bit = 1
REG = 02h
W = 4Dh
After Instruction
Carry bit = 0
REG = 02h
W = 50h
ANDLW AND Literal with W
Syntax: ANDLW k
Operands: 0 k 255
Operation: (W) .AND. k W
Status Affected: N, Z
Encoding: 0000 1011 kkkk kkkk
Description: The contents of W are ANDed with the
8-bit literal k. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
k
Process
Data
Write to W
Example: ANDLW 05Fh
Before Instruction
W = A3h
After Instruction
W = 03h
2006 Microchip Technology Inc. Preliminary DS39632C-page 315
PIC18F2455/2550/4455/4550
ANDWF AND W with f
Syntax: ANDWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .AND. (f) dest
Status Affected: N, Z
Encoding: 0001 01da ffff ffff
Description: The contents of W are ANDed with
register f. If d is 0, the result is stored
in W. If d is 1, the result is stored back
in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: ANDWF REG, 0, 0
Before Instruction
W = 17h
REG = C2h
After Instruction
W = 02h
REG = C2h
BC Branch if Carry
Syntax: BC n
Operands: -128 n 127
Operation: if Carry bit is 1
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0010 nnnn nnnn
Description: If the Carry bit is 1, then the program
will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BC 5
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 1;
PC = address (HERE + 12)
If Carry = 0;
PC = address (HERE + 2)
PIC18F2455/2550/4455/4550
DS39632C-page 316 Preliminary 2006 Microchip Technology Inc.
BCF Bit Clear f
Syntax: BCF f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 0 f<b>
Status Affected: None
Encoding: 1001 bbba ffff ffff
Description: Bit b in register f is cleared.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: BCF FLAG_REG, 7, 0
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
BN Branch if Negative
Syntax: BN n
Operands: -128 n 127
Operation: if Negative bit is 1
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0110 nnnn nnnn
Description: If the Negative bit is 1, then the
program will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 1;
PC = address (Jump)
If Negative = 0;
PC = address (HERE + 2)
2006 Microchip Technology Inc. Preliminary DS39632C-page 317
PIC18F2455/2550/4455/4550
BNC Branch if Not Carry
Syntax: BNC n
Operands: -128 n 127
Operation: if Carry bit is 0
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0011 nnnn nnnn
Description: If the Carry bit is 0, then the program
will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BNC Jump
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 0;
PC = address (Jump)
If Carry = 1;
PC = address (HERE + 2)
BNN Branch if Not Negative
Syntax: BNN n
Operands: -128 n 127
Operation: if Negative bit is 0
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0111 nnnn nnnn
Description: If the Negative bit is 0, then the
program will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BNN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 0;
PC = address (Jump)
If Negative = 1;
PC = address (HERE + 2)
PIC18F2455/2550/4455/4550
DS39632C-page 318 Preliminary 2006 Microchip Technology Inc.
BNOV Branch if Not Overflow
Syntax: BNOV n
Operands: -128 n 127
Operation: if Overflow bit is 0
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0101 nnnn nnnn
Description: If the Overflow bit is 0, then the
program will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BNOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 0;
PC = address (Jump)
If Overflow = 1;
PC = address (HERE + 2)
BNZ Branch if Not Zero
Syntax: BNZ n
Operands: -128 n 127
Operation: if Zero bit is 0
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0001 nnnn nnnn
Description: If the Zero bit is 0, then the program
will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BNZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 0;
PC = address (Jump)
If Zero = 1;
PC = address (HERE + 2)
2006 Microchip Technology Inc. Preliminary DS39632C-page 319
PIC18F2455/2550/4455/4550
BRA Unconditional Branch
Syntax: BRA n
Operands: -1024 n 1023
Operation: (PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 0nnn nnnn nnnn
Description: Add the 2s complement number 2n to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: HERE BRA Jump
Before Instruction
PC = address (HERE)
After Instruction
PC = address (Jump)
BSF Bit Set f
Syntax: BSF f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 1 f<b>
Status Affected: None
Encoding: 1000 bbba ffff ffff
Description: Bit b in register f is set.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah
PIC18F2455/2550/4455/4550
DS39632C-page 320 Preliminary 2006 Microchip Technology Inc.
BTFSC Bit Test File, Skip if Clear
Syntax: BTFSC f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: skip if (f<b>) = 0
Status Affected: None
Encoding: 1011 bbba ffff ffff
Description: If bit b in register f is 0, then the next
instruction is skipped. If bit b is 0, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If a is 0, the Access Bank is selected. If
a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f 95 (5Fh).
See Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (TRUE)
If FLAG<1> = 1;
PC = address (FALSE)
BTFSS Bit Test File, Skip if Set
Syntax: BTFSS f, b {,a}
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: skip if (f<b>) = 1
Status Affected: None
Encoding: 1010 bbba ffff ffff
Description: If bit b in register f is 1, then the next
instruction is skipped. If bit b is 1, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If a is 0, the Access Bank is selected. If
a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh).
See Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (FALSE)
If FLAG<1> = 1;
PC = address (TRUE)
2006 Microchip Technology Inc. Preliminary DS39632C-page 321
PIC18F2455/2550/4455/4550
BTG Bit Toggle f
Syntax: BTG f, b {,a}
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: (f<b>) f<b>
Status Affected: None
Encoding: 0111 bbba ffff ffff
Description: Bit b in data memory location f is
inverted.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: BTG PORTC, 4, 0
Before Instruction:
PORTC = 0111 0101 [75h]
After Instruction:
PORTC = 0110 0101 [65h]
BOV Branch if Overflow
Syntax: BOV n
Operands: -128 n 127
Operation: if Overflow bit is 1
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0100 nnnn nnnn
Description: If the Overflow bit is 1, then the
program will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 1;
PC = address (Jump)
If Overflow = 0;
PC = address (HERE + 2)
PIC18F2455/2550/4455/4550
DS39632C-page 322 Preliminary 2006 Microchip Technology Inc.
BZ Branch if Zero
Syntax: BZ n
Operands: -128 n 127
Operation: if Zero bit is 1
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0000 nnnn nnnn
Description: If the Zero bit is 1, then the program
will branch.
The 2s complement number 2n is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
n
Process
Data
No
operation
Example: HERE BZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 1;
PC = address (Jump)
If Zero = 0;
PC = address (HERE + 2)
CALL Subroutine Call
Syntax: CALL k {,s}
Operands: 0 k 1048575
s [0,1]
Operation: (PC) + 4 TOS,
k PC<20:1>,
if s = 1
(W) WS,
(STATUS) STATUSS,
(BSR) BSRS
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If s = 1, the W, STATUS and
BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If s = 0, no
update occurs (default). Then, the
20-bit value k is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
k<7:0>,
Push PC to
stack
Read literal
k<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: HERE CALL THERE,1
Before Instruction
PC = address (HERE)
After Instruction
PC = address (THERE)
TOS = address (HERE + 4)
WS = W
BSRS = BSR
STATUSS = STATUS
2006 Microchip Technology Inc. Preliminary DS39632C-page 323
PIC18F2455/2550/4455/4550
CLRF Clear f
Syntax: CLRF f {,a}
Operands: 0 f 255
a [0,1]
Operation: 000h f,
1 Z
Status Affected: Z
Encoding: 0110 101a ffff ffff
Description: Clears the contents of the specified
register.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: CLRF FLAG_REG,1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h
CLRWDT Clear Watchdog Timer
Syntax: CLRWDT
Operands: None
Operation: 000h WDT,
000h WDT postscaler,
1 TO,
1 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
No
operation
Example: CLRWDT
Before Instruction
WDT Counter = ?
After Instruction
WDT Counter = 00h
WDT Postscaler = 0
TO = 1
PD = 1
PIC18F2455/2550/4455/4550
DS39632C-page 324 Preliminary 2006 Microchip Technology Inc.
COMF Complement f
Syntax: COMF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) dest
Status Affected: N, Z
Encoding: 0001 11da ffff ffff
Description: The contents of register f are
complemented. If d is 0, the result is
stored in W. If d is 1, the result is
stored back in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: COMF REG, 0, 0
Before Instruction
REG = 13h
After Instruction
REG = 13h
W = ECh
CPFSEQ Compare f with W, Skip if f = W
Syntax: CPFSEQ f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 001a ffff ffff
Description: Compares the contents of data memory
location f to the contents of W by
performing an unsigned subtraction.
If f = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSEQ REG, 0
NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
W = ?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG W;
PC = Address (NEQUAL)
2006 Microchip Technology Inc. Preliminary DS39632C-page 325
PIC18F2455/2550/4455/4550
CPFSGT Compare f with W, Skip if f > W
Syntax: CPFSGT f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) (W),
skip if (f) > (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 010a ffff ffff
Description: Compares the contents of data memory
location f to the contents of the W by
performing an unsigned subtraction.
If the contents of f are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC = Address (HERE)
W = ?
After Instruction
If REG > W;
PC = Address (GREATER)
If REG W;
PC = Address (NGREATER)
CPFSLT Compare f with W, Skip if f < W
Syntax: CPFSLT f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
location f to the contents of W by
performing an unsigned subtraction.
If the contents of f are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSLT REG, 1
NLESS :
LESS :
Before Instruction
PC = Address (HERE)
W = ?
After Instruction
If REG < W;
PC = Address (LESS)
If REG W;
PC = Address (NLESS)
PIC18F2455/2550/4455/4550
DS39632C-page 326 Preliminary 2006 Microchip Technology Inc.
DAW Decimal Adjust W Register
Syntax: DAW
Operands: None
Operation: If [W<3:0> > 9] or [DC = 1] then
(W<3:0>) + 6 W<3:0>;
else
(W<3:0>) W<3:0>
If [W<7:4> + DC > 9] or [C = 1] then
(W<7:4>) + 6 + DC W<7:4>;
else
(W<7:4>) + DC W<7:4>
Status Affected: C
Encoding: 0000 0000 0000 0111
Description: DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register W
Process
Data
Write
W
Example 1: DAW
Before Instruction
W = A5h
C = 0
DC = 0
After Instruction
W = 05h
C = 1
DC = 0
Example 2:
Before Instruction
W = CEh
C = 0
DC = 0
After Instruction
W = 34h
C = 1
DC = 0
DECF Decrement f
Syntax: DECF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0000 01da ffff ffff
Description: Decrement register f. If d is 0, the
result is stored in W. If d is 1, the
result is stored back in register f
(default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: DECF CNT, 1, 0
Before Instruction
CNT = 01h
Z = 0
After Instruction
CNT = 00h
Z = 1
2006 Microchip Technology Inc. Preliminary DS39632C-page 327
PIC18F2455/2550/4455/4550
DECFSZ Decrement f, Skip if 0
Syntax: DECFSZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0010 11da ffff ffff
Description: The contents of register f are
decremented. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f (default).
If the result is 0, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP
CONTINUE
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT 1
If CNT = 0;
PC = Address (CONTINUE)
If CNT 0;
PC = Address (HERE + 2)
DCFSNZ Decrement f, Skip if Not 0
Syntax: DCFSNZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 11da ffff ffff
Description: The contents of register f are
decremented. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f (default).
If the result is not 0, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE DCFSNZ TEMP, 1, 0
ZERO :
NZERO :
Before Instruction
TEMP = ?
After Instruction
TEMP = TEMP 1,
If TEMP = 0;
PC = Address (ZERO)
If TEMP 0;
PC = Address (NZERO)
PIC18F2455/2550/4455/4550
DS39632C-page 328 Preliminary 2006 Microchip Technology Inc.
GOTO Unconditional Branch
Syntax: GOTO k
Operands: 0 k 1048575
Operation: k PC<20:1>
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: GOTO allows an unconditional branch
anywhere within the entire
2-Mbyte memory range. The 20-bit
value k is loaded into PC<20:1>. GOTO
is always a two-cycle instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
k<7:0>,
No
operation
Read literal
k<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: GOTO THERE
After Instruction
PC = Address (THERE)
INCF Increment f
Syntax: INCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0010 10da ffff ffff
Description: The contents of register f are
incremented. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: INCF CNT, 1, 0
Before Instruction
CNT = FFh
Z = 0
C = ?
DC = ?
After Instruction
CNT = 00h
Z = 1
C = 1
DC = 1
2006 Microchip Technology Inc. Preliminary DS39632C-page 329
PIC18F2455/2550/4455/4550
INCFSZ Increment f, Skip if 0
Syntax: INCFSZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0011 11da ffff ffff
Description: The contents of register f are
incremented. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f. (default)
If the result is 0, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE INCFSZ CNT, 1, 0
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT + 1
If CNT = 0;
PC = Address (ZERO)
If CNT 0;
PC = Address (NZERO)
INFSNZ Increment f, Skip if Not 0
Syntax: INFSNZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 10da ffff ffff
Description: The contents of register f are
incremented. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f (default).
If the result is not 0, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE INFSNZ REG, 1, 0
ZERO
NZERO
Before Instruction
PC = Address (HERE)
After Instruction
REG = REG + 1
If REG 0;
PC = Address (NZERO)
If REG = 0;
PC = Address (ZERO)
PIC18F2455/2550/4455/4550
DS39632C-page 330 Preliminary 2006 Microchip Technology Inc.
IORLW Inclusive OR Literal with W
Syntax: IORLW k
Operands: 0 k 255
Operation: (W) .OR. k W
Status Affected: N, Z
Encoding: 0000 1001 kkkk kkkk
Description: The contents of W are ORed with the
eight-bit literal k. The result is placed in
W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write to W
Example: IORLW 35h
Before Instruction
W = 9Ah
After Instruction
W = BFh
IORWF Inclusive OR W with f
Syntax: IORWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .OR. (f) dest
Status Affected: N, Z
Encoding: 0001 00da ffff ffff
Description: Inclusive OR W with register f. If d is
0, the result is placed in W. If d is 1,
the result is placed back in register f
(default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: IORWF RESULT, 0, 1
Before Instruction
RESULT = 13h
W = 91h
After Instruction
RESULT = 13h
W = 93h
2006 Microchip Technology Inc. Preliminary DS39632C-page 331
PIC18F2455/2550/4455/4550
LFSR Load FSR
Syntax: LFSR f, k
Operands: 0 f 2
0 k 4095
Operation: k FSRf
Status Affected: None
Encoding: 1110
1111
1110
0
00ff
k7kkk
k11kkk
kkkk
Description: The 12-bit literal k is loaded into the
File Select Register pointed to by f.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
k MSB
Process
Data
Write
literal k MSB
to FSRfH
Decode Read literal
k LSB
Process
Data
Write literal k
to FSRfL
Example: LFSR 2, 3ABh
After Instruction
FSR2H = 03h
FSR2L = ABh
MOVF Move f
Syntax: MOVF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: f dest
Status Affected: N, Z
Encoding: 0101 00da ffff ffff
Description: The contents of register f are moved to
a destination dependent upon the
status of d. If d is 0, the result is
placed in W. If d is 1, the result is
placed back in register f (default).
Location f can be anywhere in the
256-byte bank.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write W
Example: MOVF REG, 0, 0
Before Instruction
REG = 22h
W = FFh
After Instruction
REG = 22h
W = 22h
PIC18F2455/2550/4455/4550
DS39632C-page 332 Preliminary 2006 Microchip Technology Inc.
MOVFF Move f to f
Syntax: MOVFF fs,fd
Operands: 0 fs 4095
0 fd 4095
Operation: (fs) fd
Status Affected: None
Encoding:
1st word (source)
2nd word (destin.)
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Description: The contents of source register fs are
moved to destination register fd.
Location of source fs can be anywhere
in the 4096-byte data space (000h to
FFFh) and location of destination fd
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
(src)
Process
Data
No
operation
Decode No
operation
No dummy
read
No
operation
Write
register f
(dest)
Example: MOVFF REG1, REG2
Before Instruction
REG1 = 33h
REG2 = 11h
After Instruction
REG1 = 33h
REG2 = 33h
MOVLB Move Literal to Low Nibble in BSR
Syntax: MOVLW k
Operands: 0 k 255
Operation: k BSR
Status Affected: None
Encoding: 0000 0001 kkkk kkkk
Description: The eight-bit literal k is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains 0
regardless of the value of k7:k4.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write literal
k to BSR
Example: MOVLB 5
Before Instruction
BSR Register = 02h
After Instruction
BSR Register = 05h
2006 Microchip Technology Inc. Preliminary DS39632C-page 333
PIC18F2455/2550/4455/4550
MOVLW Move Literal to W
Syntax: MOVLW k
Operands: 0 k 255
Operation: k W
Status Affected: None
Encoding: 0000 1110 kkkk kkkk
Description: The eight-bit literal k is loaded into W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write to W
Example: MOVLW 5Ah
After Instruction
W = 5Ah
MOVWF Move W to f
Syntax: MOVWF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (W) f
Status Affected: None
Encoding: 0110 111a ffff ffff
Description: Move data from W to register f.
Location f can be anywhere in the
256-byte bank.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: MOVWF REG, 0
Before Instruction
W = 4Fh
REG = FFh
After Instruction
W = 4Fh
REG = 4Fh
PIC18F2455/2550/4455/4550
DS39632C-page 334 Preliminary 2006 Microchip Technology Inc.
MULLW Multiply Literal with W
Syntax: MULLW k
Operands: 0 k 255
Operation: (W) x k PRODH:PRODL
Status Affected: None
Encoding: 0000 1101 kkkk kkkk
Description: An unsigned multiplication is carried
out between the contents of W and the
8-bit literal k. The 16-bit result is
placed in PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A zero result
is possible but not detected.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write
registers
PRODH:
PRODL
Example: MULLW 0C4h
Before Instruction
W = E2h
PRODH = ?
PRODL = ?
After Instruction
W = E2h
PRODH = ADh
PRODL = 08h
MULWF Multiply W with f
Syntax: MULWF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (W) x (f) PRODH:PRODL
Status Affected: None
Encoding: 0000 001a ffff ffff
Description: An unsigned multiplication is carried
out between the contents of W and the
register file location f. The 16-bit
result is stored in the PRODH:PRODL
register pair. PRODH contains the
high byte. Both W and f are
unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A zero
result is possible but not detected.
If a is 0, the Access Bank is
selected. If a is 1, the BSR is used
to select the GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 26.2.3
Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
registers
PRODH:
PRODL
Example: MULWF REG, 1
Before Instruction
W = C4h
REG = B5h
PRODH = ?
PRODL = ?
After Instruction
W = C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h
2006 Microchip Technology Inc. Preliminary DS39632C-page 335
PIC18F2455/2550/4455/4550
NEGF Negate f
Syntax: NEGF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) + 1 f
Status Affected: N, OV, C, DC, Z
Encoding: 0110 110a ffff ffff
Description: Location f is negated using twos
complement. The result is placed in the
data memory location f.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: NEGF REG, 1
Before Instruction
REG = 0011 1010 [3Ah]
After Instruction
REG = 1100 0110 [C6h]
NOP No Operation
Syntax: NOP
Operands: None
Operation: No operation
Status Affected: None
Encoding: 0000
1111
0
xxxx
0
xxxx
0
xxxx
Description: No operation.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
Example:
None.
PIC18F2455/2550/4455/4550
DS39632C-page 336 Preliminary 2006 Microchip Technology Inc.
POP Pop Top of Return Stack
Syntax: POP
Operands: None
Operation: (TOS) bit bucket
Status Affected: None
Encoding: 0000 0000 0000 0110
Description: The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Pop TOS
value
No
operation
Example: POP
GOTO NEW
Before Instruction
TOS = 0031A2h
Stack (1 level down) = 014332h
After Instruction
TOS = 014332h
PC = NEW
PUSH Push Top of Return Stack
Syntax: PUSH
Operands: None
Operation: (PC + 2) TOS
Status Affected: None
Encoding: 0000 0000 0000 0101
Description: The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Push PC + 2
onto return
stack
No
operation
No
operation
Example: PUSH
Before Instruction
TOS = 345Ah
PC = 0124h
After Instruction
PC = 0126h
TOS = 0126h
Stack (1 level down) = 345Ah
2006 Microchip Technology Inc. Preliminary DS39632C-page 337
PIC18F2455/2550/4455/4550
RCALL Relative Call
Syntax: RCALL n
Operands: -1024 n 1023
Operation: (PC) + 2 TOS,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 1nnn nnnn nnnn
Description: Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2s complement
number 2n to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
n
Push PC to
stack
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: HERE RCALL Jump
Before Instruction
PC = Address (HERE)
After Instruction
PC = Address (Jump)
TOS = Address (HERE + 2)
RESET Reset
Syntax: RESET
Operands: None
Operation: Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected: All
Encoding: 0000 0000 1111 1111
Description: This instruction provides a way to
execute a MCLR Reset in software.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Start
Reset
No
operation
No
operation
Example: RESET
After Instruction
Registers = Reset Value
Flags* = Reset Value
PIC18F2455/2550/4455/4550
DS39632C-page 338 Preliminary 2006 Microchip Technology Inc.
RETFIE Return from Interrupt
Syntax: RETFIE {s}
Operands: s [0,1]
Operation: (TOS) PC,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected: GIE/GIEH, PEIE/GIEL.
Encoding: 0000 0000 0001 000s
Description: Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If s = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers, W,
STATUS and BSR. If s = 0, no update
of these registers occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
Pop PC from
stack
Set GIEH or
GIEL
No
operation
No
operation
No
operation
No
operation
Example: RETFIE 1
After Interrupt
PC = TOS
W = WS
BSR = BSRS
STATUS = STATUSS
GIE/GIEH, PEIE/GIEL = 1
RETLW Return Literal to W
Syntax: RETLW k
Operands: 0 k 255
Operation: k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 1100 kkkk kkkk
Description: W is loaded with the eight-bit literal k.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Pop PC from
stack, Write
to W
No
operation
No
operation
No
operation
No
operation
Example:
CALL TABLE ; W contains table
; offset value
; W now has
; table value
:
TABLE
ADDWF PCL ; W = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
W = 07h
After Instruction
W = value of kn
2006 Microchip Technology Inc. Preliminary DS39632C-page 339
PIC18F2455/2550/4455/4550
RETURN Return from Subroutine
Syntax: RETURN {s}
Operands: s [0,1]
Operation: (TOS) PC,
if s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 0000 0001 001s
Description: Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
s= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers, W, STATUS and BSR. If
s = 0, no update of these registers
occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
Pop PC
from stack
No
operation
No
operation
No
operation
No
operation
Example: RETURN
After Instruction:
PC = TOS
RLCF Rotate Left f through Carry
Syntax: RLCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n + 1>,
(f<7>) C,
(C) dest<0>
Status Affected: C, N, Z
Encoding: 0011 01da ffff ffff
Description: The contents of register f are rotated
one bit to the left through the Carry
flag. If d is 0, the result is placed in
W. If d is 1, the result is stored back
in register f (default).
If a is 0, the Access Bank is
selected. If a is 1, the BSR is used to
select the GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 26.2.3
Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: RLCF REG, 0, 0
Before Instruction
REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 1100 1100
C = 1
C register f
PIC18F2455/2550/4455/4550
DS39632C-page 340 Preliminary 2006 Microchip Technology Inc.
RLNCF Rotate Left f (No Carry)
Syntax: RLNCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n + 1>,
(f<7>) dest<0>
Status Affected: N, Z
Encoding: 0100 01da ffff ffff
Description: The contents of register f are rotated
one bit to the left. If d is 0, the result
is placed in W. If d is 1, the result is
stored back in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: RLNCF REG, 1, 0
Before Instruction
REG = 1010 1011
After Instruction
REG = 0101 0111
register f
RRCF Rotate Right f through Carry
Syntax: RRCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n 1>,
(f<0>) C,
(C) dest<7>
Status Affected: C, N, Z
Encoding: 0011 00da ffff ffff
Description: The contents of register f are rotated
one bit to the right through the Carry
flag. If d is 0, the result is placed in W.
If d is 1, the result is placed back in
register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: RRCF REG, 0, 0
Before Instruction
REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0
C register f
2006 Microchip Technology Inc. Preliminary DS39632C-page 341
PIC18F2455/2550/4455/4550
RRNCF Rotate Right f (No Carry)
Syntax: RRNCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n 1>,
(f<0>) dest<7>
Status Affected: N, Z
Encoding: 0100 00da ffff ffff
Description: The contents of register f are rotated
one bit to the right. If d is 0, the result
is placed in W. If d is 1, the result is
placed back in register f (default).
If a is 0, the Access Bank will be
selected, overriding the BSR value. If a
is 1, then the bank will be selected as
per the BSR value (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example 1: RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2: RRNCF REG, 0, 0
Before Instruction
W = ?
REG = 1101 0111
After Instruction
W = 1110 1011
REG = 1101 0111
register f
SETF Set f
Syntax: SETF f {,a}
Operands: 0 f 255
a [0,1]
Operation: FFh f
Status Affected: None
Encoding: 0110 100a ffff ffff
Description: The contents of the specified register
are set to FFh.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write
register f
Example: SETF REG,1
Before Instruction
REG = 5Ah
After Instruction
REG = FFh
PIC18F2455/2550/4455/4550
DS39632C-page 342 Preliminary 2006 Microchip Technology Inc.
SLEEP Enter Sleep mode
Syntax: SLEEP
Operands: None
Operation: 00h WDT,
0 WDT postscaler,
1 TO,
0 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0011
Description: The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
Go to
Sleep
Example: SLEEP
Before Instruction
TO = ?
PD = ?
After Instruction
TO = 1
PD = 0
If WDT causes wake-up, this bit is cleared.
SUBFWB Subtract f from W with Borrow
Syntax: SUBFWB f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) (f) (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 01da ffff ffff
Description: Subtract register f and Carry flag
(borrow) from W (2s complement
method). If d is 0, the result is stored
in W. If d is 1, the result is stored in
register f (default).
If a is 0, the Access Bank is
selected. If a is 1, the BSR is used
to select the GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 26.2.3
Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example 1: SUBFWB REG, 1, 0
Before Instruction
REG = 3
W = 2
C = 1
After Instruction
REG = FF
W = 2
C = 0
Z = 0
N = 1 ; result is negative
Example 2: SUBFWB REG, 0, 0
Before Instruction
REG = 2
W = 5
C = 1
After Instruction
REG = 2
W = 3
C = 1
Z = 0
N = 0 ; result is positive
Example 3: SUBFWB REG, 1, 0
Before Instruction
REG = 1
W = 2
C = 0
After Instruction
REG = 0
W = 2
C = 1
Z = 1 ; result is zero
N = 0
2006 Microchip Technology Inc. Preliminary DS39632C-page 343
PIC18F2455/2550/4455/4550
SUBLW Subtract W from Literal
Syntax: SUBLW k
Operands: 0 k 255
Operation: k (W) W
Status Affected: N, OV, C, DC, Z
Encoding: 0000 1000 kkkk kkkk
Description W is subtracted from the eight-bit
literal k. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write to W
Example 1: SUBLW 02h
Before Instruction
W = 01h
C = ?
After Instruction
W = 01h
C = 1 ; result is positive
Z = 0
N = 0
Example 2: SUBLW 02h
Before Instruction
W = 02h
C = ?
After Instruction
W = 00h
C = 1 ; result is zero
Z = 1
N = 0
Example 3: SUBLW 02h
Before Instruction
W = 03h
C = ?
After Instruction
W = FFh ; (2s complement)
C = 0 ; result is negative
Z = 0
N = 1
SUBWF Subtract W from f
Syntax: SUBWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) (W) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 11da ffff ffff
Description: Subtract W from register f (2s
complement method). If d is 0, the
result is stored in W. If d is 1, the
result is stored back in register f
(default).
If a is 0, the Access Bank is
selected. If a is 1, the BSR is used
to select the GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f 95 (5Fh). See Section 26.2.3
Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example 1: SUBWF REG, 1, 0
Before Instruction
REG = 3
W = 2
C = ?
After Instruction
REG = 1
W = 2
C = 1 ; result is positive
Z = 0
N = 0
Example 2: SUBWF REG, 0, 0
Before Instruction
REG = 2
W = 2
C = ?
After Instruction
REG = 2
W = 0
C = 1 ; result is zero
Z = 1
N = 0
Example 3: SUBWF REG, 1, 0
Before Instruction
REG = 1
W = 2
C = ?
After Instruction
REG = FFh ;(2s complement)
W = 2
C = 0 ; result is negative
Z = 0
N = 1
PIC18F2455/2550/4455/4550
DS39632C-page 344 Preliminary 2006 Microchip Technology Inc.
SUBWFB Subtract W from f with Borrow
Syntax: SUBWFB f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) (W) (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 10da ffff ffff
Description: Subtract W and the Carry flag (borrow)
from register f (2s complement
method). If d is 0, the result is stored
in W. If d is 1, the result is stored back
in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example 1: SUBWFB REG, 1, 0
Before Instruction
REG = 19h (0001 1001)
W = 0Dh (0000 1101)
C = 1
After Instruction
REG = 0Ch (0000 1011)
W = 0Dh (0000 1101)
C = 1
Z = 0
N = 0 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 1Bh (0001 1011)
W = 1Ah (0001 1010)
C = 0
After Instruction
REG = 1Bh (0001 1011)
W = 00h
C = 1
Z = 1 ; result is zero
N = 0
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 03h (0000 0011)
W = 0Eh (0000 1101)
C = 1
After Instruction
REG = F5h (1111 0100)
; *2s comp+
W = 0Eh (0000 1101)
C = 0
Z = 0
N = 1 ; result is negative
SWAPF Swap f
Syntax: SWAPF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Affected: None
Encoding: 0011 10da ffff ffff
Description: The upper and lower nibbles of register
f are exchanged. If d is 0, the result
is placed in W. If d is 1, the result is
placed in register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: SWAPF REG, 1, 0
Before Instruction
REG = 53h
After Instruction
REG = 35h
2006 Microchip Technology Inc. Preliminary DS39632C-page 345
PIC18F2455/2550/4455/4550
TBLRD Table Read
Syntax: TBLRD ( *; *+; *-; +*)
Operands: None
Operation: if TBLRD *
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR No Change;
if TBLRD *+
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPTR;
if TBLRD *-
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) 1 TBLPTR;
if TBLRD +*
(TBLPTR) + 1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT
Status Affected: None
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLRD instruction can modify the value
of TBLPTR as follows:
no change
post-increment
post-decrement
pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
operation
No operation
(Write
TABLAT)
TBLRD Table Read (Continued)
Example 1: TBLRD *+ ;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
MEMORY (00A356h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 00A357h
Example 2: TBLRD +* ;
Before Instruction
TABLAT = AAh
TBLPTR = 01A357h
MEMORY (01A357h) = 12h
MEMORY (01A358h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 01A358h
PIC18F2455/2550/4455/4550
DS39632C-page 346 Preliminary 2006 Microchip Technology Inc.
TBLWT Table Write
Syntax: TBLWT ( *; *+; *-; +*)
Operands: None
Operation: if TBLWT*
(TABLAT) Holding Register;
TBLPTR No Change;
if TBLWT*+
(TABLAT) Holding Register;
(TBLPTR) + 1 TBLPTR;
if TBLWT*-
(TABLAT) Holding Register;
(TBLPTR) 1 TBLPTR;
if TBLWT+*
(TBLPTR) + 1 TBLPTR;
(TABLAT) Holding Register
Status Affected: None
Encoding: 0000 0000 0000 11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction uses the 3 LSBs of TBLPTR
to determine which of the
8 holding registers the TABLAT is written to.
The holding registers are used to
program the contents of Program
Memory (P.M.). (Refer to Section 6.0
Flash Program Memory for additional
details on programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range. The LSb of
the TBLPTR selects which byte of the
program memory location to access.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
no change
post-increment
post-decrement
pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
No
operation
No
operation
(Read
TABLAT)
No
operation
No
operation
(Write to
Holding
Register)
TBLWT Table Write (Continued)
Example 1: TBLWT *+;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
HOLDING REGISTER
(00A356h) = FFh
After Instructions (table write completion)
TABLAT = 55h
TBLPTR = 00A357h
HOLDING REGISTER
(00A356h) = 55h
Example 2: TBLWT +*;
Before Instruction
TABLAT = 34h
TBLPTR = 01389Ah
HOLDING REGISTER
(01389Ah) = FFh
HOLDING REGISTER
(01389Bh) = FFh
After Instruction (table write completion)
TABLAT = 34h
TBLPTR = 01389Bh
HOLDING REGISTER
(01389Ah) = FFh
HOLDING REGISTER
(01389Bh) = 34h
2006 Microchip Technology Inc. Preliminary DS39632C-page 347
PIC18F2455/2550/4455/4550
TSTFSZ Test f, Skip if 0
Syntax: TSTFSZ f {,a}
Operands: 0 f 255
a [0,1]
Operation: skip if f = 0
Status Affected: None
Encoding: 0110 011a ffff ffff
Description: If f = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE TSTFSZ CNT, 1
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
If CNT = 00h,
PC = Address (ZERO)
If CNT 00h,
PC = Address (NZERO)
XORLW Exclusive OR Literal with W
Syntax: XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W
Status Affected: N, Z
Encoding: 0000 1010 kkkk kkkk
Description: The contents of W are XORed with
the 8-bit literal k. The result is placed
in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal k
Process
Data
Write to W
Example: XORLW 0AFh
Before Instruction
W = B5h
After Instruction
W = 1Ah
PIC18F2455/2550/4455/4550
DS39632C-page 348 Preliminary 2006 Microchip Technology Inc.
XORWF Exclusive OR W with f
Syntax: XORWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .XOR. (f) dest
Status Affected: N, Z
Encoding: 0001 10da ffff ffff
Description: Exclusive OR the contents of W with
register f. If d is 0, the result is stored
in W. If d is 1, the result is stored back
in the register f (default).
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank (default).
If a is 0 and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 26.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register f
Process
Data
Write to
destination
Example: XORWF REG, 1, 0
Before Instruction
REG = AFh
W = B5h
After Instruction
REG = 1Ah
W = B5h
Aadir WREG y F
Aadir WREG y seguir poco a f
Y WREG con F
Claro f
Complementar f
Comparar f con WREG, skip =
Comparar f con WREG, omita>
Comparar f con WREG, omita <
Disminuir f
Disminuir f, Saltar si es 0
Disminuir f, Omitir si no 0
Incremento de f
Incrementar f, Saltar si es 0
Incremento de f, Omitir si no 0
Inclusive OR WREG con f
Mueva f
Mueva fs (fuente) a primera palabra
fd (destino) segunda palabra
Mueva WREG af
Multiplicar WREG con F
Niega f
Girar a la izquierda a travs de f Carry
Girar a la izquierda f (n Carry)
Gire f Derecho a travs de Carry
Gire f Derecha (No Carry)
Establecer f
Reste f desde WREG con
pedir prestado
Reste WREG de f
Reste WREG de f con
pedir prestado
Nibbles Intercambia en f
Prueba de f, vaya si 0
OR exclusivo WREG con f
Bit Clear f
Set Bit f
Prueba Bit f, Saltar si Clear
Prueba Bit f, Omitir si Set
Bit Toggle f
Bifurcacin si Carry
Bifurcacin si Negativo
Bifurcacin si no llevar
Rama cuando no negativa
Bifurcacin si no Overflow
Poder si no es cero
Bifurcacin si Overflow
Rama Incondicionalmente
Bifurcacin si Zero
Llame subrutina primera palabra
Segunda palabra
Borrar temporizador de vigilancia
Decimal Ajuste WREG
Ir a direccin primera palabra
Segunda palabra
No Operacin
No Operacin
Pop parte superior del tubo de retorno (TOS)
Empuje la parte superior de la pila de retorno (TOS)
Llamar relativa
Dispositivo Software Restablecer
Regreso de habilitacin de interrupcin
Regresa con literal en WREG
Retorno desde subrutina
Entra en el modo de espera
Aadir literal y WREG
Y literal con WREG
Inclusive OR literal con WREG
Mueva literal (12-bit) segunda palabra
al FSR (f) 1a palabra
Mueva literal a BSR <3:00>
Mueva literal a WREG
Multiplicar literal con WREG
Regresa con literal en WREG
Reste WREG desde literal
OR exclusivo literal con WREG
Table Read
Tabla Leer con post-incremento
Tabla Leer con el post-decremento
Tabla Leer con pre-incremento
Tabla de escritura
Tabla de escritura con el post-incremento
Tabla de escritura con el post-decremento
Tabla de escritura con el pre-incremento
ADDLW AADIR Literal a W
Sintaxis: ADDLW k
Operandos: 0 k 255
Operacin: (W) + k W
Estado afectado: N, OV, C, DC, Z
Codificacin: 0000 1111 kkkk kkkk
Descripcin: El contenido de W se aaden a la
8-bit literal "k" y el resultado se coloca en
W.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
literal "k"
Proceso
Datos
Escriba a W
Ejemplo: ADDLW 15h
Antes de Instruccin
W = 10h
Despus de Instruccin
W = 25h
ADDWF AADIR W af
Sintaxis: ADDWF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (W) + (f) dest
Estado afectado: N, OV, C, DC, Z
Codificacin: 0010 01DA ffff ffff
Descripcin: Agrega W a registrarse 'f'. Si 'd' es '0 ', el
resultado se almacena en W. Si 'd' es '1 ', la
resultado se almacena en el registro 'f'
(Por defecto).
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: ADDWF REG, 0, 0
Antes de Instruccin
W = 17h
REG = 0C2h
Despus de Instruccin
W = 0D9h
REG = 0C2h
Nota: Todas las instrucciones PIC18 pueden tomar un argumento etiqueta opcional, que precede a la regla mnemotcnica de instrucciones, para su uso en
direccionamiento simblico. Si se utiliza una etiqueta, el formato de la instruccin se convierte en: argumento (s) {label} instrucciones.
PIC18F2455/2550/4455/4550
DS39632C pginas 314 Preliminar 2006 Microchip Technology Inc.
ADDWFC AADIR W y seguir poco a f
Sintaxis: ADDWFC f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (W) + (f) + (C) dest
Estado afectado: N, OV, C, DC, Z
Codificacin: 0010 00da ffff ffff
Descripcin: Agrega W, la bandera de acarreo y la memoria de datos
location 'f'. Si 'd' es '0 ', el resultado es
colocado en W. Si 'd' es '1 ', el resultado es
colocado en la memoria los datos de ubicacin 'f'.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: ADDWFC REG, 0, 1
Antes de Instruccin
Llevar a bit = 1
REG = 02h
W = 4Dh
Despus de Instruccin
Llevar a bit = 0
REG = 02h
W = 50h
Andlw y literal con W
Sintaxis: andlw k
Operandos: 0 k 255
Operacin: (W) AND.. k W
Estado afectado: N, Z
Codificacin: 0000 1011 kkkk kkkk
Descripcin: El contenido de W se asocian con un AND con el
8-bit literal 'k'. El resultado se coloca en W.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer literal
'K'
Proceso
Datos
Escriba a W
Ejemplo: andlw 05Fh
Antes de Instruccin
W = A3h
Despus de Instruccin
W = 03h
2006 Microchip Technology Inc. DS39632C pginas Preliminar 315
PIC18F2455/2550/4455/4550
ANDWF Y W con f
Sintaxis: ANDWF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (W) AND.. (F) dest
Estado afectado: N, Z
Codificacin: 0001 01DA ffff ffff
Descripcin: El contenido de W se asocian con un AND con
registrarse 'f'. Si 'd' es '0 ', el resultado se almacena
en W. Si 'd' es '1 ', el resultado se almacena
en el registro 'f' (por defecto).
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: ANDWF REG, 0, 0
Antes de Instruccin
W = 17h
REG = C2h
Despus de Instruccin
W = 02h
REG = C2h
BC Bifurcacin si Carry
Sintaxis: BC n
Operandos: -128 n 127
Operacin: si el bit de acarreo es '1 '
(PC) + 2 + 2n PC
Estado afectado: Ninguno
Codificacin: 1110 0010 nnnn nnnn
Descripcin: Si el bit de acarreo es '1 ', entonces el programa
se ramifican.
Del 2 nmero complementario '2 n 'es
aadido a la PC. Desde el PC tendr
incrementado a buscar a la prxima
la instruccin, la nueva direccin ser
PC + 2 + 2n. Esta instruccin es entonces una
instruccin de dos ciclos.
Palabras: 1
Ciclos: 1 (2)
Q ciclo de actividades:
Si Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Si No Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
No
operacin
Ejemplo: AQU BC 5
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
Si Carry = 1;
PC = direccin (HERE + 12)
Si Carry = 0;
PC = direccin (HERE + 2)
PIC18F2455/2550/4455/4550
DS39632C pginas 316 Preliminar 2006 Microchip Technology Inc.
Bit Clear BCF f
Sintaxis: BCF f, b {un}
Operandos: 0 f 255
0 b 7
a [0,1]
Funcionamiento: 0 f <b>
Estado afectado: Ninguno
Codificacin: 1001 BBBA ffff ffff
Descripcin: Bit 'b' en el registro 'f' se borra.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escribir
registrarse 'f'
Ejemplo: BCF FLAG_REG, 7, 0
Antes de Instruccin
FLAG_REG = C7H
Despus de Instruccin
FLAG_REG = 47h
BN Bifurcacin si Negativo
Sintaxis: BN n
Operandos: -128 n 127
Operacin: si poco negativo es '1 '
(PC) + 2 + 2n PC
Estado afectado: Ninguno
Codificacin: 1110 0110 nnnn nnnn
Descripcin: Si el bit negativo es '1 ', entonces el
del programa se bifurcar.
Del 2 nmero complementario '2 n 'es
aadido a la PC. Desde el PC tendr
incrementado a buscar a la prxima
la instruccin, la nueva direccin ser
PC + 2 + 2n. Esta instruccin es entonces una
instruccin de dos ciclos.
Palabras: 1
Ciclos: 1 (2)
Q ciclo de actividades:
Si Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Si No Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
No
operacin
Ejemplo: AQU BN Jump
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
Si = Negativo 1;
PC = direccin (Salto)
Si = 0 negativos;
PC = direccin (HERE + 2)
2006 Microchip Technology Inc. DS39632C pginas Preliminar 317
PIC18F2455/2550/4455/4550
BNC Poder si no llevar
Sintaxis: BNC n
Operandos: -128 n 127
Operacin: si el bit de acarreo es '0 '
(PC) + 2 + 2n PC
Estado afectado: Ninguno
Codificacin: 1110 0011 nnnn nnnn
Descripcin: Si el bit de acarreo es '0 ', entonces el programa
se ramifican.
Del 2 nmero complementario '2 n 'es
aadido a la PC. Desde el PC tendr
incrementado a buscar a la prxima
la instruccin, la nueva direccin ser
PC + 2 + 2n. Esta instruccin es entonces una
instruccin de dos ciclos.
Palabras: 1
Ciclos: 1 (2)
Q ciclo de actividades:
Si Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Si No Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
No
operacin
Ejemplo: AQU BNC Jump
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
Si Carry = 0;
PC = direccin (Salto)
Si Carry = 1;
PC = direccin (HERE + 2)
BNN Rama cuando no negativa
Sintaxis: BNN n
Operandos: -128 n 127
Operacin: si poco negativo es '0 '
(PC) + 2 + 2n PC
Estado afectado: Ninguno
Codificacin: 1110 0111 nnnn nnnn
Descripcin: Si el bit negativo es '0 ', entonces la
del programa se bifurcar.
Del 2 nmero complementario '2 n 'es
aadido a la PC. Desde el PC tendr
incrementado a buscar a la prxima
la instruccin, la nueva direccin ser
PC + 2 + 2n. Esta instruccin es entonces una
instruccin de dos ciclos.
Palabras: 1
Ciclos: 1 (2)
Q ciclo de actividades:
Si Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Si No Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
No
operacin
Ejemplo: AQU BNN Jump
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
Si = 0 negativos;
PC = direccin (Salto)
Si = Negativo 1;
PC = direccin (HERE + 2)
PIC18F2455/2550/4455/4550
DS39632C pginas 318 Preliminar 2006 Microchip Technology Inc.
BNOV Poder si no Overflow
Sintaxis: BNOV n
Operandos: -128 n 127
Operacin: si desbordamiento bit es '0 '
(PC) + 2 + 2n PC
Estado afectado: Ninguno
Codificacin: 1110 0101 nnnn nnnn
Descripcin: Si el bit de desbordamiento es '0 ', entonces la
del programa se bifurcar.
Del 2 nmero complementario '2 n 'es
aadido a la PC. Desde el PC tendr
incrementado a buscar a la prxima
la instruccin, la nueva direccin ser
PC + 2 + 2n. Esta instruccin es entonces una
instruccin de dos ciclos.
Palabras: 1
Ciclos: 1 (2)
Q ciclo de actividades:
Si Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Si No Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
No
operacin
Ejemplo: AQU BNOV Jump
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
Si Overflow = 0;
PC = direccin (Salto)
Si Overflow = 1;
PC = direccin (HERE + 2)
BNZ Poder si no es cero
Sintaxis: BNZ n
Operandos: -128 n 127
Operacin: si el bit cero es '0 '
(PC) + 2 + 2n PC
Estado afectado: Ninguno
Codificacin: 1110 0001 nnnn nnnn
Descripcin: Si el bit cero es '0 ', entonces el programa
se ramifican.
Del 2 nmero complementario '2 n 'es
aadido a la PC. Desde el PC tendr
incrementado a buscar a la prxima
la instruccin, la nueva direccin ser
PC + 2 + 2n. Esta instruccin es entonces una
instruccin de dos ciclos.
Palabras: 1
Ciclos: 1 (2)
Q ciclo de actividades:
Si Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Si No Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
No
operacin
Ejemplo: AQU BNZ Jump
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
Si cero = 0;
PC = direccin (Salto)
Si Zero = 1;
PC = direccin (HERE + 2)
2006 Microchip Technology Inc. DS39632C pginas Preliminar 319
PIC18F2455/2550/4455/4550
BRA Incondicional Rama
Sintaxis: BRA n
Operandos: -1,024 n 1023
Operacin: (PC) + 2 + 2n PC
Estado afectado: Ninguno
Codificacin: 1101 0nnn nnnn nnnn
Descripcin: Aadir el nmero complementario del 2 '2 n 'para
el PC. Desde el PC tendr
incrementado a buscar a la prxima
la instruccin, la nueva direccin ser
PC + 2 + 2n. Esta instruccin es una
instruccin de dos ciclos.
Palabras: 1
Ciclos: 2
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU BRA Jump
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
PC = direccin (Salto)
BSF Bit Set f
Sintaxis: BSF f, b {un}
Operandos: 0 f 255
0 b 7
a [0,1]
Operacin: 1 f <b>
Estado afectado: Ninguno
Codificacin: 1000 BBBA ffff ffff
Descripcin: Bit 'b' en el registro 'f' se establece.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escribir
registrarse 'f'
Ejemplo: BSF FLAG_REG, 7, 1
Antes de Instruccin
FLAG_REG = 0Ah
Despus de Instruccin
FLAG_REG = 8Ah
PIC18F2455/2550/4455/4550
DS39632C pginas 320 Preliminar 2006 Microchip Technology Inc.
BTFSC Bit archivo de prueba, Saltar si Clear
Sintaxis: BTFSC f, b {un}
Operandos: 0 f 255
0 b 7
a [0,1]
Operacin: skip if (f <b>) = 0
Estado afectado: Ninguno
Codificacin: 1011 BBBA ffff ffff
Descripcin: Si el bit "b" en el registro "f" es '0 ', entonces el siguiente
instruccin se salta. Si 'b' bit es '0 ',
la siguiente instruccin extrada durante el
ejecucin de la instruccin actual se descarta
y un NOP se ejecuta en lugar, haciendo
esta una instruccin de dos ciclos.
Si 'a' es '0 ', se selecciona el Banco de Acceso. Si
'A' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, esta instruccin opera en
Indexado Literal Offset Dirigindose
modo cada vez que f 95 (5Fh).
Vea la seccin 26.2.3 "Byte-Oriented y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1 (2)
Nota: 3 ciclos si saltar y seguido
por una instruccin de 2 palabras.
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
No
operacin
Si saltar:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
Si saltar y seguido por la instruccin 2 palabras:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
Si FLAG <1> = 0;
PC = direccin (TRUE)
Si FLAG <1> = 1;
PC = direccin (FALSO)
BTFSS Bit archivo de prueba, Omitir si Set
Sintaxis: BTFSS f, b {un}
Operandos: 0 f 255
0 b <7
a [0,1]
Operacin: skip if (f <b>) = 1
Estado afectado: Ninguno
Codificacin: 1010 BBBA ffff ffff
Descripcin: Si el bit "b" en el registro "f" es '1 ', entonces el siguiente
instruccin se salta. Si 'b' bit es '1 ', entonces
la siguiente instruccin extrada durante el
ejecucin de la instruccin actual se descarta
y un NOP se ejecuta en lugar, haciendo
esta una instruccin de dos ciclos.
Si 'a' es '0 ', se selecciona el Banco de Acceso. Si
'A' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh).
Vea la seccin 26.2.3 "Byte-Oriented y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1 (2)
Nota: 3 ciclos si saltar y seguido
por una instruccin de 2 palabras.
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
No
operacin
Si saltar:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
Si saltar y seguido por la instruccin 2 palabras:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
Si FLAG <1> = 0;
PC = direccin (FALSO)
Si FLAG <1> = 1;
PC = direccin (TRUE)
2006 Microchip Technology Inc. DS39632C pginas Preliminar 321
PIC18F2455/2550/4455/4550
BTG Bit Toggle f
Sintaxis: BTG f, b {un}
Operandos: 0 f 255
0 b <7
a [0,1]
Operacin: (f <b>) f <b>
Estado afectado: Ninguno
Codificacin: 0111 BBBA ffff ffff
Descripcin: Bit 'b' en la posicin de memoria de datos 'f' es
invertida.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escribir
registrarse 'f'
Ejemplo: BTG PORTC, 4, 0
Antes de la instruccin:
PORTC = 0111 0101 [75h]
Despus de la instruccin:
PORTC = 0110 0101 [65h]
BOV Bifurcacin si Overflow
Sintaxis: BOV n
Operandos: -128 n 127
Operacin: si desbordamiento bit es '1 '
(PC) + 2 + 2n PC
Estado afectado: Ninguno
Codificacin: 1110 0100 nnnn nnnn
Descripcin: Si el bit de desbordamiento es '1 ', entonces la
del programa se bifurcar.
Del 2 nmero complementario '2 n 'es
aadido a la PC. Desde el PC tendr
incrementado a buscar a la prxima
la instruccin, la nueva direccin ser
PC + 2 + 2n. Esta instruccin es entonces una
instruccin de dos ciclos.
Palabras: 1
Ciclos: 1 (2)
Q ciclo de actividades:
Si Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Si No Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
No
operacin
Ejemplo: AQU BOV Jump
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
Si Overflow = 1;
PC = direccin (Salto)
Si Overflow = 0;
PC = direccin (HERE + 2)
PIC18F2455/2550/4455/4550
DS39632C pginas 322 Preliminar 2006 Microchip Technology Inc.
BZ Bifurcacin si Zero
Sintaxis: BZ n
Operandos: -128 n 127
Operacin: si el bit cero es '1 '
(PC) + 2 + 2n PC
Estado afectado: Ninguno
Codificacin: 1110 0000 nnnn nnnn
Descripcin: Si el bit cero es '1 ', entonces el programa
se ramifican.
Del 2 nmero complementario '2 n 'es
aadido a la PC. Desde el PC tendr
incrementado a buscar a la prxima
la instruccin, la nueva direccin ser
PC + 2 + 2n. Esta instruccin es entonces una
instruccin de dos ciclos.
Palabras: 1
Ciclos: 1 (2)
Q ciclo de actividades:
Si Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Si No Jump:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Proceso
Datos
No
operacin
Ejemplo: AQU BZ Jump
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
Si Zero = 1;
PC = direccin (Salto)
Si cero = 0;
PC = direccin (HERE + 2)
Llamada a subprograma Call
Sintaxis: CALL {k, s}
Operandos: 0 k 1048575
s [0,1]
Operacin: (PC) + 4 TOS,
k PC <20:01>,
si s = 1
(W) WS,
(STATUS) STATUSS,
(BSR) BSRS
Estado afectado: Ninguno
Codificacin:
Primera palabra (k <07:00>)
Segunda palabra (k <19:08>)
1110
1111
110s
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Descripcin: Llamada a subprograma de todo 2 Mbytes
rango de memoria. En primer lugar, la direccin del remitente
(PC + 4) se inserta en el retorno
apilar. Si 's' = 1, el W, STATUS y
BSR
registros tambin se introducen en los
registros respectivos sombra, WS,
STATUSS y BSRS. Si 's' = 0, sin
actualizacin se produce (por defecto). Entonces, la
Valor de 20 bits "k" se carga en PC <20:01>.
CALL es una instruccin de dos ciclos.
Palabras: 2
Ciclos: 2
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer literal
'K' <07:00>,
Empuje PC
montn
Leer literal
'K' <19:08>,
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: CALL AQU HAY, 1
Antes de Instruccin
PC = direccin (AQU)
Despus de Instruccin
PC = direccin (NO)
TOS = direccin (HERE + 4)
WS = W
BSRS = BSR
STATUSS = ESTADO
2006 Microchip Technology Inc. DS39632C pginas Preliminar 323
PIC18F2455/2550/4455/4550
CLRF Claro f
Sintaxis: CLRF F {,} un
Operandos: 0 f 255
a [0,1]
Operacin: 000h f,
1 Z
Estado afectado: Z
Codificacin: 0110 101a ffff ffff
Descripcin: Borra el contenido de la especificada
registrarse.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escribir
registrarse 'f'
Ejemplo: CLRF FLAG_REG, 1
Antes de Instruccin
FLAG_REG = 5Ah
Despus de Instruccin
FLAG_REG = 00h
CLRWDT Borrar temporizador de vigilancia
Sintaxis: CLRWDT
Operandos: Ninguno
Operacin: 000h WDT,
000h postscaler WDT,
1 A,
1 PD
Estado Afectado: TO, PD
Codificacin: 0000 0000 0000 0100
Descripcin: La instruccin CLRWDT restablece el
Watchdog Timer. Tambin restablece el
postscaler del WDT. Los bits de estado, AL
y PD, se establecen.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode No
operacin
Proceso
Datos
No
operacin
Ejemplo: CLRWDT
Antes de Instruccin
Contador WDT =?
Despus de Instruccin
Contador WDT = 00h
WDT postscaler = 0
A = 1
PD = 1
PIC18F2455/2550/4455/4550
DS39632C pginas 324 Preliminar 2006 Microchip Technology Inc.
COMF Complemento f
Sintaxis: COMF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f) dest
Estado afectado: N, Z
Codificacin: 0001 11da ffff ffff
Descripcin: El contenido del registro 'f' son
complementado. Si 'd' es '0 ', el resultado es
almacenada en W. Si 'd' es '1 ', el resultado es
almacenado de nuevo en el registro 'f' (por defecto).
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: COMF REG, 0, 0
Antes de Instruccin
REG = 13h
Despus de Instruccin
REG = 13h
W = ECh
CPFSEQ Comparar f con W, Saltar si f = W
Sintaxis: CPFSEQ F {,} un
Operandos: 0 f 255
a [0,1]
Operacin: (f) - (W),
skip if (f) = (W)
(Comparacin sin signo)
Estado afectado: Ninguno
Codificacin: 0110 001a ffff ffff
Descripcin: Compara el contenido de la memoria de datos
ubicacin "f" al contenido de W por
la realizacin de una resta sin signo.
Si 'f' = W, entonces la instruccin extrada es
descarta y se ejecuta un NOP
en su lugar, haciendo de este un ciclo de dos
instrucciones.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1 (2)
Nota: 3 ciclos si saltar y seguido
por una instruccin de 2 palabras.
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
No
operacin
Si saltar:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
Si saltar y seguido por la instruccin 2 palabras:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU CPFSEQ REG, 0
Nequal:
EQUAL:
Antes de Instruccin
PC Direccin = AQUI
#NAME?
REG =?
Despus de Instruccin
Si REG = W;
PC = Direccin (EQUAL)
Si REG W;
PC = Direccin (Nequal)
2006 Microchip Technology Inc. DS39632C pginas Preliminar 325
PIC18F2455/2550/4455/4550
CPFSGT Comparar f con W, Omitir si f> W
Sintaxis: CPFSGT F {,} un
Operandos: 0 f 255
a [0,1]
Operacin: (f) - (W),
skip if (f)> (W)
(Comparacin sin signo)
Estado afectado: Ninguno
Codificacin: 0110 010a ffff ffff
Descripcin: Compara el contenido de la memoria de datos
ubicacin "f" al contenido de la W por
la realizacin de una resta sin signo.
Si el contenido de 'f' es mayor que el
contenido de WREG, entonces el exagerado
instruccin se descarta y un NOP es
ejecutado en su lugar, haciendo de este un
instruccin de dos ciclos.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1 (2)
Nota: 3 ciclos si saltar y seguido
por una instruccin de 2 palabras.
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
No
operacin
Si saltar:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
Si saltar y seguido por la instruccin 2 palabras:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU CPFSGT REG, 0
NGREATER:
MAYOR:
Antes de Instruccin
PC = Direccin (AQU)
#NAME?
Despus de Instruccin
Si REG> W;
PC = Direccin (MAYOR)
Si REG W;
PC = Direccin (NGREATER)
CPFSLT Comparar f con W, Omitir si f <W
Sintaxis: CPFSLT F {,} un
Operandos: 0 f 255
a [0,1]
Operacin: (f) - (W),
skip if (f) <(W)
(Comparacin sin signo)
Estado afectado: Ninguno
Codificacin: 0110 000a ffff ffff
Descripcin: Compara el contenido de la memoria de datos
ubicacin "f" al contenido de W por
la realizacin de una resta sin signo.
Si el contenido de 'f' son menos de la
contenido de W, entonces el exagerado
instruccin se descarta y un NOP es
ejecutado en su lugar, haciendo de este un
instruccin de dos ciclos.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Palabras: 1
Ciclos: 1 (2)
Nota: 3 ciclos si saltar y seguido
por una instruccin de 2 palabras.
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
No
operacin
Si saltar:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
Si saltar y seguido por la instruccin 2 palabras:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU CPFSLT REG, 1
Alvo:
MENOS:
Antes de Instruccin
PC = Direccin (AQU)
#NAME?
Despus de Instruccin
Si REG <W;
PC = Direccin (LESS)
Si REG W;
PC = Direccin (alvo)
PIC18F2455/2550/4455/4550
DS39632C pginas 326 Preliminar 2006 Microchip Technology Inc.
DAW Decimal Ajuste W Registrarse
Sintaxis: DAW
Operandos: Ninguno
Funcionamiento: Si [W <03:00 >> 9] o [DC = 1] y luego
(W <03:00>) + 6 W <3:00> ;
ms
(W <03:00>) W <3:00>
Si [W <7:04> + DC> 9] o [C = 1] y luego
(W <7:4>) + 6 + DC W <7:04>;
ms
(W <07:04>) + DC W <7:04>
Estado afectado: C
Codificacin: 0000 0000 0000 0111
Descripcin: DAW ajusta el valor de ocho bits en W,
resultante de la adicin anterior de dos
las variables (cada una en formato BCD para llevar)
y produce un BCD empaquetado correcto
resultado.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse W
Proceso
Datos
Escribir
W
Ejemplo 1: DAW
Antes de Instruccin
W = A5H
C = 0
DC = 0
Despus de Instruccin
W = 05h
C = 1
DC = 0
Ejemplo 2:
Antes de Instruccin
W = CEH
C = 0
DC = 0
Despus de Instruccin
W = 34h
C = 1
DC = 0
DECF Disminuir f
Sintaxis: DECF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f) - 1 dest
Estado afectado: C, CC, N, OV, Z
Codificacin: 0000 01DA ffff ffff
Descripcin: Disminuye el Registro 'f'. Si 'd' es '0 ', el
resultado se almacena en W. Si 'd' es '1 ', la
resultado se almacena en el registro 'f'
(Por defecto).
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: DECF CNT, 1, 0
Antes de Instruccin
CNT = 01h
Z = 0
Despus de Instruccin
CNT = 00h
Z = 1
2006 Microchip Technology Inc. DS39632C pginas Preliminar 327
PIC18F2455/2550/4455/4550
DECFSZ Disminuir f, Saltar si es 0
Sintaxis: DECFSZ f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f) - 1 dest,
saltar si el resultado = 0
Estado afectado: Ninguno
Codificacin: 0010 11da ffff ffff
Descripcin: El contenido del registro 'f' son
decrementado. Si 'd' es '0 ', el resultado es
colocado en W. Si 'd' es '1 ', el resultado es
se coloc de nuevo en el registro 'f' (por defecto).
Si el resultado es '0 ', la siguiente instruccin,
que ya se capta, se desecha
y un NOP se ejecuta en lugar, haciendo
es una instruccin de dos ciclos.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1 (2)
Nota: 3 ciclos si saltar y seguido
por una instruccin de 2 palabras.
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Si saltar:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
Si saltar y seguido por la instruccin 2 palabras:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU DECFSZ CNT, 1, 1
GOTO BUCLE
CONTINUAR
Antes de Instruccin
PC = Direccin (AQU)
Despus de Instruccin
CNT CNT = - 1
Si CNT = 0;
PC = Direccin (CONTINUE)
Si CNT 0;
PC = Direccin (HERE + 2)
DCFSNZ Disminuir f, Omitir si no 0
Sintaxis: DCFSNZ f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f) - 1 dest,
saltar si el resultado 0
Estado afectado: Ninguno
Codificacin: 0100 11da ffff ffff
Descripcin: El contenido del registro 'f' son
decrementado. Si 'd' es '0 ', el resultado es
colocado en W. Si 'd' es '1 ', el resultado es
se coloc de nuevo en el registro 'f' (por defecto).
Si el resultado no es '0 ', la siguiente
instruccin, que ya se fue a buscar, es
descarta y se ejecuta un NOP
en cambio, lo que es un ciclo de dos
instrucciones.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1 (2)
Nota: 3 ciclos si saltar y seguido
por una instruccin de 2 palabras.
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Si saltar:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
Si saltar y seguido por la instruccin 2 palabras:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU DCFSNZ TEMP, 1, 0
ZERO:
NZERO:
Antes de Instruccin
TEMP =?
Despus de Instruccin
TEMP TEMP = - 1,
Si TEMP = 0;
PC = Direccin (CERO)
Si TEMP 0;
PC = Direccin (NZERO)
PIC18F2455/2550/4455/4550
DS39632C pginas 328 Preliminar 2006 Microchip Technology Inc.
GOTO Incondicional Rama
Sintaxis: GOTO k
Operandos: 0 k 1048575
Operacin: k PC <20:01>
Estado afectado: Ninguno
Codificacin:
Primera palabra (k <07:00>)
Segunda palabra (k <19:08>)
1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Descripcin: GOTO permite un salto incondicional
en cualquier lugar dentro de la totalidad
Rango de memoria de 2 Mbytes. El de 20 bits
valor "k" se carga en PC <20:01>. GOTO
es siempre una instruccin de dos ciclos.
Palabras: 2
Ciclos: 2
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer literal
'K' <07:00>,
No
operacin
Leer literal
'K' <19:08>,
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: GOTO NO
Despus de Instruccin
PC = Direccin (NO)
INCF Incremento de f
Sintaxis: INCF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f) + 1 dest
Estado afectado: C, CC, N, OV, Z
Codificacin: 0010 10da ffff ffff
Descripcin: El contenido del registro 'f' son
incrementado. Si 'd' es '0 ', el resultado es
colocado en W. Si 'd' es '1 ', el resultado es
se coloc de nuevo en el registro 'f' (por defecto).
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: INCF CNT, 1, 0
Antes de Instruccin
CNT = FFh
Z = 0
C =?
#NAME?
Despus de Instruccin
CNT = 00h
Z = 1
C = 1
CC = 1
2006 Microchip Technology Inc. DS39632C pginas Preliminar 329
PIC18F2455/2550/4455/4550
INCFSZ Incremento de f, Saltar si es 0
Sintaxis: INCFSZ f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f) + 1 dest,
saltar si el resultado = 0
Estado afectado: Ninguno
Codificacin: 0011 11da ffff ffff
Descripcin: El contenido del registro 'f' son
incrementado. Si 'd' es '0 ', el resultado es
colocado en W. Si 'd' es '1 ', el resultado es
se coloc de nuevo en el registro 'f'. (Por defecto)
Si el resultado es '0 ', la siguiente instruccin,
que ya se capta, se desecha
y un NOP se ejecuta en lugar, haciendo
es una instruccin de dos ciclos.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1 (2)
Nota: 3 ciclos si saltar y seguido
por una instruccin de 2 palabras.
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Si saltar:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
Si saltar y seguido por la instruccin 2 palabras:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU INCFSZ CNT, 1, 0
NZERO:
ZERO:
Antes de Instruccin
PC = Direccin (AQU)
Despus de Instruccin
CNT CNT = + 1
Si CNT = 0;
PC = Direccin (CERO)
Si CNT 0;
PC = Direccin (NZERO)
INFSNZ Incremento de f, Omitir si no 0
Sintaxis: INFSNZ f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f) + 1 dest,
saltar si el resultado 0
Estado afectado: Ninguno
Codificacin: 0100 10da ffff ffff
Descripcin: El contenido del registro 'f' son
incrementado. Si 'd' es '0 ', el resultado es
colocado en W. Si 'd' es '1 ', el resultado es
se coloc de nuevo en el registro 'f' (por defecto).
Si el resultado no es '0 ', la siguiente
instruccin, que ya se fue a buscar, es
descarta y se ejecuta un NOP
en cambio, lo que es un ciclo de dos
instrucciones.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1 (2)
Nota: 3 ciclos si saltar y seguido
por una instruccin de 2 palabras.
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Si saltar:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
Si saltar y seguido por la instruccin 2 palabras:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU INFSNZ REG, 1, 0
ZERO
NZERO
Antes de Instruccin
PC = Direccin (AQU)
Despus de Instruccin
REG = REG + 1
Si REG 0;
PC = Direccin (NZERO)
Si REG = 0;
PC = Direccin (CERO)
PIC18F2455/2550/4455/4550
DS39632C pginas 330 Preliminar 2006 Microchip Technology Inc.
IORLW Inclusive OR Literal con W
Sintaxis: IORLW k
Operandos: 0 k 255
Operacin:. (W) OR. k W
Estado afectado: N, Z
Codificacin: 0000 1001 kkkk kkkk
Descripcin: El contenido de W se ORed con el
ocho bits literal 'k'. El resultado se coloca en
W.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
literal "k"
Proceso
Datos
Escriba a W
Ejemplo: IORLW 35h
Antes de Instruccin
W = 9Ah
Despus de Instruccin
W = BFh
IORWF Inclusive OR W con f
Sintaxis: IORWF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin:. (W) OR. (F) dest
Estado afectado: N, Z
Codificacin: 0001 00da ffff ffff
Descripcin: Inclusive OR W con registro 'f'. Si 'd' es
'0 ', El resultado se coloca en W. Si' d 'es '1',
el resultado se vuelve a colocar en el registro 'f'
(Por defecto).
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: IORWF RESULTADO, 0, 1
Antes de Instruccin
RESULTADO = 13h
W = 91h
Despus de Instruccin
RESULTADO = 13h
W = 93h
2006 Microchip Technology Inc. DS39632C pginas Preliminar 331
PIC18F2455/2550/4455/4550
FSR Cargar LFSR
Sintaxis: LFSR f, k
Operandos: 0 f 2
0 k 4095
Operacin: k FSRf
Estado afectado: Ninguno
Codificacin: 1110
1111
1110
0
00ff
k7kkk
k11kkk
kkkk
Descripcin: El literal 'k' de 12 bits se carga en el
Seleccionar archivo Registro apuntado por 'f'.
Palabras: 2
Ciclos: 2
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer literal
'K' MSB
Proceso
Datos
Escribir
literal "k" MSB
a FSRfH
Decode Leer literal
'K' LSB
Proceso
Datos
Escribe literal 'k'
a FSRfL
Ejemplo: LFSR 2, 3ABh
Despus de Instruccin
FSR2H = 03h
FSR2L = ABh
MOVF Mueva f
Sintaxis: MOVF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: f dest
Estado afectado: N, Z
Codificacin: 0101 00da ffff ffff
Descripcin: El contenido del registro 'f' se mueven a
un destino depende de la
estado de 'd'. Si 'd' es '0 ', el resultado es
colocado en W. Si 'd' es '1 ', el resultado es
se coloc de nuevo en el registro 'f' (por defecto).
Ubicacin 'f' puede estar en cualquier lugar en el
Banco de 256 bytes.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escribe W
Ejemplo: MOVF REG, 0, 0
Antes de Instruccin
REG = 22h
W = FFh
Despus de Instruccin
REG = 22h
W = 22h
PIC18F2455/2550/4455/4550
DS39632C pginas 332 Preliminar 2006 Microchip Technology Inc.
MOVFF Mueva f af
Sintaxis: fs MOVFF, fd
Operandos: 0 fs 4095
0 fd 4095
Operacin: (fs) fd
Estado afectado: Ninguno
Codificacin:
Primera palabra (fuente)
Segunda palabra (destin.)
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Descripcin: El contenido de la fuente registran 'FS' son
trasladado a registro destino 'fd'.
Lugar de origen 'fs' puede estar en cualquier lugar
en el espacio de datos de 4096 bytes (000h a
FFFh) y la ubicacin de destino 'fd'
Tambin puede ser en cualquier lugar de 000h a
FFFh.
El origen o el destino pueden ser W
(Una situacin especial til).
MOVFF es particularmente til para los
la transferencia de una ubicacin de memoria de datos a un
registro perifrico (tales como la transmisin
tampn o un puerto de E / S).
La instruccin MOVFF no puede utilizar el
PCL, TOSU, TOSH o TOSL como
registro de destino.
Palabras: 2
Ciclos: 2
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
(Src)
Proceso
Datos
No
operacin
Decode No
operacin
No maniqu
leer
No
operacin
Escribir
registrarse 'f'
(Dest)
Ejemplo: REG1 MOVFF, REG2
Antes de Instruccin
REG1 = 33h
REG2 = 11h
Despus de Instruccin
REG1 = 33h
REG2 = 33h
MOVLB Mueva Literal a Menor Nibble en BSR
Sintaxis: MOVLW k
Operandos: 0 k 255
Operacin: k BSR
Estado afectado: Ninguno
Codificacin: 0000 0001 kkkk kkkk
Descripcin: El literal 'k' de ocho bits se carga en el
Bank Select Register (BSR). El valor
de BSR <7:4> permanece siempre '0 '
independientemente del valor de K7: K4.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
literal "k"
Proceso
Datos
Escribe literal
'K' a BSR
Ejemplo: MOVLB 5
Antes de Instruccin
BSR Registro = 02h
Despus de Instruccin
BSR Registro = 05h
2006 Microchip Technology Inc. DS39632C pginas Preliminar 333
PIC18F2455/2550/4455/4550
Movlw Mueva Literal a W
Sintaxis: MOVLW k
Operandos: 0 k 255
Operacin: k W
Estado afectado: Ninguno
Codificacin: 0000 1110 kkkk kkkk
Descripcin: El literal "k" de ocho bits se carga en W.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
literal "k"
Proceso
Datos
Escriba a W
Ejemplo: MOVLW 5Ah
Despus de Instruccin
W = 5Ah
MOVWF Mover W af
Sintaxis: MOVWF f {,} un
Operandos: 0 f 255
a [0,1]
Operacin: (W) f
Estado afectado: Ninguno
Codificacin: 0110 111a ffff ffff
Descripcin: Mover datos de W para registrarse 'f'.
Ubicacin 'f' puede estar en cualquier lugar en el
Banco de 256 bytes.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escribir
registrarse 'f'
Ejemplo: MOVWF REG, 0
Antes de Instruccin
W = 4Fh
REG = FFh
Despus de Instruccin
W = 4Fh
REG = 4Fh
PIC18F2455/2550/4455/4550
DS39632C pginas 334 Preliminar 2006 Microchip Technology Inc.
MULLW Multiplicar Literal con W
Sintaxis: MULLW k
Operandos: 0 k 255
Operacin: (W) x k PRODH: Prdl
Estado afectado: Ninguno
Codificacin: 0000 1101 kkkk kkkk
Descripcin: Una multiplicacin sin signo se lleva
entre el contenido de W y el
8-bit literal 'k'. El resultado de 16 bits es
colocado en PRODH: Prdl par de registros.
PRODH contiene el byte alto.
W es sin cambios.
Ninguno de los indicadores de estado se ven afectados.
Tenga en cuenta que ni el desbordamiento ni Carry es
posible en esta operacin. Un resultado de cero
es posible, pero no detectado.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
literal "k"
Proceso
Datos
Escribir
registros
PRODH:
Prdl
Ejemplo: MULLW 0C4h
Antes de Instruccin
W = E2H
PRODH =?
Prdl =?
Despus de Instruccin
W = E2H
PRODH = ADH
Prdl = 08h
MULWF Multiplicar W con f
Sintaxis: MULWF F {,} un
Operandos: 0 f 255
a [0,1]
Operacin: (W) x (f) PRODH: Prdl
Estado afectado: Ninguno
Codificacin: 0000 001a ffff ffff
Descripcin: Una multiplicacin sin signo se lleva
entre el contenido de W y el
registrarse file location 'f'. El de 16 bits
resultado se almacena en el PRODH: Prdl
regstrese par. PRODH contiene la
byte alto. Tanto W y 'f' son
sin cambios.
Ninguno de los indicadores de estado se ven afectados.
Tenga en cuenta que ni el desbordamiento ni Carry es
posible en esta operacin. Un cero
resultado es posible, pero no detecta.
Si 'a' es '0 ', el Banco El acceso es
seleccionada. Si 'a' es '1 ', se utiliza la BSR
para seleccionar el banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, esta instruccin
opera en Indexed Literal Offset
Modo de direccionamiento siempre
f 95 (5Fh). Consulte la Seccin 26.2.3
Byte orientada y orientada-Bit
Las instrucciones de indexado Literal Offset
Mode para obtener ms informacin.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escribir
registros
PRODH:
Prdl
Ejemplo: MULWF REG, 1
Antes de Instruccin
W = C4h
REG = B5h
PRODH =?
Prdl =?
Despus de Instruccin
W = C4h
REG = B5h
PRODH = 8Ah
Prdl = 94h
2006 Microchip Technology Inc. DS39632C pginas Preliminar 335
PIC18F2455/2550/4455/4550
NEGF Negar f
Sintaxis: NEGF F {,} un
Operandos: 0 f 255
a [0,1]
Operacin: (f) + 1 f
Estado afectado: N, OV, C, DC, Z
Codificacin: 0110 110a ffff ffff
Descripcin: Location 'f' es negado el uso de dos de
complementar. El resultado se coloca en el
posicin de la memoria de datos 'f'.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escribir
registrarse 'f'
Ejemplo: NEGF REG, 1
Antes de Instruccin
REG = 0011 1010 [3Ah]
Despus de Instruccin
REG = 1100 0110 [C6H]
NOP Sin operacin
Sintaxis: NOP
Operandos: Ninguno
Operacin: Ninguna operacin
Estado afectado: Ninguno
Codificacin: 0000
1111
0
xxxx
0
xxxx
0
xxxx
Descripcin: No hay operacin.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode No
operacin
No
operacin
No
operacin
Ejemplo:
Ninguno.
PIC18F2455/2550/4455/4550
DS39632C pginas 336 Preliminar 2006 Microchip Technology Inc.
POP Pop Top of Return Stack
Sintaxis: POP
Operandos: Ninguno
Operacin: (TOS) Cuchara bits
Estado afectado: Ninguno
Codificacin: 0000 0000 0000 0110
Descripcin: El valor de TOS se quit el retorno
apilar y se desecha. El valor TOS
a continuacin, se convierte en el valor anterior que
se inserta en la pila de retorno.
Esta instruccin se proporciona para permitir
al usuario a manejar adecuadamente el retorno
apilar para incorporar una pila de software.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode No
operacin
Pop TOS
valor
No
operacin
Ejemplo: POP
GOTO NUEVO
Antes de Instruccin
TOS = 0031A2h
Stack (1 nivel hacia abajo) = 014332h
Despus de Instruccin
TOS = 014332h
PC = NUEVO
Push Push Top of Return Stack
Sintaxis: PUSH
Operandos: Ninguno
Operacin: (PC + 2) TOS
Estado afectado: Ninguno
Codificacin: 0000 0000 0000 0101
Descripcin: El PC + 2 se inserta en la parte superior de
la pila de retorno. El TOS anterior
valor es empujado hacia abajo en la pila.
Esta instruccin permite la implementacin de un
pila de software mediante la modificacin de condiciones de servicio y
a continuacin, empujando en la pila de retorno.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Empuje PC + 2
en retorno
montn
No
operacin
No
operacin
Ejemplo: PUSH
Antes de Instruccin
TOS = 345Ah
PC = 0124h
Despus de Instruccin
PC = 0126h
TOS = 0126h
Stack (1 nivel hacia abajo) = 345Ah
2006 Microchip Technology Inc. DS39632C pginas Preliminar 337
PIC18F2455/2550/4455/4550
Rcall Call relativa
Sintaxis: rcall n
Operandos: -1,024 n 1023
Operacin: (PC) + 2 TOS,
(PC) + 2 + 2n PC
Estado afectado: Ninguno
Codificacin: 1101 1nnn nnnn nnnn
Descripcin: Llamada de subprograma con un salto hasta 1K
desde la ubicacin actual. En primer lugar, el retorno
direccin (PC + 2) se inserta en la
apilar. A continuacin, agregue el complemento a 2
nmero '2 n 'al PC. Desde la voluntad de PC
han incrementado a buscar a la prxima
la instruccin, la nueva direccin ser
PC + 2 + 2n. Esta instruccin es una
instruccin de dos ciclos.
Palabras: 1
Ciclos: 2
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer literal
'N'
Empuje PC
montn
Proceso
Datos
Escriba a PC
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU rcall Jump
Antes de Instruccin
PC = Direccin (AQU)
Despus de Instruccin
PC = Direccin (Salto)
TOS = Direccin (HERE + 2)
Restaurar Volver
Sintaxis: reset
Operandos: Ninguno
Operacin: Borrar todos los registros y banderas que son
afectada por un Reset MCLR.
Estado afectado: Todo
Codificacin: 0000 0000 1111 1111
Descripcin: Esta instruccin proporciona una manera de
ejecutar un Reset MCLR en software.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Inicio
Reajustar
No
operacin
No
operacin
Ejemplo: REAJUSTE
Despus de Instruccin
Registros = Valor de reset
Banderas * = Valor de reset
PIC18F2455/2550/4455/4550
DS39632C pginas 338 Preliminar 2006 Microchip Technology Inc.
RETFIE retorno de interrupcin
Sintaxis: RETFIE {s}
Operandos: s [0,1]
Operacin: (TOS) PC,
1 GIE / GIEH o PEIE / GIEL,
si s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH no se han modificado
Estado afectado: GIE / GIEH, PEIE / GIEL.
Codificacin: 0000 0000 0001 000 s
Descripcin: Regreso de interrupcin. Stack se extrae
y (TOS) se carga Top-of-Stack en
el PC. Las interrupciones son habilitadas por
estableciendo la prioridad alta o baja
interrupciones globales bit de habilitacin. Si 's' = 1, el
contenido de la sombra registra WS,
STATUSS y BSRS se cargan en
sus correspondientes registros, W,
STATUS y BSR. Si 's' = 0, no hay ninguna actualizacin
de estos registros se produce (por defecto).
Palabras: 1
Ciclos: 2
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode No
operacin
No
operacin
Pop PC de
montn
GIEH Establezca o
GIEL
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: RETFIE 1
Despus de interrupcin
PC = TOS
W = WS
BSR = BSRS
STATUS = STATUSS
GIE / GIEH, PEIE / GIEL = 1
RETLW retorno literal a W
Sintaxis: RETLW k
Operandos: 0 k 255
Operacin: k W,
(TOS) PC,
PCLATU, PCLATH no se han modificado
Estado afectado: Ninguno
Codificacin: 0000 1100 kkkk kkkk
Descripcin: W se carga con los ocho bits literal 'k'.
El contador de programa se carga desde el
parte superior de la pila (la direccin de retorno).
La alta direccin de pestillo (PCLATH)
se mantiene sin cambios.
Palabras: 1
Ciclos: 2
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
literal "k"
Proceso
Datos
Pop PC de
pila, Escribir
a W
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo:
TABLA DE LLAMADA; W contiene mesa
; valor de desplazamiento
; W tiene ahora
; valor de la tabla
:
TABLA
ADDWF PCL; = W compensados
RETLW k0; Comience mesa
RETLW k1;
:
:
Kn RETLW; Fin de la tabla
Antes de Instruccin
W = 07h
Despus de Instruccin
W = valor de kn
2006 Microchip Technology Inc. DS39632C pginas Preliminar 339
PIC18F2455/2550/4455/4550
VUELTA La vuelta de subrutina
Sintaxis: RETORNO {s}
Operandos: s [0,1]
Operacin: (TOS) PC,
si s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH no se han modificado
Estado afectado: Ninguno
Codificacin: 0000 0000 0001 001 s
Descripcin: Regreso de subrutina. La pila es
reventadas y la parte superior de la pila (TOS)
se carga en el contador de programa. Si
'S' = 1, el contenido de la sombra
registros WS, STATUSS y BSRS son
cargado en sus correspondientes
registros, W, STATUS y BSR. Si
'S' = 0, no hay actualizacin de estos registros
ocurre (por defecto).
Palabras: 1
Ciclos: 2
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode No
operacin
Proceso
Datos
Pop PC
de la pila
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: VUELTA
Despus de la instruccin:
PC = TOS
RLCF Rotar a la izquierda a travs de f Carry
Sintaxis: RLCF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f <n>) dest <n + 1>,
(F <7>) C,
(C) dest <0>
Estado afectado: C, N, Z
Codificacin: 0011 01DA ffff ffff
Descripcin: El contenido del registro 'f' se rotan
un bit hacia la izquierda a travs de Transferencia
bandera. Si 'd' es '0 ', el resultado se coloca en
W. Si 'd' es '1 ', el resultado se almacena
en el registro 'f' (por defecto).
Si 'a' es '0 ', el Banco El acceso es
seleccionada. Si 'a' es '1 ', el BSR se utiliza para
seleccionar el banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, esta instruccin
opera en Indexed Literal Offset
Modo de direccionamiento siempre
f 95 (5Fh). Consulte la Seccin 26.2.3
Byte orientada y orientada-Bit
Las instrucciones de indexado Literal Offset
Mode para obtener ms informacin.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: RLCF REG, 0, 0
Antes de Instruccin
REG = 1110 0110
C = 0
Despus de Instruccin
REG = 1110 0110
W = 1100 1100
C = 1
C registro f
PIC18F2455/2550/4455/4550
DS39632C pginas 340 Preliminar 2006 Microchip Technology Inc.
RLNCF Rotar a la izquierda f (n Carry)
Sintaxis: RLNCF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f <n>) dest <n + 1>,
(F <7>) dest <0>
Estado afectado: N, Z
Codificacin: 0100 01DA ffff ffff
Descripcin: El contenido del registro 'f' se rotan
un bit hacia la izquierda. Si 'd' es '0 ', el resultado
se coloca en W. Si 'd' es '1 ', el resultado es
almacenado de nuevo en el registro 'f' (por defecto).
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: RLNCF REG, 1, 0
Antes de Instruccin
REG = 1010 1011
Despus de Instruccin
REG = 0101 0111
registrarse f
RRCF Rotar a la derecha a travs de f Carry
Sintaxis: RRCF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f <n>) dest <n-1>,
(F <0>) C,
(C) dest <7>
Estado afectado: C, N, Z
Codificacin: 0011 00da ffff ffff
Descripcin: El contenido del registro 'f' se rotan
un bit hacia la derecha a travs del Carry
bandera. Si 'd' es '0 ', el resultado se coloca en W.
Si 'd' es '1 ', el resultado se vuelve a colocar en
registrarse 'f' (por defecto).
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: RRCF REG, 0, 0
Antes de Instruccin
REG = 1110 0110
C = 0
Despus de Instruccin
REG = 1110 0110
W = 0111 0011
C = 0
C registro f
2006 Microchip Technology Inc. DS39632C pginas Preliminar 341
PIC18F2455/2550/4455/4550
RRNCF Rotar a la derecha f (n Carry)
Sintaxis: RRNCF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f <n>) dest <n-1>,
(F <0>) dest <7>
Estado afectado: N, Z
Codificacin: 0100 00da ffff ffff
Descripcin: El contenido del registro 'f' se rotan
un bit hacia la derecha. Si 'd' es '0 ', el resultado
se coloca en W. Si 'd' es '1 ', el resultado es
se coloc de nuevo en el registro 'f' (por defecto).
Si 'a' es '0 ', el Banco de acceso ser
seleccionada, reemplazando el valor de BSR. Si 'a'
es '1 ', entonces el banco ser seleccionado como
por el valor BSR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo 1: RRNCF REG, 1, 0
Antes de Instruccin
REG = 1101 0111
Despus de Instruccin
REG = 1110 1011
Ejemplo 2: RRNCF REG, 0, 0
Antes de Instruccin
#NAME?
REG = 1101 0111
Despus de Instruccin
W = 1110 1011
REG = 1101 0111
registrarse f
Set SETF f
Sintaxis: SETF F {,} un
Operandos: 0 f 255
a [0,1]
Operacin: FFh f
Estado afectado: Ninguno
Codificacin: 0110 100 A ffff ffff
Descripcin: El contenido del registro especificado
se ponen a FFh.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escribir
registrarse 'f'
Ejemplo: SETF REG, 1
Antes de Instruccin
REG = 5Ah
Despus de Instruccin
REG = FFh
PIC18F2455/2550/4455/4550
DS39632C pginas 342 Preliminar 2006 Microchip Technology Inc.
Entre en el modo SLEEP Sleep
Sintaxis: DEL SUEO
Operandos: Ninguno
Operacin: 00h WDT,
0 WDT postscaler,
1 A,
0 PD
Estado Afectado: TO, PD
Codificacin: 0000 0000 0000 0011
Descripcin: El bit de estado Power-Down (EP) es
compensado. El bit de estado Tiempo de espera (TO)
est ajustado. Watchdog Timer y su
postscaler se borran.
El procesador se pone en modo de suspensin
con el oscilador se detuvo.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode No
operacin
Proceso
Datos
Ir a
Sueo
Ejemplo: SLEEP
Antes de Instruccin
A =?
PD =?
Despus de Instruccin
A = 1
PD = 0
Si WDT hace despertar, este bit se borra.
SUBFWB Reste f de W con Borrow
Sintaxis: SUBFWB f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (W) - (f) - (C) dest
Estado afectado: N, OV, C, DC, Z
Codificacin: 0101 01DA ffff ffff
Descripcin: Reste registro 'f' y seguir la bandera
(Prstamos) de W (complemento a 2
mtodo). Si 'd' es '0 ', el resultado se almacena
en W. Si 'd' es '1 ', el resultado se almacena en
registrarse 'f' (por defecto).
Si 'a' es '0 ', el Banco El acceso es
seleccionada. Si 'a' es '1 ', se utiliza la BSR
para seleccionar el banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, esta instruccin
opera en Indexed Literal Offset
Modo de direccionamiento siempre
f 95 (5Fh). Consulte la Seccin 26.2.3
Byte orientada y orientada-Bit
Las instrucciones de indexado Literal Offset
Mode para obtener ms informacin.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo 1: SUBFWB REG, 1, 0
Antes de Instruccin
REG = 3
W = 2
C = 1
Despus de Instruccin
REG = FF
W = 2
C = 0
Z = 0
N = 1; resultado es negativo
Ejemplo 2: SUBFWB REG, 0, 0
Antes de Instruccin
REG = 2
W = 5
C = 1
Despus de Instruccin
REG = 2
W = 3
C = 1
Z = 0
N = 0; resultado es positivo
Ejemplo 3: SUBFWB REG, 1, 0
Antes de Instruccin
REG = 1
W = 2
C = 0
Despus de Instruccin
REG = 0
W = 2
C = 1
Z = 1; el resultado es cero
N = 0
2006 Microchip Technology Inc. DS39632C pginas Preliminar 343
PIC18F2455/2550/4455/4550
SUBLW Restar W desde Literal
Sintaxis: SUBLW k
Operandos: 0 k 255
Operacin: k - (W) W
Estado afectado: N, OV, C, DC, Z
Codificacin: 0000 1000 kkkk kkkk
Descripcin W se resta de la de ocho bits
literal "k". El resultado se coloca en W.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
literal "k"
Proceso
Datos
Escriba a W
Ejemplo 1: SUBLW 02h
Antes de Instruccin
W = 01h
C =?
Despus de Instruccin
W = 01h
C = 1; resultado es positivo
Z = 0
N = 0
Ejemplo 2: SUBLW 02h
Antes de Instruccin
W = 02h
C =?
Despus de Instruccin
W = 00h
C = 1; el resultado es cero
Z = 1
N = 0
Ejemplo 3: SUBLW 02h
Antes de Instruccin
W = 03h
C =?
Despus de Instruccin
W = FFh; (Complemento a 2)
C = 0; resultado es negativo
Z = 0
N = 1
SUBWF Restar W de f
Sintaxis: SUBWF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f) - (W) dest
Estado afectado: N, OV, C, DC, Z
Codificacin: 0101 11da ffff ffff
Descripcin: Restar W de registro 'f' (2 de
complementar el mtodo). Si 'd' es '0 ', el
resultado se almacena en W. Si 'd' es '1 ', la
resultado se almacena en el registro 'f'
(Por defecto).
Si 'a' es '0 ', el Banco El acceso es
seleccionada. Si 'a' es '1 ', se utiliza la BSR
para seleccionar el banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, esta instruccin
opera en Indexed Literal Offset
Modo de direccionamiento siempre
f 95 (5Fh). Consulte la Seccin 26.2.3
Byte orientada y orientada-Bit
Las instrucciones de indexado Literal Offset
Mode para obtener ms informacin.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo 1: SUBWF REG, 1, 0
Antes de Instruccin
REG = 3
W = 2
C =?
Despus de Instruccin
REG = 1
W = 2
C = 1; resultado es positivo
Z = 0
N = 0
Ejemplo 2: SUBWF REG, 0, 0
Antes de Instruccin
REG = 2
W = 2
C =?
Despus de Instruccin
REG = 2
W = 0
C = 1; el resultado es cero
Z = 1
N = 0
Ejemplo 3: SUBWF REG, 1, 0
Antes de Instruccin
REG = 1
W = 2
C =?
Despus de Instruccin
REG = FFh; (complemento a 2)
W = 2
C = 0; resultado es negativo
Z = 0
N = 1
PIC18F2455/2550/4455/4550
DS39632C pginas 344 Preliminar 2006 Microchip Technology Inc.
SUBWFB Resta W de f con Borrow
Sintaxis: SUBWFB f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f) - (W) - (C) dest
Estado afectado: N, OV, C, DC, Z
Codificacin: 0101 10da ffff ffff
Descripcin: Restar W y la bandera de acarreo (prestado)
de registro 'f' (complemento a 2
mtodo). Si 'd' es '0 ', el resultado se almacena
en W. Si 'd' es '1 ', el resultado se almacena
en el registro 'f' (por defecto).
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo 1: SUBWFB REG, 1, 0
Antes de Instruccin
REG = 19h (0001 1001)
W = 0Dh (0000 1101)
C = 1
Despus de Instruccin
REG = 0Ch (0000 1011)
W = 0Dh (0000 1101)
C = 1
Z = 0
N = 0; resultado es positivo
Ejemplo 2: SUBWFB REG, 0, 0
Antes de Instruccin
REG = 1Bh (0001 1011)
W = 1Ah (0001 1010)
C = 0
Despus de Instruccin
REG = 1Bh (0001 1011)
W = 00h
C = 1
Z = 1; el resultado es cero
N = 0
Ejemplo 3: SUBWFB REG, 1, 0
Antes de Instruccin
REG = 03h (0000 0011)
W = 0Eh (0000 1101)
C = 1
Despus de Instruccin
REG = F5H (1111 0100)
; [Comp de 2]
W = 0Eh (0000 1101)
C = 0
Z = 0
N = 1; resultado es negativo
Swapf Intercambio f
Sintaxis: swapf f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin: (f <03:00>) dest <07:04>,
(F <07:04>) dest <3:00>
Estado afectado: Ninguno
Codificacin: 0011 10da ffff ffff
Descripcin: Los aperitivos superior e inferior de registro
'F' se intercambian. Si 'd' es '0 ', el resultado
se coloca en W. Si 'd' es '1 ', el resultado es
colocado en el registro 'f' (por defecto).
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: swapf REG, 1, 0
Antes de Instruccin
REG = 53h
Despus de Instruccin
REG = 35h
2006 Microchip Technology Inc. DS39632C pginas Preliminar 345
PIC18F2455/2550/4455/4550
TBLRD Table Read
Sintaxis: TBLRD (*, * +, * -; + *)
Operandos: Ninguno
Operacin: si TBLRD *
(Prog Souvenirs (TBLPTR)) Tablat;
TBLPTR - Sin Cambio;
Si TBLRD * +
(Prog Souvenirs (TBLPTR)) Tablat;
(TBLPTR) + 1 TBLPTR;
si TBLRD * -
(Prog Souvenirs (TBLPTR)) Tablat;
(TBLPTR) - 1 TBLPTR;
Si TBLRD + *
(TBLPTR) + 1 TBLPTR;
(Prog Souvenirs (TBLPTR)) Tablat
Estado afectado: Ninguno
Codificacin: 0000 0000 0000 10nn
NN = 0 *
= 1 * +
= 2 * -
= 3 + *
Descripcin: Esta instruccin se utiliza para leer el contenido
de memoria de programa (P.M.). Para hacer frente a la
memoria de programa, un puntero llamado Tabla
Puntero (TBLPTR) se utiliza.
El TBLPTR (un puntero de 21 bits) apunta a
cada byte en la memoria de programa. TBLPTR
tiene un rango de direcciones de 2 Mbytes.
TBLPTR [0] = 0: Byte menos significativo
de memoria de programa
Palabra
TBLPTR [0] = 1: Byte ms significativo
de memoria de programa
Palabra
La instruccin TBLRD puede modificar el valor
de TBLPTR de la siguiente manera:
ningn cambio
post-incremento
post-decremento
preincremento
Palabras: 1
Ciclos: 2
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode No
operacin
No
operacin
No
operacin
No
operacin
No est en funcionamiento
(Leer programa
Memoria)
No
operacin
No est en funcionamiento
(Escribir
Tablat)
TBLRD Table Read (Contina)
Ejemplo 1: TBLRD * +;
Antes de Instruccin
Tablat = 55h
TBLPTR = 00A356h
MEMORY (00A356h) = 34h
Despus de Instruccin
Tablat = 34h
TBLPTR = 00A357h
Ejemplo 2: TBLRD + *;
Antes de Instruccin
Tablat = AAh
TBLPTR = 01A357h
MEMORY (01A357h) = 12h
MEMORY (01A358h) = 34h
Despus de Instruccin
Tablat = 34h
TBLPTR = 01A358h
PIC18F2455/2550/4455/4550
DS39632C pginas 346 Preliminar 2006 Microchip Technology Inc.
TBLWT Tabla de escritura
Sintaxis: TBLWT (*, * +, * -; + *)
Operandos: Ninguno
Operacin: si TBLWT *
(Tablat) Registro de retencin;
TBLPTR - Sin Cambio;
Si TBLWT * +
(Tablat) Registro de retencin;
(TBLPTR) + 1 TBLPTR;
si TBLWT * -
(Tablat) Registro de retencin;
(TBLPTR) - 1 TBLPTR;
Si TBLWT + *
(TBLPTR) + 1 TBLPTR;
(Tablat) Registro de retencin
Estado afectado: Ninguno
Codificacin: 0000 0000 0000 11nn
NN = 0 *
= 1 * +
= 2 * -
= 3 + *
Descripcin: Esta instruccin usa los 3 bits menos significativos de TBLPTR
para determinar cul de los
8 de sostenimiento registra el Tablat se escribe.
Los registros de mantenimiento se utilizan para
programar los contenidos del Programa
Memoria (P.M.). (Consulte la Seccin 6.0
Memoria de programa flash para obtener informacin adicional
detalles sobre la programacin de la memoria flash.)
El TBLPTR (un puntero de 21 bits) apunta a
cada byte en la memoria de programa. TBLPTR
tiene un rango de direcciones de 2 Mbytes. El LSB del
la TBLPTR selecciona qu byte de la
posicin de la memoria del programa de acceso.
TBLPTR [0] = 0: menos significativo
Byte de Programa
Memoria Palabra
TBLPTR [0] = 1: Most Significant
Byte de Programa
Memoria Palabra
La instruccin TBLWT puede modificar el
valor de TBLPTR como sigue:
ningn cambio
post-incremento
post-decremento
preincremento
Palabras: 1
Ciclos: 2
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
(Leer
Tablat)
No
operacin
No
operacin
(Escriba a
Tenencia
Registrarse)
TBLWT Tabla Write (Continuacin)
Ejemplo 1: TBLWT * +;
Antes de Instruccin
Tablat = 55h
TBLPTR = 00A356h
El registro de retencin
(00A356h) = FFh
Despus de Instrucciones (finalizacin de escritura tabla)
Tablat = 55h
TBLPTR = 00A357h
El registro de retencin
(00A356h) = 55h
Ejemplo 2: TBLWT + *;
Antes de Instruccin
Tablat = 34h
TBLPTR = 01389Ah
El registro de retencin
(01389Ah) = FFh
El registro de retencin
(01389Bh) = FFh
Despus de Instruccin (finalizacin de escritura tabla)
Tablat = 34h
TBLPTR = 01389Bh
El registro de retencin
(01389Ah) = FFh
El registro de retencin
(01389Bh) = 34h
2006 Microchip Technology Inc. DS39632C pginas Preliminar 347
PIC18F2455/2550/4455/4550
TSTFSZ prueba f, Saltar si es 0
Sintaxis: TSTFSZ F {,} un
Operandos: 0 f 255
a [0,1]
Operacin: saltar si f = 0
Estado afectado: Ninguno
Codificacin: 0110 011a ffff ffff
Descripcin: Si 'F' = 0, la siguiente instruccin extrada
durante la ejecucin de la instruccin actual
se desecha y se ejecuta un NOP,
haciendo de esta una instruccin de dos ciclos.
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1 (2)
Nota: 3 ciclos si saltar y seguido
por una instruccin de 2 palabras.
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
No
operacin
Si saltar:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
Si saltar y seguido por la instruccin 2 palabras:
Q1 Q2 Q3 Q4
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
No
operacin
Ejemplo: AQU TSTFSZ CNT, 1
NZERO:
ZERO:
Antes de Instruccin
PC = Direccin (AQU)
Despus de Instruccin
Si CNT = 00h,
PC = Direccin (CERO)
Si 00h CNT ,
PC = Direccin (NZERO)
XORLW OR exclusivo Literal con W
Sintaxis: XORLW k
Operandos: 0 k 255
Operacin:. (W) XOR. k W
Estado afectado: N, Z
Codificacin: 0000 1010 kkkk kkkk
Descripcin: El contenido de W se XOR con
el 8-bit literal 'k'. El resultado se coloca
en W.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
literal "k"
Proceso
Datos
Escriba a W
Ejemplo: XORLW 0AFh
Antes de Instruccin
W = B5h
Despus de Instruccin
W = 1Ah
PIC18F2455/2550/4455/4550
DS39632C pginas 348 Preliminar 2006 Microchip Technology Inc.
XORWF OR exclusiva W con f
Sintaxis: XORWF f {, {d, a}}
Operandos: 0 f 255
d [0,1]
a [0,1]
Operacin:. (W) XOR. (F) dest
Estado afectado: N, Z
Codificacin: 0001 10da ffff ffff
Descripcin: OR exclusivo el contenido de W con
registrarse 'f'. Si 'd' es '0 ', el resultado se almacena
en W. Si 'd' es '1 ', el resultado se almacena
en 'f' el registro (por defecto).
Si 'a' es '0 ', se selecciona el Banco de Acceso.
Si 'a' es '1 ', el BSR se utiliza para seleccionar el
Banco GPR (por defecto).
Si 'a' es '0 'y la instruccin ampliada
set est activada, funciona esta instruccin
en Indexed Literal Offset Dirigindose
modo cada vez que f 95 (5Fh). Ver
Seccin 26.2.3 "orientados a bytes y
Operaciones con bits orientada en indiciada
Modo de desplazamiento Literal "para ms detalles.
Palabras: 1
Ciclos: 1
Q ciclo de actividades:
Q1 Q2 Q3 Q4
Decode Leer
registrarse 'f'
Proceso
Datos
Escriba a
destino
Ejemplo: XORWF REG, 1, 0
Antes de Instruccin
REG = AFh
W = B5h
Despus de Instruccin
REG = 1Ah
W = B5h
Nota: Todas las instrucciones PIC18 pueden tomar un argumento etiqueta opcional, que precede a la regla mnemotcnica de instrucciones, para su uso en
direccionamiento simblico. Si se utiliza una etiqueta, el formato de la instruccin se convierte en: argumento (s) {label} instrucciones.