th

14 International Conference
ACTIVE SUPPRESSION OF SUBSTRATE NOISE IN CMOS
INTEGRATED CIRCUITS

G. BLAKIEWICZ
MIXED DESIGN GDAēSK UNIVERSITY OF TECHNOLOGY, POLAND

MIXDES 2007 KEYWORDS: Substrate noise, SoC, Integrated circuits, CMOS

Ciechocinek, POLAND
21 – 23 June 2007

ABSTRACT: Noise generated by digital sub-circuits becomes serious problem in fast mixed signal systems on chip
(SoC). Digitally generated noise corrupts supply voltages and is propagated inside a silicon substrate as so called
substrate noise. A discussion and simplified analysis of passive and active circuits for substrate noise suppression is
presented in this paper. An example of an active circuit is design and tested by means of simulations. The achieved
results show higher efficiency of the active circuits in substrate noise attenuation in comparison to known passive
solutions.

INTRODUCTION also transferred to the substrate and it becomes substrate

In resent years many complicated electronic systems are
realized as a system on a chip (SoC). SoCs have many
advantages, to mention a few: high degree of
miniaturization, low power consumption, high speed,
good reliability, and low cost of high volume
fabrication. These possible advantages over multi
integrated circuits implementation demand high
experience from a designer, and taking into account
problems related to interactions of many functional
blocks on the same silicon substrate. Because of very
large scale of integration and complicated nature of
modern SoCs, sometimes it is difficult to correctly
predict and avoid problems with interferences between
functional blocks, which may cause degradation of SoC
performance. The verification tests conducted on
fabricated experimental chips reveal problems with
correct functioning of some SoCs. The interactions
between noisy digital and sensitive analog sub-circuits
are frequently a reason for excessive noise and result in
performance degradation of mixed signal systems [1].
Even in uniform digital circuits, interferences between
functional blocks may cause problems, like increased
jitter of a system clock, variation in buffers delay or
false bit generation [2]. The common reason for all the
mentioned problems is too strong coupling between
sub-circuits placed close to each other on the same
substrate. The analysis of future trends in CMOS
technology and package evolution [3] predict problems
in future SoCs. In a typical SoC three basic categories
of system noise can be distinguished: noise on
power/ground supply rails, substrate noise [4], [5], and
crosstalk between signal lines. The power supply or
ground noise arises when a sub-circuit generates supply
current pulses of short rise and fall times. Such short
pulses cause voltage drop on positive and voltage
bounce on negative supply lines due to voltage drop on
series parasitic resistances and inductances of the lines.
Because the supply rails are very strongly coupled to a
silicon substrate, a significant portion of supply noise is
noise. The research in the resent decade enabled better
understanding of the main mechanisms of noise
generation and propagation [4], [5] as well as possible
prevention methods [6]-[13]. Unfortunately, the
prevention methods designed for early, relatively small
and slow SoCs may become inefficient in future very
fast systems. It is because there exists some
fundamental limitations in further reduction of parasitic
coupling inside a common substrate and in
minimization of resistances and inductances of the
supply lines and package leads. The limitations of the
commonly used methods for noise suppression can be
alleviated by using active circuits. The active
suppression circuits [8]-[13] seem to be promising
alternative to the passive circuits in efficient noise
suppression.
In this paper a short discussion about passive and active
circuits for noise suppression is presented in the second
section. The next section presents an example of an
improved active circuit design together with simulation
results. The final section contains discussion and
conclusions.
BASICS OF NOISE SUPPRESSION
The series parasitic resistances and inductances of
power supply rails and on-chip interconnections biasing
guard rings on a substrate are limiting factors for system
noise reduction. In the case of functional blocks placed
close to the edge of a chip, the interconnections
parasitic impedance can almost be reduced to value of
package impedance by using short and wide metal
paths. A more difficult situation is with blocks located
away from chip bond wire pads, where relatively long
on-chip interconnects increase the total series
impedance. For such blocks the total series resistance
and inductance less than 10-20 Ÿ and 10-20nH is
difficult to achieve without using sophisticated and
expensive packages. An interesting alternative to the
application of expensive packages and using very wide

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on-chip interconnection paths is the generation of local feedback loop to improve efficiency of noise
signals that compensate substrate noise or the suppression. A real operational amplifier is modeled by
generation of a low impedance ground inside a chip. a frequency dependent controlled voltage source of gain
The first compensation technique [10]-[13] is able to AZ  and output resistance Ro. In the active circuit the
efficiently suppress substrate noise at relatively low decoupling capacitor is connected in a negative
frequencies up to 50-100MHz range. The technique feedback loop. Due to the Miller effect, the equivalent
uses operational amplifiers to create a compensation capacitance seen from the inverting input of the
signal shifted in phase by 180O. By proper injection of amplifier is greater than the decoupling capacitance Cd,
the compensation signal into a substrate, noise can be and overall efficiency of the circuit is increased.
significantly attenuated in the vicinity of the guard
rings. The technique is only efficient at low frequencies
due to limitations of the amplifier gain bandwidth. The
second technique, based on the generation of a low
impedance ground, has better frequency characteristics.
Such technique has a potential ability to provide a high
quality ground even for low quality packages and long
on-chip interconnects. The published circuits using that
technique are based mainly on operational amplifier or
current conveyor architectures and also suffers from the
frequency limitation. Impulsive supply noise, generated
by fast switching digital circuits, with short rise and fall
times is very badly attenuated by that kind of circuits Fig. 1. Model of a passive circuit for noise suppression.
[8].
In order to design improved active circuits for noise
suppression it is crucial to understand weaknesses of the
known circuits and specify fundamental requirements
for better solutions. The active circuits for noise
suppression designed in a SoC can only have speed
characteristics similar to digital sub-circuits placed on
the same substrate. The most abrupt supply/ground
current pulses are generated by the fastest digital gate,
which is an inverter. The supply current pulses of very
short rise and fall times generated by the inverters can
only be suppressed by a circuit as fast as inverters. Any
other slower amplifiers, as for example multi-stage
operational amplifiers or current conveyors, will not be
able to deal with such pulses and they may additionally
worsen the system noise performance due to potential
instability and ringing effects caused by parasitic
Fig. 2. Model of an active circuit for noise suppression.
resonances of the on-chip supply network.
To explain basic requirements for the active noise
The efficiency of the discussed circuits is dependent on
suppression circuits, in view of commonly used passive
magnitude of the equivalent decoupling impedance Zdec,
suppression circuits, two simple models of decoupling
which forms with the coupling capacitance Cc a voltage
configurations are presented in Fig. 1 and 2. In the
divider. For the considered models, noise voltage on the
figures the passive and active decoupling circuits are
signal line can be calculated as
presented. The system noise is represented by the
voltage source Vn, which is coupled via the coupling Z dec
capacitor Cc to a signal line. The coupling capacitor can Vc Z  Vn Z  (1)
Z dec  1  jZ Cc 
represent coupling between on-chip interconnections or
it can represent a simplified case of coupling via a According to (1) for an ideal on-chip grounding
silicon substrate. The part of system noise coupled to ( Lw , Rw o 0 ) and very large decoupling capacitance,
the signal line is labeled as Vc. To reduce noise level on
the signal line, the decoupling capacitor is connected to when Z dec o 0 , a complete noise cancellation is
it. The decoupling capacitor is represented by series theoretically possible. In a realistic passive decoupling
capacitance Cd and resistance Rd to improve modeling circuit, the decoupling impedance is
accuracy at high frequencies. Additionally, Rw and Lw Z dec  jZ  jZLw  Rw  Rd  1 jZCd and the lower
represent parasitic resistance and inductance of package
boundary of noise suppression is mainly limited by the
leads, bond wires and an on-chip ground line. In the
package, bond wire and on-chip interconnection
simple passive decoupling circuit, shown in Fig. 1, the
impedances. For the considered configuration the lower
decoupling capacitor is connected between the on-chip
limits for noise suppression are
ground and the signal line. The active decoupling,
modeled in Fig. 2, uses an operational amplifier with a

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 ­° Cc where g m1 , CL and I D1 are the transconductance, the
Vc Z  at low frequencies (2)
® Cc  Cd  total load capacitance and the drain current of the first
Vn Z  °̄1 at frequencies above the resonance
It is important to notice that the passive decoupling is
completely inefficient at high frequencies above the
resonant frequency of the supply network, where the
stage, whereas g m 2 and I D 2 are the transconductance
and the drain current of the output buffer. D and E are
constants specific to selected CMOS technology and the
amplifier architecture. According to (3a) and (3b), the
improvement of noise suppression requires an
on-chip ground network behaves as inductance. This
property makes the passive noise suppression highly
inefficient at frequencies above 0.5-1GHz in typical
SoCs. It is also worth to notice that large on-chip
decoupling capacitance does not guarantee good noise
grounding. It can only provide local suppression of
differential mode noise, whereas common mode noise
enlargement of the amplifier voltage gain AZ  and a
reduction of the output resistance Ro . For a specified
and limited supply power the two requirements are
contradictory. In order to find the optimal solution the
decoupling impedance (3b) is expressed in terms of the
total supply current I DD and the output buffer biasing
remains attenuated [4], [5]. current I D2 , assuming A jZ  # GB Z and
The active decoupling circuit presented in Fig. 2 has I DD I D1  I D 2
different properties. In a properly designed active circuit
Cd !! Cc , which means at high frequencies Z dec  jZ 
(5)
1  jZ Cc  !! Z dec . Under these conditions, the E I D 2  Rd 1

equation (1) can be simplified to 1  D I DD  I D 2 Z 
jZ Cd 1  D I DD  I D 2 Z 
Z dec
Vc Z  Vn Z  The expression (5) can be used as an object of
Z dec  1  jZ C c  (3a) optimization for a selected amplifier architecture and
# Z dec jZ Cc Vn Z  technology. A typical plot of the impedance magnitude
1
!! Z dec is presented in Fig. 3 for 0.35Pm CMOS technology and
jZ C c
a constant supply power Pdiss 3.3mW .
where
Ro  Rd 1
Z dec  jZ   (3b)
1  AZ  jZ C d 1  AZ 

The expression (3b) shows that the amplifier reduces

the parasitic series resistance Rd and increases the
decoupling capacitance Cd . In the case of the ideal
amplifier AZ  o f the noise voltage Vc can
completely be attenuated even for a non-ideal package
( Lw z 0 , Rw z 0 ) and a non-ideal decoupling capacitor
( Rd z 0 ). Unfortunately a practical amplifier has limited
Fig. 3. Z dec as a function of the output biasing current.
gain bandwidth (GB), which means reduction of the
voltage gain AZ  to zero at frequency equal to GB.
The output resistance Ro of a typical amplifier is Two families of characteristics are presented in Fig. 3.
The dashed lines labelled c refer to a two-stage
relatively large and may additionally increases at high
frequencies. amplifier with the input stage composed of nMOS
In order to better understand the important tradeoffs of transistors with the aspect ratio 100/0.35 and the output
the active circuit design let us consider a simple two nMOS source follower of 100/0.35. The second family
stage amplifier consisting of the first voltage gain stage d represents an amplifier with much wider output
and the second low-resistance output buffer. For a buffer of 8000/0.35. The characteristics are plotted for
typical CMOS amplifier GB and the output resistance three frequencies 50MHz, 300MHz, and 1GHz which is
Ro can be expressed in terms of biasing currents close to the gain bandwidth of the amplifiers. For the
first amplifier a local minimum of the decupling
g m1 impedance is observed when about 60% of the total
GB # D I D1 (4a)
CL supply current flows into the output buffer. The second
amplifier provides much lower decoupling impedance
and has relatively flat characteristics. For all considered
1 E (4b)
Ro # cases the decoupling capacitor is assumed to have
g m2 I D2 Cd 10 pF , Rd 3: The plots presented in Fig. 3
show how the reduction of amplifiers output resistance

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is important, especially at high frequencies close to the
gain bandwidth of the amplifier. Other simulations
show that the equivalent decoupling impedance Z dec
can not be sufficiently reduced without a significant
reduction of the amplifier output resistance even for
relatively big decoupling capacitance Cd > 100pF. This
property can easily be observed in the next plot.
Fig. 4. Z dec as a function of frequency.
Fig. 4 presents a comparison of four amplifiers, the
parameters of the amplifiers labelled as c and d are
the same as previously, the amplifier e has the aspect
ratios 100/0.35 and 500/0.35 for the input and output
stages respectively, the amplifier f has wide 1000/0.35
nMOS transistors in the input stage and thin 100/0.35 in
the output. Comparing the curves d and e with c
and f one can easily notice that the decoupling
impedance can significantly be reduced by lowering the
amplifier output resistance even for relatively small
decoupling capacitances.
The most important conclusions from the presented
analysis are summarized as a set of guidelines for the
active circuit design:
1) It is necessary to achieve as low as possible output
resistance with opened feedback. Because of
a relatively small gain bandwidth of typical
amplifiers in comparison to a frequency spectrum of
Fig. 5. Active circuit for substrate noise suppression.
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supply noise, a high output resistance can not be
reduced by a negative feedback loop.
2) The output low-resistance stage of the amplifier
should be able to source and sink sufficiently large
current to compensate strong supply pulses.
3) To achieve a sufficiently fast and robust circuit with
small oscillations in its response, the configurations
with a single voltage gain stage and a buffer are
preferred.
4) The circuit should have high power supply rejection
ratio and should not generate power/ground noise by
itself to avoid interferences with other components
in a system.
5) To reduce overall power consumption the amplifier
should work in AB or B class.
6) It is possible to find the optimal balance of the
biasing currents for amplifier stages based on a
precise model of the amplifier and a decoupling
capacitor.
ACTIVE SUPPRESSION OF NOISE
As discussed in the previous section an amplifier with
very low output resistance is crucial for efficient noise
suppress at high frequencies. One of the possible
amplifier configuration is presented in Fig. 5. The
circuit consists of an AB-class output push-pull source
follower (M1 and M2) with biasing devices (M3 and M4)
providing low output resistance. The input voltage gain
stage is equipped with transistors M5 and M7. The
protecting guard ring is made out of p+ diffusion on a
silicon p-type substrate and connected to the output of
the amplifier by means of capacitance C2. Two
symmetric inputs of the amplifier are also capacitively
coupled to the ring (C1 and C3). The polysilicon
resistors R1 and R3 together with the capacitors C4 and
C5 provide filtering of supply current impulses
generated by the amplifier. The symmetric
configuration of the circuit significantly reduces the
biasing currents and saves supply power.
 TABLE 1. Dimensions of the transistors from Fig. 5.
Label Aspect Label
ratio W/L
M1 400/0.35 M6
M2 600/0.35 M7
M3, M4 60/0.35 M8
M5 200/0.35 M9
The output source follower is connected to the digital
supply voltages of the system (VDD1 and VGND1),
whereas the voltage gain and biasing circuits are
supplied from additional dedicated voltages (VDD2 and
VGND2). The transistors dimensions for the amplifier are
listed in Tab. 1. The total power dissipation of the
circuit is 4mW at a supply voltage 3.3V and it can
further be reduced depending on the requirements on
magnitude of suppressed noise. The presented circuit
was designed so that to be able to compensate substrate
noise current impulses of magnitude as high as 5mA.
For example, substrate current impulses of amplitude
0.5mA require only 1.5mW. Figures 6 and 7 present the
basic parameters of the amplifier shown in Fig. 5. The
open loop gain of the circuit is detailed in Fig. 6, and is
equal to 30dB at medium frequencies. The gain
bandwidth is about 800MHz.
Fig. 6. The open loop voltage gain of the amplifier from
Fig. 5.
The opened loop output resistance Ro as a function of
frequency is shown in Fig. 7. The resistance varies from
30ȍ at low, to 55ȍ at high frequency. After closing the
loop, the resistance decreases to several ohms at low
frequency and to about 40 ohms at 1GHz.
Fig. 7. The open loop output resistance of the amplifier
from Fig. 5
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The efficiency of substrate noise suppression was tested
Aspect using a ring oscillator as a substrate noise source. The
ratio W/L substrate was represented by a resistive-capacitive
3/0.35 network extracted using SubstrateStorm from Cadence.
160/0.35 Representative results are presented in Fig. 8-10, where
2/0.35 the passive decoupling circuit, from Fig. 1, is compared
0.5/12 to the active one from Fig. 2. For all simulations the
package leads and bond wires was modelled by series
inductance Lw =10nH and resistance Rw =10ȍ. Fig. 8
shows the small signal output resistance of the circuits.
The impedance of the passive circuit gradually increases
with frequency due to parasitic inductances of a
package and bond wires. The active circuit has
relatively small impedance at frequencies above
900MHz. The increase of impedance at low frequencies
is caused by the capacitive coupling of the amplifier to
the guard ring, as shown in Fig. 5.
Fig. 8. Comparison of the decoupling impedance.
The results of the time domain simulations are presented
in Fig. 9 and 10. The active circuit provides over 9dB
greater attenuation of noise power over the passive
circuit. It is observed about 2 times better suppression
of noise peak-to-peak amplitude. Additionally the active
circuit makes noise pulses narrower in time in
comparison to the passive circuit, which reduces the
pulses energy and as a result prevents from triggering
sensitive digital gates. The other simulations for a faster
ring oscillator show even better performance of the
active circuit. The active circuit does not generates
parasitic oscillations even for relatively large supply
parasitic inductances of 100nH.
Fig. 9. Substrate voltage measured close to the guard ring
achieved for the active circuit.
223
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