An Innovative Ultra Low Voltage sub-32nm SRAM

Voltage Sense Amplifier in DG-SOI Technology

Pranav Pranav•°, Bastien Giraud°, Amara Amara°

• Vellore Institute of Technology University (VITU) ° Institut Supérieur d'Electronique de Paris (I.S.E.P)
Vellore, 632014 Tamil Nadu, India 21, rue d’Assas, 75270 Paris Cedex 06, France
pranavd2me@gmail.com (bastien.giraud, amara.amara)@isep.fr

Abstract— Double-gate fully-depleted (DGFD) SOI circuits are
regarded as the next generation ULSI circuits. In this paper we
propose a high performance voltage sense amplifier in sub 32-
nm fully depleted (FD) double-gate (DG) silicon-on-insulator
(SOI) technology with planar independent self-aligned gates.
The proposed design improves the sensing delay and shows
excellent tolerance to threshold voltage mismatch (9%) and L
mismatch (9%) even at a voltage as low as 0.6 V. The proposed
architecture is compared to two other architectures directly
converted to DGSOI Technology and proves to be 50-60% faster
and more (300-400%) insensitive to mismatch. The reliability
and process variation insensitivity is also analyzed through
Monte Carlo analysis.
I. INTRODUCTION
Scaling trends in Bulk CMOS approaching physical limits
have prompted the need for alternative device structures.
Double Gate (DG) MOSFET with low sub-threshold leakage,
higher on current and excellent control of the short channel
effects has emerged as the most promising device for nano-
scale circuit design even in the ultra low voltage region [1]. In
this paper we will focus on analyzing the advantages of using
the independent control of front and back gate (FG and BG,
respectively) of the DG device to enhance the performance of
sense amplifiers at low voltage.
With power consumption becoming a major factor in the
performance of memory circuits of various embedded
applications, the operation of SRAM memory cell and sense
amplifier at low voltages seems to be very promising. With
the increase in the memory density, the time needed to
discharge a large parasitic capacitance of a bitline (with low
current of accessed memory cell) becomes very long.
Moreover at low voltage (0.6V) the bit lines take around 160
ps to develop a voltage difference of around 80mV just
sufficient for sensing. This is five times the time taken by
them to have the same voltage difference at 1.2 V. The task of
the Voltage Sense Amplifier (VSA) is to detect relatively
small voltage difference between two complementary bitlines
into a readable logic level. Small signal difference on a pair of
bitlines implies the demand for a significant mismatch
tolerance of the VSAs, especially in sub-50nm technologies,
in which process variations reach their maximum [2], causing
serious asymmetry.
The paper is organized as follows. The DG device is
briefly described in section II. Section III presents the
reference and proposed circuits. The simulation details are
described in section IVa. Part IVb covers obtained results, and
detailed L and Vth mismatch analysis. Part IVc covers the
Monte Carlo analysis. Conclusions based on the results
obtained are made in part V.
II. THE DOUBLE-GATE DEVICE CHARACTERISTICS
In this paper, we use the asymmetrical transistor
(AsymOxDG) in which the work function of the two gates is
the same (ФMF = ФMB), but the BG oxide is thicker than the FG
one (ToxB > ToxF). Table I displays the main electrical
parameters. The advantages of independent gate operation in
AsymOxDG are higher ON current with increased BG voltage
and lower total gate-source capacitance. This can be justified
by the following equation. The long channel threshold voltage
at the front gate of a DGMOS is given by [1]:
csi × coxb
VtF = ∆Φ MF + 2φF + [2φF + ∆Φ MB − VBG ]
coxf (c si + coxb )

TABLE I. ASYMMETRICAL DEVICE PARAMETERS

Symbol Label NMOS PMOS

L (nm) gate length 50 50
W (nm) gate width 100 100
Threshold
VT (mV) voltage 300 300
µ (V·m²/s) Mobility 254 125
TOX (nm) oxide thickness 1.2 FG, 3.5 BG 1.2 FG, 3.5 BG
Figure 1. DGFD Cross-section TSI (nm) Silicon thickness 10 10

This work is part of a multi-laboratories project financed by the ANR

(National Agency of France Research)

978-1-4244-2167-1/08/$25.00 ©2008 IEEE 205

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Figure 2. Latch Based Sense Amplifer (LBSA) [3]
From the equation, it can be observed that increasing the back
gate voltage in an independent gate DGNMOS reduces its
threshold voltage thereby increasing its ON current (ION) . It
should also be noted that in AsymOxDG the capacitance in
the BG is less compared to FG (ToxB > ToxF <=> CoxF > CoxB).
III. SENSE AMPLIFIERS FOR SRAM
A. Reference Circuits
Fig. 2 presents the Latch Based Sense Amplifier (LBSA)
derived from [3]. OUTL and OUTR nodes are being
precharged to 0V before sensing. At the beginning of
operation, both MP1 and MP2 transistor start to pull-up OUTL
and OUTR to VDD. The imbalance in current flow caused by
voltage difference on the front-gates (FG) of MN3 and MN4
(identified by the arrows) slows down the pull-up of one of the
output nodes. Due to cross-feedback connections in the
structure (Fig. 2), increasing voltage of one of the output
nodes, causes cutting-off of the opposite PMOS transistor thus
reducing its pull-up strength. The same feedback connection
on the back-gate of NMOS causes increase in conductivity
and better pull-down of relevant output voltage. Introduction
of the DG technology allowed an additional back-gate (BG)
connection, resulting in feedback strength and speed
improvement [3]. The disadvantage of this schematic is that
Figure 3. Isolated Input Sense Amplifier (IISA) [4]
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during sensing, there is always an open path from VDD to
ground, due to the fact that MN3 and MN4 front-gates are
always connected to the bitlines precharged to VDD.
Fig. 3 presents the Isolated Input Sense Amplifier (IISA)
derived from [4] and converted directly to DG SOI
technology. MP5 and MP6 transistors are pass transistors
controlled internally by OUTL and OUTR nodes. Before
sensing, OUTL and OUTR are precharged to ‘0’, causing
MP5 and MP6 to pass bitline voltages to nodes INL and INR.
When sensing starts, we encounter two feedback effects. The
output nodes (OUTL, OUTR) control the pull-up strength of
opposite PMOS transistor. Moreover, the output controlled
inverter MP5-MN7 (MP6-MN8) is capable of disconnecting
the MN3 (MN4) transistor from the bitline voltage.
B. Proposed DG Sense Amplifier (HPVISA)
Fig. 4 presents the High Performance Variation Immune
Sense Amplifier (HPVISA), we propose. It based on the VSA
proposed in [5] and adds additional feedbacks. The feedback
between pairs MP11, MN12 and MP10, MN9 which are used
as pass transistors allows I1 to influence the I2 node and vice
versa, just before sensing starts, increasing the basic input
voltage difference, that the sense amplifier operates on. The
addition of a new feedback, represented by INN1 and INN2,
increases the sensing speed as it constantly tries to follow the
outputs and thus forces the outputs to reach their final state as
early as possible. Introduction of 4 input points, instead of
standard 2, on the BG of transistors MP2-MP4, MN3-MN5,
increases the stability. Before the sensing starts OUTL and
OUTR are precharged to 0 by MN02 and MN03 transistors
which are activated by the SAE signal. The EQN, MN01 and
MN04 transistors are equalizing the voltage between I1 and I2
to ‘0’ during precharge activated by the signal CHRG.
Assuming that the BLL node goes low so MP10 is more ON
than MP11 which makes MN5 more ON than MN3. This is
reinforced by the feedback applied to the FG of MP11-MN12
and MP10-MN9. As a result INN2 is pulled down by MN5.
This makes the pull up of OUTL stronger by MP1.
Figure 4. High Performance Variation Immune Sense Amplifier (HPVISA)
As INN1 is high and INN2 is low this makes MN6 stronger
than MN7 and results in better pull down of the OUTR node.
This utilizes the advantages of the independent gate operation
of the DG. The PMOS transistors responsible for pull up of
the output nodes and the NMOS transistors responsible for
pull down of the INN1 and INN2 nodes are operated in
connected gate mode. This makes the structure more robust.
At the same time it’s using the advantages of the double gate
MP1 and MP2 transistors whose BG’s are connected to I1 and
I2, thus being partially closed at the beginning of sensing.
IV. SENSE AMPLIFIER SIMULATION
A. Simulation Setup
The supply voltage VDD is maintained at 0.6V for all
cases. Bitlines are precharged to VDD, and loaded with a
capacitance of 30fF corresponding to 128 memory cells in one
column. Current-controlled current sources are applied on
Figure 5. The diagram of one column SRAM used in simulations
Figure 7. Sensing delay as a function of Vth mismatch
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both bitlines to provide worst-case leakage current; 127
memory cells holding opposite state that the one being read
from the accessed cell, see Fig. 5. The VSA is activated when
the input voltage difference is equal to 80mV, corresponding
to the imbalance of the two complementary bitlines. Figs. 2 to
4 have (+) and (-) marks attached to indicate which transistor
parameters are being modified during simulations. We apply
lower voltage on the left bitline (BLL), causing OUTL to pull-
up (‘1’ logic value) and OUTR to pull-down (‘0’ logic value).
The idea of mismatch is to create imbalance favoring the state
opposite to the one expected i.e. OUTL=‘0’ and OUTR=‘1’.
Considering above mentioned conditions, (+) marked
transistors have their Vth (or L) values reduced. All OUTR
and OUTL nodes are loaded with minimum size inverters (see
Fig. 5), which are used as outputs (OUTA and OUTB). The
delay time is measured from 50% of falling edge of SAE
signal to 50% of VDD on the OUTA node (which is at VDD at
the beginning of sensing) (Fig. 6).
Figure 6. Circuit control signals and operation waveforms
Figure 8. Sensing delay as a function of L mismatch
 The average delay for the first two circuits is 64.9 ps and
TABLE II. SENSE AMPLIFIER’S PARAMETERS 321 ps respectively and for HPVISA it is 34.5 ps.
Power
Static Vth L 2) Reliability
dissipation Delay
VSA
( full read
power
[ps]
mismatch mismatch The first and second references have read error rate of 8.8%
[uW] tolerance tolerance
cycle) [uW] and 8.1% respectively. Whereas for HPVISA there was no
LBSA
1.8 0.2 64 3% 3% incorrect read for 1000 iterations.
[5]
IISA [6] 3.7 2.1 84 3% 4% 3) Standard deviation of sensing delay
HPVISA 4.8 3.6 36 9% 9% The standard deviations are 11.5 ps, 85.3 ps and 6.2 ps for
LBSA, IISA and HPVISA, respectively. The standard
B. Impact of Mismatch on Performance deviation of the proposed architecture is around 2X and
Table II. summarizes the simulated results using a 14X lower than the LBSA and IISA, respectively.
predictive custom-made DG compact model. The impact of V. CONCLUSION
transistor mismatch on the sense amplifier delay is analyzed A novel ultra low voltage sense amplifier in FD sub-32nm
in terms of Vth and L mismatch (see Fig. 7 and Fig. 8, double-gate SOI has been described and compared to two
respectively). For the mismatch analysis indispensible for previously documented sense amplifiers. HPVISA has a
sub-32 nm circuits, HPVISA proves not only more reliable sensing delay of 18 ps and displays the same level of
(9%) but also it displays only 60% speed degradation over its performance at nominal voltage (1.2V) also. The proposed
stability region of 10% mismatch compared to 80% over 3% design which takes advantage of the extra BG connection, has
mismatch for LBSA and IISA. The percentage shown on the proven to be faster, more tolerant to mismatch and insensitive
abscissa is the amount in % increase or decrease in L and Vth to process variations when compared to the existing
of each transistor in the direction shown in Figs. 2 to 4. As topologies. HPVISA operates correctly with reasonable delay
we can see, LBSA and IISA circuits become unstable at less degradation up to a mismatch of 9% in L and Vth compared
than 3% of mismatch. Robustness for less than 3% of to 4% and 3%, respectively, for the other VSAs with same
mismatch cannot be considered satisfactory for sub-32 nm dimensions. MC analysis proves the reliability of HPVISA,
circuits. by depicting no incorrect read operation. We can conclude
C. Monte Carlo analysis that DG SOI technology is very promising for sense
1K-Monte-Carlo simulations, illustrated in Fig. 9, have
amplifiers and SRAM’s in a 32nm process in spite of
been performed in order to characterize their reliability.
transistor mismatch [6].
Global process variations (the same for all transistors) are
applied as Gaussian distributions to the threshold voltage ACKNOWLEDGMENT
(VTH), the gate width (W) and the gate length (L) with a 1σ =
10%, 10% and 10%, respectively. A local variation of VTH The design kit support and fabrication have been assured
by CEA/Leti. The authors would like to thank Piotr Nasalski
with 1σ = 3.33% is also applied. This variation is fully
randomized and independent in all transistors. For the and Adam Makosiej for valuable technical discussions. We
would like to thank Dr. J.P.Raina for giving us this
comparison purposes, we take the sensing delay of each circuit
without mismatch introduced. opportunity to work in this collaboration.

1) Average Sensing delay REFERENCES

From histogram, the mean value is taken and used in [1] Rongtian Zhang, Kaushik Roy, and David B. Janes, “Double-Gate
sensing delay comparison. Fully-Depleted SOI Transistors for Low-Power High-Performance
Nano-Scale Circuit Design’’, ISLPED’01, August 6-7, 2001,
Huntington Beach, California, USA
[2] Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te
Chuang, and Kaushik Roy, “Statistical characterization and on-chip
measurement methods for local random variability of a process using
sense-amplifier-based test structure”, ISSCC, february 2007 San
Francisco, CA, USA
[3] Saibal Mukhopadhyay, Hamid Mahmoodi, and Kaushik Roy, “Design
of high performance sense amplifier using independent gate control in
sub-50nm double-gate MOSFET”, March 2005, San Jose, CA, USA.
[4] Hong-Yi Huang, and Shih-Lun Chen, “Self-isolated gain-enhanced
sense amplifier”, ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific
Conference, pp. 57-60
[5] Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu,
Amara Amara, “An Innovative sub-32nm SRAM Voltage Sense
Amplifier in Double-Gate CMOS Insensitive to Process Variations and
Transistor Mismatch”,unpublished.
[6] Bastien Giraud and Amara Amara, “Read Stability and Write Ability
Figure 9. Read delay distributions with local (Vth) and global variations (L, W Tradeoff for 6T SRAM Cells in Double-Gate CMOS”, DELTA,
and Vth) January 2008, Hong Kong.

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