Aggressive scaling of transistor dimensions with each technology generation has

resulted in increased integration density and improved device performance.

Leakage current increases with the scaling of the device dimensions. Reducing the

supply voltage reduces the dynamic power quadratically and leakage power linearly

to the first order. Hence, supply voltage scaling has remained the major focus of

low-power design. This has resulted in circuits operating at a supply voltage lower

than the threshold voltage of a transistor. However, as the supply voltage is

reduced, the sensitivity of the circuit parameters to process variations increases.

Process variations limit the circuit operation in the sub-threshold region, particularly

the memories. Nano-scaled SRAM bit-cells having minimum-sized transistors are

vulnerable to inter-die as well as intra-die process variations. All these together

result in various memory failures, i.e., read failure, hold failure, access time failure,

and write failure.

The leakage current of the memory will be increased with the capacity such that

more power will be consumed even in the standby mode. Many schemes have been

mentioned to improve the power consumption of the SRAM like dynamically

controlling n- and p-well bias voltage to and, respectively, for selected memory

cells, or dynamically varying the threshold voltages of the wordline-controlled nMOS

transistors of memory cell. However, these works need to pay the price of a special

process or large area overhead. Dual threshold voltage transistors can be used to

constitute the memory cells. Low threshold voltage transistors are mainly used in

driving bit-line to speed up the R/W operation while high threshold voltage

transistors are used in latching data to reduce leakage current. Source biasing,
dynamic power supply and Schmitt-trigger based built-in feedback mechanism have

been proposed to improve the process variation tolerance.

Various SRAM models have been published in the literature addressing these issues

using. 6T, 7 models utilize differential read operation; 5T, 8T and 10T cells employ

single-ended reading scheme. The 8T and 10T cells use an extra sensing circuit for

reading the cell contents, achieving improved read stability.

The important characteristics of an SRAM cell are determined by the plot obtained

by forcing an input on one of the internal nodes and plotting the response on the

other side, then performing the same operation on the other side describe the

stability of the hold state. The static noise margin (SNM), which is the separation

between the two curves along a 45 degree slope, indicates the level of immunity

that the cell has to unwanted voltage changes due to noise.

Another important parameter in SRAM design is the ratio of the aspect ratios of the

nMOS and pMOS transistors. Although the values of β n & βp can be adjusted to

create different butterfly characteristics, the storage FETs are commonly chosen to

have the smallest possible aspect ratios to maximize the storage density.