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Sri Ramakrishna Engineering College
Coimbatore-641 022

Dept. of Electrical and Electronics
Engineering





Lab Manual

08AB409 DIGITAL LOGIC CIRCUITS
LABORATORY

FOURTH SEMESTER

B.E - EEE

LAB IN-CHARGE: V. GOPU M. E






1
SYLLABUS

08AB408 DIGITAL LOGIC CIRCUITS LABORATORY 0 0 3 100

1. Study of Basic Digital gates.
(Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF,
RS FF, D FF)
2. Implementation of Boolean Functions, Adder/ Subtractor circuits.
3. a) Code converters, Parity generator and parity checking, Excess 3, 2s Complement,
Binary to grey code using suitable ICs .
b) Encoders and Decoders: Decimal and Implementation of 4-bit shift registers
in SISO, SIPO, PISO, PIPO modes using suitable ICs.]
4. Counters: Design and implementation of 4-bit modulo counters as synchronous an
asynchronous types using FF ICs and specific counter IC.
5. Shift Registers: Design and implementation of 4-bit shift registers in SISO, SIPO,
PISO, PIPO modes using suitable ICs.
6. Multiplexer/ De-multiplexer
Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer

Practical = 45
























2
TABLE OF CONTENTS

1. STUDY OF LOGIC GATES ......................................................................................................... 3
2. ADDER / SUBTRACTOR ............................................................................................................. 8
3. CODE CONVERTERS ................................................................................................................ 13
4. PARITY GENERATOR AND CHECKER ............................................................................... 17
5. STUDY OF FLIPFLOPS ............................................................................................................. 20
6. SHIFT REGISTERS .................................................................................................................... 25
7. ENCODER &DECODER ............................................................................................................ 32
8. MULTIPLEXER & DEMULTIPLEXER .................................................................................. 36
9. ASYNCHRONOUS COUNTERS ............................................................................................... 40
10. SYNCHRONOUS COUNTER .................................................................................................. 45






3
Exp. No: 1
Date:
STUDY OF LOGIC GATES
Aim:
To Study and verify the logic gates with the help of its truth table.

Components Required:

S.NO DESCRIPTION RANGE QUANTITY
1. IC 7400 2 input NAND gate - 1
2. IC 7402 2 input NOR gate - 1
3. IC 7404 NOT gate - 1
4. IC 7408 2 input AND gate - 1
5. IC 7432 2 input OR gate - 1
6. IC 7486 2 input XOR gate - 1
7. DC RPS +5V/1A 1
8. LED - 2
9. Bread board - 1
10. Connecting Wires - As Needed

Procedure:

1. Connect the IC according to the Pin Configuration.
2. Pin 7 is connected to the ground
3. Pin 14 is Connected to VCC
4. Output is seen through LED, If LED glows, it represents logic 1, otherwise logic 0
5. Verify the outputs through truth table

Theory:

OR Gate:
The OR Gate performs logical addition, commonly Known as OR Function. The OR
gate has two or more inputs and only one output. The operation of OR gate is such that a
HIGH (1) on the output is produced when any one of the inputs is HIGH (1). The output is
LOW (0) only when all the inputs are LOW (0).

AND Gate:
The AND Gate performs logical multiplication, commonly known as AND function.
The AND gate has two or more inputs and a single output. The output of an AND gate is
HIGH only when all the inputs are HIGH. Even if any one of the inputs is LOW, the output
will be LOW.

4
Pin Details:


IC 7432 OR Gate: IC 7400 NAND Gate:




IC 7408 AND Gate: IC 7486 XOR Gate:




IC 7404 Inverter: IC 7402 NOR Gate:




5
IC 7432- Quad 2 Input OR Gate Truth Table

A
Y=A+B
B

7432

IC 7408- Quad 2 Input AND Gate Truth Table


A
Y=AB
B

7408
IC 7404- Hex Inverter (NOT) Gate Truth Table

A Y= A

7404


IC 7402 Quad 2 input NOR Gate Truth Table

A

Y= (A+B)
B
7402

IC 7400 Quad 2 Input NAND Gate Truth Table

A
Y= (AB)
B

7400


IC 7486 Quad 2 Input Ex-OR Gate Truth Table

A
Y = A B
B

7486



A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
A B Y=AB
0 0 0
0 1 0
1 0 0
1 1 1
A Y= A
0 1
1 0
A B Y=(A+B)
0 0 1
0 1 0
1 0 0
1 1 0
A B Y=(AB)
0 0 1
0 1 1
1 0 1
1 1 0
A B Y=AB
0 0 0
0 1 1
1 0 1
1 1 0

6
NOT Gate:
The NOT performs the basic logical function called inversion or complementation.
The purpose of this logic gate is to convert one logic to the opposite logic level. It has one
input and one output. When HIGH input is applied to an inverter, a LOW output appears at
its output and vice versa.

NAND Gate:
NAND gate is a contraction of the NOT-AND gates. It has two or more inputs and
only one output. When all the inputs are HIGH, the output is LOW. If any one or both the
inputs are LOW, then the output is HIGH. The NAND called as Universal Gate

NOR Gate:
NOR gate is a contraction of the NOT-OR gates. It has two or more inputs and only
one output. When all the inputs are LOW, the output is HIGH. If any one or both the inputs
are HIGH, then the output is LOW. The NOR gate called as Universal Gate

EX-OR Gate:
An Exclusive-OR gate is a gate with two or more inputs and one output. The output
of a gate is HIGH when odd numbers of HIGH inputs are applied. If Even number of HIGH
inputs or all the inputs are LOW the output will be LOW.











Result :
Thus the all gates were studied and verified through its truth tables.









7
VIVA QUESTIONS


1) What is a Logic gate?

Logic gates are the basic elements that make up a digital system. The electronic gate
is a circuit that is able to operate on a number of binary inputs in order to perform a
particular logical function.

2) Write the names of basic logical operators.

1. NOT / INVERT
2. AND
3. OR

3) Which gates are called as the universal gates? What are its advantages?

The NAND and NOR gates are called as the universal gates. These gates are used to
perform any type of logic application.

4) Which gate is equal to AND-invert Gate?

NAND gate.

5) Which gate is equal to OR-invert Gate?

NOR gate.



Applications:

1. Used to perform various logic functions.
2. Used in digital circuits.

8
Exp. No. 2
Date:
ADDER / SUBTRACTOR
Aim:
To design and construct Adder / Subtractor circuits by using gates and to verify their
Truth tables.
Components Required:
S.NO DESCRIPTION RANGE QUANTITY
1. IC7408 2 input AND gate - 1
2. IC 7432 2 input OR gate - 1
3. IC 7486 2 input XOR gate - 1
4. Digital Trainer Kit - 1
5. LED - 1
6. Bread board - 1
7. Connecting Wires - As Needed
Procedure:
1. Connect the circuit as per the circuit diagram.
2. Give logical inputs as per the respective truth table.
3. Observe the logical output and verify with their truth table.
Theory:
Half-Adder:
The simplest combinational circuit, which performs the arithmetic addition of two
binary digits, is called a Half- adder. The half-adder has two inputs and two outputs. The
two inputs are two 1-bit numbers A and B, and the two outputs are Sum (S) of A and B
and the Carry bit denoted by C. From the truth table we can understand that the Sum
output is 1 when either of the inputs (A or B) is 1, or the carry outputs is 1 when both the
inputs (A and B) are 1.

Full Adder:
A half-adder has only two inputs and there is no provision to add a carry coming from
the lower order bits when multibit addition is performed. For this purpose, a full-adder is
designed. A Full-adder is a combinational circuit that performs the arithmetic sum of three
input bits and produces a Sum output and a Carry. It consists of three inputs and two
outputs. The two input variables denoted by X (Augend bit) and Y (Addend bit) represent
the two significant bits to be added. The third input, Z , represents the carry from the

9
previous lower significant position. The outputs are designated by the symbols S (for sum)
and C (for Carry).
HALF-ADDER Truth Table
A
S=AB+AB=A B
B

C=A B


K-MAP i)For Sum(S) ii) For Carry(C)
A B 0 1 A B 0 1
0 0

1 1
S=AB+AB=A B C=A B

FULL ADDER Truth Table
X
Y S= X Y Z
Z


C=(XY)Z+XY



i) For Sum (S) ii) For Carry(C)

X YZ X YZ
00 01 11 10 00 01 11 10




A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
X Y Z S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1



1


1

1

1


1


1

1


1

1

1



1


10
S= X Y Z C=(X Y)Z +XY
HALF-SUBTRACTOR Truth Table
X D= X Y
Y

B=X Y



K-MAP i) For D ii) For B
X Y 0 1 X Y 0 1
0 0

1 1
D=XY+XY=X Y B=X Y

FULL SUBTRACTOR
Truth Table
7486
7486



7404 7408


YZ YZ
X 00 01 11 10 X 00 01 11 10

0 0

1 1

B= XY + XZ +YZ D=X Y Z
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
X Y Z B D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

1



1

1



1



1

1

1



1


1

1 1

1




D= X Y Z
B= (X Y) Z +XY
X
Y
Z

11
Half-Subtractor:
The half subtractor is a combinational circuit which is used to perform subtraction of
two bits. It has two inputs, X (Minuend) and Y (Subtrahend) and two outputs D (difference)
and B (Borrow). From the truth table, it is clear that the difference output is 0 if X=Y and 1
if the X Y; the borrow output B is 1 whenever X<Y. If X is less than Y, then subtraction
is done by borrowing from the next higher order bit.

Full Subtractor:
A full subtractor is a combinational circuit that performs subtraction involving three
bits, namely minuend bit, subtrahend bit and the borrow from the previous stage. It has
three inputs, X (minuend), Y (Subtrahend) and Z (borrow from the previous stage) and two
outputs D (difference) and B (borrow).
























Result:
Thus the Adder and Subtractor were designed and verified with their truth tables.

12
VIVA QUESTIONS

1) Define Half adder.

The logic circuit that performs the addition of two bits is a half adder.

2) Define full adder.

The circuit that performs the addition of three bits is a full adder.

3) Define Half Subtractor.

The logic circuit that performs the Subtractor of two bits is a half Subtractor.

4) Define full Subtractor

The circuit that performs the Subtractor of three bits is a full Subtractor .

5) What is a karnaugh map?

A karnaugh map or k map is a pictorial form of truth table, in which the map
diagram is made up of squares, with each squares representing one minterm of the function.



Applications:

1. The circuit is used to perform the addition of three bits in a full adder.

2. The circuit is used to perform the addition of two bits in a half adder.

3. The circuit performs the Subtraction of two bits and three bits.


13
Exp. No: 3
Date :
CODE CONVERTERS
Aim:
To design the BCD to XS-3 code converter using suitable ICs


Components Required:
S.NO DESCRIPTION RANGE QUANTITY
1. IC 7402 2 input NOR gate - 1
2. IC 7408 2 input AND gate - 1
3. IC 7432 2 input OR gate - 1
4. IC 7486 2 input XOR gate 1
5. IC 7411 3 input AND gate 1
6. Digital Trainer Kit - 1
7. LED - 1
8. Bread board - 1
9. Connecting Wires - As Needed

Procedure:
1. Connect the circuit as per the circuit diagram
2. Give the logical inputs as per the respective truth table
3. Observe the logical output and verify with truth table.

Theory:
The availability of a large variety of codes for the same discrete information
results in the use of different codes by different digital systems. It is some times necessary
to use the output of one system as the input to another. A conversion circuit must be
inserted between two such systems. A code converter is a logic circuit that changes data
presented in one type of binary code to another type of binary code. In this connection we
are designed the circuit to convert the given codes to another.








14
BCD to XS-3Code Converter
Truth Table
BCD Code XS-3 Code
D C B A W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

DC BA DC BA
00 01 11 10 00 01 11 10









W=D+C(A+B) X=CBA+C(A+B)


DC BA DC BA
00 01 11 10 00 01 11 10





Y=BA+AB=AB Z=A




1 1 1
X X X X
1 1 X X
1 1 1
1
X X X X
1 X X
1 1
1 1
X X X X
1 X X
1 1
1 1
X X X X
1 X X

00
01
11
10

00
01
11
10

00
01
11
10

00
01
11
10

15
BCD to XS-3Code Converter

D C B A



Z=A

Y=BA+AB



X=CBA+C(A+B)





W=D+C(A+B)






Pin Detail:
IC 7411 AND Gate:



Result:
Thus the BCD to XS-3 code converters were designed and tested its performance
with truth tables

16

VIVA QUESTIONS
1) What is a karnaugh map?

A Karnaugh map or K map is a pictorial form of truth table, in which the map
diagram is made up of squares, with each squares representing one minterm of the function.

2) What is a Logic gate?

Logic gates are the basic elements that make up a digital system. The electronic
gate is a circuit that is able to operate on a number of binary inputs in order to perform a
particular logical function.

3) What is a BCD to XS-3 converter?
A BCD to XS-3 converter code converter is a logic circuit that changes data
presented in binary code to added binary value of three.

4) What is the Binary to Gray code converter and vise-versa?
A Binary to Gray code converter is a logic circuit that changes data presented in
Binary type code to Gray type code and vise-versa.

5) What is the code converter?

A code converter is a logic circuit that changes data presented in one type of binary
code to another type of binary code.





Applications:

By using code converter we change the data presented in one type of binary code to
another type of binary code.


17
Exp. No: 4
Date:
PARITY GENERATOR AND CHECKER
Aim:
To design the parity generator, parity checker and verify their performance.

Components Required:
S.NO DESCRIPTION RANGE QUANTITY
1. IC 7486 2 input XOR gate 1
2. Digital Trainer Kit - 1
3. LED - 3
4. Bread board - 1
5. Connecting Wires - As Needed

Procedure:
1. Connect the circuit as per the circuit diagram
2. Give the logical inputs as per the respective truth table
3. Observe the logical output and verify with truth table.

Theory:
Parity Generator and Parity Checker:
A parity bit is used for the purpose of detecting errors during transmission of
binary information. A parity bit is an extra bit included with a binary message to make the
number of 1s either odd or even. The message, including the parity it is transmitted and then
checked at the receiving end for errors. An error is checked if the checked parity does not
correspond with the one transmitted. The circuit that generates the parity bit in the
transmitter is called a parity generator and the circuit that checks the parity in the receiver is
called a parity checker. In even parity the added parity bit will make the total number of 1s
an even amount. In odd parity the added parity bit will make the total number of 1s an odd
amount.



Result :
Thus the Parity Generator and Checker were designed and tested their performance.


18
Parity Generator: Truth Table
7486

X 7486


Y P
Z


X YZ
00 01 11 10

0

1

P = X Y Z

Parity Checker 7486
X
Y
Z A=X Y Z P
Truth Table
P

7486
XY ZP
00 01 11 10








X Y Z Parity
Bit(P)
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

1

1
1

1

X Y Z P
Checker
Output
(A)
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
1 1
1 1

1

1
1
1

00

01

11

10

19
VIVA QUESTIONS

1. What is Parity Generator?
The circuit that generates the parity bit in the transmitter is called a parity generator
2. What is Parity Checker?
The circuit that checks the parity in the receiver is called a parity checker
3. What is even Parity?
If the added parity bit will make the total number of 1s an even then it is called as
even parity.
4. What is odd Parity?
If the added parity bit will make the total number of 1s an odd then it is called as odd
parity.
5. What is depletion mode operation MOS?

If the channel is initially doped lightly with p-type impurity a conducting channel
exists at zero gate voltage and the device is said to operate in depletion mode.


Application:

A parity bit is used for the purpose of detecting errors during transmission of binary
information.



20
Exp. No: 5
Date:
STUDY OF FLIP FLOPS
Aim:
To study the SR latch, JK flip flop, D flip flop using basic gates.

Components Required:
S.NO DESCRIPTION RANGE QUANTITY
1. IC 7400 2 input NAND gate - 1
2. IC 7402 2 input NOR gate - 1
3. IC 7411 3 input AND gate - 1
4. IC 7474 D flip-flop (dual) 1
5. IC 7476- JK flip-flop (dual) 1
6. Digital Trainer Kit - 1
7. LED - 1
8. Connecting Wires - As Needed
Procedure:
1. Connect the Circuit as per the circuit diagram and the IC as per the configuration.
2. Give the inputs as per the truth table and verify the outputs
Theory:
Flip flop:

The memory cell has only two states. It can be either 0 or 1. Such two state
sequential circuits are called flip-flops, because they flip from one state to another and then
flop back. A flip-flop is also known as bistable multivibrator, latch or toggle.
Types of flip-flop:
There four different types of flip-flop. They are S-R, J-K, D and T flip flop.

SET-RESET (S-R) FLIP-FLOP:
The S-R flip-flop has two inputs, namely SET and RESET and two outputs Q and
Q. The two outputs are complement to each other. The S-R flip-flop can be easily
implemented using NOR gates or NAND gates.

NOR-based S-R Flip-flop:
The S-R flip-flop can be constructed using two NOR gates connected back to back.
The cross-coupled connections from the output of one gate to the input of the other gate
constitute a feedback path. The output of the NOR gate is 0 if any input is 1 and output is 1
only when all inputs are 0.

21
NAND-based S-R flip-flop:
The operation of NAND S-R flip-flop can be analyzed in the same manner
employed for the NOR flip-flop. If any one of the inputs is low for the NAND gate then it
will force the output high. This flip-flop is called as S-R flip-flop, i.e., here S=0 and R=1
will set the flip-flop.

Clocked R-S flip-flop:
Synchronous circuit changes their states only when clock pulses are present. The
operation of the basic flip-flop can be modified by providing an additional control input that
determines when the state of flip-flop is to be changed. Such a circuit leads us to the
clocked S-R flip-flop, which consists of two additional AND gates at the S and R inputs.

D Flip-flop:
The D (delay) flip-flop only one input called the Delay (D) input and two outputs Q
and Q. It can be constructed from an S-R flip-flop by inserting an inverter between S and R
and assigning the symbol D to the S input. It consists of a NAND flip-flop with a gating
arrangement on its inputs.

J-K Flip-flop:
A J-K flip-flop has a characteristic similar to that of an S-R flip-flop. In addition, the
indeterminate condition of the S-R flip-flop is permitted in it. Inputs J and K behave like
inputs S and R to set and reset the flip-flop respectively. When J=K=1, the flip-flop output
toggles, i.e., switches to its complement state; if Q=0, it switches to Q=1 and vice versa.

T Flip-flop:
T flip-flop is also called Trigger or Toggle flip-flop, has only a single data (T) input,
a clock input and two outputs Q and Q. The T-type flip-flop is obtained from a J-K flip-
flop connecting its J and K inputs together. When T input is in the 0 state prior to a clock
pulse, the Q output will not change with clocking. When the T input is at a 1 level prior to
clocking, the output will be in the Q state after clocking.



Result :
Thus the flip-flops were studied and were verified with their truth tables.

22
SR Latch using NAND Logic SR Latch using NOR Logic
R R
Q Q

S Q S Q



Truth Table Truth Table







JK Flip-Flop

J Q
CLK

K Q

Truth Table










S R Q Q
0 0
No change

0 1 0 1
1 0 1 0
1 1 Indeterminate
S R Q Q
0 0 Indeterminate
0 1 1 0
1 0 0 1
1 1 No change
J K Q Q
0 0 No change
0 1 0 1
1 0 1 0
1 1 Toggling
J Q

IC 7476

K Q
CLK

23
D Flip Flop (Delay Flip flop)
D
D Q
CLK

Q

Truth Table
D
Qn

Qn+1

0 0 0
1 0 1
0 1 0
1 1 1

Pin Detail:
7476 JK Flip-flop Truth Table


7474 D Flip-flop Truth Table


J Q

IC 7476

K Q
D Q

IC 7474

Q
CLK
CLK

24
VIVA QUESTIONS
1. Define Flip flop.
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1
or 0 until directed by an input signal to change its state.

2. What are the different types of flip-flop?
There are various types of flip flops. Some of them are mentioned below they are,
RS flip-flop
SR flip-flop
D flip-flop
JK flip-flop
T flip-flop

3. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if
D=0, the output is reset.

4. What is a Master-slave flip-flop?
A Master-slave flip-flop consists of two flip-flops where one circuit serves as a
master and the other as a slave.

5. What is the operation of T flip-flop?
T flip-flop is also known as Toggle flip-flop.
When T=0 there is no change in the output.
When T=1 the output switch to the complement state (ie) the output
toggles.

Application:
1. As a bistable multivibrator
2. As a latch
3. As a toggle.








25
Exp. No: 6
Date: SHIFT REGISTERS

Aim:
To Study the Shift registers by using D Flip-Flops.

Components Required:
S.NO DESCRIPTION RANGE QUANTITY
1. IC 7404 NOT gate 1
2. IC 7408 2 input AND gate 1
3. IC 7432 2 input OR gate 1
4. IC 7486 2 input XOR gate 1
5. IC 7474 D flip-flop (dual), with preset and clear 1
6. Digital Trainer Kit - 1
7. LED - 3
8. Connecting Wires - As Needed

Procedure:
1. Connect the circuit as per the circuit diagram and pin configuration of the ICs.
2. Clear all the flip-flops by applying a high signal to the clear (reset) input.
3. Feed the data into the Serial mode or Parallel mode depends upon the circuit
operation.
4. Observe the output through LEDs and its verified with the help of Truth tables.

Theory:

SHIFT REGISTER:
A register that is used to store binary information is known as a memory register. A
register capable of shifting binary information either to the right or to the left is called a
shift register. Shift register are classified into the following four types,
Serial-in Serial-out (SISO)
Serial-in Parallel-out (SIPO)
Parallel-in Serial-out (PISO)
Parallel-in Parallel-out (PIPO)




26

Serial -In Serial- Out (Right) Shift Register (SISO)
VCC
Gnd
Data Data
Input output





Clk R S R S R S R S

High





Truth Table
















CLK
Data
Input
QA QB QC QD

1 1 0 0 0

0 0 1 0 0
1 1 0 1 0

1 1 1 0 1

X X 1 1 0

X X X 1 1

X X X X 1
7 14
2 5



3


1 4

12 9



11


13 10

12 9



11


13 10
7 14
2 5



3


1 4
I
C
7
4
7
4

I
C
7
4
7
4

I
C
7
4
7
4

I
C
7
4
7
4

QA QB QC
QD

27


Serial In Parallel Out Shift Register (SIPO)
QA QB QC QD

VCC
Gnd
Data
Input






CLK R S R S R S R S

High


Truth Table


















CLK Data
Input
QA QB QC QD

1 1 0 0 0

0 0 1 0 0

1 1 0 1 0

0 0 1 0 1
7 14
2 5



3


1 4

12 9



11


13 10

12 9



11


13 10
7 14
2 5



3


1 4
I
C
7
4
7
4

I
C
7
4
7
4

I
C
7
4
7
4

I
C
7
4
7
4


28


Parallel In Serial Out Shift Register (PISO)
DA DB DC DD




VCC
Gnd






Clk R S R S R S R S

High Qout

Truth Table



















CLK Shift/
Load
DA
DB DC DD
Qout
0 1 0 1 1 1
1 0 1 0 1 1
1 0 0 1 0 0
1 0 0 0 1 1
7 14
2 5

3

1 4

12 9

11

13 10

12 9

11

13 10

7 14
2 5

3

1 4
I
C
7
4
7
4

I
C
7
4
7
4

I
C
7
4
7
4

I
C
7
4
7
4

Shift / Load

29
Parallel-In Parallel Out Shift Register (PIPO)

DA DB DC DD

Vcc
Gnd






R S R S R S R S
CLK

High
QA QB QC QD

Truth Table








Pin Detail:
7474 D Flip-flop Truth Table


CLK DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0
7 14
2 5


3

1 4

12 9


11

13 10

12 9


11

13 10
7 14
2 5


3

1 4
I
C
7
4
7
4

I
C
7
4
7
4

I
C
7
4
7
4

I
C
7
4
7
4


30
Serial-In Serial-Out (SISO):
This type of shift register accepts data serially, i.e., one bit at a time on a single
input line. It produces the stored information on its single output also in serial output also
in serial form. Data may be shifted left (form low to high order bits) using shift-left
register or shifted right (from high to low order bits) using shift-right register.

Serial-In Parallel-Out (SIPO):
It consists of one serial input, and outputs are taken from all the flip-flop parallely.
In this register, data is shifted in serially but shifted out in parallel. In order to shift the
data out in parallel, it is necessary to have all the data available at the outputs at the same
time. Once the data is stored, each bit appears on its respective output line and all the bits
are available simultaneously, rather than on a bit-by-bit basis as with the serial output.

Parallel-In Serial-Out (PISO):
This type of shift register accepts data parallel, i.e., the bits are entered
simultaneously into their respective flip-flops rather than a bit-by-bit basis on one line.

Parallel-In Parallel-Out (PIPO):
In this type of register, data inputs can be shifted either in or out of the register in
parallel.











Result :
Thus the shift registers were studied in SISO, SIPO, PISO and PIPO modes.



31
VIVA QUESTIONS

1. What do you mean by present state?

The information stored in the memory elements at any given time defines the present
state of the sequential circuit.

2. What do you mean by next state?

The present state and the external inputs determine the outputs and the next state of
the sequential circuit.

3. Define registers.
A register is a group of flip-flops flip-flop can store one bit information. So an n-bit
register has a group of n flip-flops and is capable of storing any binary information/number
containing n-bits.

4. Define shift registers.

The binary information in a register can be moved from stage to stage within the
register or into or out of the register upon application of clock pulses. This type of bit
movement or shifting is essential for certain arithmetic and logic operations used in
microprocessors. This gives rise to group of registers called shift registers.

5. What are the different types of shift type?

There are five types. They are,
Serial In Serial Out Shift Register
Serial In Parallel Out Shift Register
Parallel In Serial Out Shift Register
Parallel In Parallel Out Shift Register
Bi-directional Shift Register

Application:

1. Used to store binary information
2. Memory register












32
Exp. No: 7
Date:
ENCODER &DECODER
Aim:
To construct 4 to 2 Encoder and 2 to 4 Decoder and verify their truth tables.
Components Required:
S.NO DESCRIPTION RANGE QUANTITY
1. IC 7404 NOT gate - 1
2 IC 7408 2 input AND gate - 1
3 IC 7432 2 input OR gate - 1
4 Digital Trainer Kit 1
5 LED 1
6 Connecting Wires - As Needed

Procedure:
1. Connect the circuit as per the circuit diagram.
2. Give logical inputs as per the respective truth table.
3. Observe the logical output and verify with their truth table
Theory:
4 to 2 Encoder:
An Encoder is a digital circuit that performs the inverse operation of a decoder.
Hence the opposite of the decoding process is called encoding. An encoder is a
combinational logic circuit that converts an active input signal into a coded output signal. It
has n input lines only one of which is active at any time and m output lines. It encodes one
of the active inputs to a coded binary output with m bits. In an encoder the number of
outputs is less than no. of inputs. Consider 4 to 2 encoder, which has 4 inputs for each 4
digit and 2 outputs generating the corresponding binary number.
The output Boolean functions are
Y0= D1+D2 Y1=D2+D3

2 to 4 Decoder:
A Decoder is similar to Demultiplexer but without any data input. Most digital
system requires the decoding of the data. Decoding is necessary in applications such as data
multiplexing, digital display, digital to analog converters and memory addressing. A
decoder is a logic circuit that converts an n bit binary input code into 2
n
output lines, Such
that each output line will be activated for only one of the possible combinations of inputs.

33
A 2 to 4 decoder has two inputs (A and B) and 4 outputs (D0-D3). Based on the two
inputs, one of the 4 outputs is selected. From the truth table it is clear that only one of the 4
outputs is selected based on the two select inputs. The logical expression for the outputs can
be written as follows:

D0= AB D1=AB D2=AB D3=AB























Result :

Thus the 4 to 2 encoder 2 to 4 Decoder were designed and verified with their truth
table.


34
4 to 2 ENCODER
Truth Table
D0 D1 D2 D3

Y1= D2+D3


Y0= D1+D2



2 to 4 DECODER
A B


D0= AB

D1=AB

D2=AB

D3=AB



Truth Table
Inputs Outputs
D0 D1 D2 D3 Y1 Y0
I 0 0 0 0 0
0 I 0 0 0 1
0 0 I 0 1 0
0 0 0 I 1 1
A B D0 D1 D2 D3
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I

35
VIVA QUESTIONS

1) Define Decoder.

A decoder is a multiple - input multiple output logic circuit that converts coded
inputs into coded outputs where the input and output codes are different.

2) Define Encoder.

An encoder has 2n input lines and n output lines. In encoder the output lines
generate the binary code corresponding to the input value.

3) What is binary decoder?

A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2n outputs lines

4) State the different classification of binary codes?

1. Weighted codes
2. Non - weighted codes
3. Reflective codes
4. Sequential codes
5. Alphanumeric codes
6. Error Detecting and correcting codes.

5) What is priority Encoder?

A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest
priority will take precedence.


Applications:

1. Telephone circuits.
2. AM/FM circuits.
3. Data multiplexing
4. Digital to analog converters and memory addressing.
5. Digital display











36
Exp. No: 8
Date:
MULTIPLEXER & DEMULTIPLEXER
Aim:
1. To design and construct the 4 to 1 MUX using gates and verify the truth table
2. To design and construct the 1 to 4 Demux using gates and verify the truth table

Components Required:
S.NO DESCRIPTION RANGE QUANTITY
1. IC 7404 NOT gate - 1
2 IC 7408 2 input AND gate - 1
3 IC 7411 3 input AND gate
4 IC 7432 2 input OR gate - 1
5 Digital Trainer Kit 1
6 LED 4
7 Connecting Wires - As Needed

Procedure:
1. Connect the circuit as per the circuit diagram.
2. Give logical inputs as per the respective truth table.
3. Observe the logical output and verify with their truth table.

Theory:
4 to 1 Multiplexer:
The term Multiplex means many into one. Multiplexing is the process of
transmitting a large number of information over a single line. A digital Multiplexer is a
combinational circuit that selects one digital information from several sources and
transmits the selected information on a single output line. A Multiplexer is also called a
data selector since it selects one of many inputs and steers the information to the output.
The 4 to 1 Mux has 4 input lines (D0-D3), a single output line (Y) and two select lines (S1
and S2) to select one of the four input lines. From the truth table, a logical expression for
the output in terms of the data input and the select inputs.






37
The data output Y = Data input D0, iff S1=0 and S2=0
Therefore Y=D0S1S2 = D0 00=D01.1=D0
Similarly Y=D1S1S2; Y= D1 when S1=0 and S2=1
Y=D2S1S2; Y =D2 when S1=1 and S2=0
Y= D3S1S2; Y =D3 when S1=1 and S2=1
If above the terms are ORed, then the final expression for the output is given by

Y = D0S1S2 + D1S1S2 + D2S1S2+ D3S1S2







1 to 4 Demultiplexer:
The word Demultiplexer means one into many. Demultiplexing is the process of
taking information from one input and transmitting the same over one several outputs. A
Demultiplexer is logic circuit that receives information on a single input and transmits the
same information over one of several (2
n
) output lines. A 1 to 4 Demux has a single input
(I), four outputs (D0-D3) and two select inputs (A and B). From the truth table, it is clear
that the data input is connected to output D0 when A=B=0 and the data input is connected
to D1 when A=0 and B=1. Similarly, the data input is connected to D2 and D3 when A=1and
B=0 and when A=B=1, respectively.
Expression is given by:
D0 =IAB D1=IAB D2=IAB D3=IAB

4 to 1 MULTIPLEXER
S1 S2
4X IC7411
D0 7432

D1
D2 Y=S1S2D0+S1S2D1+
S1S2D2 + S1S2D3
D3

38
Truth Table









1 to 4 DEMULTIPLEXER












Truth Table









Result:

Thus the 4 to 1 Multiplexer and 1 to 4 Demultiplexer were designed and verified
with their truth tables.
Data Select Inputs Output
S1 S2 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
I A B D0 D1 D2 D3
0 X X 0 0 0
1 0 0 I 0 0 0
1 0 1 0 I 0 0
1 1 0 0 0 I 0
1 1 1 0 0 0 I
D0

D1

D2

D3
I A B

39
VIVA QUESTIONS

1. Define Multiplexer.
Multiplexer is a digital switch. It allows digital information from several sources to
be routed onto a single output line.

2. Define De- Multiplexer.
De-Multiplexer is a digital switch. It allows digital information from single source
to be routed onto a several output lines.

3. Define address and word.
In a ROM, each bit combination of the input variable is called on address. Each bit
combination that comes out of the output lines is called a word.

4. Explain the different applications of open collector TTL.
a. Wired logic
b. Common bus system
c. Drive a lamp or relay

5. Define skew and clock skew.
The phase shift between the rectangular clock waveforms is referred to as skew and
the time delay between the two clock pulses is called clock skew.



Applications:

1. To Construct Telephone Lines

2. To Connect Data Bus














40
Exp. No: 9
Date:
ASYNCHRONOUS COUNTERS
Aim:
To construct the 4-bit binary Up-Down counter in asynchronous mode using JK
Flip-flop and test the performance of it.

Components Required:
S.NO DESCRIPTION RANGE QUANTITY
1. IC 7400 2 input NAND gate - 1
2 IC 7476 JK flip-flop (dual), - 2
3 Digital Trainer Kit - 1
4 LED - 4
5 Connecting Wires - As Needed

Procedure:
1. Connect the circuit as per the Circuit diagram.
2. Clear all the flip-flops by applying a high signal to the clear (reset) input.
3. Apply clock pulse to the LSB Flip-flop each time.
4. Verify the output of the circuit with the truth table.
Theory:
4 Bit Binary Up Counter
A Counter, by function, is a sequential circuit consisting of a set of flip-flops
connected in a suitable manner to count the sequence of the input pulses presented to it
digital form. An Asynchronous or Ripple counter can be constructed using minimum
hardware. In an asynchronous counter, each flip-flop is triggered by the output from the
previous flip-flop which limits its speed of operation. The settling time in asynchronous
counters, is the cumulative sum of the individual settling times of flip-flops. It is also called
a Serial counter. The Asynchronous counter is the simplest in terms of logical operations,
and is therefore the easiest to design. In this counter, all the flip-flops are not under the
control of a single clock. Here, the clock pulse is applied to the first flip-flop, i.e. the least
significant bit stage of the counter, and the successive flip-flop is triggered by the output is
constructed using clocked JK flip-flops. The system clock, a square wave, drives flip-flop
A(LSB). The output of A drives flip-flop B, the output of B drives flip-flop C, and C output
drives flip-flop D. All the J and K inputs connected to VCC(High(1)), which means that each
flip-flop toggles on the edge(-ve) clock pulse.

41
Consider initially all flip-flops to be in the logical 0 state(i.e. QA= QB= QC= QD=0).
A -ve transition in the clock input which drives flip-flop A causes QA to change from 0 to 1.
Flip-flop B doesnt change its state since it is also requires -ve transition at its clock input,
i.e. it requires its clock input(QA) to change from 1 to 0. With arrival of second clock pulse
to flip-flop A, QA goes from1 to 0. This change of state creates the ve going edge needed
to trigger flip-flop B, and thus QB goes from 0 to 1. Before the arrival of the 16
th
clock
pulse, all the flip-flops are in the logical 1 state. Clock pulse 16 causes QA, QB, QC, and QD
to go logical 0 state in turn.

4 Bit Binary Down Counter:
Circuit diagram is similar to up counter except the complement output of flip-flop is
drives the next flip-flop( as Clock Pulse). Initially all the flip-flops will be in logical 1 state.
A ve transition in the clock input, which derives flip-flop A causes QA to Change from 1 to
0. But QA is changes form 0 to 1(i.e. +ve transition), which drives the flip-flop B, the
output of flip-flop remains unchanged. During the next clock pulse QA output changes from
0 to 1 and QA changes from 1 to 0. Now B flip-flop output QB changes from 1 to 0.
Similarly whenever Complement output of each flip-flop would change the state from 1 to
0, the output of the next flip-flop to that change their states.

4 Bit Binary Up Counter
QA (LSB) QB QC QD (MSB)
High
VCC
Gnd




Clk R S R S R S R S

High
Fig: 9.1.1
13 5
4 15

1

16
2 3

9 11

6

12
7 8
13 5
4 15

1

16
2 3

9 11

6

12
7 8

I
C
7
4
7
6

I
C
7
4
7
6

I
C
7
4
7
6

I
C
7
4
7
6


42
Truth Table
















4 Bit Binary Down Counter
QA (LSB) QB QC QD (MSB)

High
VCC
Gnd







Clk R S R S R S R S

High




QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
13 5
4 15

1

16 14
2 3
13 5
4 15

1

16 14
2 3

9 11

6

12 10
7 8

9 11

6

12 10
7 8

I
C
7
4
7
6

I
C
7
4
7
6

I
C
7
4
7
6

I
C
7
4
7
6


43
Truth Table

















Result :
Thus the 4 bit binary Up-Down counter in asynchronous mode were constructed
using JK Flip-flop and their operations are tested with the help of their truth tables.










QD QC QB QA
1 1 1 1
1 1 1 0
1 1 0 1
1 1 0 0
1 0 1 1
1 0 1 0
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0

44





VIVA QUESTIONS

1. What are the classifications of sequential circuits?
The sequential circuits are classified on the basis of timing of their signals into two
types. They are,
1) Synchronous sequential circuit.
2) Asynchronous sequential circuit

2. Define race around condition.
In JK flip-flop, output is fed back to the input. Therefore change in the output results
change in the input. Due to this in the positive half of the clock pulse if both J and K are
high then output toggles continuously. This condition is called race around condition.
3. What is edge-triggered flip-flop?
The problem of race around condition can solve by edge triggering flip-flop. The
term edge triggering means that the flip-flop changes state either at the positive edge or
negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the
clock.
4. What are excitation variables?

Next state variables in asynchronous sequential circuits

5. Give the comparison between combinational circuits and sequential circuits.
Combinational circuits Sequential circuits
Memory unit is not required Memory unity is required
Parallel adder is a combinational circuit Serial adder is a sequential circuit

Applications:
1. Used to count the number of Pulses
2. Used in timers

45
Exp. No: 10
Date:
SYNCHRONOUS COUNTER
Aim:
To design the Mod 8 Synchronous Counter using JK flip-flops and to verify their
operation.

Components Required:
S.NO DESCRIPTION RANGE QUANTITY
1. IC 7408 - 1
2 IC 7476 JK flip-flop (dual) - 2
3 Digital Trainer Kit - 1
4 LED - 3
5 Connecting Wires - As Needed

Procedure:
1. Write State table, which should consists count sequences and flip-flop inputs.
2. Deduce the input functions using K map for each flip-flop.
3. Draw the circuit diagram for the deduced input functions using JK flip-flops
4. Apply clock pulse and verify the count sequences.

Theory:
3 Bit Synchronous Counter:
A Synchronous counter is also called Parallel Counter. In this counter, the clock
inputs of all the flip-flops are connected together so that the input clock signal is applied
simultaneously to each flip-flop. Also, only the LSB flip flop A has its J and K inputs
connected permanently to VCC while the J and K inputs of the other flip-flops are driven by
some combination of flip-flop outputs. The J and K inputs of the flip-flop B are connected
to with QA; The J and K inputs of the flip-flop C are connected with AND operated output
of QA and QB. The flip-flop A changes its state with the occurrence of negative transition at
each clock pulse. The flip-flop B changes its state when QA=1 and when there is negative
transition at clock input. Flip-flop C changes its state when QA=QB=1 and when there is
negative transition at clock input.



46

SYNCHRONOUS (MOD-8) UP COUNTER
Truth Table for JK Flip-flop Excitation Table for JK Flip-Flop







State Table
Present State Next State Flip-flop Inputs
QC(t) QB(t) QA(t) QC(t+1) QB(t+1) QA(t+1) JC KC JB KB JA KA
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1


K-MAP SIMPLIFICATION


QC QBQA QC QBQA
00 01 11 10 00 01 11 10

1

X

X

1
1 X X 1

JA=1 KA=1




J K Q Q
0 0 No change
0 1 0 1
1 0 1 0
1 1 Toggling
Present
State
Next
State
J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

X

1

1

X
X 1 1 X

47

QC QBQA QC QBQA
00 01 11 10 00 01 11 10

0

1

JB = QA KB = QA


QC QBQA QC QBQA
00 01 11 10 00 01 11 10



1

X X X X

JC = QBQA KC = QBQA


CIRCUIT DIAGRAM FOR SYNCHRONOUS UP COUNTER
(High)
VCC(High)

Gnd






CLK R S R S R S

High
QA(LSB) QB QC (MSB)


1

X

X
1 X X

X

X

1

X X 1

X

X

X

X
1
0

1

0

1

0

1

13 5
4 15


1

16
2 3

9 11


6

12
7 8
13 5
4 15

1

16
2 3
I
C

7
4
7
6

I
C

7
4
7
6

I
C

7
4
7
6


48
SYNCHRONOUS (MOD-8) DOWN COUNTER
State Table

K MAP SIMPLIFICATION:
QC QBQA QC QBQA
00 01 11 10 00 01 11 10





JA=1 KA=1

QC QBQA QC QBQA
00 01 11 10 00 01 11 10





JB=QA KB= QA



Present State Next State Flip-flop Inputs
QC(t) QB(t) QA(t) QC(t+1) QB(t+1) QA(t+1) JC KC JB KB JA KA
1 1 1 1 1 0 X 0 X 0 X 1
1 1 0 1 0 1 X 0 X 1 1 X
1 0 1 0 0 0 X 0 0 X X 1
1 0 0 0 1 1 X 1 1 X 1 X
0 1 1 0 1 0 0 X X 0 X 1
0 1 0 0 0 1 0 X X 1 1 X
0 0 1 0 0 0 0 X 0 X X 1
0 0 0 1 1 1 1 X 1 X 1 X

1

X

X

1
1 X X 1

X

1

1

X
X 1 1 X

1



X

X
1 X X

X

X



1
X X 1

0


1

0


1

0


1

49
QC QBQA QC QBQA
00 01 11 10 00 01 11 10

0

1

JB=QBQA KB= QBQA

CIRCUIT DIAGRAM FOR SYNCHRONOUS DOWN COUNTER

VCC(High)

VCC
Gnd






CLK R S R S R S

VCC

(High)
QA(LSB) QB QC (MSB)








1

X X X X

X
X X X
1
13 5
4 15


1

16 14
2 3

9 11


6

12 10
7 8
13 5
4 15

1

16 14
2 3
I
C

7
4
7
6

I
C

7
4
7
6

I
C

7
4
7
6


0


1

50
3 Bit Synchronous Down Counter:
In this counter, the clock inputs of all the flip-flops are connected together so that
the input clock signal is applied simultaneously to each flip-flop. Also, only the LSB flip
flop A has its J and K inputs connected permanently to VCC while the J and K inputs of the
other flip-flops are driven by some combination of flip-flop outputs. The J and K inputs of
the flip-flop B are connected to with QA; The J and K inputs of the flip-flop C are
connected with AND operated output of QA and QB. The flip-flop A changes its state with
the occurrence of negative transition at each clock pulse. The flip-flop B changes its state
when QA=1 and when there is negative transition at clock input. Flip-flop C changes its
state when QA=QB=1 and when there is negative transition at clock input.















Result:
Thus the 3 bit Synchronous up/down counter was designed, constructed and verified.





51
VIVA QUESTIONS

1. State the types of sequential circuits.

Synchronous sequential circuits and Asynchronous sequential circuits.

2. Define synchronous sequential circuit

In synchronous sequential circuits, signals can affect the memory elements only at
Discrete instant of time.

3. Define Asynchronous sequential circuit?

In asynchronous sequential circuits change in input signals can affect memory
element at any instant of time.

4. What do you mean by present state?
The information stored in the memory elements at any given time defines the
present state of the sequential circuit.

5. What do you mean by next state?
The present state and the external inputs determine the outputs and the next state of
the sequential circuit

Application:

1. Used to count the number of Pulses
2. Used in timers