2
2
2
1
2
22
2
21
2
12
2
11
2
2
2
1
a
a
*
S S
S S
b
b
with
 a
i

2
power wave travelling towards the twoport gate
 b
i

2
power wave reflected back from the twoport gate
and
 S
11

2
power reflected from port1
 S
12

2
power transmitted from port1 to port2
 S
21

2
power transmitted from port2 to port1
 S
22

2
power reflected from port2
This means that Sparameters relate traveling waves (power) to a twoport's reflection and transmission
behavior. Since the twoport is imbedded in a characteristic impedance of Z0, these 'waves' can also be
interpreted in terms of normalized voltages or currents. This is explained below.
S
11

2
a
1

2
b
1

2
Z0
Z0
a
2

2
b
2

2
S
21

2
S
12

2
S
22

2
0
Z
v * v
i * v P = =
Starting with normalized gives normalized amplitudes
power to Z0 for voltage and current
0
0
Z * i
Z
V
P = =
Power
Domain
a
1

2
Voltage
Domain
a
1
SParameters and Characteristic Impedance Z0
Agilent Technologies
Looking at the Sparameter coefficients individually, we have:
0 a
v
v
a
b
S
2
1 port towards
1 port at reflected
1
1
11
=
= =
0 a
v
v
a
b
S
1
2 port towards
1 port of out
2
1
12
=
= =
0 a
v
v
a
b
S
2
1 port towards
2 port of out
1
2
21
=
= =
0 a
v
v
a
b
S
1
2 port towards
2 port at reflected
2
2
22
=
= =
(3)
Let's now discuss some characteristic Sparameter values.
 S11, S22 .
1  all voltage amplitudes towards the twoport are inverted and reflected (0 )
0  impedance matching, no reflections at all (50 )
+1  voltage amplitudes are reflected (infinite )
Note: The magnitudes of S11 and S22 are always 1
On the other hand, the magnitude of S21 (transfer characteristics) resp. S12 (reverse) can exceed the
value of 1 in the case of amplification within a Z0 impedance system:
 S21, S12 .
< 1  input signal is amplified in the Z0 environment, the phase is inverted (transistor)
1  input signal is transmitted (unity gain), but the phase is inverted
0  no signal transmission at all
+1  unity gain signal transmission
> +1  input signal is amplified in the Z0 environment
To perform an accurate device modeling, it is very important to first understand Sparameter plots.
This is the topic of the following slides.
Considering S11 in equation (3) and introducing equations (1) and (2), we can relate the signal
towards the twoport to its reflections at the twoport input like:
) t coefficien _ reflection (
towards
refl
1
1
0
2
a
11
v
v
a
b
S = = =
=
What makes S
xx
parameters especially interesting for modeling, is that S11 and S22 can be interpreted
as complex input or output resistance of the twoport (including the termination at the opposite side of
the twoport with Z0 !!). That's why they are usually plotted in a Smith chart.
The Smith chart is a transformation of the complex impedance plane R into the complex reflection
coefficient (rho) following:
0 Z R
0 Z R
+
=
with the system's reference impedance Z0 = 50 .
This means that the right half of the complex impedance plane R is transformed into a circle in the
domain with radius '1'
Interpreting the Smith Chart for S11 and S22
R
j50
50
1
4 3
2
1 1
j
j
1
2
3
4
R  Z0
S11 = 
R + Z0
for e.g. Z0=50
Agilent Technologies
The slide above consolidates this context a little further: it shows a square with the corners (0/0),
(50/0), (50/j50) and (0/j50) in the complex impedance plane and its equivalent in the Smith chart
for Z0=50. Please watch the angelpreserving property of this transform (rectangles stay rectangles
close to their origins). Also watch how the positive and negative imaginary axis of the R plane is
transformed into the Smith chart domain ( ), and where (50/j50) is located in the Smith chart.
Also verify that the center of the Smith chart represents Z0.
I.e. for Z0 = 50 in the impedance plane, this locus is transformed right into the center of the Smith
chart at (50/j0) .
WEB INFO:
Agilent Technologies Interactive Application Note 951,
SParameter Techniques for Faster, More Accurate Network Designs.
The next slide gives Smith chart plots for different electrical components connected to a single port of a
vector network analyzer (VNA). For an ohmic resistor, all measurement results are located on the x
axis, R<Z0 is to the left of the center, R>Z0 to the right. From the scaling of the Smith chart, we can
calculate the value of the resistor as x*Z0.
For inductors and capacitors, however, the measurement result is frequency dependent and follows the
sketched traces. Note that the curves turn to the right with increasing frequency.
jL
1/jC
R
inductive
capacitive
Z0
Interpreting the Reflection SParameters
S11 and S22
Z
Note: for TwoPorts,
Sxx represents the
input impedance
at Sxx including Z0
of the opposite port!
Example: 1port
Agilent Technologies
Referring to the transfer parameters Sxy, we consider the next slide. For a capacitor inserted between
both ports of a VNA, the Sxy trace starts at '0' for DC (the capacitor is an ideal OPEN), while it tends
towards +1 for infinite frequency (the capacitor is an ideal SHORT, all power is transmitted).
For transistors, with signal amplification in the Z0 environment, but (of course) phase inversion, the
trace starts at the negative xaxis, below 1. For infinite frequency, the transistor becomes a passive
component with no gain any more. I.e. its capacitors short the energy flow to ground, and S21 tends to
'0'.
freq
Curve from 0 to +1
Curve from 1.9 to +0.2
freq
freq
P2 P1
Passive DUT
P2
P1
Active DUT
Interpreting the Polar Plots of S12 and S21
With this in mind, let's lead over to specific Sparameter device measurement and modeling aspects. A
good model is able to cover both, the reflection (Sxx) and the transmit (Sxy) Sparameters, see the next
slide.
As a first and basic aspect, it must be noted that the starting point of all Sparameter traces is
determined by the DC behavior of the component, and therefore completely dependent on the DC
model fit! Only the course, the further trace of the Sparameters can be influenced by the RF model
parameters like the capacitors, the transit times (of transistors) etc. This is very important to consider.
SParameter Device Modeling in General
Sxx
Sxy
freq
freq
Agilent Technologies
The following series of slides give examples for possible Sparameter measurement and modeling
problems.
Considering transistor Sparameter modeling, the device has to be biased during the Sparameter
measurements, see the following block diagram:
DUT
External
Bias TEEs
FS
S F
DC
Source/
Monitor
Synthesized
Sweeper
RF
DC
Sparameter
Test Set
Vector
Network
Analyzer
ICCAP
If there is a problem with the fitting of the simulated Sparameters and the measurement curves for
lowest frequencies, especially for specific bias conditions, it must be considered if there is e.g. a DC
bias voltage drop in the AC/DC bias TEE. If this occurs, the measured voltage drop is not included in a
standalone simulation of the DUT. The simulation circuit must be enhanced with this resistor Rbias !
The following slide shows this effect with a comparison of measured and simulated curves, with and
without the additional resistor Rbias in the enhanced simulation test circuit. Note that in this example,
the transit time has not yet been modeled, and therefore, the fit for higher frequencies is not yet
obtained.
DC Bias Voltage Drop in the VNA Bias TEEs
DC
AC
transistor
Lbias
Cbias
Rbias
Measurement
DC bias
voltage drop
w/o Rbias
with Rbias
Agilent Technologies
Another important aspect is the fact that using a conventionally network analyzer, the stimulus
frequency and the measurement frequency are identical. Furthermore, the bandwidth of the received
signal is typically extremely smallband (for higher resolution), around a few Hertz. Therefore, care
must be taken to ensure that only small signal power be applied for the measurement. If the applied
signal power is too high, signal distortion can occur. The next slides cover the problems which may
arise.
AC Power Level during SParameter Measurements
Due to the nonlinear
transistor curves,
a too big AC amplitude
may become distorted.
Unsymmetrical distortions
include a DC part. This DC
part will shift the DC
operating point !
iC
vBE
Agilent Technologies
Therefore, it is very important to check the signal integrity when performing VNA measurements on
nonlinear components like transistors.
This can be done as follows: the VNA is calibrated for a very low signal power, e.g. 30..40 dBm. An
Sparameter measurement is performed and the result is considered as being linear. After that, the RF
signal power is increased, a new calibration is performed and the new measurement checked against the
previous one. When a deviation of the curves occurs, the applied signal power is too high. This allows
to identify the max. applicable RF signal power for a specific transistor.
Another method, applicable to MOS and also bipolar transistors, is to measure the DC output
characteristic and to convert it into an Rout plot, see the next slide. The measurement is performed
using the AC/DC bias TEE coupler. With the first measurement, the VNA is switched off, and the
measurement result is regarded as nondistorted Rout curves. After that, the DC traces are remeasured,
and the signal power of the VNA is increased manually, until a distortion on Rout becomes visible.
This is, again, the max. applicable RF power level.
AC Power Level during SParameter Measurements
RF power ok.
too much RF power
Rout /k
Agilent Technologies
In the next slide, a method to check the correct RF signal power is introduced for bipolar transistors. A
flat trace of fT vs. iC for low iC might indicate the RF rectification effect, and thus again a too big
value of the RF signal power.
AC Power Level during SParameter Measurements
log (fT)
log (iC)
vCE
fT = 
2*PI*TFF
1
Agilent Technologies
Finally, it must be mentioned that network analyzers offer best resolution for devices with impedances
'around' Z0. Like depicted with the following slide, it is difficult to resolve the impedance for values
greater than ~1k with a Smith chart. However, since there are always inductors or capacitors
associated with such impedances, their frequency dependence helps in modeling considerably. This is
because these parasitic components will short the high impedances for higher frequencies. The S
parameter traces of both, the high impedance starting and the parasitics, will come closer to the center
of the Smith chart. Since modeling means curve fitting, these starting points are covered automatically.
As an example, see the RG modeling of MOS transistors further below.
Transistors and Network Analyzers:
Obtainable Resolution Big Impedances
Resolution
is critical
for resistances
>1k
Agilent Technologies
Last not least, the next two slides give suggestions for the pad layout for measuring Sparameters.
Probe Types and Transistor Pad Layout for DC to RF
DC probes
S
G D
B
S
B
GroundSignalGround
Probes
S
G D
B B
S
Source and Bulk are
shorted by the probes!
pitch
All 4 terminals can be
biased independently
DC
Sparameter
Agilent Technologies
Biasing the Bulk separately,
using GS probes
B
G D
S S
S
Port1
Port2
to Bulk DC power supply
Agilent Technologies
Publications:
Cascade Microtech Application Note: Layout Rules for GHz Probing, 1992,
Publication LAYOUT19
Special Aspects of VNA Calibration
Generalized Block Diagram
of a Vector Network Analyzer (VNA)
INCIDENT (R)
REFLECTED
(A)
TRANSMITTED
(B)
RECEIVER / DOWNCONVERTER
PROCESSOR / DISPLAY
SOURCE
Incident
Reflected
Transmitted
DUT
small band IF (!)
Agilent Technologies
Publications:
Agilent Technologies Application Notes
12871: Understanding the Fundamental Principles of Vector Network Analyzers,
Pub.No. 59657710E, 1997
12872: Exploring the Architectures of Network Analyzers,
Pub.No 59657708E, 1997
12874: Network Analyzer Measurements: Filter and Amplifier Examples,
Pub.No59657710E, 1997
HewlettPackard 1997 Back to Basics Seminar, D.Ballo, Network Analyzer Basics,
Pub.No. 59657917E
Cascade Microtech Application Note: On Wafer Vector Network Analyzer Calibration and
Measurements, 1997, Pub No. PYRPROBE0597

As can be seen in the next slide, there are 6 error terms in forward direction:
Directivity: crosstalk of the power coupler
Crosstalk: crosstalk inside the Sparameter test set, overlying the DUT
Source Mismatch: multiple reflections due to nonZ0 input and output
impedance of the DUT
Load Mismatch: the same for the opposite port
Reflection Tracking A/R: frequency dependence of signal path source >R>A
Transmission Tracking A/R: same for signal path source >R>B
For the reverse calibration, another 6 error terms add up to a total of 12 terms.
directivity
~
AC
source
power
splitter
DUT
R
power
coupler
B
A
reference
crosstalk
source
missmatch
load
mismatch
frequency response:
reflection tracking (A/R)
transmission tracking (B/R)
H(f)
f
.
Basic Components of a VNA
and Corresponding Error Terms
6 error terms to be corrected for each port,
i.e. 12 error terms for both ports
Agilent Technologies
It should be noted that VNA calibration means error correction for vectors, because the measured
signals represent magnitude and phase of voltages in a Z0 environment.
SParameter Error Correction
means Vector Error Correction
accounts for all major sources of systematic error
S
xy Measured
error vectors
S
xy Device
S
x
y
C
o
r
r
e
c
t
i
o
n
Agilent Technologies
The next slides shows the standards for a SHORTOPENLOADTHRU VNA calibration.
SOLT Calibration Standards
for GroundSignalGround probes (G_S_G)
OPEN
SHORT
50 LOAD
THRU
Probes in the air
calibration
All standard calkit data must be accurately entered into the VNA.
Agilent Technologies
Some notes about these calibration standards:
While in the case of the LCRZ meter for the characterization of the space charge capacitors, the
calibration corrects for a single ideal offset capacitor, a NWA calibration uses cal standards (OPEN,
SHORT, LOAD, THRU etc.) from a cal kit. These cal standards do not represent ideal standards. It
means that a SHORT is not an ideal SHORT, but instead represents rather an inductance. The same
applies to the THRU, which has a nonideal delay time. The OPEN corresponds rather to a capacitor
than to an ideal OPEN. Therefore, these nonidealities have to be entered into the NWA before
calibration. This is called 'modifying the cal kit'. After that, the calibration is performed and the
correction terms (which include the 12 error contributions from above and also those of the cal kit
components) are stored in the cal set of the NWA. Afterwards, when the measurement is performed,
the raw measured data arrays will be corrected using a correction technique related to the selected
calibration method, and referring to the specific cal set. Finally, this corrected measurement result is
displayed on the NWA monitor.
Therefore, after the calibration, a remeasurement of the OPEN will not represent an ideal open, but
instead exactly those parasitic components as described in the documentation of the OPEN. In the same
way, a THROUGH shows up after calibration with its real delay time, and a SHORT represents its
inductive behavior!
Verifying NWA Calibration
Since the NWA calibration has to be performed always very carefully, it is of particular interest to
verify the quality of the applied calibration. This can be done easily, when using a modeling tool like
ICCAP. After a remeasurement of a calibration standard, we define a test circuit representing exactly
the nonidealities of the standard. Calling a simulator, we can simulate the expected behavior of e.g. the
OPEN probes. If the calibration was executed correctly, there is an excellent match between measured
and simulated curves. This check is performed with all four SOLT calibration standards.
Note: This procedure can also be applied to check the quality of an elder calibration.
Verifying the Calibration
THRU
E.g.
1psec
OPEN
SHORT LOAD
E.g. 
9fF
E.g. 50
W
E.g.
2.4pH
remeasuring each standard after calibration
should be identical to the simulation results
of the standard, based on the calkit data
The very best cal verification is, however,
to measure an accurately known golden device
Agilent Technologies
Deembedding and Required Test Structures
When characterizing a device separately, test pads have to be added in order to be able to measure it.
This means that parasitic components due to the test structure degrade the performance of the 'inner'
DUT. If it is possible to measure those parasitics separately, without the 'inner' DUT, they can be
'subtracted' from the total measurement.
Why Deembedding ?
/Hz
/V
Agilent Technologies
In the case of a MOS transistor, we have the following situation:
Measurement and Deembedding
Source + Bulk
Source + Bulk
Reference
plane of
VNA port2
/Hz
Ground
Ground
Signal
Ground
Ground
Signal
Ground
Ground
Signal
Ground
Ground
Signal
Gate Drain
Reference
plane of
VNA port1
Reference
planes of
DUT
Agilent Technologies
And in the simplest case, where only capacitances of the test pads are just in parallel with the DUT, we
have the following situation:
In the simplest case ...
Y
DUT
= Y
Total
Y
OPEN

Agilent Technologies
This means, a simple subtraction of the Y matrices gives the performance of the inner DUT.
For higher frequencies, typically above 10GHz for Silicon, more test pad parasitics begin to play a role.
This means that not only the parallel parasitics need to be subtracted (Y matrix), but also those in series
with the inner DUT (Z matrix subtraction). In this case we not only need an OPEN dummy test
structure, but also a SHORT, where the DUT is replaced by a metal 1 short.
Note that before subtracting the Z matrix of the SHORT, the SHORT dummy has to be deembedded
first from the OPEN dummy!
The Deembedding Procedure
For OPEN And SHORT Deembedding
DUT
subtract the Y matrix
of the parallel parasitics
subtract the Z matrix
of the series parasitics
DUT
DUT
The SHORT has to be
deembedded from the OPEN first!
Agilent Technologies
For this commonly used method, it is an absolute prerequisite that there are no series components
hidden in the OPEN dummy measurement, and no parallel components in the SHORT dummy
measurement. If such hidden components are present, the simple matrix subtractions will lead to a
wrong deembedding.
Like with the calibration before, it is very important to verify the deembedding quality, before
applying it finally to the inner DUT. This can be done easily if there is also a THRU dummy structure
available.
Provided the THRU has been deembedded correctly, it can be modeled with a simple delay. If this is
the case and the delay time and characteristic impedance represent physical parameter values, it can be
assumed that the deembedding is correct.
measured
deembedded
TD
(trace)
Deembedding Verification
with a THRU Dummy
Z0
(trace)
deembedded
measured
Sxx
Sxy
Z0, TD
equiv.schematic:
(deembedded from
the OPEN and the SHORT)
Agilent Technologies
Last not least, for this chapter on deembedding, how does a bad deembedding look like?
Basically, deembedding shows up like a 'turningback' of the nondeembedded curves.
As can be seen on the next slide, overdeembedding appears as nonphysical curves for higher
frequencies, i.e.:
curves no longer turn clockwise
Sxx traces tend out of the Smith chart
the inner device cannot be modeled with physical model parameters
How does a Bad Deembedding look like?
correctly deembedded
over deembedded, = nonphysical !!
under deembedded
undeembedded DUT
deembedded DUT
Agilent Technologies
Therefore, it is recommended to include dummy structures for OPEN, SHORT and THRU on the
wafer.
Therefore ...
Deembedding Test Stuctures Proposal
OPEN SHORT THRU
Agilent Technologies
After a good and verified calibration, as well as an correct deembedding, let's now look into
RF Modeling Examples
We will look at three RF modeling examples:
Sparameter modeling for a MOS transistor based on the BSIM3v3 model
smallsignal Sparameter modeling for transistors
modeling of passive components, example: spiral inductor
Port1
Sparameter Modeling
Example: MOS Transistor
Port2
Example: BSIM3v3
Cgs_ext
Cgd_ext
Djdb_area
Djdb_perim
Djdb_area
Djdb_perim
Rsub1 .. Rsub3
Agilent Technologies
In this case, because the UCB BSIM3v3 model currently does not include a Gate resistor, and further
needs some enhancements regarding the space charge modeling and the bulk resistor characteristics,
the Berkeley BSIM3v3 model is imbedded into a subcircuit covering the missing modeling features. In
the case of the space charge capacitors, the BSIM3v3 capacitors are switched off (capacity value set
to '0'), and replaced by extra diodes which allow better access to the RF diode parameters.
BSIM3v3 SParameter Modeling Result
S11
S22
Agilent Technologies
As mentioned at the very beginning of this tutorial, the silicon modeling can also apply methods used
much for the GaAs modeling. In the case of an RF power transistor with a fixed operating point, it
might be an overkill to model that transistor for all DC bias conditions. A fixed operating point model
might be sufficient, possibly extended to features more relevant for that application like RF power
dependence etc.
The next slide gives an idea on what to do.
TAU)
Operating Point RF Modeling for Transistors
Ygd = Y12
Ygs = Y11 + Y12
Yds = Y22 + Y12
Ygm = Y21  Y12 = gm * exp(j
Ygs
Ygd
Yds
Ygm
Solved for the admittances:
+
+
=
= 1 K K *
S
S
MAG
2
12
21
Verifying the Modeling Quality
Since these
formulas include
all Sparameters,
they can be used
to check the fitting
Max Available Gain
{MAG(S21)}
2
Agilent Technologies
with the stability factor K
including all 4 Sparameters
Nonlinear Harmonic Balance Modeling
For a proper design and a good production yield, RF modeling engineers should start thinking in terms
of how the RF designers will use their model parameters in the final circuit design. Therefore, besides
the classical SPICElike Sparameter modeling, also large signal RF modeling (harmonic balance)
including checking the nonlinear signal behavior in the time domain comes into play.
Beyond SParameters ...
s11
RF R A B
85046ASPARAMETER TESTSET
DUT
cv CV
DUT 12.05pF
in out
transmit in out transmit
DC
DUT
DC input, transfer, output
CV curves, w/o TF, Ls etc
Spar, linear (no harmonics),
op.pt. dependent, imbedded in Z0
Nonlinear frequency analysis, harmonics, etc...
Time domain
Agilent Technologies
For this type of modeling, simulators such as ADS including harmonic balance features are required to
characterize the nonlinear RF performance of devices and circuits, depending on operating point and
RF signal level.
What is Harmonic Balance (HB) Simulation ?
I IR R
I IC C I IL L I ID D
Error is not Error is not
zero !!! zero !!!
Iterate again. Iterate again.
Test (Kirchoffs law): Test (Kirchoffs law):
I ID D I IR R I IC C I IL L I ni ti al Esti mate: I ni ti al Esti mate:
spectral spectral voltage voltage
Start in the Start in the
Frequency Domain Frequency Domain
Convert: ts >fs Convert: ts >fs Calculate currents Calculate currents
Wi thi n Wi thi n
tolerance tolerance
Last Esti mate Last Esti mate
wi th least error wi th least error
I IR R I IC C I IL L
I ID D
spectrum of harmonics available for all nodes/branches in the circuit
Agilent Technologies
Harmonic balance (HB) is a frequencydomain simulation technique. Signals are treated as
summations of finite numbers of sine waves, i.e. as periodic signals. This approach is valid for most
signals that might be analyzed using a network analyzer or a spectrum analyzer. It is well suited to
stimulusresponse and sweptparameter simulations. Harmonic balance simulations use one or two
sinewave stimuli to determine (for example) conversion loss vs. drive level, distortion vs. frequency,
and gain compression. Harmonic balance is also well suited to analyzing highQ, reverberant, and
frequency conversion circuits.
Harmonic Balance and TimeDomain Simulation
Harmonic balance calculates voltages and currents in much the same way as timedomain simulators
such as SPICE do. But harmonic balance must solve for the magnitudes and phases of all spectral lines
simultaneously. In effect, the entire waveform is being solved for at once. Harmonic balance is
extremely efficient if the signals are simple in the frequency domainas they are, for example, when an
amplifier is driven by a sine wave.
Circuits that have nonrepeating transient behavior are best analyzed using a timedomain (transient)
simulator which, in contrary to SPICE, also includes accurate RF models. In general, harmonic balance
is not very useful for analyzing signals that might be analyzed using an arbitrary waveform generator or
a wide bandwidth oscilloscope. Therefore, it is best to use a tool which offers a wide range of RF
simulation techniques in a single user environment.
What happens when an harmonic balance simulation is executed?
When a harmonic balance simulation is run, the following steps occur, in this order:
1. The DC operating point of the circuit is calculated.
2. A linear AC analysis is used to analyze linear and passive components in the frequency domain.
3. Nonlinear devices (only) are analyzed in the time domain. The Fourier transform is then used to
include these results in the analysis.
4. The estimated voltage spectrum is refined until Kirchhoff's current and voltage laws (KCL and
KVL) are both satisfied for the circuit. Iterative, matrixdriven techniques are used.
5. The solution is a voltage spectrum which is the same at all nodes in the circuit. The mathematical
analysis has converged. The harmonics are now balanced.
In general, all Sparameters vary as a function of input power. For transistors, usually up to 30dBm,
they can nevertheless be considered as linear, without harmonics. However, keep in mind that when the
RF signal power increases, also harmonic frequencies show up. In this case, we can no longer talk of
(linear) Sparameters.
freq
freq
DC bias
DC bias
s
i
g
n
a
l
p
o
w
e
r
Publications:
HPEEsof symposium Advanced Techniques for Communication Signal Path Design, 1997, available
from AgilentEEsof.
With respect to todays digital modulation schemes in communications systems, the operating
conditions of transistors cannot be considered as linear any more. We have to consider the magnitude
and phase of the DC bias, the base frequency and the harmonics.
For simulations, harmonic balance type simulators come into play, as said above. Regarding
measurements, nonlinear network analyzers must be consider, which allow to measure the magnitude
and phase of the base frequency plus all harmonics.
Let's now look at two examples of what can be modeled when using such measurement systems and RF
simulators.
Example: HB Modeling of a Transistor
Pin 20dBm 10dBm
Pin 10dBm
Pin 20dBm
Agilent Technologies
In the example above, the input RF signal is swept for fixed DC operating points, and the harmonics
are analyzed as a function of the input RF power. This gives the compression plot vs. RF input power
for the base frequency and the harmonics (levelwise below) as given to the left. From these signal
levels, corresponding sine functions can be derived (magnitude and phase) and the realworld, time
domain signal can be calculated (plots to the right). This finally allows the modeling engineer to check
the performance of its models with respect to its application in the realworld design, and not only for
the case where the component is inserted in a fixed Z0 impedance environment, and linear operating
conditions.
Since in realworld, for maximum power transmission, impedance matching has to be applied to the
device input and output, another harmonic balance simulation result is given below for the dynamic
loadline. In case of impedance matching, and no longer Z0=50 matching like for the linear S
parameter measurements in the previous chapter, current and voltage at each port can be out of phase,
and the static (DC) loadline of a transistor can change.
This is given in the slide below: For low frequencies, the output current can follow the output voltage
swing, and we measure the wellknown DC loadline. For high frequencies, in the GHz range, this is no
longer the case. Besides the mentioned impedance matching, also the nonquasistatic transistor
behavior shows up, delaying the amplified signal further, and the previous straight DC loadline
degrades to an ellipse or a similar distortion. Check also the dot, indicating the operating point bias for
the AC analysis.
Example: HB Dynamic Loadline Modeling
DC output characteristic
static loadline
dynamic loadline
operating point AC
Agilent Technologies
Note:
for nonlinear Sparameter measurements, a specific nonlinear vector network analyzer system
(NNWA) has to be applied.
Publications on NNWAs:
Marc Vanden Bossche, Agilent Technologies NMDG, 'Accurate and Traceable High Frequency Large
Signal Measurements of TwoPorts', European Microwave Conference, Oct. 48, 1999, Munich
Summary
Agilent Technologies
>> For successfull RF MOS designs with high yield,
accurate device models for all circuit components
are a must.
>> Basic understanding of Sparameters is essential
for modeling
>> Verification of all RF modeling steps is a must
>> Modeling engineers need to understand the
application conditions for their components